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[bsp][bluetrum] add a new board support

This commit is contained in:
greedyhao 2020-12-10 11:02:26 +08:00
parent 86756c0d4c
commit 40ef822979
59 changed files with 4484 additions and 0 deletions
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1
bsp/bluetrum/README.md Normal file
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# Bluetrum RISC-V Processor Support Package

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bsp/bluetrum/ab32vg1-ab-prougen/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=8
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=1024
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_DEBUG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_DEVICE_OPS=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# General Purpose UARTs
#
CONFIG_BSP_USING_UART0=y
CONFIG_BOARD_BLUETRUM_EVB=y

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*.dblite
*.bin
*.dcf
*.map
*.pyc
*.elf
*.old
build

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bsp/bluetrum/ab32vg1-ab-prougen/Kconfig Normal file
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mainmenu "RT-Thread Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"
config BOARD_BLUETRUM_EVB
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y

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# AB32VG1 骄龙开发板 BSP 说明
## 简介
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核的开发板，最高主频为 120Mhz，该开发板芯片为 AB5301A。
开发板外观如下图所示：
![board](figures/board.png)
该开发板常用 **板载资源** 如下：
- MCU：AB5301A，主频 120MHz，可超频至 192MHz，4Mbit FLASH ，192KB RAM。
- 常用外设
- LED: RGB灯
- 按键: 3 个, USER(s2,s3) and RESET(s1)
- 常用接口：USB 转串口、SD 卡接口
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :---------- |
| USB 转串口 | 支持 | |
| SD卡 | 即将支持 | |
| IRDA | 即将支持 | |
| 音频接口 | 即将支持 | |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA PB PE PF |
| UART | 支持 | UART0/1/2 |
| SDIO | 即将支持 | |
| ADC | 即将支持 | |
| SPI | 即将支持 | |
| I2C | 即将支持 | 软件 I2C |
| RTC | 即将支持 | |
| WDT | 即将支持 | |
| FLASH | 即将支持 | |
| PWM | 即将支持 | |
| USB Device | 暂不支持 | |
| USB Host | 暂不支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 GCC 开发环境。下面介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
运行 `scons` 编译得到 `.dcf` 固件，通过 `downloader` 进行下载
#### 运行结果
下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，红色 LED 常亮、绿色 LED 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Dec 9 2020
2006 - 2020 Copyright by rt-thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons` 命令重新编译工程。
## 注意事项
暂无
## 维护人信息
- [greedyhao](https://github.com/greedyhao)

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
if os.path.exists(SDK_ROOT + '/libcpu'):
libcpu_path_prefix = SDK_ROOT + '/libcpu'
else:
libcpu_path_prefix = os.path.dirname(SDK_ROOT) + '/libcpu'
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = True)
bsp_library_type = 'hal_libraries'
rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, bsp_library_type, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hal_drivers', 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libcpu_path_prefix, 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/09/30 Bernard The first version
*/
#include <rtthread.h>
#include "board.h"
int main(void)
{
uint32_t cnt = 0;
uint8_t pin = rt_pin_get("PE.1");
rt_pin_mode(pin, PIN_MODE_OUTPUT);
rt_kprintf("Hello, world\n");
while (1)
{
if (cnt % 2 == 0) {
rt_pin_write(pin, PIN_LOW);
} else {
rt_pin_write(pin, PIN_HIGH);
}
cnt++;
rt_thread_mdelay(1000);
}
return 0;
}

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menu "General Purpose UARTs"
menuconfig BSP_USING_UART0
bool "Enable UART0"
select RT_USING_SERIAL
default y
endmenu

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
ab32vg1_hal_msp.c
''')
CPPPATH = [cwd]
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
objs = [group]
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1_hal.h"
void hal_uart_mspinit(struct uart_handle *huart)
{
struct gpio_init gpio_init;
if (huart->instance == UART0_BASE) {
gpio_init.pin = GPIO_PIN_7;
gpio_init.pull = GPIO_PULLUP;
gpio_init.dir = GPIO_DIR_INPUT;
gpio_init.de = GPIO_DIGITAL;
gpio_init.alternate = GPIO_AF_MAP_Gx(UT0TXMAP_AF, GPIO_AF_G1) | UT0RXMAP_TX;
gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | UT0TXMAP_AF;
hal_gpio_init(GPIOA_BASE, &gpio_init);
} else if (huart->instance == UART1_BASE) {
gpio_init.pin = GPIO_PIN_4;
gpio_init.dir = GPIO_DIR_OUTPUT;
gpio_init.de = GPIO_DIGITAL;
gpio_init.alternate = GPIO_AF_MAP_Gx(UT1TXMAP_AF, GPIO_AF_G2);
gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | UT1TXMAP_AF;
hal_gpio_init(GPIOA_BASE, &gpio_init);
gpio_init.pin = GPIO_PIN_3;
gpio_init.pull = GPIO_PULLUP;
gpio_init.dir = GPIO_DIR_INPUT;
gpio_init.de = GPIO_DIGITAL;
gpio_init.alternate = GPIO_AF_MAP_Gx(UT1RXMAP_AF, GPIO_AF_G2);
gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | UT1RXMAP_AF;
hal_gpio_init(GPIOA_BASE, &gpio_init);
/* Interrupt */
}
}
#ifdef HAL_DAC_MODULE_ENABLED
void hal_dac_mspinit(struct dac_handle *hdac)
{
}
#endif
#ifdef HAL_SD_MODULE_ENABLED
void hal_sd_mspinit(sd_handle_t hsd)
{
struct gpio_init gpio_init;
gpio_init.pin = GPIO_PIN_0 | GPIO_PIN_2;
gpio_init.pull = GPIO_PULLUP;
gpio_init.dir = GPIO_DIR_INPUT;
gpio_init.de = GPIO_DIGITAL;
gpio_init.alternate = GPIO_AF_MAP_Gx(SD0MAP_AF, GPIO_AF_G2);
gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | SD0MAP_AF;
hal_gpio_init(GPIOB_BASE, &gpio_init);
gpio_init.pin = GPIO_PIN_1;
gpio_init.dir = GPIO_DIR_OUTPUT;
gpio_init.alternate = GPIO_AF_MAP_Gx(SD0MAP_AF, GPIO_AF_G2);
gpio_init.af_con = GPIO_AFEN | GPIO_AFCON0 | SD0MAP_AF;
hal_gpio_init(GPIOB_BASE, &gpio_init);
}
#endif

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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-18 greedyhao first version
*/
#include <rthw.h>
#include "board.h"
int rt_hw_usart_init(void);
void my_printf(const char *format, ...);
void timer0_cfg(uint32_t ticks);
void rt_soft_isr(int vector, void *param);
void cpu_irq_comm(void);
void set_cpu_irq_comm(void (*irq_hook)(void));
extern uint32_t __aram_start, __eram_end;
void hal_printf(const char *format, ...)
{
va_list param;
va_start(param, format);
rt_kprintf(format, param);
va_end(param);
}
void timer0_isr(int vector, void *param)
{
rt_interrupt_enter();
TMR0CPND = BIT(9);
rt_tick_increase();
rt_interrupt_leave();
}
void timer0_init(void)
{
TMR0CON = BIT(7); //TIE
TMR0CNT = 0;
rt_hw_interrupt_install(IRQ_TMR0_VECTOR, timer0_isr, RT_NULL, "tick");
}
void timer0_cfg(uint32_t ticks)
{
TMR0PR = (uint32_t)(ticks - 1UL); //1ms interrupt
TMR0CON |= BIT(0); // EN
}
void hal_mdelay(uint32_t ms)
{
rt_thread_mdelay(ms);
}
void rt_hw_systick_init(void)
{
CLKCON2 &= 0x00ffffff;
CLKCON2 |= (25 << 24); //配置x26m_div_clk = 1M (timer, ir, fmam ...用到)
CLKCON0 &= ~(7 << 23);
CLKCON0 |= BIT(24); //tmr_inc select x26m_div_clk = 1M
set_sysclk(SYSCLK_48M);
/* Setting software interrupt */
set_cpu_irq_comm(cpu_irq_comm);
rt_hw_interrupt_install(IRQ_SW_VECTOR, rt_soft_isr, RT_NULL, "sw_irq");
timer0_init();
hal_set_tick_hook(timer0_cfg);
hal_set_ticks(get_sysclk_nhz()/RT_TICK_PER_SECOND);
PICCON |= 0x10002;
}
void rt_hw_board_init(void)
{
WDT_DIS();
rt_hw_systick_init();
#ifdef RT_USING_HEAP
rt_system_heap_init(&__aram_start, &__eram_end);
#endif
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif // RT_USING_PIN
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif // RT_USING_SERIAL
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif // RT_USING_CONSOLE
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-18 greedyhao first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <rtthread.h>
#include "ab32vgx.h"
#include "drv_gpio.h"
#endif

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#ifndef CCONFIG_H__
#define CCONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* compiler configure file for RT-Thread in GCC*/
#define STDC "1989"
#define HAVE_SIGEVENT 1
#define HAVE_SIGINFO 1
#define HAVE_SIGVAL 1
#endif

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/* Define the flash max size */
__max_flash_size = 768k;
__base = 0x10000000;
__comm_vma = 0x17000;
__max_comm_size = 76k;
MEMORY
{
init : org = __base, len = 512
flash(rx) : org = __base + 512, len = __max_flash_size
comm(rx) : org = __comm_vma, len = __max_comm_size
data : org = 0x11000, len = 16k
stack : org = 0x15000, len = 8k
aram : org = 0x50000, len = 16k
dram : org = 0x54000, len = 12k
eram : org = 0x57000, len = 0xa00
}
SECTIONS
{
.init : {
*(.reset)
} > init
.comm : {
KEEP(*(.vector))
*(.com_text*)
*(.text*)
*(.rodata*)
*(.com_rodata*)
*(.rela*)
*(.data*)
*(.sdata*)
LONG(0)
} > comm AT > flash
.rti : {
. = ALIGN(4);
/* section information for initial */
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
} > comm AT > flash
.flash : {
. = ALIGN(512);
} > flash
.bss (NOLOAD):
{
__bss_start = .;
*(COMMON)
*(.bss)
*(.sbss)
*(.buf*)
__bss_end = .;
} > data
__bss_size = __bss_end - __bss_start;
.stack (NOLOAD) : {
__irq_stack_start = .;
. = 0x2000;
__irq_stack = .;
} > stack
__irq_stack_size = __irq_stack - __irq_stack_start;
.code_aecram (NOLOAD): {
__aram_start = .;
} > aram
.code_decram (NOLOAD): {
} > dram
.code_encram (NOLOAD): {
__eram_start = .;
. = 0xa00;
__eram_end = .;
} > eram
}
/* Calc the lma */
__bank_size = SIZEOF(.flash);
__comm_lma = LOADADDR(.comm);
__comm_size = SIZEOF(.comm) + SIZEOF(.rti);

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 1024
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 1024
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* General Purpose UARTs */
#define BSP_USING_UART0
#define BOARD_BLUETRUM_EVB
#endif

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import os
# toolchains options
ARCH ='risc-v'
CPU ='bluetrum'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
# else:
# RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
# EXEC_PATH = r'/opt/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.1-20190425-1021/bin'
EXEC_PATH = r'D:/Softwares/RT-ThreadStudio/repo/Extract/ToolChain_Support_Packages/RISC-V/RISC-V-GCC/10.1.0/bin'
else:
print('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'riscv64-unknown-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
# DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32'
# CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -ggdb'
AFLAGS += ' -ggdb'
else:
CFLAGS += ' -Os'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION += './riscv32-elf-xmaker -b rtthread.xm\n'

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# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
if rtconfig.PLATFORM == 'armcc':
src += Glob('*_rvds.S')
if rtconfig.PLATFORM == 'gcc':
src += Glob('*_init.S')
src += Glob('*_gcc.S')
if rtconfig.PLATFORM == 'iar':
src += Glob('*_iar.S')
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/11/18 greedyhao The first version.
*/
#include "ab32vg1.h"
.global rt_interrupt_from_thread
.global rt_interrupt_to_thread
.global rt_cur_thread_sp
.global rt_switch_flag
.global rt_interrupt_nest
/*
* rt_base_t rt_hw_interrupt_disable();
* a0 -> return
*/
.global rt_hw_interrupt_disable
rt_hw_interrupt_disable:
lw a5, PICCON(zero)
mv a0, a5
andi a5, a5, -2
sw a5, PICCON(zero)
ret
/*
* void rt_hw_interrupt_enable(rt_base_t level);
* a0 -> level
*/
.global rt_hw_interrupt_enable
rt_hw_interrupt_enable:
andi a0, a0, 1
beqz a0,enable_int_ret
lw a5, PICCON(zero)
ori a5, a5, 1
sw a5,PICCON(zero)
enable_int_ret:
ret
/* Macro for saving task context */
.macro save_context
addi sp, sp, -120
/* Save Context */
sw x1, 0(sp)
sw x4, 4(sp)
sw x5, 8(sp)
sw x6, 12(sp)
sw x7, 16(sp)
sw x8, 20(sp)
sw x9, 24(sp)
sw x10, 28(sp)
sw x11, 32(sp)
sw x12, 36(sp)
sw x13, 40(sp)
sw x14, 44(sp)
sw x15, 48(sp)
sw x16, 52(sp)
sw x17, 56(sp)
sw x18, 60(sp)
sw x19, 64(sp)
sw x20, 68(sp)
sw x21, 72(sp)
sw x22, 76(sp)
sw x23, 80(sp)
sw x24, 84(sp)
sw x25, 88(sp)
sw x26, 92(sp)
sw x27, 96(sp)
sw x28, 100(sp)
sw x29, 104(sp)
sw x30, 108(sp)
sw x31, 112(sp)
lw a5, EPC(zero) //Saves current program counter (EPC) as task program counter
sw a5, 116(sp)
sw sp, rt_cur_thread_sp, a4 //store sp in preempted tasks tcb
.endm
/* Macro for restoring task context */
.macro restore_context
la a5, rt_cur_thread_sp
lw sp, 0(a5) //get new task stack pointer
/* Load task program counter EPC*/
lw a5, 116(sp)
sw a5, EPC(zero)
/* Restore registers,
Skip global pointer because that does not change */
lw x1, 0(sp)
lw x4, 4(sp)
lw x5, 8(sp)
lw x6, 12(sp)
lw x7, 16(sp)
lw x8, 20(sp)
lw x9, 24(sp)
lw x10, 28(sp)
lw x11, 32(sp)
lw x12, 36(sp)
lw x13, 40(sp)
lw x14, 44(sp)
lw x15, 48(sp)
lw x16, 52(sp)
lw x17, 56(sp)
lw x18, 60(sp)
lw x19, 64(sp)
lw x20, 68(sp)
lw x21, 72(sp)
lw x22, 76(sp)
lw x23, 80(sp)
lw x24, 84(sp)
lw x25, 88(sp)
lw x26, 92(sp)
lw x27, 96(sp)
lw x28, 100(sp)
lw x29, 104(sp)
lw x30, 108(sp)
lw x31, 112(sp)
addi sp, sp, 120
mret
.endm
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
sw zero, rt_interrupt_from_thread, a4 /*set from thread to 0*/
sw a0, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
sb zero, rt_interrupt_nest, a4 /*rt_interrupt_nest = 0*/
li a5, 1
sw a5, rt_switch_flag, a4 // rt_switch_flag = 1;
SWINT /*kick soft interrupt*/
lw a5, PICCON(zero) /*enable interrupt*/
ori a5, a5, 1
sw a5, PICCON(zero)
ret
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
sw a1, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
li a5, 1
sw a5, rt_switch_flag, a4 // rt_switch_flag = 1;
SWINT /*kick soft interrupt*/
ret
/*
* void rt_switch_to_thread(void);
* r0 --> to
*/
.globl rt_switch_to_thread
rt_switch_to_thread:
lw a0, rt_interrupt_from_thread
lw a5, rt_cur_thread_sp
sw a5, 0(a0)
lw a0, rt_interrupt_to_thread
lw a5, 0(a0)
sw a5, rt_cur_thread_sp, a4
ret
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
* a0 --> from
* a1 --> to
*/
.global rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
lw a5, rt_switch_flag
bnez a5, _reswitch
li a5, 0x01
sw a5, rt_switch_flag, a4
sw a0, rt_interrupt_from_thread, a4 /*set rt_interrupt_from_thread*/
_reswitch:
sw a1, rt_interrupt_to_thread, a4 /*set rt_interrupt_to_thread*/
ret
//软中断服务
.global rt_soft_isr
rt_soft_isr:
li a5, 0x4 // PICPND = BIT(IRQ_SW_VECTOR); 清软中断Pending
sw a5, PICPND(zero)
ret
.globl low_prio_irq
low_prio_irq:
save_context
li a5, 1
sb a5, rt_interrupt_nest, a4 // rt_interrupt_nest = 1;
lw a5, cpu_irq_comm_hook
jalr a5
lw a5, rt_switch_flag
beqz a5, _low_prio_irq_exit // if (rt_switch_flag)
jal rt_switch_to_thread
sw zero, rt_switch_flag, a4 // rt_switch_flag = 0;
_low_prio_irq_exit:
sb zero, rt_interrupt_nest, a4 // rt_interrupt_nest = 0;
restore_context

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/11/18 greedyhao Bluetrum RISC-V porting code.
*/
#include <rthw.h>
#include <rtthread.h>
volatile rt_ubase_t rt_interrupt_from_thread = 0;
volatile rt_ubase_t rt_interrupt_to_thread = 0;
volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
volatile rt_uint32_t rt_switch_flag = 0;
rt_uint32_t rt_cur_thread_sp = 0;
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry,
void *parameter,
rt_uint8_t *stack_addr,
void *texit)
{
rt_uint32_t *stk;
register int *tp asm("x3");
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
stk--;
*stk = (rt_uint32_t)tentry; /* Start address */
stk -= 22;
*stk = (rt_uint32_t)parameter; /* Register a0 parameter*/
stk -= 6;
*stk = (rt_uint32_t)tp; /* Register thread pointer */
stk --;
*stk = (rt_uint32_t)texit; /* Register ra texit*/
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/** shutdown CPU */
void rt_hw_cpu_shutdown(void)
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}

71
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/11/18 greedyhao Bluetrum RISC-V porting code.
*/
#include <rtthread.h>
#include <stdbool.h>
#include <rthw.h>
#include "ab32vgx.h"
uint32_t irq_mask AT(.bss.irq_tbl);
void *tbl_irq_vector[IRQ_TOTAL_NUM] AT(.bss.irq_tbl);
void (*cpu_irq_comm_hook)(void);
void set_cpu_irq_comm(void (*irq_hook)(void))
{
cpu_irq_comm_hook = irq_hook;
}
AT(.com_text.irq)
void cpu_irq_comm_do(void)
{
void (*pfnct)(void);
uint32_t irq_pend = PICPND & irq_mask;
for (int i = 0; i < IRQ_TOTAL_NUM; i++) {
if (irq_pend & BIT(i)) {
pfnct = tbl_irq_vector[i];
if (pfnct) {
pfnct(); /* call ISR */
}
}
}
}
void rt_hw_interrupt_init(void)
{
}
/**
* @brief This function will install a interrupt service routine to a interrupt.
*
* @param vector
* @param handler
* @param param
* @param name
* @return rt_isr_handler_t
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector,
rt_isr_handler_t handler,
void *param,
const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < IRQ_TOTAL_NUM) {
uint32_t cpu_ie = PICCON&BIT(0);
PICCON &= ~BIT(0);
old_handler = tbl_irq_vector[vector];
tbl_irq_vector[vector] = handler;
irq_mask |= BIT(vector);
PICCON |= cpu_ie;
PICPR &= ~BIT(vector);
PICEN |= BIT(vector);
}
return old_handler;
}

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = []
CPPPATH = [cwd]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_SERIAL'):
src += ['drv_usart.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
objs = [group]
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

18
bsp/bluetrum/libraries/hal_drivers/drv_common.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-18 greedyhao first version
*/
#ifndef DRV_COMMON_H__
#define DRV_COMMON_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#endif // DRV_COMMON_H__

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bsp/bluetrum/libraries/hal_drivers/drv_gpio.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-19 greedyhao first version
*/
#include "drv_gpio.h"
#ifdef RT_USING_PIN
// #define DRV_DEBUG
#define LOG_TAG "drv.gpio"
#include <drv_log.h>
struct port_info
{
uint8_t start_pin;
uint8_t delta_pin;
uint8_t total_pin;
};
/* It needs to be adjusted to the hardware. */
static const struct port_info port_table[] =
{
{0, 8, 0}, /* PA0-PA7 */
{0, 5, 8}, /* PB0-PB5 */
{0, 8, 13}, /* PE0-PE7 */
{0, 6, 21}, /* PF0-PF6 */
};
static const hal_sfr_t port_sfr[] =
{
GPIOA_BASE,
GPIOB_BASE,
GPIOE_BASE,
GPIOF_BASE,
};
#define PIN_NUM(port, no) ((uint8_t)(port_table[port].total_pin + no - port_table[port].start_pin))
#define _PIN_PORT(pin) (uint8_t)(((pin) >> 3) & 0xFu)
#define PIN_PORT(pin) ((port_table[_PIN_PORT(pin)].delta_pin == 8) ? _PIN_PORT(pin) : _PIN_PORT(pin) + 1)
#define PORT_SFR(port) (port_sfr[(port)])
#define PIN_NO(pin) (uint8_t)((pin) & 0xFu)
// #define PIN_ABPIN(pin) (uint8_t)(port_table[PIN_PORT(pin)].total_pin + PIN_NO(pin))
static rt_base_t ab32_pin_get(const char *name)
{
rt_base_t pin = 0;
int hw_port_num, hw_pin_num = 0;
int i, name_len;
name_len = rt_strlen(name);
if ((name_len < 4) || (name_len >= 6))
{
return -RT_EINVAL;
}
if ((name[0] != 'P') || (name[2] != '.'))
{
return -RT_EINVAL;
}
if ((name[1] >= 'A') && (name[1] <= 'B'))
{
hw_port_num = (int)(name[1] - 'A');
}
else if ((name[1] >= 'E') && (name[1] <= 'G'))
{
hw_port_num = (int)(name[1] - 'A') - 2; /* Without 'C' and 'D'. */
}
else
{
return -RT_EINVAL;
}
for (i = 3; i < name_len; i++)
{
hw_pin_num *= 10;
hw_pin_num += name[i] - '0';
}
pin = PIN_NUM(hw_port_num, hw_pin_num);
LOG_D("name=%s", name);
LOG_D("hw_port_num=%d hw_pin_num=%d pin=%d", hw_port_num, hw_pin_num, pin);
return pin;
}
static void ab32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
uint8_t port = PIN_PORT(pin);
uint8_t gpio_pin = pin - port_table[port].total_pin;
hal_gpio_write(PORT_SFR(port), gpio_pin, value);
}
static int ab32_pin_read(rt_device_t dev, rt_base_t pin)
{
uint8_t port = PIN_PORT(pin);
uint8_t gpio_pin = pin - port_table[port].total_pin;
return hal_gpio_read(PORT_SFR(port), gpio_pin);
}
static void ab32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
struct gpio_init gpio_init;
uint8_t port = PIN_PORT(pin);
gpio_init.pin = BIT(pin - port_table[port].total_pin);
gpio_init.de = GPIO_DIGITAL;
gpio_init.af_con = GPIO_AFDIS;
LOG_D("port=%d pin=%d", port, gpio_init.pin);
switch (mode)
{
case PIN_MODE_INPUT:
case PIN_MODE_INPUT_PULLUP:
gpio_init.pull = GPIO_PULLUP;
gpio_init.dir = GPIO_DIR_INPUT;
break;
case PIN_MODE_INPUT_PULLDOWN:
gpio_init.pull = GPIO_PULLDOWN;
gpio_init.dir = GPIO_DIR_INPUT;
break;
case PIN_MODE_OUTPUT:
case PIN_MODE_OUTPUT_OD:
default:
gpio_init.pull = GPIO_NOPULL;
gpio_init.dir = GPIO_DIR_OUTPUT;
break;
}
hal_gpio_init(PORT_SFR(port), &gpio_init);
}
static rt_err_t ab32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
return -RT_ERROR;
}
static rt_err_t ab32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
return -RT_ERROR;
}
static rt_err_t ab32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
return -RT_ERROR;
}
const static struct rt_pin_ops _ab32_pin_ops =
{
ab32_pin_mode,
ab32_pin_write,
ab32_pin_read,
ab32_pin_attach_irq,
ab32_pin_dettach_irq,
ab32_pin_irq_enable,
ab32_pin_get,
};
int rt_hw_pin_init(void)
{
return rt_device_pin_register("pin", &_ab32_pin_ops, RT_NULL);
}
#endif

21
bsp/bluetrum/libraries/hal_drivers/drv_gpio.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-19 greedyhao first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
#include "drv_common.h"
#include "board.h"
#define __AB32_PORT(port) GPIO##port
int rt_hw_pin_init(void);
#endif // DRV_GPIO_H__

27
bsp/bluetrum/libraries/hal_drivers/drv_log.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-19 greedyhao first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

205
bsp/bluetrum/libraries/hal_drivers/drv_usart.c Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-20 greedyhao first version
*/
#include "board.h"
#include "drv_usart.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.usart"
#include <drv_log.h>
#undef RT_SERIAL_USING_DMA
enum
{
UART0_INDEX,
UART1_INDEX,
};
static struct ab32_uart_config uart_config[] =
{
{
.name = "uart0",
.instance = UART0_BASE,
},
{
.name = "uart1",
.instance = UART1_BASE,
}
};
static struct ab32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static rt_err_t ab32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct ab32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct ab32_uart, serial);
uart->handle.instance = uart->config->instance;
uart->handle.init.baud = cfg->baud_rate;
uart->handle.init.mode = UART_MODE_TX_RX;
switch (cfg->data_bits)
{
case DATA_BITS_8:
uart->handle.init.word_len = UART_WORDLENGTH_8B;
break;
case DATA_BITS_9:
uart->handle.init.word_len = UART_WORDLENGTH_9B;
break;
default:
uart->handle.init.word_len = UART_WORDLENGTH_8B;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_1:
uart->handle.init.stop_bits = UART_STOPBITS_1;
break;
case STOP_BITS_2:
uart->handle.init.stop_bits = UART_STOPBITS_2;
break;
default:
uart->handle.init.stop_bits = UART_STOPBITS_1;
break;
}
#ifdef RT_SERIAL_USING_DMA
uart->dma_rx.last_index = 0;
#endif
hal_uart_init(&uart->handle);
return RT_EOK;
}
static rt_err_t ab32_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct ab32_uart *uart;
#ifdef RT_SERIAL_USING_DMA
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct ab32_uart, serial);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
hal_uart_control(uart->handle.instance, UART_RXIT_ENABLE, HAL_DISABLE);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
hal_uart_control(uart->handle.instance, UART_RXIT_ENABLE, HAL_ENABLE);
break;
case RT_DEVICE_CTRL_CLOSE:
hal_uart_deinit(uart->handle.instance);
break;
}
return RT_EOK;
}
static int ab32_putc(struct rt_serial_device *serial, char ch)
{
struct ab32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct ab32_uart, serial);
hal_uart_clrflag(uart->handle.instance, UART_FLAG_TXPND);
hal_uart_write(uart->handle.instance, ch);
while(hal_uart_getflag(uart->handle.instance, UART_FLAG_TXPND) == 0);
return 1;
}
static int ab32_getc(struct rt_serial_device *serial)
{
int ch;
struct ab32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct ab32_uart, serial);
ch = -1;
if(hal_uart_getflag(uart->handle.instance, UART_FLAG_RXPND) != HAL_RESET) {
hal_uart_clrflag(uart->handle.instance, UART_FLAG_RXPND);
ch = hal_uart_read(uart->handle.instance);
}
return ch;
}
static rt_size_t ab32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
return -1;
}
static void uart_isr(int vector, void *param)
{
rt_interrupt_enter();
if(hal_uart_getflag(UART0_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART0_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
}
if(hal_uart_getflag(UART1_BASE, UART_FLAG_RXPND)) //RX one byte finish
{
rt_hw_serial_isr(&(uart_obj[UART1_INDEX].serial), RT_SERIAL_EVENT_RX_IND);
}
rt_interrupt_leave();
}
static const struct rt_uart_ops ab32_uart_ops =
{
.configure = ab32_configure,
.control = ab32_control,
.putc = ab32_putc,
.getc = ab32_getc,
.dma_transmit = ab32_dma_transmit
};
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ab32_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
rt_hw_interrupt_install(IRQ_UART0_2_VECTOR, uart_isr, RT_NULL, "ut_isr");
for (int i = 0; i < obj_num; i++)
{
/* init UART object */
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &ab32_uart_ops;
uart_obj[i].serial.config = config;
uart_obj[0].serial.config.baud_rate = 1500000;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
| uart_obj[i].uart_dma_flag
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif

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bsp/bluetrum/libraries/hal_drivers/drv_usart.h Normal file
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/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-20 greedyhao first version
*/
#ifndef DRV_USART_H__
#define DRV_USART_H__
#include "drv_common.h"
#ifdef RT_USING_SERIAL
/* an32 config class */
struct ab32_uart_config
{
const char *name;
hal_sfr_t instance;
// struct dma_config *dma_rx;
// struct dma_config *dma_tx;
};
/* ab32 uart driver class */
struct ab32_uart
{
struct uart_handle handle;
struct ab32_uart_config *config;
#ifdef RT_SERIAL_USING_DMA
struct
{
DMA_HandleTypeDef handle;
rt_size_t last_index;
} dma_rx;
struct
{
DMA_HandleTypeDef handle;
} dma_tx;
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
#endif
int rt_hw_usart_init(void);
#endif

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bsp/bluetrum/libraries/hal_libraries/SConscript Normal file
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import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')

85
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript Normal file
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#-*- encoding: utf-8 -*-
#---------------------------------------------------------------------------------
# @File: Sconscript for package
# @Author: Rice
# @Date: 2020-07-14 16:57:00(v0.0.1)
#
# @LICENSE: GPLv3: https://github.com/rtpkgs/buildpkg/blob/master/LICENSE.
#
#---------------------------------------------------------------------------------
import os
from building import *
Import('RTT_ROOT')
Import('rtconfig')
#---------------------------------------------------------------------------------
# Package configuration
#---------------------------------------------------------------------------------
PKGNAME = "ab32vg1_hal"
VERSION = "v1.0.0"
DEPENDS = [""]
#DEPENDS = ["PKG_USING_RW007"]
#---------------------------------------------------------------------------------
# Compile the configuration
#
# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
#
# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
# LOCAL_CCFLAGS: Local compilation parameter
# LOCAL_ASFLAGS: Local assembly parameters
#
# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH
# is empty # no pass!!!
# CCFLAGS: Global compilation parameter
# ASFLAGS: Global assembly parameters
#
# CPPDEFINES: Global macro definition
# LOCAL_CPPDEFINES: Local macro definition
#
# LIBS: Specify the static library that need to be linked
# LIBPATH: Specify the search directory for the library file (.lib/.a)
#
# LINKFLAGS: Link options
#---------------------------------------------------------------------------------
SOURCES = Glob("./source/*.c")
LOCAL_CPPPATH = []
LOCAL_CCFLAGS = ""
LOCAL_ASFLAGS = ""
CPPPATH = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')]
CCFLAGS = ""
ASFLAGS = ""
CPPDEFINES = []
LOCAL_CPPDEFINES = []
LIBS = []
LIBPATH = []
LINKFLAGS = ""
SOURCES_IGNORE = []
CPPPATH_IGNORE = []
#---------------------------------------------------------------------------------
# Main target
#---------------------------------------------------------------------------------
objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS,
CPPPATH = CPPPATH,
CCFLAGS = CCFLAGS,
ASFLAGS = ASFLAGS,
LOCAL_CPPPATH = LOCAL_CPPPATH,
LOCAL_CCFLAGS = LOCAL_CCFLAGS,
LOCAL_ASFLAGS = LOCAL_ASFLAGS,
CPPDEFINES = CPPDEFINES,
LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
LIBS = LIBS,
LIBPATH = LIBPATH,
LINKFLAGS = LINKFLAGS)
Return("objs")
#---------------------------------------------------------------------------------
# End
#---------------------------------------------------------------------------------

18
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal.h Normal file
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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_H__
#define AB32VG1_HAL_H__
#include "ab32vg1_hal_conf.h"
void hal_set_tick_hook(void (*hook)(uint32_t ticks));
void hal_set_ticks(uint32_t ticks);
void hal_mdelay(uint32_t nms);
void hal_udelay(uint16_t nus);
void hal_printf(const char *format, ...);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_CONF_H__
#define AB32VG1_HAL_CONF_H__
/* System Configuration */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_RCU_MODULE_ENABLED
#define HAL_WDT_MODULE_ENABLED
// #define HAL_DAC_MODULE_ENABLED
// #define HAL_SD_MODULE_ENABLED
/* Includes */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "ab32vg1_hal_gpio.h"
#endif
#ifdef HAL_UART_MODULE_ENABLED
#include "ab32vg1_hal_uart.h"
#endif
#ifdef HAL_RCU_MODULE_ENABLED
#include "ab32vg1_hal_rcu.h"
#endif
#ifdef HAL_WDT_MODULE_ENABLED
#include "ab32vg1_hal_wdt.h"
#endif
#ifdef HAL_DAC_MODULE_ENABLED
#include "ab32vg1_hal_dac.h"
#endif
#ifdef HAL_SD_MODULE_ENABLED
#include "ab32vg1_hal_sd.h"
#endif
#include <assert.h>
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32BG1_HAL_DAC_H__
#define AB32BG1_HAL_DAC_H__
#include "ab32vg1_hal_def.h"
struct dac_init
{
};
struct dac_handle
{
hal_sfr_t instance;
struct dac_init init;
};
/* Initialization functions */
hal_error_t hal_dac_init(struct dac_handle *hdac);
void hal_dac_deinit(uint32_t dacx);
void hal_dac_mspinit(struct dac_handle *hdac);
void hal_dac_control(uint32_t dacx, uint32_t cntl, uint32_t param);
void hal_dac_write(uint32_t dacx, uint32_t data);
uint32_t hal_dac_read(uint32_t dacx);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_DEF_H__
#define AB32VG1_HAL_DEF_H__
#include "ab32vgx.h"
typedef int hal_bool_t;
typedef long hal_base_t;
typedef unsigned long hal_ubase_t;
typedef hal_base_t hal_error_t;
typedef volatile unsigned long* hal_sfr_t;
/* HAL error code definitions */
#define HAL_EOK 0 /**< There is no error */
#define HAL_ERROR 1 /**< A generic error happens */
#define HAL_ETIMEOUT 2 /**< Timed out */
#define HAL_EFULL 3 /**< The resource is full */
#define HAL_EEMPTY 4 /**< The resource is empty */
#define HAL_ENOMEM 5 /**< No memory */
#define HAL_ENOSYS 6 /**< No system */
#define HAL_EBUSY 7 /**< Busy */
#define HAL_EIO 8 /**< IO error */
#define HAL_EINTR 9 /**< Interrupted system call */
#define HAL_EINVAL 10 /**< Invalid argument */
#define HAL_NULL ((void *)0)
#define HAL_DISABLE (0)
#define HAL_ENABLE (1)
#define HAL_RESET (0)
#define HAL_SET (1)
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_GPIO_H__
#define AB32VG1_HAL_GPIO_H__
#include "ab32vg1_hal_def.h"
struct gpio_init
{
uint8_t pin;
uint8_t dir;
uint8_t de;
uint8_t pull;
uint32_t alternate;
uint32_t af_con; /*!< Alternate function control
[4:0]: Mapping name
[6:5]: Mapping control register
[7]: Mapping enable bit */
};
typedef struct gpio_init *gpio_init_t;
enum
{
GPIOxSET = 0x00,
GPIOxCLR,
GPIOx,
GPIOxDIR,
GPIOxDE,
GPIOxFEN,
GPIOxDRV,
GPIOxPU,
GPIOxPD,
GPIOxPU200K,
GPIOxPD200K,
GPIOxPU300K,
GPIOxPD300K,
};
/* Private constants */
#define FUNCMCONx(x) *(volatile uint32_t*)(SFR0_BASE + (0x07 + (x))*4)
/* Exported constants */
#define GPIO_DIR_INPUT (0x01u)
#define GPIO_DIR_OUTPUT (0x02u)
#define GPIO_DIGITAL (0x01u)
#define GPIO_ANALOG (0x02u)
#define GPIO_AFDIS (0u << 7)
#define GPIO_AFEN (1u << 7)
#define GPIO_AFCON0 (0u << 5) /*!< When using UARTT0 UART1 HSUART SPI0 and SD0 */
#define GPIO_AFCON1 (1u << 5) /*!< When using LPWM0 LPWM1 LPWM2 LPWM3 SPI1 UART2 and CLKOUT */
#define GPIO_AFCON2 (2u << 5) /*!< When using IR TIMER3 TIMER4 TIMER5 and IIS */
#define GPIO_AFCON_MASK (0x3u << 5)
#define GPIO_GET_AFCON(af_con) (uint8_t)(((af_con) & (GPIO_AFCON_MASK)) >> 5)
#define GPIO_NOPULL (0x00u)
#define GPIO_PULLUP (0x01u)
#define GPIO_PULLDOWN (0x02u)
#define GPIO_PIN_LOW (0x00u)
#define GPIO_PIN_HIGH (0x01u)
#define GPIOA_BASE ((hal_sfr_t)(&GPIOASET))
#define GPIOB_BASE ((hal_sfr_t)(&GPIOBSET))
#define GPIOE_BASE ((hal_sfr_t)(&GPIOESET))
#define GPIOF_BASE ((hal_sfr_t)(&GPIOFSET))
#define GPIO_PIN_0 (BIT(0))
#define GPIO_PIN_1 (BIT(1))
#define GPIO_PIN_2 (BIT(2))
#define GPIO_PIN_3 (BIT(3))
#define GPIO_PIN_4 (BIT(4))
#define GPIO_PIN_5 (BIT(5))
#define GPIO_PIN_6 (BIT(6))
#define GPIO_PIN_7 (BIT(7))
#define __HAL_GPIO_SET_DIR(__PORT__, __PIN__, __DIR__) (__DIR__) ? (GPIOx_REG((__PORT__), (GPIOxDIR)) |= BIT(__PIN__)) : (GPIOx_REG((__PORT__), (GPIOxDIR)) &= ~BIT(__PIN__))
/* Include GPIO HAL Extended module */
#include "ab32vg1_hal_gpio_ex.h"
/* Initialization and de-initialization functions */
void hal_gpio_init(hal_sfr_t gpiox, gpio_init_t gpio_init);
/* IO operation function */
uint8_t hal_gpio_read(hal_sfr_t gpiox, uint8_t pin);
void hal_gpio_write(hal_sfr_t gpiox, uint8_t pin, uint8_t state);
void hal_gpio_toggle(hal_sfr_t gpiox, uint8_t pin);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_GPIO_EX_H__
#define AB32VG1_HAL_GPIO_EX_H__
/* Alternate function */
/**
* UART0:
* G1: tx:PA7 rx:PA6
* G2: tx:PB2 rx:PB1
* G3: tx:PB3 rx:PB4
* G4: tx:PE7 rx:PE6
* G5: tx:PA1 rx:PA0
* G6: tx:PE0 rx:PE1
* G7: tx:PF2 rx:map to tx
*
* UART1:
* G1: tx:PA7 rx:PA6
* G2: tx:PA4 rx:PA3
* G3: tx:PF2 rx:map to tx
*/
#define GPIO_AF_MAP_Gx(AF, Gx) ((uint32_t)((Gx) << (AF)))
#define GPIO_AF_MAP_CLR(AF) ((uint32_t)(0xfu << (AF)))
#define GPIO_AF_G1 (1u)
#define GPIO_AF_G2 (2u)
#define GPIO_AF_G3 (3u)
#define GPIO_AF_G4 (4u)
#define GPIO_AF_G5 (5u)
#define GPIO_AF_G6 (6u)
#define GPIO_AF_G7 (7u)
#define UT1RXMAP_AF (28u)
#define UT1TXMAP_AF (24u)
#define HSUTRXMAP_AF (20u)
#define HSUTTXMAP_AF (16u)
#define UT0RXMAP_AF (12u)
#define UT0TXMAP_AF ( 8u)
#define SPI0MAP_AF ( 4u)
#define SD0MAP_AF ( 0u)
#define UT1RXMAP_TX ((uint32_t)(0x3u << (UT1RXMAP_AF)))
#define UT0RXMAP_TX ((uint32_t)(0x7u << (UT0RXMAP_AF)))
#define GPIO_HSUART_G1
#define GPIO_HSUART_G2
#define GPIO_HSUART_G3
#define GPIO_HSUART_G4
#define GPIO_HSUART_G5
#define GPIO_HSUART_G6
#define GPIO_HSUART_G7
#define GPIO_HSUART_G8
#define GPIO_HSUART_G9
#define GPIO_HSUART_G10
#define GPIO_SPI0_G1
#define GPIO_SPI0_G2
#define GPIO_SPI0_G3
#define GPIO_SD0_G1
#define GPIO_SD0_G2
#define GPIO_SD0_G3
#define GPIO_SD0_G4
#define GPIO_SD0_G5
#define GPIO_SD0_G6
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_RCU_H__
#define AB32VG1_HAL_RCU_H__
#include "ab32vg1_hal_def.h"
enum rcu_periph_type {
RCU_ROM0 = 0,
RCU_ROM1,
RCU_RAM0,
RCU_RAM1,
RCU_RAM2,
RCU_RAM3,
RCU_RSV0, /*!< reserve */
RCU_RSV1, /*!< reserve */
RCU_TMR0 = 8,
RCU_SD0,
RCU_UART0,
RCU_HSUT0,
RCU_DAC,
RCU_SARADC,
RCU_USB,
RCU_FMRX,
RCU_AUDEC,
RCU_PORT,
RCU_MBIST,
RCU_SPI0,
RCU_UART1 = 21,
RCU_TMR1 = 24,
RCU_TMR2 = 25,
RCU_FMAMFDT = 26,
RCU_FMTX,
RCU_IRRX = 29,
RCU_IIS,
RCU_TMR3 = 34,
RCU_TMR4,
RCU_TMR5,
RCU_UART2,
RCU_SPI1,
};
void hal_rcu_periph_clk_enable(uint32_t periph);
void hal_rcu_periph_clk_disable(uint32_t periph);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_SD_H__
#define AB32VG1_HAL_SD_H__
#include "ab32vg1_hal_def.h"
struct sd_init
{
// uint8_t
};
struct sd_card_info
{
uint32_t rca; /*!< Specifies the Relative Card Address */
uint8_t type; /*!< Specifies the card type */
};
typedef struct sd_card_info* sd_card_info_t;
struct sd_handle
{
hal_sfr_t instance;
struct sd_init init;
struct sd_card_info sdcard;
};
typedef struct sd_handle* sd_handle_t;
#define SD0N (0x00u)
#define CARD_V1 (0x01u)
#define CARD_V2 (0x02u)
#define CARD_MMC (0x03u)
#define SDMMC_CHECK_PATTERM (0x000001AAu)
/* Initialization functions */
hal_error_t hal_sd_init(sd_handle_t hsd);
void hal_sd_deinit(uint32_t sdx);
void hal_sd_mspinit(sd_handle_t hsd);
hal_error_t hal_sd_control(uint32_t control, uint32_t arg);
void hal_sd_write(uint32_t sdx, uint32_t data);
uint32_t hal_sd_read(uint32_t sdx);
// void hal_uart_write_it(uint32_t uartx, uint8_t data);
// uint8_t hal_uart_read_it(uint32_t uartx);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_UART_H__
#define AB32VG1_HAL_UART_H__
#include "ab32vg1_hal_def.h"
/* Exported types */
/** @defgroup UART_Exported_Types UART Exported Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
struct uart_init
{
uint32_t baud; /*!< This member configures the UART communication baud rate.
Baud Rate Register[31:16] is used to configure the rx rate.
Baud Rate Register[15: 0] is used to configure the tx rate.
The baud rate register is computed using the following formula:
UARTBAUD = Fsys_clock/BaudRate-1
for example: UARTBAUD= (26000000/2)/baud-1 */
uint8_t word_len; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UARTEx_Word_Length. */
uint8_t stop_bits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits. */
uint8_t mode; /*!< Specifies whether the receive or one line mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode. */
};
/**
* @brief UART handle struction definition
*
*/
struct uart_handle
{
hal_sfr_t instance;
struct uart_init init;
};
/**
* @}
*/
/* Exported constants */
/**
* @defgroup UARTEx_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_8B (0x00u) /*!< 8 bit long UART frame */
#define UART_WORDLENGTH_9B (0x01u) /*!< 9 bit long UART frame */
/**
* @}
*/
/**
* @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
#define UART_STOPBITS_1 (0x00u) /*!< UART frame with 1 stop bit */
#define UART_STOPBITS_2 (0x01u) /*!< UART frame with 2 stop bit */
/**
* @}
*/
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
#define UART_MODE_TX (0x00u) /*!< TX mode */
#define UART_MODE_TX_RX (0x01u) /*!< RX and TX mode */
/**
* @}
*/
#define UART_FLAG_RXPND (BIT(9)) /*!< RX one byte finish flag */
#define UART_FLAG_TXPND (BIT(8)) /*!< TX one byte finish flag */
#define UART_MODULE_ENABLE (BIT(0)) /*!< UART enable bit */
#define UART_BIT9_ENABLE (BIT(1)) /*!< BIT9 enable bit */
#define UART_RXIT_ENABLE (BIT(2)) /*!< Receive interrupt enable bit */
#define UART_TXIT_ENABLE (BIT(3)) /*!< Transmit interrupt enable bit */
#define UART_SB2_ENABLE (BIT(4)) /*!< Two stop bit enable bit */
#define UART_CLK_SRC1 (BIT(5)) /*!< Clock source select bit */
#define UART_1LINE_ENABLE (BIT(6)) /*!< One-Line mode enable bit */
#define UART_RX_ENABLE (BIT(7)) /*!< Receive enable bit */
#define UART0N (0x00u) /*!< Number of UART0 */
#define UART1N (0x01u) /*!< Number of UART1 */
#define UART2N (0x02u) /*!< Number of UART2 */
#define UART0_BASE ((hal_sfr_t)(&UART0CON))
#define UART1_BASE ((hal_sfr_t)(&UART1CON))
#define UART2_BASE ((hal_sfr_t)(&UART2CON))
/* Exported function */
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
*/
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization functions */
hal_error_t hal_uart_init(struct uart_handle *huart);
void hal_uart_deinit(hal_sfr_t uartx);
void hal_uart_mspinit(struct uart_handle *huart);
/**
* @}
*/
void hal_uart_control(hal_sfr_t uartx, uint32_t cntl, uint32_t param);
void hal_uart_write(hal_sfr_t uartx, uint8_t data);
uint8_t hal_uart_read(hal_sfr_t uartx);
uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag);
void hal_uart_clrflag(hal_sfr_t uartx, uint32_t flag);
/**
* @}
*/
/* Private function */
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
void uart_config_all(struct uart_handle *huart);
/**
* @}
*/
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_WDT_H__
#define AB32VG1_HAL_WDT_H__
#include "ab32vg1_hal_def.h"
#define WDT_CLR() WDTCON = 0xa
#define WDT_EN() WDTCON = 0x110
#define WDT_DIS() WDTCON = 0xaa0
#define WDT_RST() WDTCON = 0xa000110; while (1)
#define WDT_RST_DELAY() WDTCON = 0xa100110; while (1)
#endif

18
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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_SDIO_H__
#define AB32VG1_HAL_SDIO_H__
#include "ab32vg1_hal_def.h"
struct sdio_init
{
uint32_t tmp;
};
typedef struct sdio_init* sdio_init_t;
#endif

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#include "ab32vg1_hal.h"
static uint32_t hw_ticks = 0;
void timer0_cfg(uint32_t ticks);
static void (*tick_cfg_hook)(uint32_t ticks) = HAL_NULL;
void hal_set_tick_hook(void (*hook)(uint32_t ticks))
{
tick_cfg_hook = hook;
}
void hal_set_ticks(uint32_t ticks)
{
if (ticks != hw_ticks) {
hw_ticks = ticks;
}
if (tick_cfg_hook != HAL_NULL) {
tick_cfg_hook(hw_ticks);
}
}
WEAK void hal_mdelay(uint32_t nms)
{
}
void hal_udelay(uint16_t nus)
{
int i;
for (i = 0; i < nus*10; i++) {
asm("nop");
}
}
WEAK void hal_printf(const char *format, ...)
{}

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1_hal.h"
#ifdef HAL_DAC_MODULE_ENABLED
WEAK void hal_dac_mspinit(struct dac_handle *hdac)
{}
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1_hal.h"
#ifdef HAL_GPIO_MODULE_ENABLED
#if 0
#define HAL_LOG(...) hal_printf(__VA_ARGS__)
#else
#define HAL_LOG(...)
#endif
void gpio_afinit(hal_sfr_t gpiox, uint8_t pin, uint32_t alternate, uint32_t af_con)
{
uint32_t is_rx_map_tx = (alternate & UT1RXMAP_TX) || (alternate & UT0RXMAP_TX);
if ((af_con & 0xf0u) != GPIO_AFDIS) {
gpiox[GPIOxFEN] |= BIT(pin);
switch (is_rx_map_tx)
{
case UT1RXMAP_TX:
FUNCMCONx(GPIO_GET_AFCON(af_con)) |= GPIO_AF_MAP_CLR(UT1RXMAP_AF);
break;
case UT0RXMAP_TX:
FUNCMCONx(GPIO_GET_AFCON(af_con)) |= GPIO_AF_MAP_CLR(UT0RXMAP_AF);
break;
default:
break;
}
FUNCMCONx(GPIO_GET_AFCON(af_con)) |= GPIO_AF_MAP_CLR(af_con & 0x1f);
FUNCMCONx(GPIO_GET_AFCON(af_con)) |= alternate;
HAL_LOG("af_con=0x%X AFCON=%d alternate=%d\n", af_con, GPIO_GET_AFCON(af_con), (af_con & 0x1f));
}
}
/**
* @brief Initialize the gpio.
*
* @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN).
* @param gpio_init the configuration of the specified GPIO peripheral.
*/
void hal_gpio_init(hal_sfr_t gpiox, gpio_init_t gpio_init)
{
uint8_t iocurrent = 0;
if (gpio_init == HAL_NULL) {
return;
}
for (iocurrent = 0; iocurrent < 8; iocurrent++) {
if ((gpio_init->pin & BIT(iocurrent)) == 0) {
continue;
}
gpio_afinit(gpiox, iocurrent, gpio_init->alternate, gpio_init->af_con);
switch (gpio_init->dir)
{
case GPIO_DIR_INPUT:
/* When set to input, clear all pull-ups of the port. */
gpiox[GPIOxDIR] |= BIT(iocurrent);
gpiox[GPIOxPU] &= ~BIT(iocurrent);
gpiox[GPIOxPU200K] &= ~BIT(iocurrent);
gpiox[GPIOxPD200K] &= ~BIT(iocurrent);
gpiox[GPIOxPU300K] &= ~BIT(iocurrent);
gpiox[GPIOxPD300K] &= ~BIT(iocurrent);
switch (gpio_init->pull)
{
case GPIO_PULLUP:
gpiox[GPIOxPU] |= BIT(iocurrent);
break;
case GPIO_PULLDOWN:
gpiox[GPIOxPD] |= BIT(iocurrent);
break;
case GPIO_NOPULL:
default:
break;
}
break;
case GPIO_DIR_OUTPUT:
gpiox[GPIOxDIR] &= ~BIT(iocurrent);
break;
default:
break;
}
switch (gpio_init->de)
{
case GPIO_DIGITAL:
gpiox[GPIOxDE] |= BIT(iocurrent);
break;
case GPIO_ANALOG:
gpiox[GPIOxDE] &= ~BIT(iocurrent);
break;
default:
break;
}
}
}
/**
* @brief Read the specified input port pin.
*
* @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN).
* @param pin This parameter can be GPIO_PIN_x where x can be (0.15).
* @return uint8_t The input port pin value.
*/
uint8_t hal_gpio_read(hal_sfr_t gpiox, uint8_t pin)
{
return ((gpiox[GPIOx] & BIT(pin)) != GPIO_PIN_LOW) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
}
/**
* @brief Set or clear the selected data port bit.
*
* @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN).
* @param pin This parameter can be GPIO_PIN_x where x can be (0.15).
* @param state specifies the value to be written to the selected bit.
* @arg GPIO_PIN_LOW:
* @arg GPIO_PIN_HIGH:
*/
void hal_gpio_write(hal_sfr_t gpiox, uint8_t pin, uint8_t state)
{
if (state == GPIO_PIN_LOW) {
gpiox[GPIOx] &= ~BIT(pin);
} else {
gpiox[GPIOx] |= BIT(pin);
}
}
/**
* @brief Toggle the specified GPIO pin.
*
* @param port GPIO port(GPIOAN, GPIOBN, GPIOEN, GPIOFN).
* @param pin This parameter can be GPIO_PIN_x where x can be (0.15).
*/
void hal_gpio_toggle(hal_sfr_t gpiox, uint8_t pin)
{
gpiox[GPIOx] ^= BIT(pin);
}
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1_hal.h"
#ifdef HAL_RCU_MODULE_ENABLED
void hal_rcu_periph_clk_enable(uint32_t periph)
{
if (periph <= RCU_TMR2) {
CLKGAT0 |= BIT(periph);
} else if (periph <= RCU_SPI1) {
CLKGAT1 |= BIT(periph - RCU_FMAMFDT);
}
}
void hal_rcu_periph_clk_disable(uint32_t periph)
{
if (periph <= RCU_TMR2) {
CLKGAT0 &= ~BIT(periph);
} else if (periph <= RCU_SPI1) {
CLKGAT1 &= ~BIT(periph - RCU_FMAMFDT);
}
}
#endif

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#include "ab32vg1_hal.h"
#include "ab32vg1_ll_sdio.h"
#ifdef HAL_SD_MODULE_ENABLED
#include <stdbool.h>
#define HAL_LOG(...) hal_printf(__VA_ARGS__)
/************************* LL ************************************/
#define CK8E BIT(11) //在命令/数据包后加上8CLK
#define CBUSY BIT(10) //Busy Check
#define CLRSP BIT(9) //17Byte Long Rsp
#define CRSP BIT(8) //Need Rsp
//0x40是CMD中的 01 开头。
#define RSP_NO (0x40 | CK8E)
#define RSP_1 (0x40 | CRSP | CK8E) //接收6BYTE
#define RSP_1B (0x40 | CBUSY | CRSP | CK8E) //接收6BYTE，并等待BUSY
#define RSP_2 (0x40 | CLRSP | CRSP | CK8E) //接收17BYTE
#define RSP_3 (0x40 | CRSP | CK8E) //接收6BYTE
#define RSP_6 (0x40 | CRSP | CK8E) //接收6BYTE
#define RSP_7 (0x40 | CRSP | CK8E) //接收6BYTE
#define REQ_MULTREAD (18 | 0x40 | CRSP) //多块读时，不需要增加8CLK。其实，多块读先KICK DATA，这个是无所谓的
#define RSP_BUSY_TIMEOUT 2400000 //大约2s
#define RSP_TIMEOUT 6000 //大约5ms
enum
{
SDCON = 0, /* [20]:BUSY [19:17]:CRCS [16]:DCRCE [15]:NRPS [1]:Data bus width [0]:SD enable */
SDCPND,
SDBAUD,
SDCMD,
SDARG3,
SDARG2,
SDARG1,
SDARG0,
SDDMAADR,
SDDMACNT,
};
uint8_t sysclk_update_baud(uint8_t baud);
void sdio_setbaud(hal_sfr_t sdiox, uint8_t baud)
{
sdiox[SDBAUD] = sysclk_update_baud(baud);
}
void sdio_init(hal_sfr_t sdiox, sdio_init_t init)
{
/* Set clock */
sdio_setbaud(sdiox, 199);
sdiox[SDCON] = 0;
hal_udelay(20);
sdiox[SDCON] |= BIT(0); /* SD control enable */
sdiox[SDCON] |= BIT(3); /* Keep clock output */
sdiox[SDCON] |= BIT(5); /* Data interrupt enable */
hal_mdelay(40);
}
/**
* @brief Check if SDIO command is finished.
*
* @param sdiox
* @return true is finished
* @return false
*/
bool sdio_check_finish(hal_sfr_t sdiox)
{
if (sdiox[SDCON] & BIT(12)) {
sdiox[SDCPND] = BIT(12);
return true;
}
return false;
}
/**
* @brief Check if SDIO has a response.
*
* @param sdiox
* @return true Have a response.
* @return false No response.
*/
bool sdio_check_rsp(hal_sfr_t sdiox)
{
return !(sdiox[SDCON] & BIT(15));
}
bool sdio_send_cmd(hal_sfr_t sdiox, uint32_t cmd, uint32_t arg)
{
uint32_t time_out = (cmd & CBUSY) ? RSP_BUSY_TIMEOUT : RSP_TIMEOUT;
sdiox[SDCMD] = cmd;
sdiox[SDARG3] = arg;
while (sdio_check_finish(sdiox) == false) {
if (--time_out == 0) {
HAL_LOG("cmd time out\n");
// card.abend = 1;
return false;
}
}
return sdio_check_rsp(sdiox);
}
uint8_t sdio_get_cmd_rsp(hal_sfr_t sdiox)
{
return -1;
}
uint32_t sdio_get_rsp(hal_sfr_t sdiox, uint32_t rsp)
{
return -1;
}
void sdio_read_kick(hal_sfr_t sdiox, void* buf)
{}
void sdio_write_kick(hal_sfr_t sdiox, void* buf)
{}
bool sdio_isbusy(hal_sfr_t sdiox)
{
return false;
}
void sdmmc_go_idle_state(hal_sfr_t sdiox)
{
// hal_sfr_t sdiox = hsd->instance;
sdio_send_cmd(sdiox, 0x00 | RSP_NO, 0);
}
void sdmmc_send_if_cond(hal_sfr_t sdiox)
{
// hal_sfr_t sdiox = hsd->instance;
sdio_send_cmd(sdiox, 0x08 | RSP_7, SDMMC_CHECK_PATTERM);
}
/************************* HAL ************************************/
static void sd_poweron(sd_handle_t hsd)
{
sdmmc_go_idle_state(hsd->instance);
sdmmc_send_if_cond(hsd->instance);
if (hsd->instance[SDCMD] == 0x08) {
hsd->sdcard.type = CARD_V2;
HAL_LOG("SD 2.0\n");
}
}
void hal_sd_initcard(sd_handle_t hsd)
{
struct sdio_init init = {0};
hal_sfr_t sdiox = hsd->instance;
sdio_init(sdiox, &init);
sd_poweron(hsd);
}
WEAK void hal_sd_mspinit(sd_handle_t hsd)
{
}
hal_error_t hal_sd_init(sd_handle_t hsd)
{
if (hsd == HAL_NULL) {
return -HAL_ERROR;
}
hal_sd_mspinit(hsd);
hal_sd_initcard(hsd);
return -HAL_ERROR;
}
void hal_sd_deinit(uint32_t sdx)
{
}
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1_hal.h"
#ifdef HAL_UART_MODULE_ENABLED
enum
{
UARTxCON = 0x00,
UARTxCPND,
UARTxBAUD,
UARTxDATA,
};
/**
* @brief Set the UART baud rate.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @param baud Baud rate.
*/
void hal_uart_setbaud(hal_sfr_t uartx, uint32_t baud)
{
uint32_t baud_cfg;
uartx[UARTxCON] |= UART_CLK_SRC1;
baud_cfg = (26000000/2)/baud; //1.5M
uartx[UARTxBAUD] = (baud_cfg << 16) | baud_cfg;
}
/**
* @brief Initialize the UART mode.
*
* @param huart UART handle.
* @return hal_error_t
*/
hal_error_t hal_uart_init(struct uart_handle *huart)
{
if (huart == HAL_NULL) {
return -HAL_ERROR;
}
hal_uart_mspinit(huart);
uart_config_all(huart);
return HAL_EOK;
}
/**
* @brief DeInitialize the UART peripheral.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
*/
void hal_uart_deinit(hal_sfr_t uartx)
{
uartx[UARTxCON] = 0;
}
/**
* @brief Initialize the UART MSP.
*
* @param huart UART handle.
*/
WEAK void HAL_UART_MspInit(struct uart_handle *huart)
{}
/**
* @brief Control the UART peripheral.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @param cntl
* @arg UART_MODULE_ENABLE
* @arg UART_BIT9_ENABLE
* @arg UART_RXIT_ENABLE
* @arg UART_TXIT_ENABLE
* @arg UART_SB2_ENABLE
* @arg UART_CLK_SRC1
* @arg UART_1LINE_ENABLE
* @arg UART_RX_ENABLE
* @param param
* @arg HAL_DISABLE
* @arg HAL_ENABLE
*/
void hal_uart_control(hal_sfr_t uartx, uint32_t cntl, uint32_t param)
{
if (param == HAL_ENABLE) {
uartx[UARTxCON] |= (cntl);
} else {
uartx[UARTxCON] &= ~(cntl);
}
}
/**
* @brief Send a character
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @param data The characters that need to be sent
*/
void hal_uart_write(hal_sfr_t uartx, uint8_t data)
{
uartx[UARTxDATA] = data;
}
/**
* @brief Receive a character.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @return uint8_t Received character.
*/
uint8_t hal_uart_read(hal_sfr_t uartx)
{
return (uartx[UARTxCON] & 0xff);
}
/**
* @brief Get the UART flag.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @param flag
* @arg UART_FLAG_RXPND
* @arg UART_FLAG_TXPND
* @return uint32_t
*/
uint32_t hal_uart_getflag(hal_sfr_t uartx, uint32_t flag)
{
uint32_t ret = uartx[UARTxCON] & flag;
return ret;
}
/**
* @brief Clear the UART flag.
*
* @param uartx This parameter can be UARTxN where x can be (0.2).
* @param flag
* @arg UART_FLAG_RXPND
* @arg UART_FLAG_TXPND
*/
void hal_uart_clrflag(hal_sfr_t uartx, uint32_t flag)
{
uartx[UARTxCON] |= flag;
}
/**
* @brief Configure the UART peripheral.
*
* @param huart UART handle.
*/
void uart_config_all(struct uart_handle *huart)
{
hal_uart_control(huart->instance, UART_MODULE_ENABLE, HAL_DISABLE);
CLKCON1 |= BIT(14);
if (huart->instance == UART0_BASE) {
hal_rcu_periph_clk_enable(RCU_UART0);
} else if (huart->instance == UART1_BASE) {
hal_rcu_periph_clk_enable(RCU_UART1);
} else {
return; /* Not support! */
}
hal_uart_setbaud(huart->instance, huart->init.baud);
if (huart->init.mode != UART_MODE_TX) {
hal_uart_control(huart->instance, UART_RX_ENABLE, HAL_ENABLE);
}
hal_uart_control(huart->instance, UART_MODULE_ENABLE, HAL_ENABLE);
}
#endif

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#-*- encoding: utf-8 -*-
#---------------------------------------------------------------------------------
# @File: Sconscript for package
# @Author: Rice
# @Date: 2020-07-14 16:57:00(v0.0.1)
#
# @LICENSE: GPLv3: https://github.com/rtpkgs/buildpkg/blob/master/LICENSE.
#
#---------------------------------------------------------------------------------
import os
from building import *
Import('RTT_ROOT')
Import('rtconfig')
#---------------------------------------------------------------------------------
# Package configuration
#---------------------------------------------------------------------------------
PKGNAME = "bmsis"
VERSION = "v1.0.0"
DEPENDS = [""]
#DEPENDS = ["PKG_USING_RW007"]
#---------------------------------------------------------------------------------
# Compile the configuration
#
# SOURCES: Need to compile c and c++ source, auto search when SOURCES is empty
#
# LOCAL_CPPPATH: Local file path (.h/.c/.cpp)
# LOCAL_CCFLAGS: Local compilation parameter
# LOCAL_ASFLAGS: Local assembly parameters
#
# CPPPATH: Global file path (.h/.c/.cpp), auto search when LOCAL_CPPPATH/CPPPATH
# is empty # no pass!!!
# CCFLAGS: Global compilation parameter
# ASFLAGS: Global assembly parameters
#
# CPPDEFINES: Global macro definition
# LOCAL_CPPDEFINES: Local macro definition
#
# LIBS: Specify the static library that need to be linked
# LIBPATH: Specify the search directory for the library file (.lib/.a)
#
# LINKFLAGS: Link options
#---------------------------------------------------------------------------------
SOURCES = Glob("./source/*.c")
SOURCES += Glob("./source/*.S")
LOCAL_CPPPATH = []
LOCAL_CCFLAGS = ""
LOCAL_ASFLAGS = ""
CPPPATH = [GetCurrentDir(), os.path.join(GetCurrentDir(), 'include')]
CCFLAGS = ""
ASFLAGS = ""
CPPDEFINES = []
LOCAL_CPPDEFINES = []
LIBS = []
LIBPATH = []
LINKFLAGS = ""
SOURCES_IGNORE = []
CPPPATH_IGNORE = []
#---------------------------------------------------------------------------------
# Main target
#---------------------------------------------------------------------------------
objs = DefineGroup(name = PKGNAME, src = SOURCES, depend = DEPENDS,
CPPPATH = CPPPATH,
CCFLAGS = CCFLAGS,
ASFLAGS = ASFLAGS,
LOCAL_CPPPATH = LOCAL_CPPPATH,
LOCAL_CCFLAGS = LOCAL_CCFLAGS,
LOCAL_ASFLAGS = LOCAL_ASFLAGS,
CPPDEFINES = CPPDEFINES,
LOCAL_CPPDEFINES = LOCAL_CPPDEFINES,
LIBS = LIBS,
LIBPATH = LIBPATH,
LINKFLAGS = LINKFLAGS)
Return("objs")
#---------------------------------------------------------------------------------
# End
#---------------------------------------------------------------------------------

322
bsp/bluetrum/libraries/hal_libraries/bmsis/include/ab32vg1.h Normal file
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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_H__
#define AB32VG1_H__
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "system_ab32vgx.h"
/*!< Interrupt Number Definition */
typedef enum
{
IRQ_SW_VECTOR = 2,
IRQ_TMR0_VECTOR = 3,
IRQ_TMR1_VECTOR = 4,
IRQ_TMR2_4_5_VECTOR = 5, /*!< Timer 2, 4 and 5 Interrupt */
IRQ_IRRX_VECTOR = 6, /*!< Timer 3 and IR receiver Interrupt */
IRQ_USB_VECTOR = 7,
IRQ_SD_VECTOR = 8,
IRQ_AUBUF0_1_VECTOR = 9, /*!< Audio buffer 0 and 1 Interrupt */
IRQ_SDADC_VECTOR = 10,
IRQ_AUDEC_VECTOR = 11, /*!< Audio codec, SBC encode and AEC FFT Interrupt */
IRQ_SRC_VECTOR = 12, /*!< SRC, PLC and CVSD Interrupt */
IRQ_FM_SPDIF_VECTOR = 13, /*!< FM TX, RX and SPDIF RX Interrupt */
IRQ_UART0_2_VECTOR = 14, /*!< UART 0 to 2 Interrupt */
IRQ_HSUART_VECTOR = 15,
IRQ_RTC_VECTOR = 16, /*!< RTC, LVD and WDT Interrupt */
IRQ_I2S_VECTOR = 17,
IRQ_TOTAL_NUM = 23,
} irq_type;
#endif // __ASSEMBLER__
#ifndef __ASSEMBLER__
#define SFR_RO *(volatile unsigned long const *)
#define SFR_WO *(volatile unsigned long*)
#define SFR_RW *(volatile unsigned long*)
#define SWINT() asm(".long 0xb0030057")
#define EEBREAKINT() asm(".long 0xb0040057")
#else
#define SFR_RO
#define SFR_WO
#define SFR_RW
#define SWINT .long 0xb0030057
#define EEBREAKINT .long 0xb0040057
#endif
#define SFR_BASE 0x00000000
#define SFR0_BASE (0x00000000 + 0x000)
#define SFR1_BASE (0x00000000 + 0x100)
#define SFR2_BASE (0x00000000 + 0x200)
#define SFR3_BASE (0x00000000 + 0x300)
#define SFR4_BASE (0x00000000 + 0x400)
#define SFR5_BASE (0x00000000 + 0x500)
#define SFR6_BASE (0x00000000 + 0x600)
#define SFR7_BASE (0x00000000 + 0x700)
#define SFR8_BASE (0x00000000 + 0x800)
#define SFR9_BASE (0x00000000 + 0x900)
#define SFR10_BASE (0x00000000 + 0xa00)
#define SFR11_BASE (0x00000000 + 0xb00)
#define SFR12_BASE (0x00000000 + 0xc00)
#define SFR13_BASE (0x00000000 + 0xd00)
#define SFR14_BASE (0x00000000 + 0xe00)
#define SFR15_BASE (0x00000000 + 0xf00)
#define RTC_WR 0x200
#define RTC_RD 0x100
#define RTCCNT_CMD 0x01
#define RTCALM_CMD 0x02
#define RTCRAM_CMD 0x03
#define RTCCON0_CMD 0x04
#define RTCCON1_CMD 0x05
#define RTCCON2_CMD 0x06
#define RTCCON3_CMD 0x07
#define RTCCON4_CMD 0x08
#define RTCCON5_CMD 0x09
#define RTCCON6_CMD 0x0a
#define RTCCON7_CMD 0x0b
#define RTCCON8_CMD 0x0c
#define RTCCON9_CMD 0x0d
#define RTCCON10_CMD 0x0e
#define FUNCMCON0 SFR_RW (SFR0_BASE + 0x07*4)
#define FUNCMCON1 SFR_RW (SFR0_BASE + 0x08*4)
#define FUNCMCON2 SFR_RW (SFR0_BASE + 0x09*4)
#define UART0CON SFR_RW (SFR0_BASE + 0x10*4)
#define UART0CPND SFR_WO (SFR0_BASE + 0x11*4)
#define UART0BAUD SFR_RW (SFR0_BASE + 0x12*4)
#define UART0DATA SFR_RW (SFR0_BASE + 0x13*4)
#define TMR0CON SFR_RW (SFR0_BASE + 0x14*4)
#define TMR0CPND SFR_RW (SFR0_BASE + 0x15*4)
#define TMR0CNT SFR_RW (SFR0_BASE + 0x16*4)
#define TMR0PR SFR_RW (SFR0_BASE + 0x17*4)
#define CLKCON0 SFR_RW (SFR0_BASE + 0x19*4)
#define WDTCON SFR_RW (SFR0_BASE + 0x1a*4)
#define RTCCON SFR_RW (SFR0_BASE + 0x1b*4)
#define RTCDAT SFR_RW (SFR0_BASE + 0x1c*4)
#define CLKCON1 SFR_RW (SFR0_BASE + 0x1d*4)
#define RTCCPND SFR_WO (SFR0_BASE + 0x1e*4)
#define SD0CON SFR_RW (SFR0_BASE + 0x20*4)
#define SD0CPND SFR_WO (SFR0_BASE + 0x21*4)
#define SD0BAUD SFR_RW (SFR0_BASE + 0x22*4)
#define SD0CMD SFR_RW (SFR0_BASE + 0x23*4)
#define SD0ARG3 SFR_RW (SFR0_BASE + 0x24*4)
#define SD0ARG2 SFR_RW (SFR0_BASE + 0x25*4)
#define SD0ARG1 SFR_RW (SFR0_BASE + 0x26*4)
#define SD0ARG0 SFR_RW (SFR0_BASE + 0x27*4)
#define SD0DMAADR SFR_RW (SFR0_BASE + 0x28*4)
#define SD0DMACNT SFR_RW (SFR0_BASE + 0x29*4)
#define SPI0CON SFR_RW (SFR0_BASE + 0x2a*4)
#define SPI0BUF SFR_RW (SFR0_BASE + 0x2b*4)
#define SPI0BAUD SFR_RW (SFR0_BASE + 0x2c*4)
#define SPI0CPND SFR_RW (SFR0_BASE + 0x2d*4)
#define SPI0DMACNT SFR_RW (SFR0_BASE + 0x2e*4)
#define SPI0DMAADR SFR_RW (SFR0_BASE + 0x2f*4)
#define UART1CON SFR_RW (SFR0_BASE + 0x30*4)
#define UART1CPND SFR_WO (SFR0_BASE + 0x31*4)
#define UART1BAUD SFR_RW (SFR0_BASE + 0x32*4)
#define UART1DATA SFR_RW (SFR0_BASE + 0x33*4)
#define TMR1CON SFR_RW (SFR0_BASE + 0x35*4)
#define TMR1CPND SFR_RW (SFR0_BASE + 0x36*4)
#define TMR1CNT SFR_RW (SFR0_BASE + 0x37*4)
#define TMR1PR SFR_RW (SFR0_BASE + 0x38*4)
#define TMR2CON SFR_RW (SFR0_BASE + 0x3a*4)
#define TMR2CPND SFR_RW (SFR0_BASE + 0x3b*4)
#define TMR2CNT SFR_RW (SFR0_BASE + 0x3c*4)
#define TMR2PR SFR_RW (SFR0_BASE + 0x3d*4)
#define DACDIGCON0 SFR_RW (SFR1_BASE + 0x10*4)
#define DACVOLCON SFR_RW (SFR1_BASE + 0x11*4)
#define USBCON0 SFR_RW (SFR3_BASE + 0x00*4)
#define USBCON1 SFR_RW (SFR3_BASE + 0x01*4)
#define USBCON2 SFR_RW (SFR3_BASE + 0x02*4)
#define PWRCON0 SFR_RW (SFR3_BASE + 0x1d*4)
#define LVDCON SFR_RW (SFR3_BASE + 0x1e*4)
#define CHAGCON SFR_RW (SFR3_BASE + 0x1f*4)
#define PLL0DIV SFR_RW (SFR3_BASE + 0x23*4)
#define PLL1DIV SFR_RW (SFR3_BASE + 0x24*4)
#define PLL0CON SFR_RW (SFR3_BASE + 0x26*4)
#define PLL1CON SFR_RW (SFR3_BASE + 0x27*4)
#define XO26MCON SFR_RW (SFR3_BASE + 0x29*4)
#define CLKCON2 SFR_RW (SFR3_BASE + 0x2a*4)
#define CLKGAT0 SFR_RW (SFR3_BASE + 0x2c*4)
#define LPMCON SFR_RW (SFR3_BASE + 0x2d*4)
#define MEMCON SFR_RW (SFR3_BASE + 0x2e*4)
#define CLKCON3 SFR_RW (SFR3_BASE + 0x2f*4)
#define CLKGAT1 SFR_RW (SFR3_BASE + 0x3f*4)
#define PWMCON SFR_RW (SFR4_BASE + 0x20*4)
#define PWMPRCON SFR_RW (SFR4_BASE + 0x21*4)
#define PWM01DUTY SFR_RW (SFR4_BASE + 0x22*4)
#define PWM23DUTY SFR_RW (SFR4_BASE + 0x23*4)
#define PWMCYCNUM SFR_RW (SFR4_BASE + 0x24*4)
#define PWMSTEP SFR_RW (SFR4_BASE + 0x25*4)
//0x00~0x1f reserve for CPU
#define PICCONCLR SFR_WO (SFR5_BASE + 0x0c*4)
#define PICCONSET SFR_WO (SFR5_BASE + 0x0d*4)
#define PICENCLR SFR_WO (SFR5_BASE + 0x0e*4)
#define PICENSET SFR_WO (SFR5_BASE + 0x0f*4)
#define PICCON SFR_RW (SFR5_BASE + 0x10*4)
#define PICEN SFR_RW (SFR5_BASE + 0x11*4)
#define PICPR SFR_RW (SFR5_BASE + 0x12*4)
#define PICADR SFR_RW (SFR5_BASE + 0x13*4)
#define PICPND SFR_RW (SFR5_BASE + 0x14*4)
#define EPC SFR_RW (SFR5_BASE + 0x1f*4)
#define SADCDAT0 SFR_RO (SFR5_BASE + 0x20*4)
#define SADCDAT1 SFR_RO (SFR5_BASE + 0x21*4)
#define SADCDAT2 SFR_RO (SFR5_BASE + 0x22*4)
#define SADCDAT3 SFR_RO (SFR5_BASE + 0x23*4)
#define SADCDAT4 SFR_RO (SFR5_BASE + 0x24*4)
#define SADCDAT5 SFR_RO (SFR5_BASE + 0x25*4)
#define SADCDAT6 SFR_RO (SFR5_BASE + 0x26*4)
#define SADCDAT7 SFR_RO (SFR5_BASE + 0x27*4)
#define SADCDAT8 SFR_RO (SFR5_BASE + 0x28*4)
#define SADCDAT9 SFR_RO (SFR5_BASE + 0x29*4)
#define SADCDAT10 SFR_RO (SFR5_BASE + 0x2a*4)
#define SADCDAT11 SFR_RO (SFR5_BASE + 0x2b*4)
#define SADCDAT12 SFR_RO (SFR5_BASE + 0x2c*4)
#define SADCDAT13 SFR_RO (SFR5_BASE + 0x2d*4)
#define SADCDAT14 SFR_RO (SFR5_BASE + 0x2e*4)
#define SADCDAT15 SFR_RO (SFR5_BASE + 0x2f*4)
#define AUANGCON1 SFR_RW (SFR1_BASE + 0x3d*4)
#define WKUPCON SFR_WO (SFR5_BASE + 0x39*4)
#define WKUPEDG SFR_WO (SFR5_BASE + 0x3a*4)
#define WKUPCPND SFR_WO (SFR5_BASE + 0x3b*4)
//------------------------- SFR Group6 ---------------------------------------//
#define GPIOASET SFR_RW (SFR6_BASE + 0x00*4)
#define GPIOACLR SFR_RW (SFR6_BASE + 0x01*4)
#define GPIOA SFR_RW (SFR6_BASE + 0x02*4)
#define GPIOADIR SFR_RW (SFR6_BASE + 0x03*4)
#define GPIOADE SFR_RW (SFR6_BASE + 0x04*4)
#define GPIOAFEN SFR_RW (SFR6_BASE + 0x05*4)
#define GPIOADRV SFR_RW (SFR6_BASE + 0x06*4)
#define GPIOAPU SFR_RW (SFR6_BASE + 0x07*4)
#define GPIOAPD SFR_RW (SFR6_BASE + 0x08*4)
#define GPIOAPU200K SFR_RW (SFR6_BASE + 0x09*4)
#define GPIOAPD200K SFR_RW (SFR6_BASE + 0x0a*4)
#define GPIOAPU300 SFR_RW (SFR6_BASE + 0x0b*4)
#define GPIOAPD300 SFR_RW (SFR6_BASE + 0x0c*4)
#define GPIOBSET SFR_RW (SFR6_BASE + 0x10*4)
#define GPIOBCLR SFR_RW (SFR6_BASE + 0x11*4)
#define GPIOB SFR_RW (SFR6_BASE + 0x12*4)
#define GPIOBDIR SFR_RW (SFR6_BASE + 0x13*4)
#define GPIOBDE SFR_RW (SFR6_BASE + 0x14*4)
#define GPIOBFEN SFR_RW (SFR6_BASE + 0x15*4)
#define GPIOBDRV SFR_RW (SFR6_BASE + 0x16*4)
#define GPIOBPU SFR_RW (SFR6_BASE + 0x17*4)
#define GPIOBPD SFR_RW (SFR6_BASE + 0x18*4)
#define GPIOBPU200K SFR_RW (SFR6_BASE + 0x19*4)
#define GPIOBPD200K SFR_RW (SFR6_BASE + 0x1a*4)
#define GPIOBPU300 SFR_RW (SFR6_BASE + 0x1b*4)
#define GPIOBPD300 SFR_RW (SFR6_BASE + 0x1c*4)
#define GPIOESET SFR_RW (SFR6_BASE + 0x20*4)
#define GPIOECLR SFR_RW (SFR6_BASE + 0x21*4)
#define GPIOE SFR_RW (SFR6_BASE + 0x22*4)
#define GPIOEDIR SFR_RW (SFR6_BASE + 0x23*4)
#define GPIOEDE SFR_RW (SFR6_BASE + 0x24*4)
#define GPIOEFEN SFR_RW (SFR6_BASE + 0x25*4)
#define GPIOEDRV SFR_RW (SFR6_BASE + 0x26*4)
#define GPIOEPU SFR_RW (SFR6_BASE + 0x27*4)
#define GPIOEPD SFR_RW (SFR6_BASE + 0x28*4)
#define GPIOEPU200K SFR_RW (SFR6_BASE + 0x29*4)
#define GPIOEPD200K SFR_RW (SFR6_BASE + 0x2a*4)
#define GPIOEPU300 SFR_RW (SFR6_BASE + 0x2b*4)
#define GPIOEPD300 SFR_RW (SFR6_BASE + 0x2c*4)
#define GPIOFSET SFR_RW (SFR6_BASE + 0x30*4)
#define GPIOFCLR SFR_RW (SFR6_BASE + 0x31*4)
#define GPIOF SFR_RW (SFR6_BASE + 0x32*4)
#define GPIOFDIR SFR_RW (SFR6_BASE + 0x33*4)
#define GPIOFDE SFR_RW (SFR6_BASE + 0x34*4)
#define GPIOFFEN SFR_RW (SFR6_BASE + 0x35*4)
#define GPIOFDRV SFR_RW (SFR6_BASE + 0x36*4)
#define GPIOFPU SFR_RW (SFR6_BASE + 0x37*4)
#define GPIOFPD SFR_RW (SFR6_BASE + 0x38*4)
#define GPIOFPU200K SFR_RW (SFR6_BASE + 0x39*4)
#define GPIOFPD200K SFR_RW (SFR6_BASE + 0x3a*4)
#define GPIOFPU300 SFR_RW (SFR6_BASE + 0x3b*4)
#define GPIOFPD300 SFR_RW (SFR6_BASE + 0x3c*4)
#define GPIOGSET SFR_RW (SFR7_BASE + 0x00*4)
#define GPIOGCLR SFR_RW (SFR7_BASE + 0x01*4)
#define GPIOG SFR_RW (SFR7_BASE + 0x02*4)
#define GPIOGDIR SFR_RW (SFR7_BASE + 0x03*4)
#define GPIOGDE SFR_RW (SFR7_BASE + 0x04*4)
#define GPIOGFEN SFR_RW (SFR7_BASE + 0x05*4)
#define GPIOGDRV SFR_RW (SFR7_BASE + 0x06*4)
#define GPIOGPU SFR_RW (SFR7_BASE + 0x07*4)
#define GPIOGPD SFR_RW (SFR7_BASE + 0x08*4)
#define GPIOGPU200K SFR_RW (SFR7_BASE + 0x09*4)
#define GPIOGPD200K SFR_RW (SFR7_BASE + 0x0a*4)
#define GPIOGPU300 SFR_RW (SFR7_BASE + 0x0b*4)
#define GPIOGPD300 SFR_RW (SFR7_BASE + 0x0c*4)
#define IRRXCON SFR_RW (SFR8_BASE + 0x1b*4)
#define IRRXDAT SFR_RW (SFR8_BASE + 0x1c*4)
#define IRRXCPND SFR_WO (SFR8_BASE + 0x1d*4)
#define IRRXERR0 SFR_WO (SFR8_BASE + 0x1e*4)
#define IRRXERR1 SFR_WO (SFR8_BASE + 0x1f*4)
#define USERKEY SFR_RW (SFR8_BASE + 0x20*4)
#define PROTCON1 SFR_RW (SFR8_BASE + 0x21*4)
#define FMAMFDTCON SFR_WO (SFR8_BASE + 0x29*4)
#define TMR3CON SFR_RW (SFR9_BASE + 0x00*4)
#define TMR3CPND SFR_WO (SFR9_BASE + 0x01*4)
#define TMR3CNT SFR_RW (SFR9_BASE + 0x02*4)
#define TMR3PR SFR_RW (SFR9_BASE + 0x03*4)
#define TMR3CPT SFR_RO (SFR9_BASE + 0x04*4)
#define TMR3DUTY0 SFR_WO (SFR9_BASE + 0x05*4)
#define TMR3DUTY1 SFR_WO (SFR9_BASE + 0x06*4)
#define TMR3DUTY2 SFR_WO (SFR9_BASE + 0x07*4)
#define TMR4CON SFR_RW (SFR9_BASE + 0x08*4)
#define TMR4CPND SFR_WO (SFR9_BASE + 0x09*4)
#define TMR4CNT SFR_RW (SFR9_BASE + 0x0a*4)
#define TMR4PR SFR_RW (SFR9_BASE + 0x0b*4)
#define TMR4CPT SFR_RO (SFR9_BASE + 0x0c*4)
#define TMR4DUTY0 SFR_WO (SFR9_BASE + 0x0d*4)
#define TMR4DUTY1 SFR_WO (SFR9_BASE + 0x0e*4)
#define TMR4DUTY2 SFR_WO (SFR9_BASE + 0x0f*4)
#define TMR5CON SFR_RW (SFR9_BASE + 0x10*4)
#define TMR5CPND SFR_WO (SFR9_BASE + 0x11*4)
#define TMR5CNT SFR_RW (SFR9_BASE + 0x12*4)
#define TMR5PR SFR_RW (SFR9_BASE + 0x13*4)
#define TMR5CPT SFR_RO (SFR9_BASE + 0x14*4)
#define TMR5DUTY0 SFR_WO (SFR9_BASE + 0x15*4)
#define TMR5DUTY1 SFR_WO (SFR9_BASE + 0x16*4)
#define TMR5DUTY2 SFR_WO (SFR9_BASE + 0x17*4)
#define UART2CON SFR_RW (SFR9_BASE + 0x18*4)
#define UART2CPND SFR_WO (SFR9_BASE + 0x19*4)
#define UART2BAUD SFR_RW (SFR9_BASE + 0x1a*4)
#define UART2DATA SFR_RW (SFR9_BASE + 0x1b*4)
#define PORTINTEDG SFR_RW (SFR9_BASE + 0x1e*4)
#define PORTINTEN SFR_RW (SFR9_BASE + 0x1f*4)
#define SPI1CON SFR_RW (SFR9_BASE + 0x20*4)
#define SPI1BUF SFR_RW (SFR9_BASE + 0x21*4)
#define SPI1BAUD SFR_RW (SFR9_BASE + 0x22*4)
#define SPI1CPND SFR_RW (SFR9_BASE + 0x23*4)
#define SPI1DMACNT SFR_RW (SFR9_BASE + 0x24*4)
#define SPI1DMAADR SFR_RW (SFR9_BASE + 0x25*4)
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef PROUGENGX_H__
#define PROUGENGX_H__
#include "ab32vg1.h"
#ifndef UINT_MAX
#define UINT_MAX 0xffffffff
#endif // UINT_MAX
#define BIT(n) (1ul << (n))
#define AT(x) __attribute__((section(#x)))
#define ALIGNED(n) __attribute__((aligned(n)))
#define DMA_ADR(x) ((uint32_t)x)
#define ALWAYS_INLINE __attribute__((always_inline)) inline
#define NO_INLINE __attribute__((noinline))
#define WEAK __attribute__((weak))
#define PACKED __attribute__((packed))
// #define WDT_CLR() WDTCON = 0xa
// #define WDT_EN() WDTCON = 0x110
// #define WDT_DIS() WDTCON = 0xaa0
// #define WDT_RST() WDTCON = 0xa000110; while (1)
// #define WDT_RST_DELAY() WDTCON = 0xa100110; while (1)
#define BYTE0(n) ((unsigned char)(n))
#define BYTE1(n) ((unsigned char)((n)>>8))
#define BYTE2(n) ((unsigned char)((n)>>16))
#define BYTE3(n) ((unsigned char)((n)>>24))
#define GET_LE16(ptr) (uint16_t)(*(uint16_t*)(uint8_t*)(ptr))
#define GET_LE32(ptr) (uint32_t)(*(uint32_t*)(uint8_t*)(ptr))
#define PUT_LE16(ptr, val) *(uint16_t*)(uint8_t*)(ptr) = (uint16_t)(val)
#define PUT_LE32(ptr, val) *(uint32_t*)(uint8_t*)(ptr) = (uint32_t)(val)
#define GET_BE16(ptr) get_be16(ptr)
#define GET_BE32(ptr) get_be32(ptr)
#define PUT_BE16(ptr, val) put_be16(ptr, val)
#define PUT_BE32(ptr, val) put_be32(ptr, val)
#include "ab32vg1_hal.h"
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef BMSIS_GCC_H__
#define BMSIS_GCC_H__
/* ignore some GCC warnings */
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef SYSTEM_PROUGENGX_H__
#define SYSTEM_PROUGENGX_H__
//sys_clk configure list
enum {
//select pll0out, PLL0 240M
PLL0DIV_12M,
PLL0DIV_24M,
PLL0DIV_30M,
PLL0DIV_48M,
PLL0DIV_60M,
PLL0DIV_80M,
PLL0DIV_120M,
//select osc26m
OSCDIV_2M,
OSCDIV_13M,
OSCDIV_26M,
//select adpll
};
//需要与sysclk_sel_tbl对应, 按时钟频率升序
enum {
SYSCLK_2M,
SYSCLK_12M,
SYSCLK_13M,
SYSCLK_24M,
SYSCLK_26M,
SYSCLK_30M,
SYSCLK_48M,
SYSCLK_60M,
SYSCLK_80M,
SYSCLK_120M,
};
extern uint32_t get_sysclk_nhz(void);
extern void system_init(void);
extern void set_sysclk(uint32_t sys_clk);
#endif

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vg1.h"
.global _start
.section .reset, "ax"
_start:
//load comm
la a0, __comm_vma
la a1, __comm_lma
la a2, __comm_size
/* memcpy start */
//先按32 BYTE一个循环来copy
mv t0, a0 //备份dst
srli t1, a2, 5 //长度除32的商
slli t1, t1, 5
add t1, a0, t1 //t1存放对齐的结束地址
_memcpy_loop1: //8 WORDS every cycle
lw a2, 0(a1)
lw a3, 4(a1)
lw a4, 8(a1)
lw a5, 12(a1)
sw a2, 0(a0)
sw a3, 4(a0)
sw a4, 8(a0)
sw a5, 12(a0)
lw a2, 16(a1)
lw a3, 20(a1)
lw a4, 24(a1)
lw a5, 28(a1)
sw a2, 16(a0)
sw a3, 20(a0)
sw a4, 24(a0)
sw a5, 28(a0)
addi a0, a0, 32
addi a1, a1, 32
blt a0, t1, _memcpy_loop1
mv a0, t0 //返回dst
/* memcpy end */
la a0, __irq_stack_start //Stack清成0x23
li a1, 0x23
la a2, __irq_stack_size
call memset
la ra, __irq_stack
lui a5, 0x1
sw zero, -1920(a5)
sw zero, -1916(a5)
//clear bss
la a0, __bss_start
li a1, 0
la a2, __bss_size
call memset
la a0, __comm_vma
sw a0, PICADR(zero)
call entry
// la ra, __exception
// jr ra
.section .vector, "ax"
// .org 0x10
//__exception:
// li sp, 0x10600 //出错后，不破坏错误点的堆栈数据
// jal exception_isr
// 1: j 1b
// mret
.org 0x40
jal x0, low_prio_irq
mret
.global cpu_irq_comm
.section .com_text.irq
cpu_irq_comm:
la a5, __irq_stack
mv sp, a5
j cpu_irq_comm_do
ret

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/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ab32vgx.h"
#ifndef ALIGN
#define ALIGN(n) __attribute__((aligned(n)))
#endif // ALIGN
typedef struct _sys_t {
uint8_t cnt_1us; //delay 1us cnt
uint8_t main_start; //Main是否已启动
uint8_t clk_sel; //system clock select
uint8_t sys_clk;
// uint8_t aupll_type; //区分AUPLL的频率
uint16_t rand_seed;
uint32_t uart0baud; //UART0BAUD
} sys_t;
AT(.text.sys_clk.table)
const uint8_t sysclk_sel_tbl[] = {
OSCDIV_2M, //SYS_2M
PLL0DIV_12M, //SYS_12M
OSCDIV_13M, //SYS_13M
PLL0DIV_24M, //SYS_24M
OSCDIV_26M, //SYS_26M
PLL0DIV_30M, //SYS_30M
PLL0DIV_48M, //SYS_48M
PLL0DIV_60M, //SYS_60M
PLL0DIV_80M, //SYS_80M
PLL0DIV_120M, //SYS_120M
};
AT(.text.sys_clk.table)
const uint8_t sysclk_index[] = {
2,
12,
13,
24,
26,
30,
48,
60,
80,
120,
};
sys_t sys = {0};
void my_printf(const char *format, ...);
AT(.com_text.delay)
static void delay_us(uint16_t nus)
{
int i;
for (i = 0; i < nus*10; i++) {
asm("nop");
}
}
AT(.text.sys_clk)
uint8_t get_clksel_val(uint8_t val)
{
return sysclk_sel_tbl[val];
}
AT(.text.sys_clk)
uint8_t get_cur_sysclk(void)
{
return sys.sys_clk;
}
uint32_t get_sysclk_nhz(void)
{
return sysclk_index[sys.sys_clk] * 1000000;
}
////AT(.com_text.set_flash_safety)
//static ALWAYS_INLINE void set_flash_safety(uint32_t sys_clk)
//{
// SPI0CON |= BIT(10);
// if (sys_clk > SYS_48M) {
// SPI0CON |= BIT(3); //2bit mode
// spiflash_init(0x3b, 1); //dummy = 1
// } else {
// SPI0CON &= ~BIT(3); //2bit mode
// spiflash_init(0x0b, 1); //dummy = 0
// }
//}
AT(.text.sys_clk)
uint8_t get_sd_rate(void)
{
return 0; //unit: M
}
AT(.text.sys_clk)
uint8_t set_sd_baud(uint8_t sd_rate)
{
uint8_t sd0baud=0;
uint8_t sys_clk=0;
if(sd_rate > 14){//不支持超过14M
return 0;
}
if (sys.sys_clk <= SYSCLK_26M) {
sys_clk=26;
}else if (sys.sys_clk == SYSCLK_48M) {
sys_clk=48;
} else if (sys.sys_clk <= SYSCLK_60M) {
sys_clk=52;
} else if (sys.sys_clk == SYSCLK_80M) {
sys_clk=80;
} else if (sys.sys_clk <= SYSCLK_120M) {
sys_clk=120;
}
sd0baud = sys_clk/sd_rate-1;
if(sys_clk%sd_rate*2/sd_rate) {
sd0baud=sd0baud+1;
}
return sd0baud;
}
void update_sd0baud(void)
{
if (!(SD0CON & BIT(0))) {
return;
}
uint8_t sd_rate=get_sd_rate();
if(sd_rate){
uint8_t sd0baud=set_sd_baud(sd_rate);
if(sd0baud){
SD0BAUD=sd0baud;
return ;
}
}
if (sys.sys_clk <= SYSCLK_30M) {
SD0BAUD = 1;
} else if (sys.sys_clk <= SYSCLK_60M) {
SD0BAUD = 3;
} else if (sys.sys_clk == SYSCLK_80M) {
SD0BAUD = 5;
} else if (sys.sys_clk <= SYSCLK_120M) {
SD0BAUD = 9;
}
}
AT(.text.sys_clk)
uint8_t sysclk_update_baud(uint8_t baud)
{
uint8_t sd_rate=get_sd_rate();
if(baud>20||!sd_rate) {
if (sys.sys_clk == SYSCLK_120M) {
return ((uint16_t)(baud + 1) * 25 / 10 - 1);
} else if (sys.sys_clk >= SYSCLK_80M) {
return ((baud + 1) * 2 - 1);
} else if (sys.sys_clk <= SYSCLK_30M) {
return (((baud + 1) >> 1) - 1);
}
} else if (sd_rate){
return set_sd_baud(sd_rate);
}
return baud;
}
//客户可能用到UART0(使用26M时钟源)做通信,这里可选设置系统时钟时不改波特率
WEAK void update_uart0baud_in_sysclk(uint32_t uart_baud)
{
if(UART0CON & BIT(0)) {
while (!(UART0CON & BIT(8)));
}
UART0BAUD = (uart_baud << 16) | uart_baud;
}
void set_sys_uart0baud(uint32_t baud)
{
sys.uart0baud = baud;
}
//切系统时钟前，先设置模块时钟分频较大值，保证模块不会超频的情况
AT(.com_text.sys)
void set_peripherals_clkdiv_safety(void)
{
uint32_t clkcon3 = CLKCON3;
uint32_t clkcon2 = CLKCON2;
//src clkdiv
clkcon3 &= ~0xf0; //reset src clkdiv
clkcon3 |= (1 << 4); //src clk = sys_clk / (n+1)
//sbcenc硬件要小于48M
clkcon3 &= ~(0x0f << 12); //reset sbcenc clkdiv
clkcon3 |= (2 << 12); //src clk = sys_clk / (n+1)
//aec ram硬件要小于50M
clkcon3 &= ~0x0f; //reset aec clkdiv
clkcon3 &= ~(0x0f << 19); //reset plc clkdiv
clkcon3 &= ~(0x0f << 23); //reset cvsd clkdiv
clkcon3 |= 0x02; //aec clk = sys_clk / (n+1)
clkcon3 |= (2 << 19); //plc clk = sys_clk / (n+1)
clkcon3 |= (2 << 23); //cvsd clk = sys_clk / (n+1)
//audec硬件要小于48M
clkcon2 &= ~(0x0f << 13); //reset audec clkdiv
clkcon2 |= (2 << 13); //audec clk = sys_clk / (n+1)
CLKCON3 = clkcon3;
CLKCON2 = clkcon2;
}
//根据实际系统时钟，设置合适的模块时钟分频
void set_peripherals_clkdiv(void)
{
uint32_t clkcon3 = CLKCON3;
uint32_t clkcon2 = CLKCON2;
uint32_t clkdiv;
uint8_t sys_clk = sys.sys_clk;
//src clkdiv
clkcon3 &= ~0xf0; //reset src clkdiv
if (sys_clk > SYSCLK_80M) {
clkcon3 |= (1 << 4); //src clk = sys_clk / (n+1)
}
//sbcec硬件要小于48M
clkcon3 &= ~(0x0f << 12);
if (sys_clk > SYSCLK_80M) {
clkcon3 |= (2 << 12);
} else if (sys_clk >= SYSCLK_60M) {
clkcon3 |= (1 << 12);
}
//aec ram硬件要小于50M
clkcon3 &= ~0x0f; //reset aec clkdiv
clkcon3 &= ~(0x0f << 19); //reset plc clkdiv
clkcon3 &= ~(0x0f << 23); //reset cvsd clkdiv
if (sys_clk > SYSCLK_80M) {
clkdiv = 2;
} else if (sys_clk >= SYSCLK_60M) {
clkdiv = 1;
} else {
clkdiv = 0;
}
clkcon3 |= clkdiv; //aec clk = sys_clk / (n+1)
clkcon3 |= (clkdiv << 19); //plc clk = sys_clk / (n+1)
clkcon3 |= (clkdiv << 23); //cvsd clk = sys_clk / (n+1)
//audec硬件要小于48M
clkcon2 &= ~(0x0f << 13); //reset audec clkdiv
if (sys_clk > SYSCLK_80M) {
clkdiv = 2;
} else if (sys_clk >= SYSCLK_60M) {
clkdiv = 1;
} else {
clkdiv = 0;
}
clkcon2 |= (clkdiv << 13); //audec clk = sys_clk / (n+1)
CLKCON3 = clkcon3;
CLKCON2 = clkcon2;
// if (sys_clk <= SYS_48M) {
// PWRCON0 = (PWRCON0 & ~0xf) | (sys_trim.vddcore); //VDDCORE减一档
// }
// vddcore_other_offset();
}
ALIGN(512) //注意：超过512byte时，要用lock cache
static void set_sysclk_do(uint32_t sys_clk, uint32_t clk_sel, uint32_t spll_div, uint32_t spi_baud, uint32_t spi1baud)
{
uint32_t cpu_ie;
cpu_ie = PICCON & BIT(0);
PICCONCLR = BIT(0); //关中断，切换系统时钟
set_peripherals_clkdiv_safety();
CLKCON0 &= ~(BIT(2) | BIT(3)); //sysclk sel rc2m
CLKCON2 &= ~(0x1f << 8); //reset spll div
if(clk_sel <= PLL0DIV_120M) {
//sys_clk来源PLL0的分频配置
CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6)); //sys_pll select pll0out
if (PLL0DIV != (240 * 65536 / 26)) {
PLL0DIV = 240 * 65536 / 26; //pll: 240M, XOSC: 26M
PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5));
PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则为0)
PLL0CON |= BIT(20); //update pll0div to pll0_clk
CLKCON3 &= ~(7 << 16);
CLKCON3 |= (4 << 16); //USB CLK 48M
}
} else if (clk_sel <= OSCDIV_26M) {
//sys_clk来源于XOSC26M时钟分频, 无USB时关闭PLL0
// if (!is_usb_support()) {
// PLL0CON &= ~BIT(18);
// PLL0CON &= ~(BIT(12) | BIT(6)); //close pll0
// }
CLKCON0 &= ~(BIT(4) | BIT(5) | BIT(6));
CLKCON0 |= BIT(6); //spll select xosc26m_clk
}
CLKCON2 |= (spll_div << 8);
CLKCON0 |= BIT(3); //sysclk sel spll
SPI0BAUD = spi_baud;
if (CLKGAT1 & BIT(12)) {
SPI1BAUD = spi1baud;
}
// if (spiflash_speed_up_en()) {
// set_flash_safety(sys_clk);
// }
PICCON |= cpu_ie;
}
void set_sysclk(uint32_t sys_clk)
{
uint32_t uart_baud, spll_div = 0, spi_baud = 0, spi1baud;
uint8_t cnt_1us, clk_sel;
clk_sel = get_clksel_val(sys_clk);
if(sys.clk_sel == clk_sel) {
return;
}
// if (sys_clk > SYSCLK_48M) {
// PWRCON0 = (PWRCON0 & ~0xf) | (sys_trim.vddcore + 1); //VDDCORE加一档
// }
// vddcore_other_offset();
// printf("%s: %d, %d\n", __func__, sys_clk, clk_sel);
switch (sys_clk) {
case SYSCLK_12M:
spll_div = 19; //pll0 240M
cnt_1us = 1;
spi_baud = 0;
spi1baud = 0;
break;
case SYSCLK_24M:
spll_div = 9; //pll0 240M
cnt_1us = 2;
spi_baud = 0;
spi1baud = 1;
break;
case SYSCLK_30M:
spll_div = 7; //pll0 240M
cnt_1us = 3;
spi_baud = 1; //Baud Rate =Fsys clock / (SPI_BAUD+1)
spi1baud = 1;
break;
case SYSCLK_48M:
spll_div = 4; //pll0 240M
cnt_1us = 4;
spi_baud = 1; //Baud Rate =Fsys clock / (SPI_BAUD+1)
spi1baud = 3;
break;
case SYSCLK_60M:
spll_div = 3; //pll0 240M
cnt_1us = 5;
spi_baud = 2; //Baud Rate =Fsys clock / (SPI_BAUD+1)
spi1baud = 3;
break;
case SYSCLK_80M:
spll_div = 2; //pll0 240M
cnt_1us = 7;
spi_baud = 3; //Baud Rate =Fsys clock / (SPI_BAUD+1)
spi1baud = 4;
break;
case SYSCLK_120M:
spll_div = 1; //pll0 240M
cnt_1us = 10;
spi_baud = 4; //Baud Rate =Fsys clock / (SPI_BAUD+1) //spiclk 120/5 = 24M
spi1baud = 9;
break;
case SYSCLK_26M:
spll_div = 0;
cnt_1us = 3;
spi_baud = 1;
spi1baud = 1;
break;
case SYSCLK_13M:
spll_div = 1;
cnt_1us = 1;
spi_baud = 0;
spi1baud = 0;
break;
case SYSCLK_2M:
spll_div = 1;
cnt_1us = 1;
spi_baud = 0;
spi1baud = 0;
break;
default:
return;
}
//先判断PLL0是否打开
if(clk_sel <= PLL0DIV_120M) {
if (!(PLL0CON & BIT(12))) {
PLL0CON &= ~(BIT(3) | BIT(4) | BIT(5));
PLL0CON |= BIT(3); //Select PLL/VCO frequency band (PLL大于206M vcos = 0x01, 否则为0)
PLL0CON |= BIT(12); //enable pll0 ldo
delay_us(100); //delay 100us
PLL0DIV = 240 * 65536 / 26; //pll0: 240M, XOSC: 26M
PLL0CON |= BIT(20); //update pll0div to pll0_clk
PLL0CON |= BIT(6); //enable analog pll0
PLL0CON |= BIT(18); //pll0 sdm enable
delay_us(1000); //wait pll0 stable
}
}
sys.cnt_1us = cnt_1us;
sys.sys_clk = sys_clk;
sys.clk_sel = clk_sel;
uart_baud = (((get_sysclk_nhz() + (sys.uart0baud / 2)) / sys.uart0baud) - 1);
set_sysclk_do(sys_clk, clk_sel,spll_div, spi_baud, spi1baud);
set_peripherals_clkdiv();
update_sd0baud(); //更新下SD0BAUD
update_uart0baud_in_sysclk(uart_baud);
}