support cv181x c906_little (#8680)

2024-03-28 23:35:54 +08:00 · 2024-03-28 23:35:54 +08:00 · 40e26f4909
parent 751c2ada43
commit 40e26f4909
69 changed files with 1737 additions and 1350 deletions
--- a/bsp/cvitek/.gitignore
+++ b/bsp/cvitek/.gitignore
@ -1,2 +1,6 @@
+cvitek_bootloader
 fip.bin
 boot.sd
+output
+c906_little/board/script
+Image.lzma
--- a/bsp/cvitek/README.md
+++ b/bsp/cvitek/README.md
@ -8,7 +8,7 @@

 | 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 |
 | ------- | ------- |------- | -------- | -------- |
-| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 |
+| cv180x | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 |

 - 小核

@ -18,10 +18,30 @@

 > 注：异构芯片需单独编译每个核的 OS

+## 编译
+异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行:
+
+1. 开发板选择
+Linux平台下，可以先执行：
+```shell
+$ scons --menuconfig
+```
+
+选择当前需要编译的目标开发板类型
+```shell
+Board Type (milkv-duo)  --->
+    ( ) milkv-duo
+    (X) milkv-duo256m
+```
+
+2. 编译
+```shell
+$ scons
+```

 ## 运行

-编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。
+编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。

 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。
 2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。
@ -39,10 +59,22 @@

 ## 支持开发板
 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
+- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m)

 ## FAQ
 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。

+2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory
+
+可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。
+或使用以下命令下载安装:
+```shell
+$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb
+```
+
 ## 联系人信息

 维护人：[flyingcys](https://github.com/flyingcys)
+
+更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io)
--- a/bsp/cvitek/c906_little/.config
+++ b/bsp/cvitek/c906_little/.config
@ -1001,6 +1001,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set

 #
 # Display
@ -1087,3 +1088,5 @@ CONFIG_BSP_USING_C906_LITTLE=y
 CONFIG_PLIC_PHY_ADDR=0x70000000
 CONFIG_IRQ_MAX_NR=128
 CONFIG_TIMER_CLK_FREQ=25000000
+# CONFIG_BOARD_TYPE_MILKV_DUO is not set
+CONFIG_BOARD_TYPE_MILKV_DUO256M=y
--- a/bsp/cvitek/c906_little/Kconfig
+++ b/bsp/cvitek/c906_little/Kconfig
@ -38,3 +38,13 @@ config IRQ_MAX_NR
 config TIMER_CLK_FREQ
    int
    default 25000000
+
+choice
+    prompt "Board Type"
+    default BOARD_TYPE_MILKV_DUO256M
+
+    config BOARD_TYPE_MILKV_DUO
+        bool "milkv-duo"
+    config BOARD_TYPE_MILKV_DUO256M
+        bool "milkv-duo256m"
+endchoice
--- a/bsp/cvitek/c906_little/README.md
+++ b/bsp/cvitek/c906_little/README.md
@ -17,20 +17,37 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin
 ```

 ## 编译
-1. Linux平台下，可以先执行：
+1. 依赖安装
+
+```shell
+$ sudo apt install -y scons libncurses5-dev wget flex bison
+```
+
+
+2. Linux平台下，先执行：
 ```shell
 $ scons --menuconfig
 ```

-它会自动下载env相关脚本到~/.env目录，然后执行
+选择当前需要编译的目标开发板类型
+```shell
+Board Type (milkv-duo)  --->
+    ( ) milkv-duo
+    (X) milkv-duo256m
+```
+
+它会自动下载 env 相关脚本到 ~/.env 目录，然后执行
 ```shell
 $ source ~/.env/env.sh
 $ pkgs --update
 ```
-更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。

 编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。

+第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。
+
+下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。

 ## 运行
 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。
--- a/bsp/cvitek/c906_little/SConstruct
+++ b/bsp/cvitek/c906_little/SConstruct
@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 # include libraries
 objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))

+if GetDepend('BOARD_TYPE_MILKV_DUO256M'):
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld')
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x')
+
 # make a building
 DoBuilding(TARGET, objs)
--- a/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld
+++ b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld
@ -7,6 +7,8 @@
 * Date           Author       Notes
 * 2024/01/11     flyingcys    The first version
 */
+INCLUDE ./cvi_board_memmap.ld
+
 _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
 /* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
 /*_HEAP_SIZE =  0x20000;*/
@ -15,9 +17,6 @@ _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
 _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
 _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;

-CVIMMAP_FREERTOS_ADDR = 0x83f40000;
-CVIMMAP_FREERTOS_SIZE = 0xc0000;
-
 /* Define Memories in the system */

 MEMORY
--- a/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld
+++ b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld
@ -0,0 +1,30 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x82473000;
+CVIMMAP_BOOTLOGO_SIZE = 0x0;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x4000000;
+CVIMMAP_FREERTOS_ADDR = 0x83f40000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0;
+CVIMMAP_FREERTOS_SIZE = 0xc0000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x0;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x82473000;
+CVIMMAP_ION_SIZE = 0x1acd000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x0;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81400000;
+CVIMMAP_UIMAG_SIZE = 0xf00000;
--- a/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld
+++ b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld
@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024/01/11     flyingcys    The first version
+ */
+INCLUDE ./cvi_board_memmap.ld
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000;
+/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */
+/*_HEAP_SIZE =  0x20000;*/
+
+_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
+_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
+_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE
+}
+
+/* Specify the default entry point to the program */
+
+/*ENTRY(_vector_table)*/
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.text : {
+   KEEP (*(.vectors))
+   *(.boot)
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+   *(.plt)
+   *(.gnu_warning)
+   *(.gcc_execpt_table)
+   *(.glue_7)
+   *(.glue_7t)
+   *(.ARM.extab)
+   *(.gnu.linkonce.armextab.*)
+
+   /* section information for finsh shell */
+   . = ALIGN(8);
+   __fsymtab_start = .;
+   KEEP(*(FSymTab))
+   __fsymtab_end = .;
+   . = ALIGN(8);
+   __vsymtab_start = .;
+   KEEP(*(VSymTab))
+   __vsymtab_end = .;
+   . = ALIGN(8);
+
+   /* section information for initial. */
+   . = ALIGN(8);
+   __rt_init_start = .;
+   KEEP(*(SORT(.rti_fn*)))
+   __rt_init_end = .;
+   . = ALIGN(8);
+
+   __rt_utest_tc_tab_start = .;
+   KEEP(*(UtestTcTab))
+   __rt_utest_tc_tab_end = .;
+} > psu_ddr_0_MEM_0
+
+.init (ALIGN(64)) : {
+   KEEP (*(.init))
+} > psu_ddr_0_MEM_0
+
+.fini (ALIGN(64)) : {
+   KEEP (*(.fini))
+} > psu_ddr_0_MEM_0
+
+.interp : {
+   KEEP (*(.interp))
+} > psu_ddr_0_MEM_0
+
+.note-ABI-tag : {
+   KEEP (*(.note-ABI-tag))
+} > psu_ddr_0_MEM_0
+
+.rodata : {
+   . = ALIGN(64);
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.srodata*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > psu_ddr_0_MEM_0
+
+.rodata1 : {
+   . = ALIGN(64);
+   __rodata1_start = .;
+   *(.rodata1)
+   *(.rodata1.*)
+   __rodata1_end = .;
+} > psu_ddr_0_MEM_0
+
+.data : {
+   . = ALIGN(64);
+   _data = .;
+   *(.data)
+   *(.data.*)
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.d.*)
+   *(.jcr)
+   *(.got)
+   *(.got.plt)
+   _edata = .;
+} > psu_ddr_0_MEM_0
+
+.data1 : {
+   . = ALIGN(64);
+   __data1_start = .;
+   *(.data1)
+   *(.data1.*)
+   __data1_end = .;
+} > psu_ddr_0_MEM_0
+
+.got : {
+   *(.got)
+} > psu_ddr_0_MEM_0
+
+.got1 : {
+   *(.got1)
+} > psu_ddr_0_MEM_0
+
+.got2 : {
+   *(.got2)
+} > psu_ddr_0_MEM_0
+
+.ctors : {
+   . = ALIGN(64);
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.dtors : {
+   . = ALIGN(64);
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   __DTOR_END__ = .;
+   ___DTORS_END___ = .;
+} > psu_ddr_0_MEM_0
+
+.fixup : {
+   __fixup_start = .;
+   *(.fixup)
+   __fixup_end = .;
+} > psu_ddr_0_MEM_0
+
+.eh_frame : {
+   *(.eh_frame)
+} > psu_ddr_0_MEM_0
+
+.eh_framehdr : {
+   __eh_framehdr_start = .;
+   *(.eh_framehdr)
+   __eh_framehdr_end = .;
+} > psu_ddr_0_MEM_0
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > psu_ddr_0_MEM_0
+
+.bss (NOLOAD) : {
+   . = ALIGN(64);
+   _bss = .;
+   *(.bss)
+   *(.bss.*)
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(64);
+   _ebss = .;
+} > psu_ddr_0_MEM_0
+
+/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/
+    _data_lma = LOADADDR(.data);
+
+/* Generate Stack and Heap definitions */
+.stack (NOLOAD) : {
+   . = ALIGN(64);
+   _stack_end_end = .;
+   . += _STACK_SIZE;
+   _stack_top = .;
+  __rt_rvstack = .; 
+} > psu_ddr_0_MEM_0
+
+.heap (NOLOAD) : {
+   . = ALIGN(64);
+   _heap = .;
+   HeapBase = .;
+   _heap_start = .;
+   *(.heap*)
+   /*. += _HEAP_SIZE;*/
+   /*_heap_size = _HEAP_SIZE; */
+   _heap_end = .;
+   HeapLimit = .;
+} > psu_ddr_0_MEM_0
+
+HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0);
+_end = .;
+}
+
--- a/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld
+++ b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld
@ -0,0 +1,32 @@
+CONFIG_SYS_TEXT_BASE = 0x80200000;
+CVIMMAP_ATF_SIZE = 0x80000;
+CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000;
+CVIMMAP_BOOTLOGO_SIZE = 0x1c2000;
+CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000;
+CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00;
+CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400;
+CVIMMAP_DRAM_BASE = 0x80000000;
+CVIMMAP_DRAM_SIZE = 0x10000000;
+CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000;
+CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000;
+CVIMMAP_FREERTOS_ADDR = 0x8fe00000;
+CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000;
+CVIMMAP_FREERTOS_SIZE = 0x200000;
+CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000;
+CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000;
+CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000;
+CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000;
+CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000;
+CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000;
+CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0;
+CVIMMAP_ION_ADDR = 0x8b300000;
+CVIMMAP_ION_SIZE = 0x4b00000;
+CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000;
+CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000;
+CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000;
+CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000;
+CVIMMAP_MONITOR_ADDR = 0x80000000;
+CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000;
+CVIMMAP_OPENSBI_SIZE = 0x80000;
+CVIMMAP_UIMAG_ADDR = 0x81800000;
+CVIMMAP_UIMAG_SIZE = 0x1000000;
--- a/bsp/cvitek/c906_little/rtconfig.h
+++ b/bsp/cvitek/c906_little/rtconfig.h
@ -268,5 +268,6 @@
 #define PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 128
 #define TIMER_CLK_FREQ 25000000
+#define BOARD_TYPE_MILKV_DUO256M

 #endif
--- a/bsp/cvitek/c906_little/rtconfig.py
+++ b/bsp/cvitek/c906_little/rtconfig.py
@ -18,7 +18,7 @@ if os.getenv('RTT_CC'):

 if  CROSS_TOOL == 'gcc':
    PLATFORM    = 'gcc'
-    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin'
 else:
    print('Please make sure your toolchains is GNU GCC!')
    exit(0)
@ -47,9 +47,10 @@ if PLATFORM == 'gcc':
    CFLAGS += ' -DCONFIG_64BIT'

    LINKER_SCRIPTS = r'cv180x_lscript.ld'
+    LINKER_SCRIPTS_PATH = r' -L board/script/cv180x'

    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS  = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    LFLAGS  = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH
    CPATH   = ''
    LPATH   = ''

@ -63,4 +64,4 @@ if PLATFORM == 'gcc':

 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n'
+POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n'
--- a/bsp/cvitek/combine-fip.sh
+++ b/bsp/cvitek/combine-fip.sh
@ -1,23 +1,84 @@
 #!/bin/bash

-set -e
+PROJECT_PATH=$1
+IMAGE_NAME=$2

-LITTLE_BIN=$1
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+	echo "Usage: $0 <PROJECT_DIR> <IMAGE_NAME>"
+	exit 1
+fi

-. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \
-./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \
-	'fip.bin' \
-	--MONITOR_RUNADDR="${MONITOR_RUNADDR}" \
-	--BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \
-	--CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \
-	--NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \
-	--NAND_INFO='00000000'\
-	--BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \
-	--BLCP_IMG_RUNADDR=0x05200200 \
-	--BLCP_PARAM_LOADADDR=0 \
-	--BLCP=pre-build/fsbl/test/empty.bin \
-	--DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \
-	--BLCP_2ND=$LITTLE_BIN \
-	--MONITOR='pre-build/fw_dynamic.bin' \
-	--LOADER_2ND='pre-build/u-boot-raw.bin' \
-	--compress='lzma'
+ROOT_PATH=$(pwd)
+echo $ROOT_PATH
+
+function get_board_type()
+{
+	BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M")
+	BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m")
+
+	for ((i=0;i<${#BOARD_CONFIG[@]};i++))
+	do
+		config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2)
+		if [ "$config_value" == "y" ]; then
+			BOARD_TYPE=${BOARD_VALUE[i]}
+			break
+		fi
+	done
+}
+
+get_board_type
+echo "board_type: ${BOARD_TYPE}"
+
+COUNTRY=China
+function get_country()
+{
+	restult=$(curl -m 10 -s http://www.ip-api.com/json)
+	COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/')
+	echo "Country: $COUNTRY"
+}
+
+if [ "$COUNTRY" == "China" ]; then
+	cvitek_bootloader_url=https://gitee.com/flyingcys/cvitek_bootloader
+else
+	cvitek_bootloader_url=https://github.com/flyingcys/cvitek_bootloader
+fi
+
+if [ ! -d cvitek_bootloader ]; then
+	echo "cvitek_bootloader not exist, clone it from ${cvitek_bootloader_url}"
+	git clone ${cvitek_bootloader_url}
+
+	if [ $? -ne 0 ]; then
+    	echo "Failed to clone ${cvitek_bootloader_url} !"
+      	exit 1
+    fi
+fi
+
+export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME}
+
+pushd cvitek_bootloader
+
+. env.sh
+
+get_build_board ${BOARD_TYPE}
+
+echo "board: ${MV_BOARD_LINK}"
+
+if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] ||  [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then
+	do_build
+	
+	CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]')
+	cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L}
+else
+	echo "Build already done, skip build"
+
+	do_combine
+
+	if [ $? -ne 0 ]; then
+		do_build
+	fi
+fi
+
+popd
+
+mkdir -p output/${MV_BOARD}
+cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin
--- a/bsp/cvitek/cv1800b/mksdimg.sh
+++ b/bsp/cvitek/cv1800b/mksdimg.sh
@ -1,7 +0,0 @@
-#/bin/sh
-set -e
-echo "start compress kernel..."
-
-lzma -c -9 -f -k Image > Image.lzma
-
-./mkimage -f multi.its -r ../boot.sd
--- a/bsp/cvitek/cv1800b/.config
+++ b/bsp/cvitek/cv1800b/.config
@ -1048,6 +1048,7 @@ CONFIG_RT_USING_LDSO=y
 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
 # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
 # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set

 #
 # Display
@ -1130,8 +1131,9 @@ CONFIG_UART_IRQ_BASE=44
 # CONFIG_RT_USING_UART4 is not set
 # CONFIG_BSP_USING_ADC is not set
 # CONFIG_BSP_USING_PWM is not set
-CONFIG_BSP_USING_CV1800B=y
+CONFIG_BSP_USING_CV180X=y
 CONFIG_C906_PLIC_PHY_ADDR=0x70000000
 CONFIG_IRQ_MAX_NR=64
 CONFIG_TIMER_CLK_FREQ=25000000
 CONFIG___STACKSIZE__=4096
+CONFIG_BOARD_TYPE_MILKV_DUO=y
--- a/bsp/cvitek/cv1800b/.gitignore
+++ b/bsp/cvitek/cv1800b/.gitignore
--- a/bsp/cvitek/cv1800b/Kconfig
+++ b/bsp/cvitek/cv1800b/Kconfig
@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
 source "board/Kconfig"

-config BSP_USING_CV1800B
+config BSP_USING_CV180X
    bool
    select ARCH_RISCV64
    select RT_USING_SYSTEM_WORKQUEUE
@ -45,3 +45,11 @@ config TIMER_CLK_FREQ
 config __STACKSIZE__
    int "stack size for interrupt"
    default 4096
+
+choice
+    prompt "Board Type"
+    default BOARD_TYPE_MILKV_DUO
+
+    config BOARD_TYPE_MILKV_DUO
+        bool "milkv-duo"
+endchoice
--- a/bsp/cvitek/cv1800b/README.md
+++ b/bsp/cvitek/cv1800b/README.md
@ -49,8 +49,9 @@ $ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin
 1. 依赖安装

 ```shell
-$ sudo apt install -y device-tree-compiler
+$ sudo apt install -y scons libncurses5-dev device-tree-compiler
 ```
+
 2. Linux平台下，可以先执行：
 ```shell
 $ scons --menuconfig
@ -61,7 +62,7 @@ $ scons --menuconfig
 $ source ~/.env/env.sh
 $ pkgs --update
 ```
-更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生 rtthread.elf 文件。

 编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。

--- a/bsp/cvitek/cv1800b/README_en.md
+++ b/bsp/cvitek/cv1800b/README_en.md
--- a/bsp/cvitek/cv1800b/SConscript
+++ b/bsp/cvitek/cv1800b/SConscript
--- a/bsp/cvitek/cv1800b/SConstruct
+++ b/bsp/cvitek/cv1800b/SConstruct
--- a/bsp/cvitek/cv1800b/applications/SConscript
+++ b/bsp/cvitek/cv1800b/applications/SConscript
--- a/bsp/cvitek/cv1800b/applications/main.c
+++ b/bsp/cvitek/cv1800b/applications/main.c
--- a/bsp/cvitek/cv1800b/board/Kconfig
+++ b/bsp/cvitek/cv1800b/board/Kconfig
--- a/bsp/cvitek/cv1800b/board/SConscript
+++ b/bsp/cvitek/cv1800b/board/SConscript
--- a/bsp/cvitek/cv1800b/board/board.c
+++ b/bsp/cvitek/cv1800b/board/board.c
--- a/bsp/cvitek/cv1800b/board/board.h
+++ b/bsp/cvitek/cv1800b/board/board.h
--- a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb
+++ b/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb
--- a/bsp/cvitek/cv1800b/link.lds
+++ b/bsp/cvitek/cv1800b/link.lds
--- a/bsp/cvitek/cv1800b/link_stacksize.lds
+++ b/bsp/cvitek/cv1800b/link_stacksize.lds
--- a/bsp/cvitek/cv1800b/multi.its
+++ b/bsp/cvitek/cv1800b/multi.its
--- a/bsp/cvitek/cv1800b/rtconfig.h
+++ b/bsp/cvitek/cv1800b/rtconfig.h
@ -311,10 +311,11 @@
 #define BSP_USING_UART
 #define RT_USING_UART0
 #define UART_IRQ_BASE 44
-#define BSP_USING_CV1800B
+#define BSP_USING_CV180X
 #define C906_PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 64
 #define TIMER_CLK_FREQ 25000000
 #define __STACKSIZE__ 4096
+#define BOARD_TYPE_MILKV_DUO

 #endif
--- a/bsp/cvitek/cv1800b/rtconfig.py
+++ b/bsp/cvitek/cv1800b/rtconfig.py
@ -25,6 +25,7 @@ if os.getenv('RTT_EXEC_PATH'):
    EXEC_PATH = os.getenv('RTT_EXEC_PATH')

 BUILD = 'debug'
+CHIP_TYPE = 'cv180x'

 if PLATFORM == 'gcc':
    # toolchains
@ -56,4 +57,5 @@ if PLATFORM == 'gcc':
    CXXFLAGS = CFLAGS

 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n'
--- a/bsp/cvitek/drivers/.ignore_format.yml
+++ b/bsp/cvitek/drivers/.ignore_format.yml
@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries
--- a/bsp/cvitek/drivers/SConscript
+++ b/bsp/cvitek/drivers/SConscript
@ -2,17 +2,23 @@ from building import *

 cwd     = GetCurrentDir()
 src     = Split('''
-drv_uart.c
-drv_por.c
+    drv_uart.c
+    drv_por.c
 ''')
 CPPDEFINES = []

 CPPPATH = [cwd]

-if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'):
-    CPPPATH += [cwd + r'/cv1800b']
+CHIP_TYPE = 'cv180x'
+if GetDepend('BOARD_TYPE_MILKV_DUO256M'):
+    CHIP_TYPE = 'cv181x'
+elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'):
+    CHIP_TYPE = 'cv180x'

-if GetDepend('BSP_USING_CV1800B'):
+CPPPATH += [cwd + r'/libraries']
+CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE]
+
+if GetDepend('BSP_USING_CV180X'):
    src += ['drv_gpio.c']

 if GetDepend('BSP_USING_I2C'):
@ -26,7 +32,8 @@ if GetDepend('BSP_USING_WDT'):

 if GetDepend('BSP_USING_PWM'):
    src += ['drv_pwm.c']
-    CPPPATH += [cwd + r'/cv1800b/pwm']
+    CPPPATH += [cwd + r'/libraries/cv180x/pwm']
+    
 CPPDEFINES += ['-DCONFIG_64BIT']

 if GetDepend('BSP_USING_RTC'):
--- a/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h
--- a/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h
--- a/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h
--- a/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h
--- a/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h
+++ b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h
--- a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h
@ -0,0 +1,653 @@
+
+#define CAM_MCLK0__CAM_MCLK0 0
+#define CAM_MCLK0__AUX1 2
+#define CAM_MCLK0__XGPIOA_0 3
+#define CAM_PD0__IIS1_MCLK 1
+#define CAM_PD0__XGPIOA_1 3
+#define CAM_PD0__CAM_HS0 4
+#define CAM_RST0__XGPIOA_2 3
+#define CAM_RST0__CAM_VS0 4
+#define CAM_RST0__IIC4_SCL 6
+#define CAM_MCLK1__CAM_MCLK1 0
+#define CAM_MCLK1__AUX2 2
+#define CAM_MCLK1__XGPIOA_3 3
+#define CAM_MCLK1__CAM_HS0 4
+#define CAM_PD1__IIS1_MCLK 1
+#define CAM_PD1__XGPIOA_4 3
+#define CAM_PD1__CAM_VS0 4
+#define CAM_PD1__IIC4_SDA 6
+#define IIC3_SCL__IIC3_SCL 0
+#define IIC3_SCL__XGPIOA_5 3
+#define IIC3_SDA__IIC3_SDA 0
+#define IIC3_SDA__XGPIOA_6 3
+#define SD0_CLK__SDIO0_CLK 0
+#define SD0_CLK__IIC1_SDA 1
+#define SD0_CLK__SPI0_SCK 2
+#define SD0_CLK__XGPIOA_7 3
+#define SD0_CLK__PWM_15 5
+#define SD0_CLK__EPHY_LNK_LED 6
+#define SD0_CLK__DBG_0 7
+#define SD0_CMD__SDIO0_CMD 0
+#define SD0_CMD__IIC1_SCL 1
+#define SD0_CMD__SPI0_SDO 2
+#define SD0_CMD__XGPIOA_8 3
+#define SD0_CMD__PWM_14 5
+#define SD0_CMD__EPHY_SPD_LED 6
+#define SD0_CMD__DBG_1 7
+#define SD0_D0__SDIO0_D_0 0
+#define SD0_D0__CAM_MCLK1 1
+#define SD0_D0__SPI0_SDI 2
+#define SD0_D0__XGPIOA_9 3
+#define SD0_D0__UART3_TX 4
+#define SD0_D0__PWM_13 5
+#define SD0_D0__WG0_D0 6
+#define SD0_D0__DBG_2 7
+#define SD0_D1__SDIO0_D_1 0
+#define SD0_D1__IIC1_SDA 1
+#define SD0_D1__AUX0 2
+#define SD0_D1__XGPIOA_10 3
+#define SD0_D1__UART1_TX 4
+#define SD0_D1__PWM_12 5
+#define SD0_D1__WG0_D1 6
+#define SD0_D1__DBG_3 7
+#define SD0_D2__SDIO0_D_2 0
+#define SD0_D2__IIC1_SCL 1
+#define SD0_D2__AUX1 2
+#define SD0_D2__XGPIOA_11 3
+#define SD0_D2__UART1_RX 4
+#define SD0_D2__PWM_11 5
+#define SD0_D2__WG1_D0 6
+#define SD0_D2__DBG_4 7
+#define SD0_D3__SDIO0_D_3 0
+#define SD0_D3__CAM_MCLK0 1
+#define SD0_D3__SPI0_CS_X 2
+#define SD0_D3__XGPIOA_12 3
+#define SD0_D3__UART3_RX 4
+#define SD0_D3__PWM_10 5
+#define SD0_D3__WG1_D1 6
+#define SD0_D3__DBG_5 7
+#define SD0_CD__SDIO0_CD 0
+#define SD0_CD__XGPIOA_13 3
+#define SD0_PWR_EN__SDIO0_PWR_EN 0
+#define SD0_PWR_EN__XGPIOA_14 3
+#define SPK_EN__XGPIOA_15 3
+#define UART0_TX__UART0_TX 0
+#define UART0_TX__CAM_MCLK1 1
+#define UART0_TX__PWM_4 2
+#define UART0_TX__XGPIOA_16 3
+#define UART0_TX__UART1_TX 4
+#define UART0_TX__AUX1 5
+#define UART0_TX__DBG_6 7
+#define UART0_RX__UART0_RX 0
+#define UART0_RX__CAM_MCLK0 1
+#define UART0_RX__PWM_5 2
+#define UART0_RX__XGPIOA_17 3
+#define UART0_RX__UART1_RX 4
+#define UART0_RX__AUX0 5
+#define UART0_RX__DBG_7 7
+#define EMMC_RSTN__EMMC_RSTN 0
+#define EMMC_RSTN__XGPIOA_21 3
+#define EMMC_RSTN__AUX2 4
+#define EMMC_DAT2__EMMC_DAT_2 0
+#define EMMC_DAT2__SPINOR_HOLD_X 1
+#define EMMC_DAT2__SPINAND_HOLD 2
+#define EMMC_DAT2__XGPIOA_26 3
+#define EMMC_CLK__EMMC_CLK 0
+#define EMMC_CLK__SPINOR_SCK 1
+#define EMMC_CLK__SPINAND_CLK 2
+#define EMMC_CLK__XGPIOA_22 3
+#define EMMC_DAT0__EMMC_DAT_0 0
+#define EMMC_DAT0__SPINOR_MOSI 1
+#define EMMC_DAT0__SPINAND_MOSI 2
+#define EMMC_DAT0__XGPIOA_25 3
+#define EMMC_DAT3__EMMC_DAT_3 0
+#define EMMC_DAT3__SPINOR_WP_X 1
+#define EMMC_DAT3__SPINAND_WP 2
+#define EMMC_DAT3__XGPIOA_27 3
+#define EMMC_CMD__EMMC_CMD 0
+#define EMMC_CMD__SPINOR_MISO 1
+#define EMMC_CMD__SPINAND_MISO 2
+#define EMMC_CMD__XGPIOA_23 3
+#define EMMC_DAT1__EMMC_DAT_1 0
+#define EMMC_DAT1__SPINOR_CS_X 1
+#define EMMC_DAT1__SPINAND_CS 2
+#define EMMC_DAT1__XGPIOA_24 3
+#define JTAG_CPU_TMS__JTAG_CPU_TMS 0
+#define JTAG_CPU_TMS__CAM_MCLK0 1
+#define JTAG_CPU_TMS__PWM_7 2
+#define JTAG_CPU_TMS__XGPIOA_19 3
+#define JTAG_CPU_TMS__UART1_RTS 4
+#define JTAG_CPU_TMS__AUX0 5
+#define JTAG_CPU_TMS__UART1_TX 6
+#define JTAG_CPU_TMS__VO_D_28 7
+#define JTAG_CPU_TCK__JTAG_CPU_TCK 0
+#define JTAG_CPU_TCK__CAM_MCLK1 1
+#define JTAG_CPU_TCK__PWM_6 2
+#define JTAG_CPU_TCK__XGPIOA_18 3
+#define JTAG_CPU_TCK__UART1_CTS 4
+#define JTAG_CPU_TCK__AUX1 5
+#define JTAG_CPU_TCK__UART1_RX 6
+#define JTAG_CPU_TCK__VO_D_29 7
+#define JTAG_CPU_TRST__JTAG_CPU_TRST 0
+#define JTAG_CPU_TRST__XGPIOA_20 3
+#define JTAG_CPU_TRST__VO_D_30 6
+#define IIC0_SCL__IIC0_SCL 0
+#define IIC0_SCL__UART1_TX 1
+#define IIC0_SCL__UART2_TX 2
+#define IIC0_SCL__XGPIOA_28 3
+#define IIC0_SCL__WG0_D0 5
+#define IIC0_SCL__DBG_10 7
+#define IIC0_SDA__IIC0_SDA 0
+#define IIC0_SDA__UART1_RX 1
+#define IIC0_SDA__UART2_RX 2
+#define IIC0_SDA__XGPIOA_29 3
+#define IIC0_SDA__WG0_D1 5
+#define IIC0_SDA__WG1_D0 6
+#define IIC0_SDA__DBG_11 7
+#define AUX0__AUX0 0
+#define AUX0__XGPIOA_30 3
+#define AUX0__IIS1_MCLK 4
+#define AUX0__VO_D_31 5
+#define AUX0__WG1_D1 6
+#define AUX0__DBG_12 7
+#define PWR_VBAT_DET__PWR_VBAT_DET 0
+#define PWR_RSTN__PWR_RSTN 0
+#define PWR_SEQ1__PWR_SEQ1 0
+#define PWR_SEQ1__PWR_GPIO_3 3
+#define PWR_SEQ2__PWR_SEQ2 0
+#define PWR_SEQ2__PWR_GPIO_4 3
+#define PWR_SEQ3__PWR_SEQ3 0
+#define PWR_SEQ3__PWR_GPIO_5 3
+#define PTEST__PWR_PTEST 0
+#define PWR_WAKEUP0__PWR_WAKEUP0 0
+#define PWR_WAKEUP0__PWR_IR0 1
+#define PWR_WAKEUP0__PWR_UART0_TX 2
+#define PWR_WAKEUP0__PWR_GPIO_6 3
+#define PWR_WAKEUP0__UART1_TX 4
+#define PWR_WAKEUP0__IIC4_SCL 5
+#define PWR_WAKEUP0__EPHY_LNK_LED 6
+#define PWR_WAKEUP0__WG2_D0 7
+#define PWR_WAKEUP1__PWR_WAKEUP1 0
+#define PWR_WAKEUP1__PWR_IR1 1
+#define PWR_WAKEUP1__PWR_GPIO_7 3
+#define PWR_WAKEUP1__UART1_TX 4
+#define PWR_WAKEUP1__IIC4_SCL 5
+#define PWR_WAKEUP1__EPHY_LNK_LED 6
+#define PWR_WAKEUP1__WG0_D0 7
+#define PWR_BUTTON1__PWR_BUTTON1 0
+#define PWR_BUTTON1__PWR_GPIO_8 3
+#define PWR_BUTTON1__UART1_RX 4
+#define PWR_BUTTON1__IIC4_SDA 5
+#define PWR_BUTTON1__EPHY_SPD_LED 6
+#define PWR_BUTTON1__WG2_D1 7
+#define PWR_ON__PWR_ON 0
+#define PWR_ON__PWR_GPIO_9 3
+#define PWR_ON__UART1_RX 4
+#define PWR_ON__IIC4_SDA 5
+#define PWR_ON__EPHY_SPD_LED 6
+#define PWR_ON__WG0_D1 7
+#define XTAL_XIN__PWR_XTAL_CLKIN 0
+#define PWR_GPIO0__PWR_GPIO_0 0
+#define PWR_GPIO0__UART2_TX 1
+#define PWR_GPIO0__PWR_UART0_RX 2
+#define PWR_GPIO0__PWM_8 4
+#define PWR_GPIO1__PWR_GPIO_1 0
+#define PWR_GPIO1__UART2_RX 1
+#define PWR_GPIO1__EPHY_LNK_LED 3
+#define PWR_GPIO1__PWM_9 4
+#define PWR_GPIO1__PWR_IIC_SCL 5
+#define PWR_GPIO1__IIC2_SCL 6
+#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7
+#define PWR_GPIO2__PWR_GPIO_2 0
+#define PWR_GPIO2__PWR_SECTICK 2
+#define PWR_GPIO2__EPHY_SPD_LED 3
+#define PWR_GPIO2__PWM_10 4
+#define PWR_GPIO2__PWR_IIC_SDA 5
+#define PWR_GPIO2__IIC2_SDA 6
+#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7
+#define CLK32K__CLK32K 0
+#define CLK32K__AUX0 1
+#define CLK32K__PWR_MCU_JTAG_TDI 2
+#define CLK32K__PWR_GPIO_10 3
+#define CLK32K__PWM_2 4
+#define CLK32K__KEY_COL0 5
+#define CLK32K__CAM_MCLK0 6
+#define CLK32K__DBG_0 7
+#define CLK25M__CLK25M 0
+#define CLK25M__AUX1 1
+#define CLK25M__PWR_MCU_JTAG_TDO 2
+#define CLK25M__PWR_GPIO_11 3
+#define CLK25M__PWM_3 4
+#define CLK25M__KEY_COL1 5
+#define CLK25M__CAM_MCLK1 6
+#define CLK25M__DBG_1 7
+#define IIC2_SCL__IIC2_SCL 0
+#define IIC2_SCL__PWM_14 1
+#define IIC2_SCL__PWR_GPIO_12 3
+#define IIC2_SCL__UART2_RX 4
+#define IIC2_SCL__KEY_COL2 7
+#define IIC2_SDA__IIC2_SDA 0
+#define IIC2_SDA__PWM_15 1
+#define IIC2_SDA__PWR_GPIO_13 3
+#define IIC2_SDA__UART2_TX 4
+#define IIC2_SDA__IIS1_MCLK 5
+#define IIC2_SDA__IIS2_MCLK 6
+#define IIC2_SDA__KEY_COL3 7
+#define UART2_TX__UART2_TX 0
+#define UART2_TX__PWM_11 1
+#define UART2_TX__PWR_UART1_TX 2
+#define UART2_TX__PWR_GPIO_14 3
+#define UART2_TX__KEY_ROW3 4
+#define UART2_TX__UART4_TX 5
+#define UART2_TX__IIS2_BCLK 6
+#define UART2_TX__WG2_D0 7
+#define UART2_RTS__UART2_RTS 0
+#define UART2_RTS__PWM_8 1
+#define UART2_RTS__PWR_GPIO_15 3
+#define UART2_RTS__KEY_ROW0 4
+#define UART2_RTS__UART4_RTS 5
+#define UART2_RTS__IIS2_DO 6
+#define UART2_RTS__WG1_D0 7
+#define UART2_RX__UART2_RX 0
+#define UART2_RX__PWM_10 1
+#define UART2_RX__PWR_UART1_RX 2
+#define UART2_RX__PWR_GPIO_16 3
+#define UART2_RX__KEY_COL3 4
+#define UART2_RX__UART4_RX 5
+#define UART2_RX__IIS2_DI 6
+#define UART2_RX__WG2_D1 7
+#define UART2_CTS__UART2_CTS 0
+#define UART2_CTS__PWM_9 1
+#define UART2_CTS__PWR_GPIO_17 3
+#define UART2_CTS__KEY_ROW1 4
+#define UART2_CTS__UART4_CTS 5
+#define UART2_CTS__IIS2_LRCK 6
+#define UART2_CTS__WG1_D1 7
+#define SD1_D3__PWR_SD1_D3_VO32 0
+#define SD1_D3__SPI2_CS_X 1
+#define SD1_D3__IIC1_SCL 2
+#define SD1_D3__PWR_GPIO_18 3
+#define SD1_D3__CAM_MCLK0 4
+#define SD1_D3__UART3_CTS 5
+#define SD1_D3__PWR_SPINOR1_CS_X 6
+#define SD1_D3__PWM_4 7
+#define SD1_D2__PWR_SD1_D2_VO33 0
+#define SD1_D2__IIC1_SCL 1
+#define SD1_D2__UART2_TX 2
+#define SD1_D2__PWR_GPIO_19 3
+#define SD1_D2__CAM_MCLK0 4
+#define SD1_D2__UART3_TX 5
+#define SD1_D2__PWR_SPINOR1_HOLD_X 6
+#define SD1_D2__PWM_5 7
+#define SD1_D1__PWR_SD1_D1_VO34 0
+#define SD1_D1__IIC1_SDA 1
+#define SD1_D1__UART2_RX 2
+#define SD1_D1__PWR_GPIO_20 3
+#define SD1_D1__CAM_MCLK1 4
+#define SD1_D1__UART3_RX 5
+#define SD1_D1__PWR_SPINOR1_WP_X 6
+#define SD1_D1__PWM_6 7
+#define SD1_D0__PWR_SD1_D0_VO35 0
+#define SD1_D0__SPI2_SDI 1
+#define SD1_D0__IIC1_SDA 2
+#define SD1_D0__PWR_GPIO_21 3
+#define SD1_D0__CAM_MCLK1 4
+#define SD1_D0__UART3_RTS 5
+#define SD1_D0__PWR_SPINOR1_MISO 6
+#define SD1_D0__PWM_7 7
+#define SD1_CMD__PWR_SD1_CMD_VO36 0
+#define SD1_CMD__SPI2_SDO 1
+#define SD1_CMD__IIC3_SCL 2
+#define SD1_CMD__PWR_GPIO_22 3
+#define SD1_CMD__CAM_VS0 4
+#define SD1_CMD__EPHY_LNK_LED 5
+#define SD1_CMD__PWR_SPINOR1_MOSI 6
+#define SD1_CMD__PWM_8 7
+#define SD1_CLK__PWR_SD1_CLK_VO37 0
+#define SD1_CLK__SPI2_SCK 1
+#define SD1_CLK__IIC3_SDA 2
+#define SD1_CLK__PWR_GPIO_23 3
+#define SD1_CLK__CAM_HS0 4
+#define SD1_CLK__EPHY_SPD_LED 5
+#define SD1_CLK__PWR_SPINOR1_SCK 6
+#define SD1_CLK__PWM_9 7
+#define RSTN__RSTN 0
+#define PWM0_BUCK__PWM_0 0
+#define PWM0_BUCK__XGPIOB_0 3
+#define ADC3__CAM_MCLK0 1
+#define ADC3__IIC4_SCL 2
+#define ADC3__XGPIOB_1 3
+#define ADC3__PWM_12 4
+#define ADC3__EPHY_LNK_LED 5
+#define ADC3__WG2_D0 6
+#define ADC3__UART3_TX 7
+#define ADC2__CAM_MCLK1 1
+#define ADC2__IIC4_SDA 2
+#define ADC2__XGPIOB_2 3
+#define ADC2__PWM_13 4
+#define ADC2__EPHY_SPD_LED 5
+#define ADC2__WG2_D1 6
+#define ADC2__UART3_RX 7
+#define ADC1__XGPIOB_3 3
+#define ADC1__KEY_COL2 4
+#define USB_ID__USB_ID 0
+#define USB_ID__XGPIOB_4 3
+#define USB_VBUS_EN__USB_VBUS_EN 0
+#define USB_VBUS_EN__XGPIOB_5 3
+#define PKG_TYPE0__PKG_TYPE0 0
+#define USB_VBUS_DET__USB_VBUS_DET 0
+#define USB_VBUS_DET__XGPIOB_6 3
+#define USB_VBUS_DET__CAM_MCLK0 4
+#define USB_VBUS_DET__CAM_MCLK1 5
+#define PKG_TYPE1__PKG_TYPE1 0
+#define PKG_TYPE2__PKG_TYPE2 0
+#define MUX_SPI1_MISO__UART3_RTS 1
+#define MUX_SPI1_MISO__IIC1_SDA 2
+#define MUX_SPI1_MISO__XGPIOB_8 3
+#define MUX_SPI1_MISO__PWM_9 4
+#define MUX_SPI1_MISO__KEY_COL1 5
+#define MUX_SPI1_MISO__SPI1_SDI 6
+#define MUX_SPI1_MISO__DBG_14 7
+#define MUX_SPI1_MOSI__UART3_RX 1
+#define MUX_SPI1_MOSI__IIC1_SCL 2
+#define MUX_SPI1_MOSI__XGPIOB_7 3
+#define MUX_SPI1_MOSI__PWM_8 4
+#define MUX_SPI1_MOSI__KEY_COL0 5
+#define MUX_SPI1_MOSI__SPI1_SDO 6
+#define MUX_SPI1_MOSI__DBG_13 7
+#define MUX_SPI1_CS__UART3_CTS 1
+#define MUX_SPI1_CS__CAM_MCLK0 2
+#define MUX_SPI1_CS__XGPIOB_10 3
+#define MUX_SPI1_CS__PWM_11 4
+#define MUX_SPI1_CS__KEY_ROW3 5
+#define MUX_SPI1_CS__SPI1_CS_X 6
+#define MUX_SPI1_CS__DBG_16 7
+#define MUX_SPI1_SCK__UART3_TX 1
+#define MUX_SPI1_SCK__CAM_MCLK1 2
+#define MUX_SPI1_SCK__XGPIOB_9 3
+#define MUX_SPI1_SCK__PWM_10 4
+#define MUX_SPI1_SCK__KEY_ROW2 5
+#define MUX_SPI1_SCK__SPI1_SCK 6
+#define MUX_SPI1_SCK__DBG_15 7
+#define PAD_ETH_TXM__UART3_RTS 1
+#define PAD_ETH_TXM__IIC1_SDA 2
+#define PAD_ETH_TXM__XGPIOB_24 3
+#define PAD_ETH_TXM__PWM_12 4
+#define PAD_ETH_TXM__CAM_MCLK1 5
+#define PAD_ETH_TXM__SPI1_SDI 6
+#define PAD_ETH_TXM__IIS2_BCLK 7
+#define PAD_ETH_TXP__UART3_RX 1
+#define PAD_ETH_TXP__IIC1_SCL 2
+#define PAD_ETH_TXP__XGPIOB_25 3
+#define PAD_ETH_TXP__PWM_13 4
+#define PAD_ETH_TXP__CAM_MCLK0 5
+#define PAD_ETH_TXP__SPI1_SDO 6
+#define PAD_ETH_TXP__IIS2_LRCK 7
+#define PAD_ETH_RXM__UART3_CTS 1
+#define PAD_ETH_RXM__CAM_MCLK0 2
+#define PAD_ETH_RXM__XGPIOB_26 3
+#define PAD_ETH_RXM__PWM_14 4
+#define PAD_ETH_RXM__CAM_VS0 5
+#define PAD_ETH_RXM__SPI1_CS_X 6
+#define PAD_ETH_RXM__IIS2_DI 7
+#define PAD_ETH_RXP__UART3_TX 1
+#define PAD_ETH_RXP__CAM_MCLK1 2
+#define PAD_ETH_RXP__XGPIOB_27 3
+#define PAD_ETH_RXP__PWM_15 4
+#define PAD_ETH_RXP__CAM_HS0 5
+#define PAD_ETH_RXP__SPI1_SCK 6
+#define PAD_ETH_RXP__IIS2_DO 7
+#define VIVO_D10__PWM_1 0
+#define VIVO_D10__VI1_D_10 1
+#define VIVO_D10__VO_D_23 2
+#define VIVO_D10__XGPIOB_11 3
+#define VIVO_D10__RMII0_IRQ 4
+#define VIVO_D10__CAM_MCLK0 5
+#define VIVO_D10__IIC1_SDA 6
+#define VIVO_D10__UART2_TX 7
+#define VIVO_D9__PWM_2 0
+#define VIVO_D9__VI1_D_9 1
+#define VIVO_D9__VO_D_22 2
+#define VIVO_D9__XGPIOB_12 3
+#define VIVO_D9__CAM_MCLK1 5
+#define VIVO_D9__IIC1_SCL 6
+#define VIVO_D9__UART2_RX 7
+#define VIVO_D8__PWM_3 0
+#define VIVO_D8__VI1_D_8 1
+#define VIVO_D8__VO_D_21 2
+#define VIVO_D8__XGPIOB_13 3
+#define VIVO_D8__RMII0_MDIO 4
+#define VIVO_D8__SPI3_SDO 5
+#define VIVO_D8__IIC2_SCL 6
+#define VIVO_D8__CAM_VS0 7
+#define VIVO_D7__VI2_D_7 0
+#define VIVO_D7__VI1_D_7 1
+#define VIVO_D7__VO_D_20 2
+#define VIVO_D7__XGPIOB_14 3
+#define VIVO_D7__RMII0_RXD1 4
+#define VIVO_D7__SPI3_SDI 5
+#define VIVO_D7__IIC2_SDA 6
+#define VIVO_D7__CAM_HS0 7
+#define VIVO_D6__VI2_D_6 0
+#define VIVO_D6__VI1_D_6 1
+#define VIVO_D6__VO_D_19 2
+#define VIVO_D6__XGPIOB_15 3
+#define VIVO_D6__RMII0_REFCLKI 4
+#define VIVO_D6__SPI3_SCK 5
+#define VIVO_D6__UART2_TX 6
+#define VIVO_D6__CAM_VS0 7
+#define VIVO_D5__VI2_D_5 0
+#define VIVO_D5__VI1_D_5 1
+#define VIVO_D5__VO_D_18 2
+#define VIVO_D5__XGPIOB_16 3
+#define VIVO_D5__RMII0_RXD0 4
+#define VIVO_D5__SPI3_CS_X 5
+#define VIVO_D5__UART2_RX 6
+#define VIVO_D5__CAM_HS0 7
+#define VIVO_D4__VI2_D_4 0
+#define VIVO_D4__VI1_D_4 1
+#define VIVO_D4__VO_D_17 2
+#define VIVO_D4__XGPIOB_17 3
+#define VIVO_D4__RMII0_MDC 4
+#define VIVO_D4__IIC1_SDA 5
+#define VIVO_D4__UART2_CTS 6
+#define VIVO_D4__CAM_VS0 7
+#define VIVO_D3__VI2_D_3 0
+#define VIVO_D3__VI1_D_3 1
+#define VIVO_D3__VO_D_16 2
+#define VIVO_D3__XGPIOB_18 3
+#define VIVO_D3__RMII0_TXD0 4
+#define VIVO_D3__IIC1_SCL 5
+#define VIVO_D3__UART2_RTS 6
+#define VIVO_D3__CAM_HS0 7
+#define VIVO_D2__VI2_D_2 0
+#define VIVO_D2__VI1_D_2 1
+#define VIVO_D2__VO_D_15 2
+#define VIVO_D2__XGPIOB_19 3
+#define VIVO_D2__RMII0_TXD1 4
+#define VIVO_D2__CAM_MCLK1 5
+#define VIVO_D2__PWM_2 6
+#define VIVO_D2__UART2_TX 7
+#define VIVO_D1__VI2_D_1 0
+#define VIVO_D1__VI1_D_1 1
+#define VIVO_D1__VO_D_14 2
+#define VIVO_D1__XGPIOB_20 3
+#define VIVO_D1__RMII0_RXDV 4
+#define VIVO_D1__IIC3_SDA 5
+#define VIVO_D1__PWM_3 6
+#define VIVO_D1__IIC4_SCL 7
+#define VIVO_D0__VI2_D_0 0
+#define VIVO_D0__VI1_D_0 1
+#define VIVO_D0__VO_D_13 2
+#define VIVO_D0__XGPIOB_21 3
+#define VIVO_D0__RMII0_TXCLK 4
+#define VIVO_D0__IIC3_SCL 5
+#define VIVO_D0__WG1_D0 6
+#define VIVO_D0__IIC4_SDA 7
+#define VIVO_CLK__VI2_CLK 0
+#define VIVO_CLK__VI1_CLK 1
+#define VIVO_CLK__VO_CLK1 2
+#define VIVO_CLK__XGPIOB_22 3
+#define VIVO_CLK__RMII0_TXEN 4
+#define VIVO_CLK__CAM_MCLK0 5
+#define VIVO_CLK__WG1_D1 6
+#define VIVO_CLK__UART2_RX 7
+#define PAD_MIPIRX5N__VI1_D_11 1
+#define PAD_MIPIRX5N__VO_D_12 2
+#define PAD_MIPIRX5N__XGPIOC_0 3
+#define PAD_MIPIRX5N__CAM_MCLK0 5
+#define PAD_MIPIRX5N__WG0_D0 6
+#define PAD_MIPIRX5N__DBG_0 7
+#define PAD_MIPIRX5P__VI1_D_12 1
+#define PAD_MIPIRX5P__VO_D_11 2
+#define PAD_MIPIRX5P__XGPIOC_1 3
+#define PAD_MIPIRX5P__IIS1_MCLK 4
+#define PAD_MIPIRX5P__CAM_MCLK1 5
+#define PAD_MIPIRX5P__WG0_D1 6
+#define PAD_MIPIRX5P__DBG_1 7
+#define PAD_MIPIRX4N__VI0_CLK 1
+#define PAD_MIPIRX4N__VI1_D_13 2
+#define PAD_MIPIRX4N__XGPIOC_2 3
+#define PAD_MIPIRX4N__IIC1_SDA 4
+#define PAD_MIPIRX4N__CAM_MCLK0 5
+#define PAD_MIPIRX4N__KEY_ROW0 6
+#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
+#define PAD_MIPIRX4P__VI0_D_0 1
+#define PAD_MIPIRX4P__VI1_D_14 2
+#define PAD_MIPIRX4P__XGPIOC_3 3
+#define PAD_MIPIRX4P__IIC1_SCL 4
+#define PAD_MIPIRX4P__CAM_MCLK1 5
+#define PAD_MIPIRX4P__KEY_ROW1 6
+#define PAD_MIPIRX4P__MUX_SPI1_CS 7
+#define PAD_MIPIRX3N__VI0_D_1 1
+#define PAD_MIPIRX3N__VI1_D_15 2
+#define PAD_MIPIRX3N__XGPIOC_4 3
+#define PAD_MIPIRX3N__CAM_MCLK0 4
+#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
+#define PAD_MIPIRX3P__VI0_D_2 1
+#define PAD_MIPIRX3P__VI1_D_16 2
+#define PAD_MIPIRX3P__XGPIOC_5 3
+#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
+#define PAD_MIPIRX2N__VI0_D_3 1
+#define PAD_MIPIRX2N__VO_D_10 2
+#define PAD_MIPIRX2N__XGPIOC_6 3
+#define PAD_MIPIRX2N__VI1_D_17 4
+#define PAD_MIPIRX2N__IIC4_SCL 5
+#define PAD_MIPIRX2N__DBG_6 7
+#define PAD_MIPIRX2P__VI0_D_4 1
+#define PAD_MIPIRX2P__VO_D_9 2
+#define PAD_MIPIRX2P__XGPIOC_7 3
+#define PAD_MIPIRX2P__VI1_D_18 4
+#define PAD_MIPIRX2P__IIC4_SDA 5
+#define PAD_MIPIRX2P__DBG_7 7
+#define PAD_MIPIRX1N__VI0_D_5 1
+#define PAD_MIPIRX1N__VO_D_8 2
+#define PAD_MIPIRX1N__XGPIOC_8 3
+#define PAD_MIPIRX1N__KEY_ROW3 6
+#define PAD_MIPIRX1N__DBG_8 7
+#define PAD_MIPIRX1P__VI0_D_6 1
+#define PAD_MIPIRX1P__VO_D_7 2
+#define PAD_MIPIRX1P__XGPIOC_9 3
+#define PAD_MIPIRX1P__IIC1_SDA 4
+#define PAD_MIPIRX1P__KEY_ROW2 6
+#define PAD_MIPIRX1P__DBG_9 7
+#define PAD_MIPIRX0N__VI0_D_7 1
+#define PAD_MIPIRX0N__VO_D_6 2
+#define PAD_MIPIRX0N__XGPIOC_10 3
+#define PAD_MIPIRX0N__IIC1_SCL 4
+#define PAD_MIPIRX0N__CAM_MCLK1 5
+#define PAD_MIPIRX0N__DBG_10 7
+#define PAD_MIPIRX0P__VI0_D_8 1
+#define PAD_MIPIRX0P__VO_D_5 2
+#define PAD_MIPIRX0P__XGPIOC_11 3
+#define PAD_MIPIRX0P__CAM_MCLK0 4
+#define PAD_MIPIRX0P__DBG_11 7
+#define PAD_MIPI_TXM4__SD1_CLK 1
+#define PAD_MIPI_TXM4__VO_D_24 2
+#define PAD_MIPI_TXM4__XGPIOC_18 3
+#define PAD_MIPI_TXM4__CAM_MCLK1 4
+#define PAD_MIPI_TXM4__PWM_12 5
+#define PAD_MIPI_TXM4__IIC1_SDA 6
+#define PAD_MIPI_TXM4__DBG_18 7
+#define PAD_MIPI_TXP4__SD1_CMD 1
+#define PAD_MIPI_TXP4__VO_D_25 2
+#define PAD_MIPI_TXP4__XGPIOC_19 3
+#define PAD_MIPI_TXP4__CAM_MCLK0 4
+#define PAD_MIPI_TXP4__PWM_13 5
+#define PAD_MIPI_TXP4__IIC1_SCL 6
+#define PAD_MIPI_TXP4__DBG_19 7
+#define PAD_MIPI_TXM3__SD1_D0 1
+#define PAD_MIPI_TXM3__VO_D_26 2
+#define PAD_MIPI_TXM3__XGPIOC_20 3
+#define PAD_MIPI_TXM3__IIC2_SDA 4
+#define PAD_MIPI_TXM3__PWM_14 5
+#define PAD_MIPI_TXM3__IIC1_SDA 6
+#define PAD_MIPI_TXM3__CAM_VS0 7
+#define PAD_MIPI_TXP3__SD1_D1 1
+#define PAD_MIPI_TXP3__VO_D_27 2
+#define PAD_MIPI_TXP3__XGPIOC_21 3
+#define PAD_MIPI_TXP3__IIC2_SCL 4
+#define PAD_MIPI_TXP3__PWM_15 5
+#define PAD_MIPI_TXP3__IIC1_SCL 6
+#define PAD_MIPI_TXP3__CAM_HS0 7
+#define PAD_MIPI_TXM2__VI0_D_13 1
+#define PAD_MIPI_TXM2__VO_D_0 2
+#define PAD_MIPI_TXM2__XGPIOC_16 3
+#define PAD_MIPI_TXM2__IIC1_SDA 4
+#define PAD_MIPI_TXM2__PWM_8 5
+#define PAD_MIPI_TXM2__SPI0_SCK 6
+#define PAD_MIPI_TXM2__SD1_D2 7
+#define PAD_MIPI_TXP2__VI0_D_14 1
+#define PAD_MIPI_TXP2__VO_CLK0 2
+#define PAD_MIPI_TXP2__XGPIOC_17 3
+#define PAD_MIPI_TXP2__IIC1_SCL 4
+#define PAD_MIPI_TXP2__PWM_9 5
+#define PAD_MIPI_TXP2__SPI0_CS_X 6
+#define PAD_MIPI_TXP2__SD1_D3 7
+#define PAD_MIPI_TXM1__VI0_D_11 1
+#define PAD_MIPI_TXM1__VO_D_2 2
+#define PAD_MIPI_TXM1__XGPIOC_14 3
+#define PAD_MIPI_TXM1__IIC2_SDA 4
+#define PAD_MIPI_TXM1__PWM_10 5
+#define PAD_MIPI_TXM1__SPI0_SDO 6
+#define PAD_MIPI_TXM1__DBG_14 7
+#define PAD_MIPI_TXP1__VI0_D_12 1
+#define PAD_MIPI_TXP1__VO_D_1 2
+#define PAD_MIPI_TXP1__XGPIOC_15 3
+#define PAD_MIPI_TXP1__IIC2_SCL 4
+#define PAD_MIPI_TXP1__PWM_11 5
+#define PAD_MIPI_TXP1__SPI0_SDI 6
+#define PAD_MIPI_TXP1__DBG_15 7
+#define PAD_MIPI_TXM0__VI0_D_9 1
+#define PAD_MIPI_TXM0__VO_D_4 2
+#define PAD_MIPI_TXM0__XGPIOC_12 3
+#define PAD_MIPI_TXM0__CAM_MCLK1 4
+#define PAD_MIPI_TXM0__PWM_14 5
+#define PAD_MIPI_TXM0__CAM_VS0 6
+#define PAD_MIPI_TXM0__DBG_12 7
+#define PAD_MIPI_TXP0__VI0_D_10 1
+#define PAD_MIPI_TXP0__VO_D_3 2
+#define PAD_MIPI_TXP0__XGPIOC_13 3
+#define PAD_MIPI_TXP0__CAM_MCLK0 4
+#define PAD_MIPI_TXP0__PWM_15 5
+#define PAD_MIPI_TXP0__CAM_HS0 6
+#define PAD_MIPI_TXP0__DBG_13 7
+#define PAD_AUD_AINL_MIC__XGPIOC_23 3
+#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
+#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
+#define PAD_AUD_AINR_MIC__XGPIOC_22 3
+#define PAD_AUD_AINR_MIC__IIS1_DO 4
+#define PAD_AUD_AINR_MIC__IIS2_DI 5
+#define PAD_AUD_AINR_MIC__IIS1_DI 6
+#define PAD_AUD_AOUTL__XGPIOC_25 3
+#define PAD_AUD_AOUTL__IIS1_LRCK 4
+#define PAD_AUD_AOUTL__IIS2_LRCK 5
+#define PAD_AUD_AOUTR__XGPIOC_24 3
+#define PAD_AUD_AOUTR__IIS1_DI 4
+#define PAD_AUD_AOUTR__IIS2_DO 5
+#define PAD_AUD_AOUTR__IIS1_DO 6
+#define GPIO_RTX__XGPIOB_23 3
+#define GPIO_RTX__PWM_1 4
+#define GPIO_RTX__CAM_MCLK0 5
+#define GPIO_ZQ__PWR_GPIO_24 3
+#define GPIO_ZQ__PWM_2 4
--- a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h
@ -0,0 +1,46 @@
+#ifndef _CV181X_PINMUX_H_
+#define _CV181X_PINMUX_H_
+
+#define PINMUX_UART0    0
+#define PINMUX_UART1    1
+#define PINMUX_UART2    2
+#define PINMUX_UART3    3
+#define PINMUX_UART3_2  4
+#define PINMUX_I2C0     5
+#define PINMUX_I2C1     6
+#define PINMUX_I2C2     7
+#define PINMUX_I2C3     8
+#define PINMUX_I2C4     9
+#define PINMUX_I2C4_2   10
+#define PINMUX_SPI0     11
+#define PINMUX_SPI1     12
+#define PINMUX_SPI2     13
+#define PINMUX_SPI2_2   14
+#define PINMUX_SPI3     15
+#define PINMUX_SPI3_2   16
+#define PINMUX_I2S0     17
+#define PINMUX_I2S1     18
+#define PINMUX_I2S2     19
+#define PINMUX_I2S3     20
+#define PINMUX_USBID    21
+#define PINMUX_SDIO0    22
+#define PINMUX_SDIO1    23
+#define PINMUX_ND       24
+#define PINMUX_EMMC     25
+#define PINMUX_SPI_NOR  26
+#define PINMUX_SPI_NAND 27
+#define PINMUX_CAM0     28
+#define PINMUX_CAM1     29
+#define PINMUX_PCM0     30
+#define PINMUX_PCM1     31
+#define PINMUX_CSI0     32
+#define PINMUX_CSI1     33
+#define PINMUX_CSI2     34
+#define PINMUX_DSI      35
+#define PINMUX_VI0      36
+#define PINMUX_VO       37
+#define PINMUX_PWM1     38
+#define PINMUX_UART4    39
+#define PINMUX_SPI_NOR1 40
+
+#endif // end of _CV181X_PINMUX_H_
--- a/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h
+++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h
@ -0,0 +1,475 @@
+// $Module: fmux_gpio $
+// $RegisterBank Version: V 1.0.00 $
+// $Author: ghost $
+// $Date: Fri, 30 Jul 2021 08:58:54 PM $
+//
+
+//GEN REG ADDR/OFFSET/MASK
+#define  FMUX_GPIO_REG_IOCTRL_CAM_MCLK0  0x0
+#define  FMUX_GPIO_REG_IOCTRL_CAM_PD0  0x4
+#define  FMUX_GPIO_REG_IOCTRL_CAM_RST0  0x8
+#define  FMUX_GPIO_REG_IOCTRL_CAM_MCLK1  0xc
+#define  FMUX_GPIO_REG_IOCTRL_CAM_PD1  0x10
+#define  FMUX_GPIO_REG_IOCTRL_IIC3_SCL  0x14
+#define  FMUX_GPIO_REG_IOCTRL_IIC3_SDA  0x18
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CLK  0x1c
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CMD  0x20
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D0  0x24
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D1  0x28
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D2  0x2c
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D3  0x30
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CD  0x34
+#define  FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN  0x38
+#define  FMUX_GPIO_REG_IOCTRL_SPK_EN  0x3c
+#define  FMUX_GPIO_REG_IOCTRL_UART0_TX  0x40
+#define  FMUX_GPIO_REG_IOCTRL_UART0_RX  0x44
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_RSTN  0x48
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT2  0x4c
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_CLK  0x50
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT0  0x54
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT3  0x58
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_CMD  0x5c
+#define  FMUX_GPIO_REG_IOCTRL_EMMC_DAT1  0x60
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS  0x64
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK  0x68
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST  0x6c
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SCL  0x70
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SDA  0x74
+#define  FMUX_GPIO_REG_IOCTRL_AUX0  0x78
+#define  FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET  0x7c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_RSTN  0x80
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ1  0x84
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ2  0x88
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ3  0x8c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0  0x90
+#define  FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1  0x94
+#define  FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1  0x98
+#define  FMUX_GPIO_REG_IOCTRL_PWR_ON  0x9c
+#define  FMUX_GPIO_REG_IOCTRL_XTAL_XIN  0xa0
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO0  0xa4
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO1  0xa8
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO2  0xac
+#define  FMUX_GPIO_REG_IOCTRL_CLK32K  0xb0
+#define  FMUX_GPIO_REG_IOCTRL_CLK25M  0xb4
+#define  FMUX_GPIO_REG_IOCTRL_IIC2_SCL  0xb8
+#define  FMUX_GPIO_REG_IOCTRL_IIC2_SDA  0xbc
+#define  FMUX_GPIO_REG_IOCTRL_UART2_TX  0xc0
+#define  FMUX_GPIO_REG_IOCTRL_UART2_RTS  0xc4
+#define  FMUX_GPIO_REG_IOCTRL_UART2_RX  0xc8
+#define  FMUX_GPIO_REG_IOCTRL_UART2_CTS  0xcc
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D3  0xd0
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D2  0xd4
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D1  0xd8
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D0  0xdc
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CMD  0xe0
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CLK  0xe4
+#define  FMUX_GPIO_REG_IOCTRL_RSTN  0xe8
+#define  FMUX_GPIO_REG_IOCTRL_PWM0_BUCK  0xec
+#define  FMUX_GPIO_REG_IOCTRL_ADC3  0xf0
+#define  FMUX_GPIO_REG_IOCTRL_ADC2  0xf4
+#define  FMUX_GPIO_REG_IOCTRL_ADC1  0xf8
+#define  FMUX_GPIO_REG_IOCTRL_USB_ID  0xfc
+#define  FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN  0x100
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE0  0x104
+#define  FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET  0x108
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE1  0x10c
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE2  0x110
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO  0x114
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI  0x118
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS  0x11c
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK  0x120
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM  0x124
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP  0x128
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM  0x12c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP  0x130
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D10  0x134
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D9  0x138
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D8  0x13c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D7  0x140
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D6  0x144
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D5  0x148
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D4  0x14c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D3  0x150
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D2  0x154
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D1  0x158
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_D0  0x15c
+#define  FMUX_GPIO_REG_IOCTRL_VIVO_CLK  0x160
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N  0x164
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P  0x168
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N  0x16c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P  0x170
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N  0x174
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P  0x178
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N  0x17c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P  0x180
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N  0x184
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P  0x188
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N  0x18c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P  0x190
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4  0x194
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4  0x198
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3  0x19c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3  0x1a0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2  0x1a4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2  0x1a8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1  0x1ac
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1  0x1b0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0  0x1b4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0  0x1b8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC  0x1bc
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC  0x1c0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL  0x1c4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR  0x1c8
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_RTX  0x1cc
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_ZQ  0x1d0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0   0x0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0   0x4
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_PD0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0   0x8
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_RST0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1   0xc
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1   0x10
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CAM_PD1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL   0x14
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA   0x18
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK   0x1c
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD   0x20
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D0   0x24
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D1   0x28
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D2   0x2c
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D3   0x30
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CD   0x34
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN   0x38
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPK_EN   0x3c
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_TX   0x40
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_RX   0x44
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN   0x48
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2   0x4c
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK   0x50
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0   0x54
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3   0x58
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD   0x5c
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1   0x60
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS   0x64
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK   0x68
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST   0x6c
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL   0x70
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA   0x74
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_AUX0   0x78
+#define  FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_AUX0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET   0x7c
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN   0x80
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1   0x84
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2   0x88
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3   0x8c
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0   0x90
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1   0x94
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1   0x98
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_ON   0x9c
+#define  FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_ON_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN   0xa0
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0   0xa4
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1   0xa8
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2   0xac
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CLK32K   0xb0
+#define  FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CLK32K_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_CLK25M   0xb4
+#define  FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_CLK25M_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL   0xb8
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA   0xbc
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_TX   0xc0
+#define  FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_TX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS   0xc4
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_RTS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_RX   0xc8
+#define  FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_RX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS   0xcc
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART2_CTS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D3   0xd0
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D2   0xd4
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D1   0xd8
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D0   0xdc
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD   0xe0
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK   0xe4
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_RSTN   0xe8
+#define  FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK   0xec
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC3   0xf0
+#define  FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC2   0xf4
+#define  FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC1   0xf8
+#define  FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_ID   0xfc
+#define  FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_ID_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN   0x100
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0   0x104
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET   0x108
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1   0x10c
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2   0x110
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO   0x114
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI   0x118
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS   0x11c
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK   0x120
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM   0x124
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP   0x128
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM   0x12c
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP   0x130
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10   0x134
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D10_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9   0x138
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D9_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8   0x13c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D8_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7   0x140
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D7_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6   0x144
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D6_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5   0x148
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D5_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4   0x14c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3   0x150
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2   0x154
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1   0x158
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0   0x15c
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK   0x160
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N   0x164
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P   0x168
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N   0x16c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P   0x170
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N   0x174
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P   0x178
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N   0x17c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P   0x180
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N   0x184
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P   0x188
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N   0x18c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P   0x190
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4   0x194
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4   0x198
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3   0x19c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3   0x1a0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2   0x1a4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2   0x1a8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1   0x1ac
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1   0x1b0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0   0x1b4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0   0x1b8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC   0x1bc
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC   0x1c0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL   0x1c4
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR   0x1c8
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX   0x1cc
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ   0x1d0
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK   0x7
--- a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
+++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h
@ -0,0 +1,35 @@
+/*
+ * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
+ *
+ * File Name: pinctrl.h
+ * Description:
+ */
+
+#ifndef __PINCTRL_CV181X_H__
+#define __PINCTRL_CV181X_H__
+
+//#include "../core.h"
+#include "cv181x_pinlist_swconfig.h"
+#include "cv181x_reg_fmux_gpio.h"
+
+#define  PAD_MIPI_TXM4__MIPI_TXM4 0
+#define  PAD_MIPI_TXP4__MIPI_TXP4 0
+#define  PAD_MIPI_TXM3__MIPI_TXM3 0
+#define  PAD_MIPI_TXP3__MIPI_TXP3 0
+#define  PAD_MIPI_TXM2__MIPI_TXM2 0
+#define  PAD_MIPI_TXP2__MIPI_TXP2 0
+#define  PAD_MIPI_TXM1__MIPI_TXM1 0
+#define  PAD_MIPI_TXP1__MIPI_TXP1 0
+#define  PAD_MIPI_TXM0__MIPI_TXM0 0
+#define  PAD_MIPI_TXP0__MIPI_TXP0 0
+
+#define PINMUX_BASE 0x03001000
+#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
+#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
+#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
+#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
+		mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
+		PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \
+		PINMUX_VALUE(PIN_NAME, FUNC_NAME))
+
+#endif /* __PINCTRL_CV181X_H__ */
--- a/bsp/cvitek/drivers/libraries/mmio.h
+++ b/bsp/cvitek/drivers/libraries/mmio.h
--- a/bsp/cvitek/drivers/libraries/types.h
+++ b/bsp/cvitek/drivers/libraries/types.h
--- a/bsp/cvitek/cv1800b/mkimage
+++ b/bsp/cvitek/cv1800b/mkimage
--- a/bsp/cvitek/mksdimg.sh
+++ b/bsp/cvitek/mksdimg.sh
@ -0,0 +1,37 @@
+#/bin/sh
+set -e
+
+PROJECT_PATH=$1
+IMAGE_NAME=$2
+
+if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then
+	echo "Usage: $0 <PROJECT_DIR> <IMAGE_NAME>"
+	exit 1
+fi
+
+ROOT_PATH=$(pwd)
+echo ${ROOT_PATH}
+
+function get_board_type()
+{
+	BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M")
+	BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m")
+
+	for ((i=0;i<${#BOARD_CONFIG[@]};i++))
+	do
+		config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2)
+		if [ "$config_value" == "y" ]; then
+			BOARD_TYPE=${BOARD_VALUE[i]}
+			break
+		fi
+	done
+}
+
+get_board_type
+
+echo "start compress kernel..."
+
+lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/Image.lzma
+
+mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE}
+./mkimage -f ${PROJECT_PATH}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.sd
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
@ -1 +0,0 @@
-<EFBFBD>ｭﾞ
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
@ -1,2 +0,0 @@
-MONITOR_RUNADDR=0x0000000080000000
-BLCP_2ND_RUNADDR=0x0000000083f40000
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin
--- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
+++ b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
@ -1,35 +0,0 @@
-#ifndef __BOARD_MMAP__83494f74__
-#define __BOARD_MMAP__83494f74__
-
-#define CONFIG_SYS_TEXT_BASE 0x80200000  /* offset 2.0MiB */
-#define CVIMMAP_ATF_SIZE 0x80000  /* 512.0KiB */
-#define CVIMMAP_BOOTLOGO_ADDR 0x82473000  /* offset 36.44921875MiB */
-#define CVIMMAP_BOOTLOGO_SIZE 0x0  /* 0.0KiB */
-#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000  /* offset 35.0MiB */
-#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00  /* offset 19.9990234375MiB */
-#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400  /* 1.0KiB */
-#define CVIMMAP_DRAM_BASE 0x80000000  /* offset 0.0KiB */
-#define CVIMMAP_DRAM_SIZE 0x4000000  /* 64.0MiB */
-#define CVIMMAP_FREERTOS_ADDR 0x83f40000  /* offset 63.25MiB */
-#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0  /* 0.0KiB */
-#define CVIMMAP_FREERTOS_SIZE 0xc0000  /* 768.0KiB */
-#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000  /* offset 63.25MiB */
-#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000  /* offset 20.0MiB */
-#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000  /* 15.0MiB */
-#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000  /* offset 36.44921875MiB */
-#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0  /* 0.0KiB */
-#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000  /* offset 36.44921875MiB */
-#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0  /* 0.0KiB */
-#define CVIMMAP_ION_ADDR 0x82473000  /* offset 36.44921875MiB */
-#define CVIMMAP_ION_SIZE 0x1acd000  /* 26.80078125MiB */
-#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000  /* offset 36.44921875MiB */
-#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0  /* 0.0KiB */
-#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000  /* offset 0.0KiB */
-#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000  /* 63.25MiB */
-#define CVIMMAP_MONITOR_ADDR 0x80000000  /* offset 0.0KiB */
-#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000  /* offset 512.0KiB */
-#define CVIMMAP_OPENSBI_SIZE 0x80000  /* 512.0KiB */
-#define CVIMMAP_UIMAG_ADDR 0x81400000  /* offset 20.0MiB */
-#define CVIMMAP_UIMAG_SIZE 0xf00000  /* 15.0MiB */
-
-#endif /* __BOARD_MMAP__83494f74__ */
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
@ -1,38 +0,0 @@
-#!/usr/bin/env python3
-
-import logging
-import struct
-import argparse
-
-CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD
-CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE
-
-CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0
-
-
-def gen_chip_conf(args):
-    logging.info("gen_chip_conf")
-    regs = [
-        (0x0E00000C, 0xA0000001),  # ATF_DBG_REG = 0x0E00000C
-        (0x0E00000C, 0xA0000002),
-        # (CHIP_CONF_CMD_DELAY_MS, 100),
-        # (CHIP_CONF_CMD_DELAY_US, 100),
-        (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF),
-    ]
-
-    chip_conf = b"".join(struct.pack("<II", a, v) for a, v in regs)
-    logging.info("chip_conf=%d bytes", len(chip_conf))
-
-    with open(args.CHIP_CONF, "wb") as fp:
-        fp.write(chip_conf)
-
-
-def main():
-    parser = argparse.ArgumentParser(description="generate test cases")
-    parser.add_argument("CHIP_CONF", type=str)
-    args = parser.parse_args()
-    gen_chip_conf(args)
-
-
-if __name__ == "__main__":
-    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py
@ -1,252 +0,0 @@
-#!/usr/bin/env python3
-# PYTHON_ARGCOMPLETE_OK
-
-import logging
-import argparse
-from struct import unpack
-
-from Crypto.Cipher import AES
-from Crypto.Hash import SHA256
-from Crypto.PublicKey import RSA
-from Crypto.Signature import pkcs1_15
-
-try:
-    import argcomplete
-except ImportError:
-    argcomplete = None
-
-from fiptool import FIP, IMAGE_ALIGN, init_logging
-
-ENCRYPTION_KEY_SIZE = 16
-ENCRYPTION_BLOCK_SIZE = 16
-IV_ZERO = b"\0" * ENCRYPTION_BLOCK_SIZE
-
-
-class SignedFIP(FIP):
-    def __init__(self, root_priv_path, bl_priv_path):
-        super().__init__()
-
-        with open(root_priv_path, "rb") as fp:
-            din = fp.read()
-            self.root_priv = RSA.import_key(din)
-
-        with open(bl_priv_path, "rb") as fp:
-            din = fp.read()
-            self.bl_priv = RSA.import_key(din)
-
-    def read_fip(self, path):
-        super().read_fip(path)
-
-        # Verity the reading of fip.bin
-        with open(path, "rb") as fp:
-            assert fp.read() == self.make()
-
-    def rsa_to_n(self, rsa):
-        return rsa.n.to_bytes(rsa.size_in_bytes(), byteorder="big")
-
-    def print_kpub_hash(self, bytes):
-        bytes_str = ['{:02x}'.format(int(i)) for i in bytes]
-        logging.info("KPUB_HASH:" + "".join(bytes_str))
-
-    def sign_bl_pk(self):
-        self.param1["ROOT_PK"].content = self.rsa_to_n(self.root_priv)
-        kpub_hash = SHA256.new(self.param1["ROOT_PK"].content[:256])
-        self.print_kpub_hash(kpub_hash.digest())
-
-        self.param1["BL_PK"].content = self.rsa_to_n(self.bl_priv)
-
-        digest = SHA256.new(self.rsa_to_n(self.bl_priv))
-
-        sig = pkcs1_15.new(self.root_priv).sign(digest)
-        self.param1["BL_PK_SIG"].content = sig
-
-    def sign_by_bl_priv(self, image):
-        digest = SHA256.new(image)
-        return pkcs1_15.new(self.bl_priv).sign(digest)
-
-    def sign(self):
-        logging.info("sign fip.bin")
-
-        self.param1["FIP_FLAGS"].content = self.FIP_FLAGS_SCS_MASK | self.param1["FIP_FLAGS"].toint()
-
-        self.sign_bl_pk()
-
-        cc = self.param1["CHIP_CONF"].content
-        cc_size = unpack("<I", self.param1["CHIP_CONF_SIZE"].content)[0]
-        logging.debug("CHIP_CONF_SIZE=%#x", cc_size)
-        cc = cc[:cc_size]
-
-        self.param1["CHIP_CONF_SIG"].content = self.sign_by_bl_priv(cc)
-        self.param1["BL2_IMG_SIG"].content = self.sign_by_bl_priv(self.body1["BL2"].content)
-
-        if self.body1["BLCP"].content:
-            logging.debug("sign blcp")
-            self.param1["BLCP_IMG_SIG"].content = self.sign_by_bl_priv(self.body1["BLCP"].content)
-
-        self.sign_fip2()
-
-    def sign_fip2(self):
-        logging.debug("sign_fip2:")
-
-        sig_size = len(self.rsa_to_n(self.bl_priv))
-
-        for name in ["BLCP_2ND", "MONITOR"]:
-            e = self.body2[name]
-            if not e.content:
-                continue
-
-            logging.info("sign %s: len=%#x", name, len(e.content))
-
-            image = bytearray(self.pad(e.content + b"\xCE" * sig_size, IMAGE_ALIGN))
-            sig = self.sign_by_bl_priv(image[:-sig_size])
-            assert sig_size == len(sig)
-            image[-sig_size:] = sig
-
-            e.content = image
-
-        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
-        if loader_2nd_loadaddr:
-            logging.info("sign %s at %#x", "LOADER_2ND_LOADADDR", loader_2nd_loadaddr)
-
-            # Only data after CKSUM field are signed.
-            # The value CKSUM include signature and is updated later.
-            e = self.body2["LOADER_2ND"]
-            e.content = self.pad(e.content + b"\xCE" * sig_size, IMAGE_ALIGN)
-            # SIZE is after CKSUM, update it before signing
-            self._update_ldr_2nd_hdr()
-
-            image = bytearray(e.content)
-            sig = self.sign_by_bl_priv(image[self.ldr_2nd_hdr["CKSUM"].end : -sig_size])
-            assert sig_size == len(sig)
-            image[-sig_size:] = sig
-
-            e.content = image
-
-
-class EncryptedFIP(SignedFIP):
-    def __init__(self, root_priv_path, bl_priv_path, ldr_ek_path, bl_ek_path):
-        super().__init__(root_priv_path, bl_priv_path)
-
-        with open(ldr_ek_path, "rb") as fp:
-            self.ldr_ek = fp.read()
-
-        with open(bl_ek_path, "rb") as fp:
-            self.bl_ek = fp.read()
-
-    def _aes_encrypt(self, key, plain):
-        return AES.new(key, iv=IV_ZERO, mode=AES.MODE_CBC).encrypt(plain)
-
-    def encrypt(self):
-        logging.debug("encrypt:")
-
-        self.param1["FIP_FLAGS"].content = self.FIP_FLAGS_ENCRYPTED_MASK | self.param1["FIP_FLAGS"].toint()
-
-        self.param1["BL_EK"].content = self._aes_encrypt(self.ldr_ek, self.bl_ek)
-        self.body1["BL2"].content = self._aes_encrypt(self.bl_ek, self.body1["BL2"].content)
-
-        for name in ["BLCP_2ND", "MONITOR"]:
-            e = self.body2[name]
-            if not e.content:
-                continue
-
-            logging.info("encrypt %s: len=%#x", name, len(e.content))
-            e.content = self._aes_encrypt(self.bl_ek, e.content)
-
-        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
-        if loader_2nd_loadaddr:
-            logging.info("encrypt %s at %#x", "LOADER_2ND_LOADADDR", loader_2nd_loadaddr)
-
-            # Only data after header are encrypted
-            e = self.body2["LOADER_2ND"]
-
-            hdr_size = self._param_size(self.ldr_2nd_hdr)
-            hdr, body = e.content[:hdr_size], e.content[hdr_size:]
-
-            body = self._aes_encrypt(self.bl_ek, body)
-            e.content = hdr + body
-
-
-def sign_fip(args):
-    logging.debug("sign_fip:")
-
-    fip = SignedFIP(args.root_priv, args.bl_priv)
-    fip.read_fip(args.SRC_FIP)
-
-    fip.sign()
-
-    fip_bin = fip.make()
-    fip.print_fip_params()
-    with open(args.DEST_FIP, "wb") as fp:
-        fp.write(fip_bin)
-
-
-def encrypt_fip(args):
-    logging.debug("encrypt_fip:")
-
-    fip = EncryptedFIP(args.root_priv, args.bl_priv, args.ldr_ek, args.bl_ek)
-    fip.read_fip(args.SRC_FIP)
-
-    fip.sign()
-    fip.encrypt()
-
-    fip_bin = fip.make()
-    fip.print_fip_params()
-    with open(args.DEST_FIP, "wb") as fp:
-        fp.write(fip_bin)
-
-
-def parse_args():
-    parser = argparse.ArgumentParser(description="FIP tools")
-
-    parser.add_argument(
-        "-v",
-        "--verbose",
-        help="Increase output verbosity",
-        action="store_const",
-        const=logging.DEBUG,
-        default=logging.INFO,
-    )
-
-    def auto_int(x):
-        return int(x, 0)
-
-    subparsers = parser.add_subparsers(dest="subcmd", help="Sub-command help")
-
-    pr_encrypt = subparsers.add_parser("sign-enc")
-    pr_encrypt.set_defaults(func=encrypt_fip)
-    pr_encrypt.add_argument("--ldr-ek", type=str)
-    pr_encrypt.add_argument("--bl-ek", type=str)
-
-    pr_sign = subparsers.add_parser("sign")
-    pr_sign.set_defaults(func=sign_fip)
-
-    for pr in [pr_sign, pr_encrypt]:
-        pr.add_argument("--root-priv", type=str)
-        pr.add_argument("--bl-priv", type=str)
-        pr.add_argument("SRC_FIP", type=str, help="Source fip.bin")
-        pr.add_argument("DEST_FIP", type=str, help="Signed fip.bin")
-
-    if argcomplete:
-        argcomplete.autocomplete(parser)
-
-    args = parser.parse_args()
-    init_logging(stdout_level=args.verbose)
-    logging.info("PROG: %s", parser.prog)
-
-    if not args.subcmd:
-        parser.print_help()
-        raise SystemExit(1)
-
-    for a, v in sorted(vars(args).items()):
-        logging.debug("%s=%r", a, v)
-
-    return args
-
-
-def main():
-    args = parse_args()
-    args.func(args)
-
-
-if __name__ == "__main__":
-    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py
@ -1,802 +0,0 @@
-#!/usr/bin/env python3
-# PYTHON_ARGCOMPLETE_OK
-
-import sys
-import logging
-import os
-import os.path
-import argparse
-from collections import OrderedDict
-import binascii
-from struct import pack, unpack
-import lzma
-import pprint
-
-
-PYTHON_MIN_VERSION = (3, 5, 2)  # Ubuntu 16.04 LTS contains Python v3.5.2 by default
-
-
-if sys.version_info < PYTHON_MIN_VERSION:
-    print("Python >= %r is required" % (PYTHON_MIN_VERSION,))
-    sys.exit(-1)
-
-
-try:
-    import coloredlogs
-except ImportError:
-    coloredlogs = None
-
-try:
-    import argcomplete
-except ImportError:
-    argcomplete = None
-
-
-LOADER_2ND_MAGIC_ORIG = b"BL33"
-LOADER_2ND_MAGIC_LZMA = b"B3MA"
-LOADER_2ND_MAGIC_LZ4 = b"B3Z4"
-
-LOADER_2ND_MAGIC_LIST = [
-    LOADER_2ND_MAGIC_ORIG,
-    LOADER_2ND_MAGIC_LZMA,
-    LOADER_2ND_MAGIC_LZ4,
-]
-
-IMAGE_ALIGN = 512
-PARAM1_SIZE = 0x1000
-PARAM1_SIZE_WO_SIG = 0x800
-PARAM2_SIZE = 0x1000
-
-
-def round_up(divident, divisor):
-    return ((divident + divisor - 1) // divisor) * divisor
-
-
-def lzma_compress(body):
-    z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME)
-    compressed = z.compress(body)
-    compressed += z.flush()
-
-    return compressed
-
-
-def lz4_compress(body):
-    try:
-        import lz4.frame
-    except ImportError:
-        logging.error("lz4 is not installed. Run 'pip install lz4'.")
-        raise
-
-    compressed = lz4.frame.compress(body)
-    return compressed
-
-
-class Entry:
-    __slots__ = "name", "type", "addr", "_content", "entry_size"
-
-    def __init__(self):
-        self.addr = None
-        self._content = None
-
-    @property
-    def end(self):
-        return self.addr + self.entry_size
-
-    @property
-    def content(self):
-        return self._content
-
-    @content.setter
-    def content(self, value):
-        if type(value) == int:
-            value = value.to_bytes(self.entry_size, "little")
-
-        if self.entry_size is not None:
-            if len(value) > self.entry_size:
-                raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size))
-            value = value + b"\0" * (self.entry_size - len(value))
-
-        self._content = value
-
-    @classmethod
-    def make(cls, name, entry_size, _type, init=None):
-        entry = Entry()
-        entry.name = name
-        entry.type = _type
-        entry.entry_size = entry_size
-
-        if type(init) in (bytes, bytearray):
-            entry.content = bytes(init)
-        elif entry_size is not None:
-            entry.content = b"\0" * entry.entry_size
-        else:
-            entry.content = b""
-
-        return (name, entry)
-
-    def toint(self):
-        if self.type != int:
-            raise TypeError("%s is not int type" % self.name)
-
-        return int.from_bytes(self.content, "little")
-
-    def tostr(self):
-        v = self.content
-        if self.type == int:
-            v = "%#08x" % self.toint()
-        elif type(self.content) in [bytes, bytearray]:
-            v = v.hex()
-            if len(v) > 32:
-                v = v[:32] + "..."
-
-        return v
-
-    def __str__(self):
-        v = self.tostr()
-        return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size)
-
-    def __repr__(self):
-        v = self.tostr()
-        return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type)
-
-
-class FIP:
-    param1 = OrderedDict(
-        [
-            Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"),
-            Entry.make("MAGIC2", 4, int),
-            Entry.make("PARAM_CKSUM", 4, int),
-            Entry.make("NAND_INFO", 128, int),
-            Entry.make("NOR_INFO", 36, int),
-            Entry.make("FIP_FLAGS", 8, int),
-            Entry.make("CHIP_CONF_SIZE", 4, int),
-            Entry.make("BLCP_IMG_CKSUM", 4, int),
-            Entry.make("BLCP_IMG_SIZE", 4, int),
-            Entry.make("BLCP_IMG_RUNADDR", 4, int),
-            Entry.make("BLCP_PARAM_LOADADDR", 4, int),
-            Entry.make("BLCP_PARAM_SIZE", 4, int),
-            Entry.make("BL2_IMG_CKSUM", 4, int),
-            Entry.make("BL2_IMG_SIZE", 4, int),
-            Entry.make("BLD_IMG_SIZE", 4, int),
-            Entry.make("PARAM2_LOADADDR", 4, int),
-            Entry.make("RESERVED1", 4, int),
-            Entry.make("CHIP_CONF", 760, bytes),
-            Entry.make("BL_EK", 32, bytes),
-            Entry.make("ROOT_PK", 512, bytes),
-            Entry.make("BL_PK", 512, bytes),
-            Entry.make("BL_PK_SIG", 512, bytes),
-            Entry.make("CHIP_CONF_SIG", 512, bytes),
-            Entry.make("BL2_IMG_SIG", 512, bytes),
-            Entry.make("BLCP_IMG_SIG", 512, bytes),
-        ]
-    )
-
-    body1 = OrderedDict(
-        [
-            Entry.make("BLCP", None, bytes),
-            Entry.make("BL2", None, bytes),
-        ]
-    )
-
-    param2 = OrderedDict(
-        [
-            Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"),
-            Entry.make("PARAM2_CKSUM", 4, int),
-            Entry.make("RESERVED1", 4, bytes),
-            # DDR param
-            Entry.make("DDR_PARAM_CKSUM", 4, int),
-            Entry.make("DDR_PARAM_LOADADDR", 4, int),
-            Entry.make("DDR_PARAM_SIZE", 4, int),
-            Entry.make("DDR_PARAM_RESERVED", 4, int),
-            # BLCP_2ND
-            Entry.make("BLCP_2ND_CKSUM", 4, int),
-            Entry.make("BLCP_2ND_LOADADDR", 4, int),
-            Entry.make("BLCP_2ND_SIZE", 4, int),
-            Entry.make("BLCP_2ND_RUNADDR", 4, int),
-            # ATF-BL31 or OpenSBI
-            Entry.make("MONITOR_CKSUM", 4, int),
-            Entry.make("MONITOR_LOADADDR", 4, int),
-            Entry.make("MONITOR_SIZE", 4, int),
-            Entry.make("MONITOR_RUNADDR", 4, int),
-            # u-boot
-            Entry.make("LOADER_2ND_RESERVED0", 4, int),
-            Entry.make("LOADER_2ND_LOADADDR", 4, int),
-            Entry.make("LOADER_2ND_RESERVED1", 4, int),
-            Entry.make("LOADER_2ND_RESERVED2", 4, int),
-            # Reserved
-            Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes),
-        ]
-    )
-
-    body2 = OrderedDict(
-        [
-            Entry.make("DDR_PARAM", None, bytes),
-            Entry.make("BLCP_2ND", None, bytes),
-            Entry.make("MONITOR", None, bytes),
-            Entry.make("LOADER_2ND", None, bytes),
-        ]
-    )
-
-    ldr_2nd_hdr = OrderedDict(
-        [
-            Entry.make("JUMP0", 4, int),
-            Entry.make("MAGIC", 4, int),
-            Entry.make("CKSUM", 4, int),
-            Entry.make("SIZE", 4, int),
-            Entry.make("RUNADDR", 8, int),
-            Entry.make("RESERVED1", 4, int),
-            Entry.make("RESERVED2", 4, int),
-        ]
-    )
-
-    FIP_FLAGS_SCS_MASK = 0x000c
-    FIP_FLAGS_ENCRYPTED_MASK = 0x0030
-
-    def _param_size(self, param):
-        return max((e.end for e in param.values()))
-
-    def _gen_param(self):
-        addr = 0
-        for entry in self.param1.values():
-            entry.addr = addr
-            addr += entry.entry_size
-
-        assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr
-
-        addr = 0
-        for entry in self.param2.values():
-            entry.addr = addr
-            addr += entry.entry_size
-
-        assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size
-
-        addr = 0
-        for entry in self.ldr_2nd_hdr.values():
-            entry.addr = addr
-            addr += entry.entry_size
-
-    def __init__(self):
-        self.compress_algo = None
-        self._gen_param()
-
-    def image_crc(self, image):
-        crc = binascii.crc_hqx(image, 0)
-        crc = pack("<H", crc) + b"\xFE\xCA"
-        return crc
-
-    def pad(self, data, block_size):
-        if type(data) not in [bytearray, bytes]:
-            raise TypeError("Need bytearray or bytes")
-
-        r = len(data) % block_size
-        if r:
-            data += b"\0" * (block_size - r)
-
-        return data
-
-    def _pprint_attr(self, name):
-        v = getattr(self, name)
-
-        if type(v) == OrderedDict:
-            v = list(v.values())
-        logging.info("print(%s):\n" % name + pprint.pformat(v, 4, 140))
-
-    def print_fip_params(self):
-        self._pprint_attr("param1")
-        self._pprint_attr("param2")
-        self._pprint_attr("ldr_2nd_hdr")
-
-    def read_fip(self, path):
-        logging.debug("read_fip:")
-
-        with open(path, "rb") as fp:
-            fip_bin = fp.read()
-
-        fip_bin = bytearray(fip_bin)
-
-        e = self.param1["MAGIC1"]
-        if fip_bin[e.addr : e.end] != e.content:
-            raise ValueError("Unknown magic %r" % fip_bin[e.addr : e.end])
-
-        # Read param1 from fip.bin
-        for e in self.param1.values():
-            e.content = fip_bin[e.addr : e.end]
-
-        self.read_end = PARAM1_SIZE
-
-        # Read BLCP
-        e = self.param1["BLCP_IMG_SIZE"]
-        blcp_img_size = unpack("<I", fip_bin[e.addr : e.end])[0]
-        if blcp_img_size:
-            start = self.read_end
-            self.read_end = start + blcp_img_size
-            self.body1["BLCP"].content = fip_bin[start : self.read_end]
-
-        # Read FSBL as BL2
-        e = self.param1["BL2_IMG_SIZE"]
-        bl2_img_size = unpack("<I", fip_bin[e.addr : e.end])[0]
-        if bl2_img_size:
-            start = self.read_end
-            self.read_end = start + bl2_img_size
-            self.body1["BL2"].content = fip_bin[start : self.read_end]
-
-        logging.info("read_fip end=%#x", self.read_end)
-        self.rest_fip = fip_bin[self.read_end :]
-
-        self.read_fip2(fip_bin)
-
-    def read_fip2(self, fip_bin):
-        param2_loadaddr = self.param1["PARAM2_LOADADDR"].toint()
-        param2_bin = fip_bin[param2_loadaddr : param2_loadaddr + PARAM2_SIZE]
-
-        for e in self.param2.values():
-            e.content = param2_bin[e.addr : e.end]
-
-        self.read_end = param2_loadaddr + PARAM2_SIZE
-
-        # Read DDR_PARAM, BLCP_2ND, and MONITOR
-        for name in ["DDR_PARAM", "BLCP_2ND", "MONITOR"]:
-            size = self.param2[name + "_SIZE"].toint()
-            loadaddr = self.param2[name + "_LOADADDR"].toint()
-            self.body2[name].content = fip_bin[loadaddr : loadaddr + size]
-            self.read_end = loadaddr + size
-
-        # Read LOADER_2ND
-        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
-        if loader_2nd_loadaddr:
-            self.read_loader_2nd(fip_bin)
-
-        logging.info("read_fip2 end=%#x", self.read_end)
-        self.rest_fip = fip_bin[self.read_end :]
-
-    def read_loader_2nd(self, fip_bin):
-        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
-
-        self._parse_ldr_2nd_hdr(fip_bin[loader_2nd_loadaddr:])
-
-        if self.ldr_2nd_hdr["MAGIC"].content not in LOADER_2ND_MAGIC_LIST:
-            raise ValueError("%r" % self.ldr_2nd_hdr["MAGIC"].content)
-
-        ldr_2nd_size = self.ldr_2nd_hdr["SIZE"].toint()
-
-        self.body2["LOADER_2ND"].content = fip_bin[loader_2nd_loadaddr : loader_2nd_loadaddr + ldr_2nd_size]
-
-        self.read_end = loader_2nd_loadaddr + ldr_2nd_size
-        self.rest_fip = fip_bin[self.read_end :]
-
-    def add_chip_conf(self, args):
-        logging.debug("add_chip_conf:")
-
-        with open(args.CHIP_CONF, "rb") as fp:
-            image = fp.read()
-
-        if image.startswith(b"APLB"):
-            image = image[8:]  # strip old BLP header
-
-        self.param1["CHIP_CONF"].content = image
-
-    def add_blcp(self, args):
-        logging.debug("add_blcp:")
-
-        with open(args.BLCP, "rb") as fp:
-            image = fp.read()
-
-        image = self.pad(image, IMAGE_ALIGN)
-
-        self.param1["BLCP_IMG_RUNADDR"].content = args.BLCP_IMG_RUNADDR
-        self.body1["BLCP"].content = image
-
-    def add_bl2(self, args):
-        logging.debug("add_bl2:")
-
-        with open(args.BL2, "rb") as fp:
-            image = fp.read()
-
-        bl2_fill = 0
-        if args.BL2_FILL:
-            bl2_fill = args.BL2_FILL
-
-        image += b"\xA9" * (bl2_fill - len(image))
-        image = self.pad(image, IMAGE_ALIGN)
-
-        self.body1["BL2"].content = image
-
-    def add_nor_info(self, args):
-        logging.debug("add_nor_info:")
-        self.param1["NOR_INFO"].content = args.NOR_INFO
-
-    def add_nand_info(self, args):
-        logging.debug("add_nand_info:")
-        self.param1["NAND_INFO"].content = args.NAND_INFO
-
-    def update_param1_cksum(self, image):
-        image = bytearray(image)
-        crc = self.image_crc(image[self.param1["NAND_INFO"].addr : PARAM1_SIZE_WO_SIG])
-
-        param_cksum = self.param1["PARAM_CKSUM"]
-        param_cksum.content = crc
-        image[param_cksum.addr : param_cksum.end] = crc
-        return image
-
-    def make_fip1(self):
-        logging.debug("make_fip1:")
-
-        chip_conf = self.param1["CHIP_CONF"].content
-        self.param1["CHIP_CONF_SIZE"].content = len(chip_conf)
-
-        blcp = self.body1["BLCP"].content
-        self.param1["BLCP_IMG_CKSUM"].content = self.image_crc(blcp)
-        self.param1["BLCP_IMG_SIZE"].content = len(blcp)
-
-        bl2 = self.body1["BL2"].content
-        self.param1["BL2_IMG_CKSUM"].content = self.image_crc(bl2)
-        self.param1["BL2_IMG_SIZE"].content = len(bl2)
-
-        # Pack body1
-        body1_bin = b""
-        for entry in self.body1.values():
-            if len(entry.content) % IMAGE_ALIGN:
-                raise ValueError("%s (%d) is not align to %d" % (entry.name, len(entry.content), IMAGE_ALIGN))
-
-            logging.info("add %s (%#x)", entry.name, len(entry.content))
-            body1_bin += entry.content
-
-        logging.debug("len(body1_bin) is %d", len(body1_bin))
-
-        # Param1 cksum
-        param1_bin = b"".join((entry.content for entry in self.param1.values()))
-        param1_bin = self.update_param1_cksum(param1_bin)
-
-        if len(param1_bin) != PARAM1_SIZE:
-            raise ValueError("param1_bin is %d bytes" % len(param1_bin))
-
-        fip1_bin = param1_bin + body1_bin
-        logging.debug("len(fip1_bin) is %d", len(fip1_bin))
-
-        return fip1_bin
-
-    def add_ddr_param(self, args):
-        with open(args.DDR_PARAM, "rb") as fp:
-            ddr_param = fp.read()
-
-        logging.debug("ddr_param=%#x bytes", len(ddr_param))
-        self.body2["DDR_PARAM"].content = ddr_param
-
-    def add_blcp_2nd(self, args):
-        with open(args.BLCP_2ND, "rb") as fp:
-            blcp_2nd = fp.read()
-
-        logging.debug("blcp_2nd=%#x bytes", len(blcp_2nd))
-        self.body2["BLCP_2ND"].content = blcp_2nd
-
-    def add_monitor(self, args):
-        with open(args.MONITOR, "rb") as fp:
-            monitor = fp.read()
-
-        logging.debug("monitor=%#x bytes", len(monitor))
-        self.body2["MONITOR"].content = monitor
-
-    def add_loader_2nd(self, args):
-        with open(args.LOADER_2ND, "rb") as fp:
-            loader_2nd = fp.read()
-
-        logging.debug("loader_2nd=%#x bytes", len(loader_2nd))
-
-        e = self.ldr_2nd_hdr["MAGIC"]
-        magic = loader_2nd[e.addr : e.end]
-        if magic != LOADER_2ND_MAGIC_ORIG:
-            raise ValueError("loader_2nd's magic should be %r, but %r" % (LOADER_2ND_MAGIC_ORIG, magic))
-
-        self.compress_algo = args.compress
-        self.body2["LOADER_2ND"].content = loader_2nd
-
-    def pack_ddr_param(self, fip_bin):
-        if not len(self.body2["DDR_PARAM"].content):
-            return
-
-        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
-
-        # Pack DDR_PARAM to body2
-        ddr_param = self.pad(self.body2["DDR_PARAM"].content, IMAGE_ALIGN)
-
-        self.param2["DDR_PARAM_CKSUM"].content = self.image_crc(ddr_param)
-        self.param2["DDR_PARAM_SIZE"].content = len(ddr_param)
-        self.param2["DDR_PARAM_LOADADDR"].content = len(fip_bin)
-
-        return fip_bin + ddr_param
-
-    def pack_blcp_2nd(self, fip_bin, blcp_2nd_runaddr):
-        logging.debug("pack_blcp_2nd:")
-        if not len(self.body2["BLCP_2ND"].content):
-            return
-
-        runaddr = int(blcp_2nd_runaddr)
-
-        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
-
-        # Pack MONITOR to body2
-        body = self.pad(self.body2["BLCP_2ND"].content, IMAGE_ALIGN)
-
-        self.param2["BLCP_2ND_CKSUM"].content = self.image_crc(body)
-        self.param2["BLCP_2ND_SIZE"].content = len(body)
-        self.param2["BLCP_2ND_LOADADDR"].content = len(fip_bin)
-        self.param2["BLCP_2ND_RUNADDR"].content = runaddr
-
-        return fip_bin + body
-
-    def pack_monitor(self, fip_bin, monitor_runaddr):
-        logging.debug("pack_monitor:")
-        if not len(self.body2["MONITOR"].content):
-            return
-
-        monitor_runaddr = int(monitor_runaddr)
-
-        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
-
-        # Pack MONITOR to body2
-        monitor = self.pad(self.body2["MONITOR"].content, IMAGE_ALIGN)
-
-        self.param2["MONITOR_CKSUM"].content = self.image_crc(monitor)
-        self.param2["MONITOR_SIZE"].content = len(monitor)
-        self.param2["MONITOR_LOADADDR"].content = len(fip_bin)
-        self.param2["MONITOR_RUNADDR"].content = monitor_runaddr
-
-        return fip_bin + monitor
-
-    def _parse_ldr_2nd_hdr(self, image):
-        for e in self.ldr_2nd_hdr.values():
-            e.content = image[e.addr : e.end]
-
-    def _update_ldr_2nd_hdr(self):
-        image = self.body2["LOADER_2ND"].content
-        hdr_size = self._param_size(self.ldr_2nd_hdr)
-        hdr, body = image[:hdr_size], image[hdr_size:]
-
-        # Update SIZE
-        self.ldr_2nd_hdr["SIZE"].content = len(image)
-
-        # Update CKSUM
-        hdr = bytearray(b"".join((e.content for e in self.ldr_2nd_hdr.values())))
-        # CKSUM is calculated after "CKSUM" field
-        hdr_cksum = self.ldr_2nd_hdr["CKSUM"]
-        crc = self.image_crc((hdr + body)[hdr_cksum.end :])
-        hdr_cksum.content = crc
-        hdr = bytearray(b"".join((e.content for e in self.ldr_2nd_hdr.values())))
-
-        self.body2["LOADER_2ND"].content = hdr + body
-
-    def _compress_ldr_2nd(self):
-        image = self.body2["LOADER_2ND"].content
-        hdr_size = self._param_size(self.ldr_2nd_hdr)
-        hdr, body = image[:hdr_size], image[hdr_size:]
-
-        magic = self.ldr_2nd_hdr["MAGIC"].content
-        if magic == LOADER_2ND_MAGIC_ORIG:
-            # if image is uncompressed, compress it.
-            if self.compress_algo is None:
-                pass
-            elif self.compress_algo == "lzma":
-                self.ldr_2nd_hdr["MAGIC"].content = LOADER_2ND_MAGIC_LZMA
-                body = lzma_compress(body)
-                logging.info("lzma loader_2nd=%#x bytes wo header", len(body))
-            elif self.compress_algo == "lz4":
-                self.ldr_2nd_hdr["MAGIC"].content = LOADER_2ND_MAGIC_LZ4
-                body = lz4_compress(body)
-                logging.info("lz4 loader_2nd=%#x bytes wo header", len(body))
-            else:
-                raise NotImplementedError("'%r' is not supported." % self.compress_algo)
-        elif magic in LOADER_2ND_MAGIC_LIST:
-            logging.info("loader_2nd is already compressed")
-        else:
-            raise ValueError("unknown loader_2nd magic (%r)", magic)
-
-        self.body2["LOADER_2ND"].content = self.pad(hdr + body, IMAGE_ALIGN)
-
-    def pack_loader_2nd(self, fip_bin):
-        logging.debug("pack_loader_2nd:")
-        if not len(self.body2["LOADER_2ND"].content):
-            return
-
-        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
-        self.param2["LOADER_2ND_LOADADDR"].content = len(fip_bin)
-
-        self._parse_ldr_2nd_hdr(self.body2["LOADER_2ND"].content)
-        self._compress_ldr_2nd()
-        self._update_ldr_2nd_hdr()
-
-        # Append LOADER_2ND to body2
-        return fip_bin + self.body2["LOADER_2ND"].content
-
-    def insert_param1(self, fip_bin, name, value):
-        fip_bin = bytearray(fip_bin)
-        e = self.param1[name]
-        e.content = value
-        fip_bin[e.addr : e.end] = value
-        return self.update_param1_cksum(fip_bin)
-
-    def append_fip2(self, fip1_bin, args):
-        logging.debug("make_fip2:")
-        fip_bin = bytearray(fip1_bin)
-
-        # Update PARAM2_LOADADDR
-        param2_loadaddr = len(fip1_bin)
-        fip_bin = self.insert_param1(fip_bin, "PARAM2_LOADADDR", pack("<I", param2_loadaddr))
-
-        # Add an empty PARAM2
-        fip_bin += b"\0" * PARAM2_SIZE
-
-        # Pack body
-        fip_bin = self.pack_ddr_param(fip_bin)
-
-        if len(self.body2["BLCP_2ND"].content):
-            runaddr = self.param2["BLCP_2ND_RUNADDR"].toint()
-            if not runaddr:
-                runaddr = int(args.BLCP_2ND_RUNADDR)
-            fip_bin = self.pack_blcp_2nd(fip_bin, runaddr)
-
-        if len(self.body2["MONITOR"].content):
-            runaddr = self.param2["MONITOR_RUNADDR"].toint()
-            if not runaddr:
-                runaddr = int(args.MONITOR_RUNADDR)
-            fip_bin = self.pack_monitor(fip_bin, runaddr)
-
-        if len(self.body2["LOADER_2ND"].content):
-            fip_bin = self.pack_loader_2nd(fip_bin)
-
-        # Pack param2_bin
-        param2_bin = b"".join((entry.content for entry in self.param2.values()))
-        self.param2["PARAM2_CKSUM"].content = self.image_crc(param2_bin[self.param2["PARAM2_CKSUM"].end :])
-        param2_bin = b"".join((entry.content for entry in self.param2.values()))  # update cksum
-
-        logging.debug("len(param2_bin) is %d", len(param2_bin))
-        assert len(param2_bin) == PARAM2_SIZE
-
-        fip_bin[param2_loadaddr : param2_loadaddr + PARAM2_SIZE] = param2_bin
-
-        return fip_bin
-
-    def make(self, args=None):
-        fip_bin = self.make_fip1()
-        if len(self.body2["DDR_PARAM"].content):
-            fip_bin = self.append_fip2(fip_bin, args)
-
-        logging.info("generated fip_bin is %d bytes", len(fip_bin))
-
-        if getattr(self, "rest_fip", None):
-            logging.error("the rest of fip is not used: %#x bytes ", len(self.rest_fip))
-
-        return fip_bin
-
-
-METHODS = {
-    "NOR_INFO": FIP.add_nor_info,
-    "NAND_INFO": FIP.add_nand_info,
-    "CHIP_CONF": FIP.add_chip_conf,
-    "BLCP": FIP.add_blcp,
-    "BL2": FIP.add_bl2,
-    "DDR_PARAM": FIP.add_ddr_param,
-    "BLCP_2ND": FIP.add_blcp_2nd,
-    "MONITOR": FIP.add_monitor,
-    "LOADER_2ND": FIP.add_loader_2nd,
-}
-
-
-def generate_fip(args):
-    logging.debug("generate_fip:")
-    fip = FIP()
-
-    if args.OLD_FIP:
-        fip.read_fip(args.OLD_FIP)
-
-    for m, f in METHODS.items():
-        if getattr(args, m):
-            f(fip, args)
-
-    fip_bin = fip.make(args)
-    fip.print_fip_params()
-
-    if args.output:
-        with open(args.output, "wb") as fp:
-            fp.write(fip_bin)
-
-
-def parse_args():
-    parser = argparse.ArgumentParser(description="FIP tools")
-
-    parser.add_argument(
-        "-v",
-        "--verbose",
-        help="Increase output verbosity",
-        action="store_const",
-        const=logging.DEBUG,
-        default=logging.INFO,
-    )
-
-    subparsers = parser.add_subparsers(dest="subcmd", help="Sub-command help")
-    pr_gen = subparsers.add_parser("genfip", help="Generate keys")
-
-    for name in list(METHODS):
-        if name in ["NOR_INFO", "NAND_INFO"]:
-            pr_gen.add_argument("--" + name, type=bytes.fromhex)
-        else:
-            pr_gen.add_argument("--" + name, dest=name, type=str, help="Add %s into FIP" % name)
-
-    def auto_int(x):
-        return int(x, 0)
-
-    pr_gen.add_argument("--BLCP_IMG_RUNADDR", type=auto_int)
-    pr_gen.add_argument("--BLCP_PARAM_LOADADDR", type=auto_int)
-
-    pr_gen.add_argument("--BLCP_2ND_RUNADDR", type=auto_int)
-
-    pr_gen.add_argument("--MONITOR_RUNADDR", type=auto_int)
-
-    pr_gen.add_argument("--compress", choices=["lzma", "lz4", ""])
-
-    pr_gen.add_argument("--OLD_FIP", type=str)
-    pr_gen.add_argument("--BLOCK_SIZE", type=auto_int)
-    pr_gen.add_argument("--BL2_FILL", type=auto_int)
-
-    pr_gen.add_argument("output", type=str, help="Output filename")
-
-    pr_gen.set_defaults(func=generate_fip)
-
-    if argcomplete:
-        argcomplete.autocomplete(parser)
-
-    args = parser.parse_args()
-    init_logging(stdout_level=args.verbose)
-    logging.info("PROG: %s", parser.prog)
-
-    if not args.subcmd:
-        parser.print_help()
-        raise SystemExit(1)
-
-    for a, v in sorted(vars(args).items()):
-        logging.debug("  %s=%r", a, v)
-
-    return args
-
-
-def main():
-    args = parse_args()
-    args.func(args)
-
-
-def init_logging(log_file=None, file_level="DEBUG", stdout_level="WARNING"):
-    root_logger = logging.getLogger()
-    root_logger.setLevel(logging.NOTSET)
-
-    fmt = "%(asctime)s %(levelname)8s:%(name)s:%(message)s"
-
-    if log_file is not None:
-        file_handler = logging.FileHandler(log_file, encoding="utf-8")
-        file_handler.setFormatter(logging.Formatter(fmt))
-        file_handler.setLevel(file_level)
-        root_logger.addHandler(file_handler)
-
-    if coloredlogs:
-        os.environ["COLOREDLOGS_DATE_FORMAT"] = "%H:%M:%S"
-
-        field_styles = {
-            "asctime": {"color": "green"},
-            "hostname": {"color": "magenta"},
-            "levelname": {"color": "black", "bold": True},
-            "name": {"color": "blue"},
-            "programname": {"color": "cyan"},
-        }
-
-        level_styles = coloredlogs.DEFAULT_LEVEL_STYLES
-        level_styles["debug"]["color"] = "cyan"
-
-        coloredlogs.install(
-            level=stdout_level,
-            fmt=fmt,
-            field_styles=field_styles,
-            level_styles=level_styles,
-            milliseconds=True,
-        )
-
-
-if __name__ == "__main__":
-    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk
@ -1,85 +0,0 @@
-#
-# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Enable workarounds for selected Cortex-A53 errata
-ERRATA_A53_835769	:=	1
-ERRATA_A53_843419	:=	1
-ERRATA_A53_855873	:=	1
-
-PAGE_SIZE_64KB := 1
-TEST_FROM_SPINOR1 := 0
-
-DEFINES += -DLZ4_USER_MEMORY_FUNCTIONS=1
-
-# ifeq ($(FSBL_SECURE_BOOT_SUPPORT),1)
-DEFINES += \
-	-DNO_ALLOCS \
-	-DARGTYPE=3 \
-	-DLTC_NO_FILE \
-	-DLTM_NO_FILE \
-	-DLTM_DESC \
-	-DLTC_SOURCE
-
-CRYPT_INCLUDES := \
-	-Ilib/libtommath \
-	-Ilib/libtomcrypt/src/headers \
-	-Ilib/BigDigits
-
-CRYPT_SOURCES := \
-	lib/BigDigits/bigdigits.c \
-	lib/libtomcrypt/src/hashes/sha2/sha256.c
-# endif
-
-INCLUDES += \
-	-Iinclude \
-	${CPU_INCLUDES} \
-	-Iplat/ \
-	-Iplat/${CHIP_ARCH}/include/uart \
-	-Iplat/${CHIP_ARCH}/include/usb \
-	-Iplat/${CHIP_ARCH}/include \
-	-Iplat/${CHIP_ARCH}/include/${BOOT_CPU} \
-	-Ilib/utils \
-	-Ilib/lzma \
-	-Ilib/lz4 \
-	-Ilib/crc \
-	${STDLIB_INCLUDES} \
-	${CRYPT_INCLUDES}
-
-#BL_COMMON_SOURCES = \
-	${CPU_SOURCES} \
-	lib/tf_printf/tf_printf.c \
-	plat/${CHIP_ARCH}/platform.c \
-	plat/${CHIP_ARCH}/security/security.c \
-	${STDLIB_SRCS} \
-	${CRYPT_SOURCES}
-
-#DECOMPRESSION_SOURCES = \
-	lib/lzma/LzmaDec.c \
-	lib/lz4/lz4_all.c \
-	lib/lz4/xxhash.c
-
-#BL2_SRCS = \
-	${BL_COMMON_SOURCES} \
-	plat/${CHIP_ARCH}/platform_device.c \
-	plat/${CHIP_ARCH}/bl2/bl2_opt.c \
-	lib/utils/decompress.c \
-	plat/${CHIP_ARCH}/usb/cps_cvi.c  \
-	plat/${CHIP_ARCH}/usb/usb_tty.c  \
-	plat/${CHIP_ARCH}/usb/dwc2_udc_otg.c  \
-	plat/${CHIP_ARCH}/usb/dwc2_udc_otg_xfer_dma.c  \
-	plat/${CHIP_ARCH}/usb/cv_usb.c  \
-	lib/crc/crc16.c \
-	${DECOMPRESSION_SOURCES}
-
-BL2_SOURCES = \
-	${BL2_CPU_SOURCES} \
-	${BL2_SRCS} \
-	plat/${CHIP_ARCH}/bl2/bl2_main.c
-
-#include plat/${CHIP_ARCH}/ddr/ddr.mk
-
-BL2_LINKERFILE := plat/${CHIP_ARCH}/bl2/bl2.ld.S
-BL2_RLS_OBJS := plat/${CHIP_ARCH}/bl2_objs/${PROJECT_FULLNAME}/bl2/*.o
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp_param.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp_param.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm
@ -1,16 +0,0 @@
-sys.up
-
-; Reset
-break;
-WAIT !ISRUN() ;wait until target stop
-
-; MWriteS32 PM:0x0C000000++0x3ffff 0x14000000
-MWriteS32 PM:0x4400000++0xf 0x14000000
-MWriteS32 0x4400000++0xf 0x14000000
-Register.Set pc 0x04400000
-
-; MWriteS32 PM:0x03000008 0x4 // wdt reset enable
-; MWriteS32 PM:0x03010004 0x1 // Set timeout range reigster
-; MWriteS32 PM:0x0301000c 0x76 // Counter restart register
-; MWriteS32 PM:0x03010000 0x13
-print "CLEAR ROM"
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm
@ -1,14 +0,0 @@
-DO up.cmm
-
-MWriteS32 PM:0x4400000++0xf 0x14000000
-MWriteS32 PM:0x4418000++0xf 0x6F
-Register.Set pc 0x04400000
-print "clear ROM"
-
-LoadBINARY ..\cv181x_c906b_bl1.bin 0x04418000 %S32
-print "C906B BL1 loaded"
-
-Data.Set PM:0x3003024 %LONG Data.Long(PM:0x3003024)|(1<<5)
-print "Release C906B"
-
-END
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm
@ -1,13 +0,0 @@
-DO up.cmm
-
-MWriteS32 PM:0x4400000++0xf 0x14000000
-Register.Set pc 0x04400000
-print "clear ROM"
-
-LoadBINARY ..\cv181x_ca53_bl1.bin 0x04400000 %S32
-print "CA53 BL1 loaded"
-
-Register.Set r0 0
-Register.Set pc 0x04400000
-
-END
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm
@ -1,40 +0,0 @@
-
-;winclear
-system.reset
-translation.reset
-
-system.cpu cortexa53
-system.config debugaccessport 0
-system.config apbaccessport 0
-system.config axiaccessport 1
-system.config memoryaccessport 1
-; set corenumber first
-sys.config corenumber 1
-; then set corebase and ctibase
-sys.config corebase 0x81010000
-sys.config ctibase  0x81020000
-sys.jc 5mhz
-
-Wait 10.ms
-system.option enreset on
-system.option trst on
-system.option resetbreak on
-system.option waitreset 500.ms
-OPTION.SerialWire ON
-
-sys.down
-Wait 50.ms
-sys.up
-
-if system.up()
-(
-	; data.list
-)
-else
-(
-	dialog.ok "system.up failed"
-)
-
-; Reset
-break;
-WAIT !ISRUN() ;wait until target stop
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_c906b_bl1.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_c906b_bl1.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/ddr_param.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/ddr_param.bin
--- a/bsp/cvitek/pre-build/fsbl/test/empty.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/empty.bin
--- a/bsp/cvitek/pre-build/fw_dynamic.bin
+++ b/bsp/cvitek/pre-build/fw_dynamic.bin
--- a/bsp/cvitek/pre-build/u-boot-raw.bin
+++ b/bsp/cvitek/pre-build/u-boot-raw.bin