diff --git a/bsp/cvitek/.gitignore b/bsp/cvitek/.gitignore index 97d926d957..93694d216f 100755 --- a/bsp/cvitek/.gitignore +++ b/bsp/cvitek/.gitignore @@ -1,2 +1,6 @@ +cvitek_bootloader fip.bin -boot.sd \ No newline at end of file +boot.sd +output +c906_little/board/script +Image.lzma \ No newline at end of file diff --git a/bsp/cvitek/README.md b/bsp/cvitek/README.md index d9c7ae1077..a343b557ce 100755 --- a/bsp/cvitek/README.md +++ b/bsp/cvitek/README.md @@ -8,7 +8,7 @@ | 芯片名称 | 芯片架构 | 内存大小 | 默认日志串口 | 备注 | | ------- | ------- |------- | -------- | -------- | -| cv1800b | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 | +| cv180x | RISC-V C906 | 64MByte | uart0 | 默认开启 MMU，运行 RT-SMART 模式 | - 小核 @@ -18,10 +18,30 @@ > 注：异构芯片需单独编译每个核的 OS +## 编译 +异构芯片需单独编译每个核的 OS，在大/小核对应的目录下，依次执行: + +1. 开发板选择 +Linux平台下，可以先执行： +```shell +$ scons --menuconfig +``` + +选择当前需要编译的目标开发板类型 +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + (X) milkv-duo256m +``` + +2. 编译 +```shell +$ scons +``` ## 运行 -编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 +编译成功后，会在 `bsp/cvitek/output` 对应开发板型号目录下自动生成 `fip.bin` 和 `boot.sd` 文件，其中大核运行文件在 `boot.sd` 中，小核的运行文件在 `fip.bin` 中。 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 2. 将根目录下的 `fip.bin` 和 `boot.sd` 复制 SD 卡第一个分区中。 @@ -39,10 +59,22 @@ ## 支持开发板 - milk-v duo: [https://milkv.io/duo](https://milkv.io/duo) +- milk-v duo256m: [https://milkv.io/duo256m](https://milkv.io/docs/duo/getting-started/duo256m) ## FAQ 1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。 +2. 错误：./mkimage: error while loading shared libraries: libssl.so.1.1: cannot open shared object file: No such file or directory + +可在 [http://security.ubuntu.com/ubuntu/pool/main/o/openssl](http://security.ubuntu.com/ubuntu/pool/main/o/openssl) 下载 `libssl1.1_1.1.1f-1ubuntu2_amd64.deb` 文件后安装即可解决。 +或使用以下命令下载安装: +```shell +$ wget http://security.ubuntu.com/ubuntu/pool/main/o/openssl/libssl1.1_1.1.1f-1ubuntu2_amd64.deb +$ sudo dpkg -i libssl1.1_1.1.1f-1ubuntu2_amd64.deb +``` + ## 联系人信息 -维护人：[flyingcys](https://github.com/flyingcys) \ No newline at end of file +维护人：[flyingcys](https://github.com/flyingcys) + +更多信息请参考 [https://riscv-rtthread-programming-manual.readthedocs.io](https://riscv-rtthread-programming-manual.readthedocs.io) \ No newline at end of file diff --git a/bsp/cvitek/c906_little/.config b/bsp/cvitek/c906_little/.config index 56756b1f7d..4e65cfbb5f 100644 --- a/bsp/cvitek/c906_little/.config +++ b/bsp/cvitek/c906_little/.config @@ -1001,6 +1001,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set # # Display @@ -1087,3 +1088,5 @@ CONFIG_BSP_USING_C906_LITTLE=y CONFIG_PLIC_PHY_ADDR=0x70000000 CONFIG_IRQ_MAX_NR=128 CONFIG_TIMER_CLK_FREQ=25000000 +# CONFIG_BOARD_TYPE_MILKV_DUO is not set +CONFIG_BOARD_TYPE_MILKV_DUO256M=y diff --git a/bsp/cvitek/c906_little/Kconfig b/bsp/cvitek/c906_little/Kconfig index 2e6980adea..a759cc313d 100755 --- a/bsp/cvitek/c906_little/Kconfig +++ b/bsp/cvitek/c906_little/Kconfig @@ -37,4 +37,14 @@ config IRQ_MAX_NR config TIMER_CLK_FREQ int - default 25000000 \ No newline at end of file + default 25000000 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO256M + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" + config BOARD_TYPE_MILKV_DUO256M + bool "milkv-duo256m" +endchoice diff --git a/bsp/cvitek/c906_little/README.md b/bsp/cvitek/c906_little/README.md index 71a3d6135d..5f7e0e8591 100755 --- a/bsp/cvitek/c906_little/README.md +++ b/bsp/cvitek/c906_little/README.md @@ -17,20 +17,37 @@ $ export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin ``` ## 编译 -1. Linux平台下，可以先执行： +1. 依赖安装 + +```shell +$ sudo apt install -y scons libncurses5-dev wget flex bison +``` + + +2. Linux平台下，先执行： ```shell $ scons --menuconfig ``` -它会自动下载env相关脚本到~/.env目录，然后执行 +选择当前需要编译的目标开发板类型 +```shell +Board Type (milkv-duo) ---> + ( ) milkv-duo + (X) milkv-duo256m +``` + +它会自动下载 env 相关脚本到 ~/.env 目录，然后执行 ```shell $ source ~/.env/env.sh $ pkgs --update ``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf 文件。 编译完成后脚本自动调用 `combine-fip.sh` 脚本进行打包，并生成 `fip.sd`, 该文件即为 SD 卡启动的 c906_little 文件。 +第一次调用 `combine-fip.sh` 脚本时会自动下载打包需要的 `opsbsbi`、`fsbl`、`uboot` 等相关文件至 `bsp/cvitek/cvitek_bootloader` 目录，请耐心等待。 + +下载完成后会自动解压、编译，后续再次编译同一类型开发板只会调用相关文件打包合成 `fip.bin`。如需手工编译相关 `cvitek_bootloader` 文件，可在 `bsp/cvitek/cvitek_bootloader` 目录下执行 `bash build.sh lunch` 选择对应的开发板编译。 ## 运行 1. 将 SD 卡分为 2 个分区，第 1 个分区用于存放 bin 文件，第 2 个分区用于作为数据存储分区，分区格式为 `FAT32`。 diff --git a/bsp/cvitek/c906_little/SConstruct b/bsp/cvitek/c906_little/SConstruct index b331ef4db8..0a1878479d 100755 --- a/bsp/cvitek/c906_little/SConstruct +++ b/bsp/cvitek/c906_little/SConstruct @@ -37,5 +37,9 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) # include libraries objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0)) +if GetDepend('BOARD_TYPE_MILKV_DUO256M'): + env['LINKFLAGS'] = env['LINKFLAGS'].replace('cv180x_lscript.ld', 'cv181x_lscript.ld') + env['LINKFLAGS'] = env['LINKFLAGS'].replace('-L board/script/cv180x', '-L board/script/cv181x') + # make a building DoBuilding(TARGET, objs) diff --git a/bsp/cvitek/c906_little/cv180x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld similarity index 98% rename from bsp/cvitek/c906_little/cv180x_lscript.ld rename to bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld index 180e319311..a91067f725 100755 --- a/bsp/cvitek/c906_little/cv180x_lscript.ld +++ b/bsp/cvitek/c906_little/board/script/cv180x/cv180x_lscript.ld @@ -7,6 +7,8 @@ * Date Author Notes * 2024/01/11 flyingcys The first version */ +INCLUDE ./cvi_board_memmap.ld + _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; /* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ /*_HEAP_SIZE = 0x20000;*/ @@ -15,9 +17,6 @@ _EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; _EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; -CVIMMAP_FREERTOS_ADDR = 0x83f40000; -CVIMMAP_FREERTOS_SIZE = 0xc0000; - /* Define Memories in the system */ MEMORY diff --git a/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld new file mode 100755 index 0000000000..9f2f155826 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv180x/cvi_board_memmap.ld @@ -0,0 +1,30 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x82473000; +CVIMMAP_BOOTLOGO_SIZE = 0x0; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82300000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x813ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x4000000; +CVIMMAP_FREERTOS_ADDR = 0x83f40000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x0; +CVIMMAP_FREERTOS_SIZE = 0xc0000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x83f40000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81400000; +CVIMMAP_FSBL_UNZIP_SIZE = 0xf00000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x82473000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x0; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x82473000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x82473000; +CVIMMAP_ION_SIZE = 0x1acd000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x82473000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x0; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0x3f40000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81400000; +CVIMMAP_UIMAG_SIZE = 0xf00000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld new file mode 100755 index 0000000000..a91067f725 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cv181x_lscript.ld @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/01/11 flyingcys The first version + */ +INCLUDE ./cvi_board_memmap.ld + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x20000; +/* _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; */ +/*_HEAP_SIZE = 0x20000;*/ + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_ddr_0_MEM_0 : ORIGIN = CVIMMAP_FREERTOS_ADDR , LENGTH = CVIMMAP_FREERTOS_SIZE +} + +/* Specify the default entry point to the program */ + +/*ENTRY(_vector_table)*/ +ENTRY(_start) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; +} > psu_ddr_0_MEM_0 + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_ddr_0_MEM_0 + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_ddr_0_MEM_0 + +.interp : { + KEEP (*(.interp)) +} > psu_ddr_0_MEM_0 + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_ddr_0_MEM_0 + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.srodata*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_ddr_0_MEM_0 + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_ddr_0_MEM_0 + +.data : { + . = ALIGN(64); + _data = .; + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + _edata = .; +} > psu_ddr_0_MEM_0 + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_ddr_0_MEM_0 + +.got : { + *(.got) +} > psu_ddr_0_MEM_0 + +.got1 : { + *(.got1) +} > psu_ddr_0_MEM_0 + +.got2 : { + *(.got2) +} > psu_ddr_0_MEM_0 + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_ddr_0_MEM_0 + +.eh_frame : { + *(.eh_frame) +} > psu_ddr_0_MEM_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_ddr_0_MEM_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_ddr_0_MEM_0 + +.bss (NOLOAD) : { + . = ALIGN(64); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + _ebss = .; +} > psu_ddr_0_MEM_0 + +/*_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );*/ + _data_lma = LOADADDR(.data); + +/* Generate Stack and Heap definitions */ +.stack (NOLOAD) : { + . = ALIGN(64); + _stack_end_end = .; + . += _STACK_SIZE; + _stack_top = .; + __rt_rvstack = .; +} > psu_ddr_0_MEM_0 + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + *(.heap*) + /*. += _HEAP_SIZE;*/ + /*_heap_size = _HEAP_SIZE; */ + _heap_end = .; + HeapLimit = .; +} > psu_ddr_0_MEM_0 + +HeapLimit = ORIGIN(psu_ddr_0_MEM_0) + LENGTH(psu_ddr_0_MEM_0); +_end = .; +} + diff --git a/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld new file mode 100755 index 0000000000..d2b8744044 --- /dev/null +++ b/bsp/cvitek/c906_little/board/script/cv181x/cvi_board_memmap.ld @@ -0,0 +1,32 @@ +CONFIG_SYS_TEXT_BASE = 0x80200000; +CVIMMAP_ATF_SIZE = 0x80000; +CVIMMAP_BOOTLOGO_ADDR = 0x8b13e000; +CVIMMAP_BOOTLOGO_SIZE = 0x1c2000; +CVIMMAP_CONFIG_SYS_INIT_SP_ADDR = 0x82800000; +CVIMMAP_CVI_UPDATE_HEADER_ADDR = 0x817ffc00; +CVIMMAP_CVI_UPDATE_HEADER_SIZE = 0x400; +CVIMMAP_DRAM_BASE = 0x80000000; +CVIMMAP_DRAM_SIZE = 0x10000000; +CVIMMAP_FRAMEBUFFER_ADDR = 0x8b13e000; +CVIMMAP_FRAMEBUFFER_SIZE = 0x1c2000; +CVIMMAP_FREERTOS_ADDR = 0x8fe00000; +CVIMMAP_FREERTOS_RESERVED_ION_SIZE = 0x1600000; +CVIMMAP_FREERTOS_SIZE = 0x200000; +CVIMMAP_FSBL_C906L_START_ADDR = 0x8fe00000; +CVIMMAP_FSBL_UNZIP_ADDR = 0x81800000; +CVIMMAP_FSBL_UNZIP_SIZE = 0x1000000; +CVIMMAP_H26X_BITSTREAM_ADDR = 0x8b300000; +CVIMMAP_H26X_BITSTREAM_SIZE = 0x200000; +CVIMMAP_H26X_ENC_BUFF_ADDR = 0x8b500000; +CVIMMAP_H26X_ENC_BUFF_SIZE = 0x0; +CVIMMAP_ION_ADDR = 0x8b300000; +CVIMMAP_ION_SIZE = 0x4b00000; +CVIMMAP_ISP_MEM_BASE_ADDR = 0x8b500000; +CVIMMAP_ISP_MEM_BASE_SIZE = 0x1400000; +CVIMMAP_KERNEL_MEMORY_ADDR = 0x80000000; +CVIMMAP_KERNEL_MEMORY_SIZE = 0xfe00000; +CVIMMAP_MONITOR_ADDR = 0x80000000; +CVIMMAP_OPENSBI_FDT_ADDR = 0x80080000; +CVIMMAP_OPENSBI_SIZE = 0x80000; +CVIMMAP_UIMAG_ADDR = 0x81800000; +CVIMMAP_UIMAG_SIZE = 0x1000000; \ No newline at end of file diff --git a/bsp/cvitek/c906_little/rtconfig.h b/bsp/cvitek/c906_little/rtconfig.h index 40db54549b..d4fced8b33 100755 --- a/bsp/cvitek/c906_little/rtconfig.h +++ b/bsp/cvitek/c906_little/rtconfig.h @@ -268,5 +268,6 @@ #define PLIC_PHY_ADDR 0x70000000 #define IRQ_MAX_NR 128 #define TIMER_CLK_FREQ 25000000 +#define BOARD_TYPE_MILKV_DUO256M #endif diff --git a/bsp/cvitek/c906_little/rtconfig.py b/bsp/cvitek/c906_little/rtconfig.py index dd7ed95f05..50c32d5561 100755 --- a/bsp/cvitek/c906_little/rtconfig.py +++ b/bsp/cvitek/c906_little/rtconfig.py @@ -18,7 +18,7 @@ if os.getenv('RTT_CC'): if CROSS_TOOL == 'gcc': PLATFORM = 'gcc' - EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin' + EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' else: print('Please make sure your toolchains is GNU GCC!') exit(0) @@ -47,9 +47,10 @@ if PLATFORM == 'gcc': CFLAGS += ' -DCONFIG_64BIT' LINKER_SCRIPTS = r'cv180x_lscript.ld' + LINKER_SCRIPTS_PATH = r' -L board/script/cv180x' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LFLAGS = DEVICE + ' -nostartfiles -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS + LINKER_SCRIPTS_PATH CPATH = '' LPATH = '' @@ -63,4 +64,4 @@ if PLATFORM == 'gcc': DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -POST_ACTION += 'cd .. && ./combine-fip.sh c906_little/rtthread.bin\n' \ No newline at end of file +POST_ACTION += 'cd .. && bash combine-fip.sh ' + os.getcwd() + ' rtthread.bin' + ' \n' \ No newline at end of file diff --git a/bsp/cvitek/combine-fip.sh b/bsp/cvitek/combine-fip.sh index fee521077c..82e2edf5b1 100755 --- a/bsp/cvitek/combine-fip.sh +++ b/bsp/cvitek/combine-fip.sh @@ -1,23 +1,84 @@ #!/bin/bash -set -e +PROJECT_PATH=$1 +IMAGE_NAME=$2 -LITTLE_BIN=$1 +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi -. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \ -./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \ - 'fip.bin' \ - --MONITOR_RUNADDR="${MONITOR_RUNADDR}" \ - --BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \ - --CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \ - --NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \ - --NAND_INFO='00000000'\ - --BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \ - --BLCP_IMG_RUNADDR=0x05200200 \ - --BLCP_PARAM_LOADADDR=0 \ - --BLCP=pre-build/fsbl/test/empty.bin \ - --DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \ - --BLCP_2ND=$LITTLE_BIN \ - --MONITOR='pre-build/fw_dynamic.bin' \ - --LOADER_2ND='pre-build/u-boot-raw.bin' \ - --compress='lzma' \ No newline at end of file +ROOT_PATH=$(pwd) +echo $ROOT_PATH + +function get_board_type() +{ + BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M") + BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m") + + for ((i=0;i<${#BOARD_CONFIG[@]};i++)) + do + config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2) + if [ "$config_value" == "y" ]; then + BOARD_TYPE=${BOARD_VALUE[i]} + break + fi + done +} + +get_board_type +echo "board_type: ${BOARD_TYPE}" + +COUNTRY=China +function get_country() +{ + restult=$(curl -m 10 -s http://www.ip-api.com/json) + COUNTRY=$(echo $restult | sed 's/.*"country":"\([^"]*\)".*/\1/') + echo "Country: $COUNTRY" +} + +if [ "$COUNTRY" == "China" ]; then + cvitek_bootloader_url=https://gitee.com/flyingcys/cvitek_bootloader +else + cvitek_bootloader_url=https://github.com/flyingcys/cvitek_bootloader +fi + +if [ ! -d cvitek_bootloader ]; then + echo "cvitek_bootloader not exist, clone it from ${cvitek_bootloader_url}" + git clone ${cvitek_bootloader_url} + + if [ $? -ne 0 ]; then + echo "Failed to clone ${cvitek_bootloader_url} !" + exit 1 + fi +fi + +export BLCP_2ND_PATH=${PROJECT_PATH}/${IMAGE_NAME} + +pushd cvitek_bootloader + +. env.sh + +get_build_board ${BOARD_TYPE} + +echo "board: ${MV_BOARD_LINK}" + +if [ ! -d opensbi/build/platform/generic ] || [ ! -d fsbl/build/${MV_BOARD_LINK} ] || [ ! -d u-boot-2021.10/build/${MV_BOARD_LINK} ]; then + do_build + + CHIP_ARCH_L=$(echo $CHIP_ARCH | tr '[:upper:]' '[:lower:]') + cp -rf build/output/${MV_BOARD_LINK}/cvi_board_memmap.ld ${ROOT_PATH}/c906_little/board/script/${CHIP_ARCH_L} +else + echo "Build already done, skip build" + + do_combine + + if [ $? -ne 0 ]; then + do_build + fi +fi + +popd + +mkdir -p output/${MV_BOARD} +cp -rf cvitek_bootloader/install/soc_${MV_BOARD_LINK}/fip.bin output/${MV_BOARD}/fip.bin \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/mksdimg.sh b/bsp/cvitek/cv1800b/mksdimg.sh deleted file mode 100755 index 60dd65a076..0000000000 --- a/bsp/cvitek/cv1800b/mksdimg.sh +++ /dev/null @@ -1,7 +0,0 @@ -#/bin/sh -set -e -echo "start compress kernel..." - -lzma -c -9 -f -k Image > Image.lzma - -./mkimage -f multi.its -r ../boot.sd \ No newline at end of file diff --git a/bsp/cvitek/cv1800b/.config b/bsp/cvitek/cv180x/.config similarity index 99% rename from bsp/cvitek/cv1800b/.config rename to bsp/cvitek/cv180x/.config index fd58346a23..306a0d77ca 100644 --- a/bsp/cvitek/cv1800b/.config +++ b/bsp/cvitek/cv180x/.config @@ -1048,6 +1048,7 @@ CONFIG_RT_USING_LDSO=y # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set # # Display @@ -1130,8 +1131,9 @@ CONFIG_UART_IRQ_BASE=44 # CONFIG_RT_USING_UART4 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_PWM is not set -CONFIG_BSP_USING_CV1800B=y +CONFIG_BSP_USING_CV180X=y CONFIG_C906_PLIC_PHY_ADDR=0x70000000 CONFIG_IRQ_MAX_NR=64 CONFIG_TIMER_CLK_FREQ=25000000 CONFIG___STACKSIZE__=4096 +CONFIG_BOARD_TYPE_MILKV_DUO=y diff --git a/bsp/cvitek/cv1800b/.gitignore b/bsp/cvitek/cv180x/.gitignore similarity index 100% rename from bsp/cvitek/cv1800b/.gitignore rename to bsp/cvitek/cv180x/.gitignore diff --git a/bsp/cvitek/cv1800b/Kconfig b/bsp/cvitek/cv180x/Kconfig similarity index 83% rename from bsp/cvitek/cv1800b/Kconfig rename to bsp/cvitek/cv180x/Kconfig index 18394dca61..2758a776fb 100755 --- a/bsp/cvitek/cv1800b/Kconfig +++ b/bsp/cvitek/cv180x/Kconfig @@ -19,7 +19,7 @@ source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "board/Kconfig" -config BSP_USING_CV1800B +config BSP_USING_CV180X bool select ARCH_RISCV64 select RT_USING_SYSTEM_WORKQUEUE @@ -45,3 +45,11 @@ config TIMER_CLK_FREQ config __STACKSIZE__ int "stack size for interrupt" default 4096 + +choice + prompt "Board Type" + default BOARD_TYPE_MILKV_DUO + + config BOARD_TYPE_MILKV_DUO + bool "milkv-duo" +endchoice diff --git a/bsp/cvitek/cv1800b/README.md b/bsp/cvitek/cv180x/README.md similarity index 95% rename from bsp/cvitek/cv1800b/README.md rename to bsp/cvitek/cv180x/README.md index 9293cf2e29..006c07ee1a 100755 --- a/bsp/cvitek/cv1800b/README.md +++ b/bsp/cvitek/cv180x/README.md @@ -49,8 +49,9 @@ $ export RTT_EXEC_PATH=/opt/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin 1. 依赖安装 ```shell -$ sudo apt install -y device-tree-compiler +$ sudo apt install -y scons libncurses5-dev device-tree-compiler ``` + 2. Linux平台下，可以先执行： ```shell $ scons --menuconfig @@ -61,7 +62,7 @@ $ scons --menuconfig $ source ~/.env/env.sh $ pkgs --update ``` -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生rtthread.elf文件。 +更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。编译正确无误，会产生 rtthread.elf 文件。 编译完成后脚本自动调用 `./mksdimg.sh` 脚本进行打包，并生成 `boot.sd`, 该文件即为 SD 卡启动的 kernel 文件。 diff --git a/bsp/cvitek/cv1800b/README_en.md b/bsp/cvitek/cv180x/README_en.md similarity index 100% rename from bsp/cvitek/cv1800b/README_en.md rename to bsp/cvitek/cv180x/README_en.md diff --git a/bsp/cvitek/cv1800b/SConscript b/bsp/cvitek/cv180x/SConscript similarity index 100% rename from bsp/cvitek/cv1800b/SConscript rename to bsp/cvitek/cv180x/SConscript diff --git a/bsp/cvitek/cv1800b/SConstruct b/bsp/cvitek/cv180x/SConstruct similarity index 100% rename from bsp/cvitek/cv1800b/SConstruct rename to bsp/cvitek/cv180x/SConstruct diff --git a/bsp/cvitek/cv1800b/applications/SConscript b/bsp/cvitek/cv180x/applications/SConscript similarity index 100% rename from bsp/cvitek/cv1800b/applications/SConscript rename to bsp/cvitek/cv180x/applications/SConscript diff --git a/bsp/cvitek/cv1800b/applications/main.c b/bsp/cvitek/cv180x/applications/main.c similarity index 100% rename from bsp/cvitek/cv1800b/applications/main.c rename to bsp/cvitek/cv180x/applications/main.c diff --git a/bsp/cvitek/cv1800b/board/Kconfig b/bsp/cvitek/cv180x/board/Kconfig similarity index 100% rename from bsp/cvitek/cv1800b/board/Kconfig rename to bsp/cvitek/cv180x/board/Kconfig diff --git a/bsp/cvitek/cv1800b/board/SConscript b/bsp/cvitek/cv180x/board/SConscript similarity index 100% rename from bsp/cvitek/cv1800b/board/SConscript rename to bsp/cvitek/cv180x/board/SConscript diff --git a/bsp/cvitek/cv1800b/board/board.c b/bsp/cvitek/cv180x/board/board.c similarity index 100% rename from bsp/cvitek/cv1800b/board/board.c rename to bsp/cvitek/cv180x/board/board.c diff --git a/bsp/cvitek/cv1800b/board/board.h b/bsp/cvitek/cv180x/board/board.h similarity index 100% rename from bsp/cvitek/cv1800b/board/board.h rename to bsp/cvitek/cv180x/board/board.h diff --git a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb b/bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb similarity index 100% rename from bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb rename to bsp/cvitek/cv180x/cv1800b_milkv_duo_sd.dtb diff --git a/bsp/cvitek/cv1800b/link.lds b/bsp/cvitek/cv180x/link.lds similarity index 100% rename from bsp/cvitek/cv1800b/link.lds rename to bsp/cvitek/cv180x/link.lds diff --git a/bsp/cvitek/cv1800b/link_stacksize.lds b/bsp/cvitek/cv180x/link_stacksize.lds similarity index 100% rename from bsp/cvitek/cv1800b/link_stacksize.lds rename to bsp/cvitek/cv180x/link_stacksize.lds diff --git a/bsp/cvitek/cv1800b/multi.its b/bsp/cvitek/cv180x/multi.its similarity index 100% rename from bsp/cvitek/cv1800b/multi.its rename to bsp/cvitek/cv180x/multi.its diff --git a/bsp/cvitek/cv1800b/rtconfig.h b/bsp/cvitek/cv180x/rtconfig.h similarity index 99% rename from bsp/cvitek/cv1800b/rtconfig.h rename to bsp/cvitek/cv180x/rtconfig.h index 236544eee3..ea9b8dd4e5 100755 --- a/bsp/cvitek/cv1800b/rtconfig.h +++ b/bsp/cvitek/cv180x/rtconfig.h @@ -311,10 +311,11 @@ #define BSP_USING_UART #define RT_USING_UART0 #define UART_IRQ_BASE 44 -#define BSP_USING_CV1800B +#define BSP_USING_CV180X #define C906_PLIC_PHY_ADDR 0x70000000 #define IRQ_MAX_NR 64 #define TIMER_CLK_FREQ 25000000 #define __STACKSIZE__ 4096 +#define BOARD_TYPE_MILKV_DUO #endif diff --git a/bsp/cvitek/cv1800b/rtconfig.py b/bsp/cvitek/cv180x/rtconfig.py similarity index 90% rename from bsp/cvitek/cv1800b/rtconfig.py rename to bsp/cvitek/cv180x/rtconfig.py index 0914d5c010..4ca7b664bb 100755 --- a/bsp/cvitek/cv1800b/rtconfig.py +++ b/bsp/cvitek/cv180x/rtconfig.py @@ -25,6 +25,7 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' +CHIP_TYPE = 'cv180x' if PLATFORM == 'gcc': # toolchains @@ -56,4 +57,5 @@ if PLATFORM == 'gcc': CXXFLAGS = CFLAGS DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n' +POST_ACTION = OBJCPY + ' -O binary $TARGET Image \n' + SIZE + ' $TARGET \n' +POST_ACTION += 'cd .. && bash mksdimg.sh ' + os.getcwd() + ' Image \n' diff --git a/bsp/cvitek/drivers/.ignore_format.yml b/bsp/cvitek/drivers/.ignore_format.yml new file mode 100755 index 0000000000..821281b7e9 --- /dev/null +++ b/bsp/cvitek/drivers/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- libraries \ No newline at end of file diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript index 83c882470c..f5cde6b1e8 100755 --- a/bsp/cvitek/drivers/SConscript +++ b/bsp/cvitek/drivers/SConscript @@ -2,17 +2,23 @@ from building import * cwd = GetCurrentDir() src = Split(''' -drv_uart.c -drv_por.c + drv_uart.c + drv_por.c ''') CPPDEFINES = [] CPPPATH = [cwd] -if GetDepend('BSP_USING_CV1800B') or GetDepend('BSP_USING_C906_LITTLE'): - CPPPATH += [cwd + r'/cv1800b'] +CHIP_TYPE = 'cv180x' +if GetDepend('BOARD_TYPE_MILKV_DUO256M'): + CHIP_TYPE = 'cv181x' +elif GetDepend('BOARD_TYPE_MILKV_DUO') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINOR') or GetDepend('BOARD_TYPE_MILKV_DUO_SPINAND'): + CHIP_TYPE = 'cv180x' -if GetDepend('BSP_USING_CV1800B'): +CPPPATH += [cwd + r'/libraries'] +CPPPATH += [cwd + r'/libraries/' + CHIP_TYPE] + +if GetDepend('BSP_USING_CV180X'): src += ['drv_gpio.c'] if GetDepend('BSP_USING_I2C'): @@ -26,7 +32,8 @@ if GetDepend('BSP_USING_WDT'): if GetDepend('BSP_USING_PWM'): src += ['drv_pwm.c'] - CPPPATH += [cwd + r'/cv1800b/pwm'] + CPPPATH += [cwd + r'/libraries/cv180x/pwm'] + CPPDEFINES += ['-DCONFIG_64BIT'] if GetDepend('BSP_USING_RTC'): diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinlist_swconfig.h diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_pinmux.h diff --git a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h rename to bsp/cvitek/drivers/libraries/cv180x/cv180x_reg_fmux_gpio.h diff --git a/bsp/cvitek/drivers/cv1800b/pinctrl.h b/bsp/cvitek/drivers/libraries/cv180x/pinctrl.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/pinctrl.h rename to bsp/cvitek/drivers/libraries/cv180x/pinctrl.h diff --git a/bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h b/bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h old mode 100644 new mode 100755 similarity index 100% rename from bsp/cvitek/drivers/cv1800b/pwm/cvi_pwm.h rename to bsp/cvitek/drivers/libraries/cv180x/pwm/cvi_pwm.h diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h new file mode 100755 index 0000000000..64d4ec9cdb --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinlist_swconfig.h @@ -0,0 +1,653 @@ + +#define CAM_MCLK0__CAM_MCLK0 0 +#define CAM_MCLK0__AUX1 2 +#define CAM_MCLK0__XGPIOA_0 3 +#define CAM_PD0__IIS1_MCLK 1 +#define CAM_PD0__XGPIOA_1 3 +#define CAM_PD0__CAM_HS0 4 +#define CAM_RST0__XGPIOA_2 3 +#define CAM_RST0__CAM_VS0 4 +#define CAM_RST0__IIC4_SCL 6 +#define CAM_MCLK1__CAM_MCLK1 0 +#define CAM_MCLK1__AUX2 2 +#define CAM_MCLK1__XGPIOA_3 3 +#define CAM_MCLK1__CAM_HS0 4 +#define CAM_PD1__IIS1_MCLK 1 +#define CAM_PD1__XGPIOA_4 3 +#define CAM_PD1__CAM_VS0 4 +#define CAM_PD1__IIC4_SDA 6 +#define IIC3_SCL__IIC3_SCL 0 +#define IIC3_SCL__XGPIOA_5 3 +#define IIC3_SDA__IIC3_SDA 0 +#define IIC3_SDA__XGPIOA_6 3 +#define SD0_CLK__SDIO0_CLK 0 +#define SD0_CLK__IIC1_SDA 1 +#define SD0_CLK__SPI0_SCK 2 +#define SD0_CLK__XGPIOA_7 3 +#define SD0_CLK__PWM_15 5 +#define SD0_CLK__EPHY_LNK_LED 6 +#define SD0_CLK__DBG_0 7 +#define SD0_CMD__SDIO0_CMD 0 +#define SD0_CMD__IIC1_SCL 1 +#define SD0_CMD__SPI0_SDO 2 +#define SD0_CMD__XGPIOA_8 3 +#define SD0_CMD__PWM_14 5 +#define SD0_CMD__EPHY_SPD_LED 6 +#define SD0_CMD__DBG_1 7 +#define SD0_D0__SDIO0_D_0 0 +#define SD0_D0__CAM_MCLK1 1 +#define SD0_D0__SPI0_SDI 2 +#define SD0_D0__XGPIOA_9 3 +#define SD0_D0__UART3_TX 4 +#define SD0_D0__PWM_13 5 +#define SD0_D0__WG0_D0 6 +#define SD0_D0__DBG_2 7 +#define SD0_D1__SDIO0_D_1 0 +#define SD0_D1__IIC1_SDA 1 +#define SD0_D1__AUX0 2 +#define SD0_D1__XGPIOA_10 3 +#define SD0_D1__UART1_TX 4 +#define SD0_D1__PWM_12 5 +#define SD0_D1__WG0_D1 6 +#define SD0_D1__DBG_3 7 +#define SD0_D2__SDIO0_D_2 0 +#define SD0_D2__IIC1_SCL 1 +#define SD0_D2__AUX1 2 +#define SD0_D2__XGPIOA_11 3 +#define SD0_D2__UART1_RX 4 +#define SD0_D2__PWM_11 5 +#define SD0_D2__WG1_D0 6 +#define SD0_D2__DBG_4 7 +#define SD0_D3__SDIO0_D_3 0 +#define SD0_D3__CAM_MCLK0 1 +#define SD0_D3__SPI0_CS_X 2 +#define SD0_D3__XGPIOA_12 3 +#define SD0_D3__UART3_RX 4 +#define SD0_D3__PWM_10 5 +#define SD0_D3__WG1_D1 6 +#define SD0_D3__DBG_5 7 +#define SD0_CD__SDIO0_CD 0 +#define SD0_CD__XGPIOA_13 3 +#define SD0_PWR_EN__SDIO0_PWR_EN 0 +#define SD0_PWR_EN__XGPIOA_14 3 +#define SPK_EN__XGPIOA_15 3 +#define UART0_TX__UART0_TX 0 +#define UART0_TX__CAM_MCLK1 1 +#define UART0_TX__PWM_4 2 +#define UART0_TX__XGPIOA_16 3 +#define UART0_TX__UART1_TX 4 +#define UART0_TX__AUX1 5 +#define UART0_TX__DBG_6 7 +#define UART0_RX__UART0_RX 0 +#define UART0_RX__CAM_MCLK0 1 +#define UART0_RX__PWM_5 2 +#define UART0_RX__XGPIOA_17 3 +#define UART0_RX__UART1_RX 4 +#define UART0_RX__AUX0 5 +#define UART0_RX__DBG_7 7 +#define EMMC_RSTN__EMMC_RSTN 0 +#define EMMC_RSTN__XGPIOA_21 3 +#define EMMC_RSTN__AUX2 4 +#define EMMC_DAT2__EMMC_DAT_2 0 +#define EMMC_DAT2__SPINOR_HOLD_X 1 +#define EMMC_DAT2__SPINAND_HOLD 2 +#define EMMC_DAT2__XGPIOA_26 3 +#define EMMC_CLK__EMMC_CLK 0 +#define EMMC_CLK__SPINOR_SCK 1 +#define EMMC_CLK__SPINAND_CLK 2 +#define EMMC_CLK__XGPIOA_22 3 +#define EMMC_DAT0__EMMC_DAT_0 0 +#define EMMC_DAT0__SPINOR_MOSI 1 +#define EMMC_DAT0__SPINAND_MOSI 2 +#define EMMC_DAT0__XGPIOA_25 3 +#define EMMC_DAT3__EMMC_DAT_3 0 +#define EMMC_DAT3__SPINOR_WP_X 1 +#define EMMC_DAT3__SPINAND_WP 2 +#define EMMC_DAT3__XGPIOA_27 3 +#define EMMC_CMD__EMMC_CMD 0 +#define EMMC_CMD__SPINOR_MISO 1 +#define EMMC_CMD__SPINAND_MISO 2 +#define EMMC_CMD__XGPIOA_23 3 +#define EMMC_DAT1__EMMC_DAT_1 0 +#define EMMC_DAT1__SPINOR_CS_X 1 +#define EMMC_DAT1__SPINAND_CS 2 +#define EMMC_DAT1__XGPIOA_24 3 +#define JTAG_CPU_TMS__JTAG_CPU_TMS 0 +#define JTAG_CPU_TMS__CAM_MCLK0 1 +#define JTAG_CPU_TMS__PWM_7 2 +#define JTAG_CPU_TMS__XGPIOA_19 3 +#define JTAG_CPU_TMS__UART1_RTS 4 +#define JTAG_CPU_TMS__AUX0 5 +#define JTAG_CPU_TMS__UART1_TX 6 +#define JTAG_CPU_TMS__VO_D_28 7 +#define JTAG_CPU_TCK__JTAG_CPU_TCK 0 +#define JTAG_CPU_TCK__CAM_MCLK1 1 +#define JTAG_CPU_TCK__PWM_6 2 +#define JTAG_CPU_TCK__XGPIOA_18 3 +#define JTAG_CPU_TCK__UART1_CTS 4 +#define JTAG_CPU_TCK__AUX1 5 +#define JTAG_CPU_TCK__UART1_RX 6 +#define JTAG_CPU_TCK__VO_D_29 7 +#define JTAG_CPU_TRST__JTAG_CPU_TRST 0 +#define JTAG_CPU_TRST__XGPIOA_20 3 +#define JTAG_CPU_TRST__VO_D_30 6 +#define IIC0_SCL__IIC0_SCL 0 +#define IIC0_SCL__UART1_TX 1 +#define IIC0_SCL__UART2_TX 2 +#define IIC0_SCL__XGPIOA_28 3 +#define IIC0_SCL__WG0_D0 5 +#define IIC0_SCL__DBG_10 7 +#define IIC0_SDA__IIC0_SDA 0 +#define IIC0_SDA__UART1_RX 1 +#define IIC0_SDA__UART2_RX 2 +#define IIC0_SDA__XGPIOA_29 3 +#define IIC0_SDA__WG0_D1 5 +#define IIC0_SDA__WG1_D0 6 +#define IIC0_SDA__DBG_11 7 +#define AUX0__AUX0 0 +#define AUX0__XGPIOA_30 3 +#define AUX0__IIS1_MCLK 4 +#define AUX0__VO_D_31 5 +#define AUX0__WG1_D1 6 +#define AUX0__DBG_12 7 +#define PWR_VBAT_DET__PWR_VBAT_DET 0 +#define PWR_RSTN__PWR_RSTN 0 +#define PWR_SEQ1__PWR_SEQ1 0 +#define PWR_SEQ1__PWR_GPIO_3 3 +#define PWR_SEQ2__PWR_SEQ2 0 +#define PWR_SEQ2__PWR_GPIO_4 3 +#define PWR_SEQ3__PWR_SEQ3 0 +#define PWR_SEQ3__PWR_GPIO_5 3 +#define PTEST__PWR_PTEST 0 +#define PWR_WAKEUP0__PWR_WAKEUP0 0 +#define PWR_WAKEUP0__PWR_IR0 1 +#define PWR_WAKEUP0__PWR_UART0_TX 2 +#define PWR_WAKEUP0__PWR_GPIO_6 3 +#define PWR_WAKEUP0__UART1_TX 4 +#define PWR_WAKEUP0__IIC4_SCL 5 +#define PWR_WAKEUP0__EPHY_LNK_LED 6 +#define PWR_WAKEUP0__WG2_D0 7 +#define PWR_WAKEUP1__PWR_WAKEUP1 0 +#define PWR_WAKEUP1__PWR_IR1 1 +#define PWR_WAKEUP1__PWR_GPIO_7 3 +#define PWR_WAKEUP1__UART1_TX 4 +#define PWR_WAKEUP1__IIC4_SCL 5 +#define PWR_WAKEUP1__EPHY_LNK_LED 6 +#define PWR_WAKEUP1__WG0_D0 7 +#define PWR_BUTTON1__PWR_BUTTON1 0 +#define PWR_BUTTON1__PWR_GPIO_8 3 +#define PWR_BUTTON1__UART1_RX 4 +#define PWR_BUTTON1__IIC4_SDA 5 +#define PWR_BUTTON1__EPHY_SPD_LED 6 +#define PWR_BUTTON1__WG2_D1 7 +#define PWR_ON__PWR_ON 0 +#define PWR_ON__PWR_GPIO_9 3 +#define PWR_ON__UART1_RX 4 +#define PWR_ON__IIC4_SDA 5 +#define PWR_ON__EPHY_SPD_LED 6 +#define PWR_ON__WG0_D1 7 +#define XTAL_XIN__PWR_XTAL_CLKIN 0 +#define PWR_GPIO0__PWR_GPIO_0 0 +#define PWR_GPIO0__UART2_TX 1 +#define PWR_GPIO0__PWR_UART0_RX 2 +#define PWR_GPIO0__PWM_8 4 +#define PWR_GPIO1__PWR_GPIO_1 0 +#define PWR_GPIO1__UART2_RX 1 +#define PWR_GPIO1__EPHY_LNK_LED 3 +#define PWR_GPIO1__PWM_9 4 +#define PWR_GPIO1__PWR_IIC_SCL 5 +#define PWR_GPIO1__IIC2_SCL 6 +#define PWR_GPIO1__PWR_MCU_JTAG_TMS 7 +#define PWR_GPIO2__PWR_GPIO_2 0 +#define PWR_GPIO2__PWR_SECTICK 2 +#define PWR_GPIO2__EPHY_SPD_LED 3 +#define PWR_GPIO2__PWM_10 4 +#define PWR_GPIO2__PWR_IIC_SDA 5 +#define PWR_GPIO2__IIC2_SDA 6 +#define PWR_GPIO2__PWR_MCU_JTAG_TCK 7 +#define CLK32K__CLK32K 0 +#define CLK32K__AUX0 1 +#define CLK32K__PWR_MCU_JTAG_TDI 2 +#define CLK32K__PWR_GPIO_10 3 +#define CLK32K__PWM_2 4 +#define CLK32K__KEY_COL0 5 +#define CLK32K__CAM_MCLK0 6 +#define CLK32K__DBG_0 7 +#define CLK25M__CLK25M 0 +#define CLK25M__AUX1 1 +#define CLK25M__PWR_MCU_JTAG_TDO 2 +#define CLK25M__PWR_GPIO_11 3 +#define CLK25M__PWM_3 4 +#define CLK25M__KEY_COL1 5 +#define CLK25M__CAM_MCLK1 6 +#define CLK25M__DBG_1 7 +#define IIC2_SCL__IIC2_SCL 0 +#define IIC2_SCL__PWM_14 1 +#define IIC2_SCL__PWR_GPIO_12 3 +#define IIC2_SCL__UART2_RX 4 +#define IIC2_SCL__KEY_COL2 7 +#define IIC2_SDA__IIC2_SDA 0 +#define IIC2_SDA__PWM_15 1 +#define IIC2_SDA__PWR_GPIO_13 3 +#define IIC2_SDA__UART2_TX 4 +#define IIC2_SDA__IIS1_MCLK 5 +#define IIC2_SDA__IIS2_MCLK 6 +#define IIC2_SDA__KEY_COL3 7 +#define UART2_TX__UART2_TX 0 +#define UART2_TX__PWM_11 1 +#define UART2_TX__PWR_UART1_TX 2 +#define UART2_TX__PWR_GPIO_14 3 +#define UART2_TX__KEY_ROW3 4 +#define UART2_TX__UART4_TX 5 +#define UART2_TX__IIS2_BCLK 6 +#define UART2_TX__WG2_D0 7 +#define UART2_RTS__UART2_RTS 0 +#define UART2_RTS__PWM_8 1 +#define UART2_RTS__PWR_GPIO_15 3 +#define UART2_RTS__KEY_ROW0 4 +#define UART2_RTS__UART4_RTS 5 +#define UART2_RTS__IIS2_DO 6 +#define UART2_RTS__WG1_D0 7 +#define UART2_RX__UART2_RX 0 +#define UART2_RX__PWM_10 1 +#define UART2_RX__PWR_UART1_RX 2 +#define UART2_RX__PWR_GPIO_16 3 +#define UART2_RX__KEY_COL3 4 +#define UART2_RX__UART4_RX 5 +#define UART2_RX__IIS2_DI 6 +#define UART2_RX__WG2_D1 7 +#define UART2_CTS__UART2_CTS 0 +#define UART2_CTS__PWM_9 1 +#define UART2_CTS__PWR_GPIO_17 3 +#define UART2_CTS__KEY_ROW1 4 +#define UART2_CTS__UART4_CTS 5 +#define UART2_CTS__IIS2_LRCK 6 +#define UART2_CTS__WG1_D1 7 +#define SD1_D3__PWR_SD1_D3_VO32 0 +#define SD1_D3__SPI2_CS_X 1 +#define SD1_D3__IIC1_SCL 2 +#define SD1_D3__PWR_GPIO_18 3 +#define SD1_D3__CAM_MCLK0 4 +#define SD1_D3__UART3_CTS 5 +#define SD1_D3__PWR_SPINOR1_CS_X 6 +#define SD1_D3__PWM_4 7 +#define SD1_D2__PWR_SD1_D2_VO33 0 +#define SD1_D2__IIC1_SCL 1 +#define SD1_D2__UART2_TX 2 +#define SD1_D2__PWR_GPIO_19 3 +#define SD1_D2__CAM_MCLK0 4 +#define SD1_D2__UART3_TX 5 +#define SD1_D2__PWR_SPINOR1_HOLD_X 6 +#define SD1_D2__PWM_5 7 +#define SD1_D1__PWR_SD1_D1_VO34 0 +#define SD1_D1__IIC1_SDA 1 +#define SD1_D1__UART2_RX 2 +#define SD1_D1__PWR_GPIO_20 3 +#define SD1_D1__CAM_MCLK1 4 +#define SD1_D1__UART3_RX 5 +#define SD1_D1__PWR_SPINOR1_WP_X 6 +#define SD1_D1__PWM_6 7 +#define SD1_D0__PWR_SD1_D0_VO35 0 +#define SD1_D0__SPI2_SDI 1 +#define SD1_D0__IIC1_SDA 2 +#define SD1_D0__PWR_GPIO_21 3 +#define SD1_D0__CAM_MCLK1 4 +#define SD1_D0__UART3_RTS 5 +#define SD1_D0__PWR_SPINOR1_MISO 6 +#define SD1_D0__PWM_7 7 +#define SD1_CMD__PWR_SD1_CMD_VO36 0 +#define SD1_CMD__SPI2_SDO 1 +#define SD1_CMD__IIC3_SCL 2 +#define SD1_CMD__PWR_GPIO_22 3 +#define SD1_CMD__CAM_VS0 4 +#define SD1_CMD__EPHY_LNK_LED 5 +#define SD1_CMD__PWR_SPINOR1_MOSI 6 +#define SD1_CMD__PWM_8 7 +#define SD1_CLK__PWR_SD1_CLK_VO37 0 +#define SD1_CLK__SPI2_SCK 1 +#define SD1_CLK__IIC3_SDA 2 +#define SD1_CLK__PWR_GPIO_23 3 +#define SD1_CLK__CAM_HS0 4 +#define SD1_CLK__EPHY_SPD_LED 5 +#define SD1_CLK__PWR_SPINOR1_SCK 6 +#define SD1_CLK__PWM_9 7 +#define RSTN__RSTN 0 +#define PWM0_BUCK__PWM_0 0 +#define PWM0_BUCK__XGPIOB_0 3 +#define ADC3__CAM_MCLK0 1 +#define ADC3__IIC4_SCL 2 +#define ADC3__XGPIOB_1 3 +#define ADC3__PWM_12 4 +#define ADC3__EPHY_LNK_LED 5 +#define ADC3__WG2_D0 6 +#define ADC3__UART3_TX 7 +#define ADC2__CAM_MCLK1 1 +#define ADC2__IIC4_SDA 2 +#define ADC2__XGPIOB_2 3 +#define ADC2__PWM_13 4 +#define ADC2__EPHY_SPD_LED 5 +#define ADC2__WG2_D1 6 +#define ADC2__UART3_RX 7 +#define ADC1__XGPIOB_3 3 +#define ADC1__KEY_COL2 4 +#define USB_ID__USB_ID 0 +#define USB_ID__XGPIOB_4 3 +#define USB_VBUS_EN__USB_VBUS_EN 0 +#define USB_VBUS_EN__XGPIOB_5 3 +#define PKG_TYPE0__PKG_TYPE0 0 +#define USB_VBUS_DET__USB_VBUS_DET 0 +#define USB_VBUS_DET__XGPIOB_6 3 +#define USB_VBUS_DET__CAM_MCLK0 4 +#define USB_VBUS_DET__CAM_MCLK1 5 +#define PKG_TYPE1__PKG_TYPE1 0 +#define PKG_TYPE2__PKG_TYPE2 0 +#define MUX_SPI1_MISO__UART3_RTS 1 +#define MUX_SPI1_MISO__IIC1_SDA 2 +#define MUX_SPI1_MISO__XGPIOB_8 3 +#define MUX_SPI1_MISO__PWM_9 4 +#define MUX_SPI1_MISO__KEY_COL1 5 +#define MUX_SPI1_MISO__SPI1_SDI 6 +#define MUX_SPI1_MISO__DBG_14 7 +#define MUX_SPI1_MOSI__UART3_RX 1 +#define MUX_SPI1_MOSI__IIC1_SCL 2 +#define MUX_SPI1_MOSI__XGPIOB_7 3 +#define MUX_SPI1_MOSI__PWM_8 4 +#define MUX_SPI1_MOSI__KEY_COL0 5 +#define MUX_SPI1_MOSI__SPI1_SDO 6 +#define MUX_SPI1_MOSI__DBG_13 7 +#define MUX_SPI1_CS__UART3_CTS 1 +#define MUX_SPI1_CS__CAM_MCLK0 2 +#define MUX_SPI1_CS__XGPIOB_10 3 +#define MUX_SPI1_CS__PWM_11 4 +#define MUX_SPI1_CS__KEY_ROW3 5 +#define MUX_SPI1_CS__SPI1_CS_X 6 +#define MUX_SPI1_CS__DBG_16 7 +#define MUX_SPI1_SCK__UART3_TX 1 +#define MUX_SPI1_SCK__CAM_MCLK1 2 +#define MUX_SPI1_SCK__XGPIOB_9 3 +#define MUX_SPI1_SCK__PWM_10 4 +#define MUX_SPI1_SCK__KEY_ROW2 5 +#define MUX_SPI1_SCK__SPI1_SCK 6 +#define MUX_SPI1_SCK__DBG_15 7 +#define PAD_ETH_TXM__UART3_RTS 1 +#define PAD_ETH_TXM__IIC1_SDA 2 +#define PAD_ETH_TXM__XGPIOB_24 3 +#define PAD_ETH_TXM__PWM_12 4 +#define PAD_ETH_TXM__CAM_MCLK1 5 +#define PAD_ETH_TXM__SPI1_SDI 6 +#define PAD_ETH_TXM__IIS2_BCLK 7 +#define PAD_ETH_TXP__UART3_RX 1 +#define PAD_ETH_TXP__IIC1_SCL 2 +#define PAD_ETH_TXP__XGPIOB_25 3 +#define PAD_ETH_TXP__PWM_13 4 +#define PAD_ETH_TXP__CAM_MCLK0 5 +#define PAD_ETH_TXP__SPI1_SDO 6 +#define PAD_ETH_TXP__IIS2_LRCK 7 +#define PAD_ETH_RXM__UART3_CTS 1 +#define PAD_ETH_RXM__CAM_MCLK0 2 +#define PAD_ETH_RXM__XGPIOB_26 3 +#define PAD_ETH_RXM__PWM_14 4 +#define PAD_ETH_RXM__CAM_VS0 5 +#define PAD_ETH_RXM__SPI1_CS_X 6 +#define PAD_ETH_RXM__IIS2_DI 7 +#define PAD_ETH_RXP__UART3_TX 1 +#define PAD_ETH_RXP__CAM_MCLK1 2 +#define PAD_ETH_RXP__XGPIOB_27 3 +#define PAD_ETH_RXP__PWM_15 4 +#define PAD_ETH_RXP__CAM_HS0 5 +#define PAD_ETH_RXP__SPI1_SCK 6 +#define PAD_ETH_RXP__IIS2_DO 7 +#define VIVO_D10__PWM_1 0 +#define VIVO_D10__VI1_D_10 1 +#define VIVO_D10__VO_D_23 2 +#define VIVO_D10__XGPIOB_11 3 +#define VIVO_D10__RMII0_IRQ 4 +#define VIVO_D10__CAM_MCLK0 5 +#define VIVO_D10__IIC1_SDA 6 +#define VIVO_D10__UART2_TX 7 +#define VIVO_D9__PWM_2 0 +#define VIVO_D9__VI1_D_9 1 +#define VIVO_D9__VO_D_22 2 +#define VIVO_D9__XGPIOB_12 3 +#define VIVO_D9__CAM_MCLK1 5 +#define VIVO_D9__IIC1_SCL 6 +#define VIVO_D9__UART2_RX 7 +#define VIVO_D8__PWM_3 0 +#define VIVO_D8__VI1_D_8 1 +#define VIVO_D8__VO_D_21 2 +#define VIVO_D8__XGPIOB_13 3 +#define VIVO_D8__RMII0_MDIO 4 +#define VIVO_D8__SPI3_SDO 5 +#define VIVO_D8__IIC2_SCL 6 +#define VIVO_D8__CAM_VS0 7 +#define VIVO_D7__VI2_D_7 0 +#define VIVO_D7__VI1_D_7 1 +#define VIVO_D7__VO_D_20 2 +#define VIVO_D7__XGPIOB_14 3 +#define VIVO_D7__RMII0_RXD1 4 +#define VIVO_D7__SPI3_SDI 5 +#define VIVO_D7__IIC2_SDA 6 +#define VIVO_D7__CAM_HS0 7 +#define VIVO_D6__VI2_D_6 0 +#define VIVO_D6__VI1_D_6 1 +#define VIVO_D6__VO_D_19 2 +#define VIVO_D6__XGPIOB_15 3 +#define VIVO_D6__RMII0_REFCLKI 4 +#define VIVO_D6__SPI3_SCK 5 +#define VIVO_D6__UART2_TX 6 +#define VIVO_D6__CAM_VS0 7 +#define VIVO_D5__VI2_D_5 0 +#define VIVO_D5__VI1_D_5 1 +#define VIVO_D5__VO_D_18 2 +#define VIVO_D5__XGPIOB_16 3 +#define VIVO_D5__RMII0_RXD0 4 +#define VIVO_D5__SPI3_CS_X 5 +#define VIVO_D5__UART2_RX 6 +#define VIVO_D5__CAM_HS0 7 +#define VIVO_D4__VI2_D_4 0 +#define VIVO_D4__VI1_D_4 1 +#define VIVO_D4__VO_D_17 2 +#define VIVO_D4__XGPIOB_17 3 +#define VIVO_D4__RMII0_MDC 4 +#define VIVO_D4__IIC1_SDA 5 +#define VIVO_D4__UART2_CTS 6 +#define VIVO_D4__CAM_VS0 7 +#define VIVO_D3__VI2_D_3 0 +#define VIVO_D3__VI1_D_3 1 +#define VIVO_D3__VO_D_16 2 +#define VIVO_D3__XGPIOB_18 3 +#define VIVO_D3__RMII0_TXD0 4 +#define VIVO_D3__IIC1_SCL 5 +#define VIVO_D3__UART2_RTS 6 +#define VIVO_D3__CAM_HS0 7 +#define VIVO_D2__VI2_D_2 0 +#define VIVO_D2__VI1_D_2 1 +#define VIVO_D2__VO_D_15 2 +#define VIVO_D2__XGPIOB_19 3 +#define VIVO_D2__RMII0_TXD1 4 +#define VIVO_D2__CAM_MCLK1 5 +#define VIVO_D2__PWM_2 6 +#define VIVO_D2__UART2_TX 7 +#define VIVO_D1__VI2_D_1 0 +#define VIVO_D1__VI1_D_1 1 +#define VIVO_D1__VO_D_14 2 +#define VIVO_D1__XGPIOB_20 3 +#define VIVO_D1__RMII0_RXDV 4 +#define VIVO_D1__IIC3_SDA 5 +#define VIVO_D1__PWM_3 6 +#define VIVO_D1__IIC4_SCL 7 +#define VIVO_D0__VI2_D_0 0 +#define VIVO_D0__VI1_D_0 1 +#define VIVO_D0__VO_D_13 2 +#define VIVO_D0__XGPIOB_21 3 +#define VIVO_D0__RMII0_TXCLK 4 +#define VIVO_D0__IIC3_SCL 5 +#define VIVO_D0__WG1_D0 6 +#define VIVO_D0__IIC4_SDA 7 +#define VIVO_CLK__VI2_CLK 0 +#define VIVO_CLK__VI1_CLK 1 +#define VIVO_CLK__VO_CLK1 2 +#define VIVO_CLK__XGPIOB_22 3 +#define VIVO_CLK__RMII0_TXEN 4 +#define VIVO_CLK__CAM_MCLK0 5 +#define VIVO_CLK__WG1_D1 6 +#define VIVO_CLK__UART2_RX 7 +#define PAD_MIPIRX5N__VI1_D_11 1 +#define PAD_MIPIRX5N__VO_D_12 2 +#define PAD_MIPIRX5N__XGPIOC_0 3 +#define PAD_MIPIRX5N__CAM_MCLK0 5 +#define PAD_MIPIRX5N__WG0_D0 6 +#define PAD_MIPIRX5N__DBG_0 7 +#define PAD_MIPIRX5P__VI1_D_12 1 +#define PAD_MIPIRX5P__VO_D_11 2 +#define PAD_MIPIRX5P__XGPIOC_1 3 +#define PAD_MIPIRX5P__IIS1_MCLK 4 +#define PAD_MIPIRX5P__CAM_MCLK1 5 +#define PAD_MIPIRX5P__WG0_D1 6 +#define PAD_MIPIRX5P__DBG_1 7 +#define PAD_MIPIRX4N__VI0_CLK 1 +#define PAD_MIPIRX4N__VI1_D_13 2 +#define PAD_MIPIRX4N__XGPIOC_2 3 +#define PAD_MIPIRX4N__IIC1_SDA 4 +#define PAD_MIPIRX4N__CAM_MCLK0 5 +#define PAD_MIPIRX4N__KEY_ROW0 6 +#define PAD_MIPIRX4N__MUX_SPI1_SCK 7 +#define PAD_MIPIRX4P__VI0_D_0 1 +#define PAD_MIPIRX4P__VI1_D_14 2 +#define PAD_MIPIRX4P__XGPIOC_3 3 +#define PAD_MIPIRX4P__IIC1_SCL 4 +#define PAD_MIPIRX4P__CAM_MCLK1 5 +#define PAD_MIPIRX4P__KEY_ROW1 6 +#define PAD_MIPIRX4P__MUX_SPI1_CS 7 +#define PAD_MIPIRX3N__VI0_D_1 1 +#define PAD_MIPIRX3N__VI1_D_15 2 +#define PAD_MIPIRX3N__XGPIOC_4 3 +#define PAD_MIPIRX3N__CAM_MCLK0 4 +#define PAD_MIPIRX3N__MUX_SPI1_MISO 7 +#define PAD_MIPIRX3P__VI0_D_2 1 +#define PAD_MIPIRX3P__VI1_D_16 2 +#define PAD_MIPIRX3P__XGPIOC_5 3 +#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7 +#define PAD_MIPIRX2N__VI0_D_3 1 +#define PAD_MIPIRX2N__VO_D_10 2 +#define PAD_MIPIRX2N__XGPIOC_6 3 +#define PAD_MIPIRX2N__VI1_D_17 4 +#define PAD_MIPIRX2N__IIC4_SCL 5 +#define PAD_MIPIRX2N__DBG_6 7 +#define PAD_MIPIRX2P__VI0_D_4 1 +#define PAD_MIPIRX2P__VO_D_9 2 +#define PAD_MIPIRX2P__XGPIOC_7 3 +#define PAD_MIPIRX2P__VI1_D_18 4 +#define PAD_MIPIRX2P__IIC4_SDA 5 +#define PAD_MIPIRX2P__DBG_7 7 +#define PAD_MIPIRX1N__VI0_D_5 1 +#define PAD_MIPIRX1N__VO_D_8 2 +#define PAD_MIPIRX1N__XGPIOC_8 3 +#define PAD_MIPIRX1N__KEY_ROW3 6 +#define PAD_MIPIRX1N__DBG_8 7 +#define PAD_MIPIRX1P__VI0_D_6 1 +#define PAD_MIPIRX1P__VO_D_7 2 +#define PAD_MIPIRX1P__XGPIOC_9 3 +#define PAD_MIPIRX1P__IIC1_SDA 4 +#define PAD_MIPIRX1P__KEY_ROW2 6 +#define PAD_MIPIRX1P__DBG_9 7 +#define PAD_MIPIRX0N__VI0_D_7 1 +#define PAD_MIPIRX0N__VO_D_6 2 +#define PAD_MIPIRX0N__XGPIOC_10 3 +#define PAD_MIPIRX0N__IIC1_SCL 4 +#define PAD_MIPIRX0N__CAM_MCLK1 5 +#define PAD_MIPIRX0N__DBG_10 7 +#define PAD_MIPIRX0P__VI0_D_8 1 +#define PAD_MIPIRX0P__VO_D_5 2 +#define PAD_MIPIRX0P__XGPIOC_11 3 +#define PAD_MIPIRX0P__CAM_MCLK0 4 +#define PAD_MIPIRX0P__DBG_11 7 +#define PAD_MIPI_TXM4__SD1_CLK 1 +#define PAD_MIPI_TXM4__VO_D_24 2 +#define PAD_MIPI_TXM4__XGPIOC_18 3 +#define PAD_MIPI_TXM4__CAM_MCLK1 4 +#define PAD_MIPI_TXM4__PWM_12 5 +#define PAD_MIPI_TXM4__IIC1_SDA 6 +#define PAD_MIPI_TXM4__DBG_18 7 +#define PAD_MIPI_TXP4__SD1_CMD 1 +#define PAD_MIPI_TXP4__VO_D_25 2 +#define PAD_MIPI_TXP4__XGPIOC_19 3 +#define PAD_MIPI_TXP4__CAM_MCLK0 4 +#define PAD_MIPI_TXP4__PWM_13 5 +#define PAD_MIPI_TXP4__IIC1_SCL 6 +#define PAD_MIPI_TXP4__DBG_19 7 +#define PAD_MIPI_TXM3__SD1_D0 1 +#define PAD_MIPI_TXM3__VO_D_26 2 +#define PAD_MIPI_TXM3__XGPIOC_20 3 +#define PAD_MIPI_TXM3__IIC2_SDA 4 +#define PAD_MIPI_TXM3__PWM_14 5 +#define PAD_MIPI_TXM3__IIC1_SDA 6 +#define PAD_MIPI_TXM3__CAM_VS0 7 +#define PAD_MIPI_TXP3__SD1_D1 1 +#define PAD_MIPI_TXP3__VO_D_27 2 +#define PAD_MIPI_TXP3__XGPIOC_21 3 +#define PAD_MIPI_TXP3__IIC2_SCL 4 +#define PAD_MIPI_TXP3__PWM_15 5 +#define PAD_MIPI_TXP3__IIC1_SCL 6 +#define PAD_MIPI_TXP3__CAM_HS0 7 +#define PAD_MIPI_TXM2__VI0_D_13 1 +#define PAD_MIPI_TXM2__VO_D_0 2 +#define PAD_MIPI_TXM2__XGPIOC_16 3 +#define PAD_MIPI_TXM2__IIC1_SDA 4 +#define PAD_MIPI_TXM2__PWM_8 5 +#define PAD_MIPI_TXM2__SPI0_SCK 6 +#define PAD_MIPI_TXM2__SD1_D2 7 +#define PAD_MIPI_TXP2__VI0_D_14 1 +#define PAD_MIPI_TXP2__VO_CLK0 2 +#define PAD_MIPI_TXP2__XGPIOC_17 3 +#define PAD_MIPI_TXP2__IIC1_SCL 4 +#define PAD_MIPI_TXP2__PWM_9 5 +#define PAD_MIPI_TXP2__SPI0_CS_X 6 +#define PAD_MIPI_TXP2__SD1_D3 7 +#define PAD_MIPI_TXM1__VI0_D_11 1 +#define PAD_MIPI_TXM1__VO_D_2 2 +#define PAD_MIPI_TXM1__XGPIOC_14 3 +#define PAD_MIPI_TXM1__IIC2_SDA 4 +#define PAD_MIPI_TXM1__PWM_10 5 +#define PAD_MIPI_TXM1__SPI0_SDO 6 +#define PAD_MIPI_TXM1__DBG_14 7 +#define PAD_MIPI_TXP1__VI0_D_12 1 +#define PAD_MIPI_TXP1__VO_D_1 2 +#define PAD_MIPI_TXP1__XGPIOC_15 3 +#define PAD_MIPI_TXP1__IIC2_SCL 4 +#define PAD_MIPI_TXP1__PWM_11 5 +#define PAD_MIPI_TXP1__SPI0_SDI 6 +#define PAD_MIPI_TXP1__DBG_15 7 +#define PAD_MIPI_TXM0__VI0_D_9 1 +#define PAD_MIPI_TXM0__VO_D_4 2 +#define PAD_MIPI_TXM0__XGPIOC_12 3 +#define PAD_MIPI_TXM0__CAM_MCLK1 4 +#define PAD_MIPI_TXM0__PWM_14 5 +#define PAD_MIPI_TXM0__CAM_VS0 6 +#define PAD_MIPI_TXM0__DBG_12 7 +#define PAD_MIPI_TXP0__VI0_D_10 1 +#define PAD_MIPI_TXP0__VO_D_3 2 +#define PAD_MIPI_TXP0__XGPIOC_13 3 +#define PAD_MIPI_TXP0__CAM_MCLK0 4 +#define PAD_MIPI_TXP0__PWM_15 5 +#define PAD_MIPI_TXP0__CAM_HS0 6 +#define PAD_MIPI_TXP0__DBG_13 7 +#define PAD_AUD_AINL_MIC__XGPIOC_23 3 +#define PAD_AUD_AINL_MIC__IIS1_BCLK 4 +#define PAD_AUD_AINL_MIC__IIS2_BCLK 5 +#define PAD_AUD_AINR_MIC__XGPIOC_22 3 +#define PAD_AUD_AINR_MIC__IIS1_DO 4 +#define PAD_AUD_AINR_MIC__IIS2_DI 5 +#define PAD_AUD_AINR_MIC__IIS1_DI 6 +#define PAD_AUD_AOUTL__XGPIOC_25 3 +#define PAD_AUD_AOUTL__IIS1_LRCK 4 +#define PAD_AUD_AOUTL__IIS2_LRCK 5 +#define PAD_AUD_AOUTR__XGPIOC_24 3 +#define PAD_AUD_AOUTR__IIS1_DI 4 +#define PAD_AUD_AOUTR__IIS2_DO 5 +#define PAD_AUD_AOUTR__IIS1_DO 6 +#define GPIO_RTX__XGPIOB_23 3 +#define GPIO_RTX__PWM_1 4 +#define GPIO_RTX__CAM_MCLK0 5 +#define GPIO_ZQ__PWR_GPIO_24 3 +#define GPIO_ZQ__PWM_2 4 diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h new file mode 100755 index 0000000000..9b3e81ef42 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_pinmux.h @@ -0,0 +1,46 @@ +#ifndef _CV181X_PINMUX_H_ +#define _CV181X_PINMUX_H_ + +#define PINMUX_UART0 0 +#define PINMUX_UART1 1 +#define PINMUX_UART2 2 +#define PINMUX_UART3 3 +#define PINMUX_UART3_2 4 +#define PINMUX_I2C0 5 +#define PINMUX_I2C1 6 +#define PINMUX_I2C2 7 +#define PINMUX_I2C3 8 +#define PINMUX_I2C4 9 +#define PINMUX_I2C4_2 10 +#define PINMUX_SPI0 11 +#define PINMUX_SPI1 12 +#define PINMUX_SPI2 13 +#define PINMUX_SPI2_2 14 +#define PINMUX_SPI3 15 +#define PINMUX_SPI3_2 16 +#define PINMUX_I2S0 17 +#define PINMUX_I2S1 18 +#define PINMUX_I2S2 19 +#define PINMUX_I2S3 20 +#define PINMUX_USBID 21 +#define PINMUX_SDIO0 22 +#define PINMUX_SDIO1 23 +#define PINMUX_ND 24 +#define PINMUX_EMMC 25 +#define PINMUX_SPI_NOR 26 +#define PINMUX_SPI_NAND 27 +#define PINMUX_CAM0 28 +#define PINMUX_CAM1 29 +#define PINMUX_PCM0 30 +#define PINMUX_PCM1 31 +#define PINMUX_CSI0 32 +#define PINMUX_CSI1 33 +#define PINMUX_CSI2 34 +#define PINMUX_DSI 35 +#define PINMUX_VI0 36 +#define PINMUX_VO 37 +#define PINMUX_PWM1 38 +#define PINMUX_UART4 39 +#define PINMUX_SPI_NOR1 40 + +#endif // end of _CV181X_PINMUX_H_ diff --git a/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h new file mode 100755 index 0000000000..5dbf34be30 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/cv181x_reg_fmux_gpio.h @@ -0,0 +1,475 @@ +// $Module: fmux_gpio $ +// $RegisterBank Version: V 1.0.00 $ +// $Author: ghost $ +// $Date: Fri, 30 Jul 2021 08:58:54 PM $ +// + +//GEN REG ADDR/OFFSET/MASK +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK0 0x0 +#define FMUX_GPIO_REG_IOCTRL_CAM_PD0 0x4 +#define FMUX_GPIO_REG_IOCTRL_CAM_RST0 0x8 +#define FMUX_GPIO_REG_IOCTRL_CAM_MCLK1 0xc +#define FMUX_GPIO_REG_IOCTRL_CAM_PD1 0x10 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SCL 0x14 +#define FMUX_GPIO_REG_IOCTRL_IIC3_SDA 0x18 +#define FMUX_GPIO_REG_IOCTRL_SD0_CLK 0x1c +#define FMUX_GPIO_REG_IOCTRL_SD0_CMD 0x20 +#define FMUX_GPIO_REG_IOCTRL_SD0_D0 0x24 +#define FMUX_GPIO_REG_IOCTRL_SD0_D1 0x28 +#define FMUX_GPIO_REG_IOCTRL_SD0_D2 0x2c +#define FMUX_GPIO_REG_IOCTRL_SD0_D3 0x30 +#define FMUX_GPIO_REG_IOCTRL_SD0_CD 0x34 +#define FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_REG_IOCTRL_SPK_EN 0x3c +#define FMUX_GPIO_REG_IOCTRL_UART0_TX 0x40 +#define FMUX_GPIO_REG_IOCTRL_UART0_RX 0x44 +#define FMUX_GPIO_REG_IOCTRL_EMMC_RSTN 0x48 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT2 0x4c +#define FMUX_GPIO_REG_IOCTRL_EMMC_CLK 0x50 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT0 0x54 +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT3 0x58 +#define FMUX_GPIO_REG_IOCTRL_EMMC_CMD 0x5c +#define FMUX_GPIO_REG_IOCTRL_EMMC_DAT1 0x60 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_REG_IOCTRL_IIC0_SCL 0x70 +#define FMUX_GPIO_REG_IOCTRL_IIC0_SDA 0x74 +#define FMUX_GPIO_REG_IOCTRL_AUX0 0x78 +#define FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_REG_IOCTRL_PWR_RSTN 0x80 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ1 0x84 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ2 0x88 +#define FMUX_GPIO_REG_IOCTRL_PWR_SEQ3 0x8c +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_REG_IOCTRL_PWR_ON 0x9c +#define FMUX_GPIO_REG_IOCTRL_XTAL_XIN 0xa0 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_REG_IOCTRL_PWR_GPIO2 0xac +#define FMUX_GPIO_REG_IOCTRL_CLK32K 0xb0 +#define FMUX_GPIO_REG_IOCTRL_CLK25M 0xb4 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SCL 0xb8 +#define FMUX_GPIO_REG_IOCTRL_IIC2_SDA 0xbc +#define FMUX_GPIO_REG_IOCTRL_UART2_TX 0xc0 +#define FMUX_GPIO_REG_IOCTRL_UART2_RTS 0xc4 +#define FMUX_GPIO_REG_IOCTRL_UART2_RX 0xc8 +#define FMUX_GPIO_REG_IOCTRL_UART2_CTS 0xcc +#define FMUX_GPIO_REG_IOCTRL_SD1_D3 0xd0 +#define FMUX_GPIO_REG_IOCTRL_SD1_D2 0xd4 +#define FMUX_GPIO_REG_IOCTRL_SD1_D1 0xd8 +#define FMUX_GPIO_REG_IOCTRL_SD1_D0 0xdc +#define FMUX_GPIO_REG_IOCTRL_SD1_CMD 0xe0 +#define FMUX_GPIO_REG_IOCTRL_SD1_CLK 0xe4 +#define FMUX_GPIO_REG_IOCTRL_RSTN 0xe8 +#define FMUX_GPIO_REG_IOCTRL_PWM0_BUCK 0xec +#define FMUX_GPIO_REG_IOCTRL_ADC3 0xf0 +#define FMUX_GPIO_REG_IOCTRL_ADC2 0xf4 +#define FMUX_GPIO_REG_IOCTRL_ADC1 0xf8 +#define FMUX_GPIO_REG_IOCTRL_USB_ID 0xfc +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE0 0x104 +#define FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE1 0x10c +#define FMUX_GPIO_REG_IOCTRL_PKG_TYPE2 0x110 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D10 0x134 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D9 0x138 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D8 0x13c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D7 0x140 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D6 0x144 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D5 0x148 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D4 0x14c +#define FMUX_GPIO_REG_IOCTRL_VIVO_D3 0x150 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D2 0x154 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D1 0x158 +#define FMUX_GPIO_REG_IOCTRL_VIVO_D0 0x15c +#define FMUX_GPIO_REG_IOCTRL_VIVO_CLK 0x160 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_REG_IOCTRL_GPIO_RTX 0x1cc +#define FMUX_GPIO_REG_IOCTRL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0 0x0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD0 0x4 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_RST0 0x8 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_RST0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1 0xc +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_MCLK1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CAM_PD1 0x10 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CAM_PD1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL 0x14 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA 0x18 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC3_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CLK 0x1c +#define FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CMD 0x20 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D0 0x24 +#define FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D1 0x28 +#define FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D2 0x2c +#define FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_D3 0x30 +#define FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_CD 0x34 +#define FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_CD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN 0x38 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SPK_EN 0x3c +#define FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SPK_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_TX 0x40 +#define FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART0_RX 0x44 +#define FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART0_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN 0x48 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2 0x4c +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK 0x50 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0 0x54 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3 0x58 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD 0x5c +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1 0x60 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_EMMC_DAT1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS 0x64 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK 0x68 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST 0x6c +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_JTAG_CPU_TRST_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL 0x70 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA 0x74 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_AUX0 0x78 +#define FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_AUX0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET 0x7c +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN 0x80 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1 0x84 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2 0x88 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3 0x8c +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_SEQ3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0 0x90 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1 0x94 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_WAKEUP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1 0x98 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_ON 0x9c +#define FMUX_GPIO_FUNCSEL_PWR_ON_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_ON_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN 0xa0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0 0xa4 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1 0xa8 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2 0xac +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK32K 0xb0 +#define FMUX_GPIO_FUNCSEL_CLK32K_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK32K_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_CLK25M 0xb4 +#define FMUX_GPIO_FUNCSEL_CLK25M_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_CLK25M_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL 0xb8 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SCL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA 0xbc +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_IIC2_SDA_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_TX 0xc0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_TX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RTS 0xc4 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_RX 0xc8 +#define FMUX_GPIO_FUNCSEL_UART2_RX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_RX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_UART2_CTS 0xcc +#define FMUX_GPIO_FUNCSEL_UART2_CTS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_UART2_CTS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D3 0xd0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D2 0xd4 +#define FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D1 0xd8 +#define FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_D0 0xdc +#define FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CMD 0xe0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CMD_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_SD1_CLK 0xe4 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_SD1_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_RSTN 0xe8 +#define FMUX_GPIO_FUNCSEL_RSTN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_RSTN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK 0xec +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC3 0xf0 +#define FMUX_GPIO_FUNCSEL_ADC3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC2 0xf4 +#define FMUX_GPIO_FUNCSEL_ADC2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_ADC1 0xf8 +#define FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_ADC1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_ID 0xfc +#define FMUX_GPIO_FUNCSEL_USB_ID_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_ID_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN 0x100 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_EN_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0 0x104 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET 0x108 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1 0x10c +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2 0x110 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO 0x114 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI 0x118 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS 0x11c +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK 0x120 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM 0x124 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP 0x128 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM 0x12c +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP 0x130 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D10 0x134 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D10_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D9 0x138 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D9_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D8 0x13c +#define FMUX_GPIO_FUNCSEL_VIVO_D8_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D8_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D7 0x140 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D7_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D6 0x144 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D6_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D5 0x148 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D5_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D4 0x14c +#define FMUX_GPIO_FUNCSEL_VIVO_D4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D3 0x150 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D2 0x154 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D1 0x158 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_D0 0x15c +#define FMUX_GPIO_FUNCSEL_VIVO_D0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_D0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK 0x160 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_VIVO_CLK_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N 0x164 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P 0x168 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX5P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N 0x16c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P 0x170 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N 0x174 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P 0x178 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N 0x17c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P 0x180 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N 0x184 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P 0x188 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N 0x18c +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P 0x190 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4 0x194 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4 0x198 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP4_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3 0x19c +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3 0x1a0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP3_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2 0x1a4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2 0x1a8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1 0x1ac +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1 0x1b0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0 0x1b4 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0 0x1b8 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC 0x1bc +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC 0x1c0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL 0x1c4 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR 0x1c8 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX 0x1cc +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK 0x7 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ 0x1d0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0 +#define FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK 0x7 diff --git a/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h new file mode 100755 index 0000000000..58bd0938d3 --- /dev/null +++ b/bsp/cvitek/drivers/libraries/cv181x/pinctrl.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved. + * + * File Name: pinctrl.h + * Description: + */ + +#ifndef __PINCTRL_CV181X_H__ +#define __PINCTRL_CV181X_H__ + +//#include "../core.h" +#include "cv181x_pinlist_swconfig.h" +#include "cv181x_reg_fmux_gpio.h" + +#define PAD_MIPI_TXM4__MIPI_TXM4 0 +#define PAD_MIPI_TXP4__MIPI_TXP4 0 +#define PAD_MIPI_TXM3__MIPI_TXM3 0 +#define PAD_MIPI_TXP3__MIPI_TXP3 0 +#define PAD_MIPI_TXM2__MIPI_TXM2 0 +#define PAD_MIPI_TXP2__MIPI_TXP2 0 +#define PAD_MIPI_TXM1__MIPI_TXM1 0 +#define PAD_MIPI_TXP1__MIPI_TXP1 0 +#define PAD_MIPI_TXM0__MIPI_TXM0 0 +#define PAD_MIPI_TXP0__MIPI_TXP0 0 + +#define PINMUX_BASE 0x03001000 +#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK +#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET +#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME +#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \ + mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \ + PINMUX_MASK(PIN_NAME) << PINMUX_OFFSET(PIN_NAME), \ + PINMUX_VALUE(PIN_NAME, FUNC_NAME)) + +#endif /* __PINCTRL_CV181X_H__ */ diff --git a/bsp/cvitek/drivers/cv1800b/mmio.h b/bsp/cvitek/drivers/libraries/mmio.h old mode 100644 new mode 100755 similarity index 100% rename from bsp/cvitek/drivers/cv1800b/mmio.h rename to bsp/cvitek/drivers/libraries/mmio.h diff --git a/bsp/cvitek/drivers/cv1800b/types.h b/bsp/cvitek/drivers/libraries/types.h similarity index 100% rename from bsp/cvitek/drivers/cv1800b/types.h rename to bsp/cvitek/drivers/libraries/types.h diff --git a/bsp/cvitek/cv1800b/mkimage b/bsp/cvitek/mkimage similarity index 100% rename from bsp/cvitek/cv1800b/mkimage rename to bsp/cvitek/mkimage diff --git a/bsp/cvitek/mksdimg.sh b/bsp/cvitek/mksdimg.sh new file mode 100755 index 0000000000..788def063a --- /dev/null +++ b/bsp/cvitek/mksdimg.sh @@ -0,0 +1,37 @@ +#/bin/sh +set -e + +PROJECT_PATH=$1 +IMAGE_NAME=$2 + +if [ -z "$PROJECT_PATH" ] || [ -z "$IMAGE_NAME" ]; then + echo "Usage: $0 " + exit 1 +fi + +ROOT_PATH=$(pwd) +echo ${ROOT_PATH} + +function get_board_type() +{ + BOARD_CONFIG=("CONFIG_BOARD_TYPE_MILKV_DUO" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR" "CONFIG_BOARD_TYPE_MILKV_DUO_SPINAND" "CONFIG_BOARD_TYPE_MILKV_DUO256M") + BOARD_VALUE=("milkv-duo" "milkv-duo-spinor" "milkv-duo-spinand" "milkv-duo256m") + + for ((i=0;i<${#BOARD_CONFIG[@]};i++)) + do + config_value=$(grep -w "${BOARD_CONFIG[i]}" ${PROJECT_PATH}/.config | cut -d= -f2) + if [ "$config_value" == "y" ]; then + BOARD_TYPE=${BOARD_VALUE[i]} + break + fi + done +} + +get_board_type + +echo "start compress kernel..." + +lzma -c -9 -f -k ${PROJECT_PATH}/${IMAGE_NAME} > ${PROJECT_PATH}/Image.lzma + +mkdir -p ${ROOT_PATH}/output/${BOARD_TYPE} +./mkimage -f ${PROJECT_PATH}/multi.its -r ${ROOT_PATH}/output/${BOARD_TYPE}/boot.sd \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin deleted file mode 100755 index 84ea0561c0..0000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin deleted file mode 100755 index c9902e4a9e..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin +++ /dev/null @@ -1 +0,0 @@ -ﾭ \ No newline at end of file diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env deleted file mode 100755 index cff9e11100..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env +++ /dev/null @@ -1,2 +0,0 @@ -MONITOR_RUNADDR=0x0000000080000000 -BLCP_2ND_RUNADDR=0x0000000083f40000 diff --git a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin deleted file mode 100755 index d2dabd6868..0000000000 Binary files a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin and /dev/null differ diff --git a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h deleted file mode 100755 index 906c5b0ba6..0000000000 --- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __BOARD_MMAP__83494f74__ -#define __BOARD_MMAP__83494f74__ - -#define CONFIG_SYS_TEXT_BASE 0x80200000 /* offset 2.0MiB */ -#define CVIMMAP_ATF_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_BOOTLOGO_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_BOOTLOGO_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000 /* offset 35.0MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00 /* offset 19.9990234375MiB */ -#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400 /* 1.0KiB */ -#define CVIMMAP_DRAM_BASE 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_DRAM_SIZE 0x4000000 /* 64.0MiB */ -#define CVIMMAP_FREERTOS_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_FREERTOS_SIZE 0xc0000 /* 768.0KiB */ -#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000 /* offset 63.25MiB */ -#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000 /* 15.0MiB */ -#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_ION_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ION_SIZE 0x1acd000 /* 26.80078125MiB */ -#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000 /* offset 36.44921875MiB */ -#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0 /* 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000 /* 63.25MiB */ -#define CVIMMAP_MONITOR_ADDR 0x80000000 /* offset 0.0KiB */ -#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000 /* offset 512.0KiB */ -#define CVIMMAP_OPENSBI_SIZE 0x80000 /* 512.0KiB */ -#define CVIMMAP_UIMAG_ADDR 0x81400000 /* offset 20.0MiB */ -#define CVIMMAP_UIMAG_SIZE 0xf00000 /* 15.0MiB */ - -#endif /* __BOARD_MMAP__83494f74__ */ diff --git a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py deleted file mode 100755 index 2c487eda69..0000000000 --- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py +++ /dev/null @@ -1,38 +0,0 @@ -#!/usr/bin/env python3 - -import logging -import struct -import argparse - -CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD -CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE - -CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0 - - -def gen_chip_conf(args): - logging.info("gen_chip_conf") - regs = [ - (0x0E00000C, 0xA0000001), # ATF_DBG_REG = 0x0E00000C - (0x0E00000C, 0xA0000002), - # (CHIP_CONF_CMD_DELAY_MS, 100), - # (CHIP_CONF_CMD_DELAY_US, 100), - (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF), - ] - - chip_conf = b"".join(struct.pack("= %r is required" % (PYTHON_MIN_VERSION,)) - sys.exit(-1) - - -try: - import coloredlogs -except ImportError: - coloredlogs = None - -try: - import argcomplete -except ImportError: - argcomplete = None - - -LOADER_2ND_MAGIC_ORIG = b"BL33" -LOADER_2ND_MAGIC_LZMA = b"B3MA" -LOADER_2ND_MAGIC_LZ4 = b"B3Z4" - -LOADER_2ND_MAGIC_LIST = [ - LOADER_2ND_MAGIC_ORIG, - LOADER_2ND_MAGIC_LZMA, - LOADER_2ND_MAGIC_LZ4, -] - -IMAGE_ALIGN = 512 -PARAM1_SIZE = 0x1000 -PARAM1_SIZE_WO_SIG = 0x800 -PARAM2_SIZE = 0x1000 - - -def round_up(divident, divisor): - return ((divident + divisor - 1) // divisor) * divisor - - -def lzma_compress(body): - z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME) - compressed = z.compress(body) - compressed += z.flush() - - return compressed - - -def lz4_compress(body): - try: - import lz4.frame - except ImportError: - logging.error("lz4 is not installed. Run 'pip install lz4'.") - raise - - compressed = lz4.frame.compress(body) - return compressed - - -class Entry: - __slots__ = "name", "type", "addr", "_content", "entry_size" - - def __init__(self): - self.addr = None - self._content = None - - @property - def end(self): - return self.addr + self.entry_size - - @property - def content(self): - return self._content - - @content.setter - def content(self, value): - if type(value) == int: - value = value.to_bytes(self.entry_size, "little") - - if self.entry_size is not None: - if len(value) > self.entry_size: - raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size)) - value = value + b"\0" * (self.entry_size - len(value)) - - self._content = value - - @classmethod - def make(cls, name, entry_size, _type, init=None): - entry = Entry() - entry.name = name - entry.type = _type - entry.entry_size = entry_size - - if type(init) in (bytes, bytearray): - entry.content = bytes(init) - elif entry_size is not None: - entry.content = b"\0" * entry.entry_size - else: - entry.content = b"" - - return (name, entry) - - def toint(self): - if self.type != int: - raise TypeError("%s is not int type" % self.name) - - return int.from_bytes(self.content, "little") - - def tostr(self): - v = self.content - if self.type == int: - v = "%#08x" % self.toint() - elif type(self.content) in [bytes, bytearray]: - v = v.hex() - if len(v) > 32: - v = v[:32] + "..." - - return v - - def __str__(self): - v = self.tostr() - return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size) - - def __repr__(self): - v = self.tostr() - return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type) - - -class FIP: - param1 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"), - Entry.make("MAGIC2", 4, int), - Entry.make("PARAM_CKSUM", 4, int), - Entry.make("NAND_INFO", 128, int), - Entry.make("NOR_INFO", 36, int), - Entry.make("FIP_FLAGS", 8, int), - Entry.make("CHIP_CONF_SIZE", 4, int), - Entry.make("BLCP_IMG_CKSUM", 4, int), - Entry.make("BLCP_IMG_SIZE", 4, int), - Entry.make("BLCP_IMG_RUNADDR", 4, int), - Entry.make("BLCP_PARAM_LOADADDR", 4, int), - Entry.make("BLCP_PARAM_SIZE", 4, int), - Entry.make("BL2_IMG_CKSUM", 4, int), - Entry.make("BL2_IMG_SIZE", 4, int), - Entry.make("BLD_IMG_SIZE", 4, int), - Entry.make("PARAM2_LOADADDR", 4, int), - Entry.make("RESERVED1", 4, int), - Entry.make("CHIP_CONF", 760, bytes), - Entry.make("BL_EK", 32, bytes), - Entry.make("ROOT_PK", 512, bytes), - Entry.make("BL_PK", 512, bytes), - Entry.make("BL_PK_SIG", 512, bytes), - Entry.make("CHIP_CONF_SIG", 512, bytes), - Entry.make("BL2_IMG_SIG", 512, bytes), - Entry.make("BLCP_IMG_SIG", 512, bytes), - ] - ) - - body1 = OrderedDict( - [ - Entry.make("BLCP", None, bytes), - Entry.make("BL2", None, bytes), - ] - ) - - param2 = OrderedDict( - [ - Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"), - Entry.make("PARAM2_CKSUM", 4, int), - Entry.make("RESERVED1", 4, bytes), - # DDR param - Entry.make("DDR_PARAM_CKSUM", 4, int), - Entry.make("DDR_PARAM_LOADADDR", 4, int), - Entry.make("DDR_PARAM_SIZE", 4, int), - Entry.make("DDR_PARAM_RESERVED", 4, int), - # BLCP_2ND - Entry.make("BLCP_2ND_CKSUM", 4, int), - Entry.make("BLCP_2ND_LOADADDR", 4, int), - Entry.make("BLCP_2ND_SIZE", 4, int), - Entry.make("BLCP_2ND_RUNADDR", 4, int), - # ATF-BL31 or OpenSBI - Entry.make("MONITOR_CKSUM", 4, int), - Entry.make("MONITOR_LOADADDR", 4, int), - Entry.make("MONITOR_SIZE", 4, int), - Entry.make("MONITOR_RUNADDR", 4, int), - # u-boot - Entry.make("LOADER_2ND_RESERVED0", 4, int), - Entry.make("LOADER_2ND_LOADADDR", 4, int), - Entry.make("LOADER_2ND_RESERVED1", 4, int), - Entry.make("LOADER_2ND_RESERVED2", 4, int), - # Reserved - Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes), - ] - ) - - body2 = OrderedDict( - [ - Entry.make("DDR_PARAM", None, bytes), - Entry.make("BLCP_2ND", None, bytes), - Entry.make("MONITOR", None, bytes), - Entry.make("LOADER_2ND", None, bytes), - ] - ) - - ldr_2nd_hdr = OrderedDict( - [ - Entry.make("JUMP0", 4, int), - Entry.make("MAGIC", 4, int), - Entry.make("CKSUM", 4, int), - Entry.make("SIZE", 4, int), - Entry.make("RUNADDR", 8, int), - Entry.make("RESERVED1", 4, int), - Entry.make("RESERVED2", 4, int), - ] - ) - - FIP_FLAGS_SCS_MASK = 0x000c - FIP_FLAGS_ENCRYPTED_MASK = 0x0030 - - def _param_size(self, param): - return max((e.end for e in param.values())) - - def _gen_param(self): - addr = 0 - for entry in self.param1.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr - - addr = 0 - for entry in self.param2.values(): - entry.addr = addr - addr += entry.entry_size - - assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size - - addr = 0 - for entry in self.ldr_2nd_hdr.values(): - entry.addr = addr - addr += entry.entry_size - - def __init__(self): - self.compress_algo = None - self._gen_param() - - def image_crc(self, image): - crc = binascii.crc_hqx(image, 0) - crc = pack("