[bsp][stm32] optimize eth driver
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688d8994d9
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40a474fefa
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@ -260,6 +260,9 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
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/* TODO Optimize data send speed*/
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LOG_D("transmit frame lenth :%d", framelength);
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/* wait for unlocked */
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while (EthHandle.Lock == HAL_LOCKED);
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state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
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if (state != HAL_OK)
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{
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@ -410,6 +413,40 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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LOG_E("eth err");
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}
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#ifdef PHY_USING_INTERRUPT_MODE
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static void eth_phy_isr(void *args)
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{
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rt_uint32_t status = 0;
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static rt_uint8_t link_status = 1;
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
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LOG_D("phy interrupt status reg is 0x%X", status);
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
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LOG_D("phy basic status reg is 0x%X", status);
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if (status & PHY_LINKED_STATUS_MASK)
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{
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if (link_status == 0)
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{
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link_status = 1;
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LOG_D("link up");
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/* send link up. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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}
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}
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else
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{
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if (link_status == 1)
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{
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link_status = 0;
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LOG_I("link down");
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/* send link down. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
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}
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}
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}
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#endif /* PHY_USING_INTERRUPT_MODE */
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static uint8_t phy_speed = 0;
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#define PHY_LINK_MASK (1<<0)
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static void phy_monitor_thread_entry(void *parameter)
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@ -435,12 +472,12 @@ static void phy_monitor_thread_entry(void *parameter)
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if (phy_addr == 0xFF)
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{
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LOG_E("phy not probe!\r\n");
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LOG_E("phy not probe!");
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return;
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}
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else
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{
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LOG_D("found a phy, address:0x%02X\r\n", phy_addr);
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LOG_D("found a phy, address:0x%02X", phy_addr);
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}
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/* RESET PHY */
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@ -452,7 +489,7 @@ static void phy_monitor_thread_entry(void *parameter)
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while (1)
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{
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HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
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LOG_D("PHY BASIC STATUS REG:0x%04X\r\n", status);
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LOG_D("PHY BASIC STATUS REG:0x%04X", status);
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phy_speed_new = 0;
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@ -512,10 +549,21 @@ static void phy_monitor_thread_entry(void *parameter)
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/* send link up. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
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#ifdef PHY_USING_INTERRUPT_MODE
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/* configuration intterrupt pin */
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rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
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rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
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rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
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/* enable phy interrupt */
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HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MSAK_REG, PHY_INT_MASK);
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break;
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#endif
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} /* link up. */
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else
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{
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LOG_I("link down\r\n");
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LOG_I("link down");
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/* send link down. */
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eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
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}
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@ -55,6 +55,13 @@
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#define PHY_10M_MASK ((1<<12) || (1<<13))
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#define PHY_100M_MASK ((1<<14) || (1<<15))
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#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
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/* The PHY interrupt source flag register. */
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#define PHY_INTERRUPT_FLAG_REG 0x15U
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/* The PHY interrupt mask register. */
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#define PHY_INTERRUPT_MSAK_REG 0x15U
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#define PHY_LINK_CHANGE_FLAG (1<<2)
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#define PHY_LINK_CHANGE_MASK (1<<9)
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#define PHY_INT_MASK 0
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#endif /* PHY_USING_DM9161CEP */
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