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[stm32][eth] beautify codes

This commit is contained in:
Meco Man 2021-07-30 14:14:08 +08:00
parent c255c49b82
commit 3cb13b4523
2 changed files with 20 additions and 16 deletions
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24
bsp/stm32/libraries/HAL_Drivers/drv_eth.c
View File

@ -41,9 +41,9 @@ struct rt_stm32_eth
/* interface address info, hw address */
rt_uint8_t dev_addr[MAX_ADDR_LEN];
/* ETH_Speed */
uint32_t ETH_Speed;
rt_uint32_t ETH_Speed;
/* ETH_Duplex_Mode */
uint32_t ETH_Mode;
rt_uint32_t ETH_Mode;
};
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
@ -167,8 +167,14 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
{
case NIOCTL_GADDR:
/* get mac address */
if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
else return -RT_ERROR;
if (args)
{
rt_memcpy(args, stm32_eth_device.dev_addr, 6);
}
else
{
return -RT_ERROR;
}
break;
default :
@ -214,7 +220,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
{
/* Copy data to Tx buffer*/
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
rt_memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
@ -236,7 +242,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
}
/* Copy the remaining bytes */
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
rt_memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
framelength = framelength + byteslefttocopy;
}
@ -327,7 +333,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
{
/* Copy data to pbuf */
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
rt_memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
/* Point to next descriptor */
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
@ -338,7 +344,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
bufferoffset = 0;
}
/* Copy remaining data in pbuf */
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
rt_memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
bufferoffset = bufferoffset + byteslefttocopy;
}
}
@ -385,7 +391,9 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
rt_err_t result;
result = eth_device_ready(&(stm32_eth_device.parent));
if (result != RT_EOK)
{
LOG_I("RxCpltCallback err = %d", result);
}
}
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)

12
bsp/stm32/libraries/HAL_Drivers/drv_eth.h
View File

@ -28,13 +28,12 @@
/* The PHY ID one register */
#define PHY_ID1_REG 0x02U
/* The PHY ID two register */
#define PHY_ID2_REG 0x03U
/* The PHY auto-negotiate advertise register */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
#ifdef PHY_USING_LAN8720A
/* The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG 0x1DU
@ -51,9 +50,8 @@
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
#endif /* PHY_USING_LAN8720A */
#ifdef PHY_USING_DM9161CEP
#elif defined(PHY_USING_DM9161CEP)
#define PHY_Status_REG 0x11U
#define PHY_10M_MASK ((1<<12) || (1<<13))
#define PHY_100M_MASK ((1<<14) || (1<<15))
@ -69,9 +67,7 @@
#define PHY_LINK_CHANGE_MASK (1<<9)
#define PHY_INT_MASK 0
#endif /* PHY_USING_DM9161CEP */
#ifdef PHY_USING_DP83848C
#elif defined(PHY_USING_DP83848C)
#define PHY_Status_REG 0x10U
#define PHY_10M_MASK (1<<1)
#define PHY_FULL_DUPLEX_MASK (1<<2)
@ -87,6 +83,6 @@
/* The PHY interrupt mask register. */
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK (1<<5)
#endif /* PHY_USING_DP83848C */
#endif
#endif /* __DRV_ETH_H__ */