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fix trap_entry

This commit is contained in:
zhangjun 2017-07-29 15:37:20 +08:00
parent b80f83f360
commit 3c51848d33
9 changed files with 74 additions and 68 deletions
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6
bsp/risc-v/Makefile
View File

@ -105,20 +105,18 @@ DEBUG_INTERFACE = jlink
#DEBUG_INTERFACE = ftdi/openjtag #DEBUG_INTERFACE = ftdi/openjtag
GDB_CMD = -ex "tar ext 127.0.0.1:3333" GDB_CMD = -ex "tar ext 127.0.0.1:3333"
GDB_CMD += -ex "monitor reset halt" #GDB_CMD += -ex "monitor reset halt"
#GDB_CMD += -ex "monitor step 0x20400000" #GDB_CMD += -ex "monitor step 0x20400000"
GDB_CMD += --command=.gdbinit GDB_CMD += --command=.gdbinit
run: run:
setsid ${OPENOCD} > /dev/null 2>&1 & setsid ${OPENOCD} > /dev/null 2>&1 &
# (sleep 1 && echo -e "halt" && sleep 1) | telnet 127.0.0.1 4444
${GDB} ${TARGET}.axf ${GDB_CMD} ${GDB} ${TARGET}.axf ${GDB_CMD}
# arm-none-eabi-gdb ${TARGET} -ex "tar ext 127.0.0.1:3333" -ex "b main" -ex "lay n" -ex "lay n" -ex "lay n"
killall -9 openocd killall -9 openocd
programe: programe:
setsid ${OPENOCD} > /dev/null 2>&1 & setsid ${OPENOCD} > /dev/null 2>&1 &
${GDB} ${TARGET}.axf -ex "tar ext 127.0.0.1:3333" -ex "load ${TARGET}.axf" ${GDB} ${TARGET}.axf -ex "tar ext 127.0.0.1:3333" -ex "monitor step 0x20400000" -ex "load ${TARGET}.axf"
killall -9 openocd killall -9 openocd
clean: clean:

10
bsp/risc-v/applications/applications.c
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@ -8,12 +8,20 @@ static void rt_init_thread_entry(void* parameter)
#endif #endif
rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2 ); /* sleep 0.5 second and switch to other thread */ rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2 ); /* sleep 0.5 second and switch to other thread */
} }
#include <encoding.h>
#include <platform.h>
static void led_thread_entry(void* parameter) static void led_thread_entry(void* parameter)
{ {
unsigned int count=0; unsigned int count=0;
rt_hw_led_init(); rt_hw_led_init();
rt_hw_interrupt_enable(0x888);
set_csr(mstatus, MSTATUS_MIE);
asm(
"csrr a5, mie"
);
rt_kprintf("core freq at %d Hz\n", get_cpu_freq());
while (1) while (1)
{ {
/* led1 on */ /* led1 on */
@ -21,8 +29,8 @@ static void led_thread_entry(void* parameter)
/* rt_kprintf("led on, count : %d\r\n",count);*/ /* rt_kprintf("led on, count : %d\r\n",count);*/
#endif #endif
count++; count++;
rt_hw_led_on(0);
rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2 ); /* sleep 0.5 second and switch to other thread */ rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2 ); /* sleep 0.5 second and switch to other thread */
rt_hw_led_on(0);
/* led1 off */ /* led1 off */
#ifndef RT_USING_FINSH #ifndef RT_USING_FINSH

2
bsp/risc-v/applications/startup.c
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@ -29,8 +29,8 @@ static void rtthread_startup(void)
/* initialize idle thread */ /* initialize idle thread */
rt_thread_idle_init(); rt_thread_idle_init();
while(1);
/* start scheduler */ /* start scheduler */
while(1);
rt_system_scheduler_start(); rt_system_scheduler_start();
/* never reach here */ /* never reach here */

5
bsp/risc-v/drivers/board.c
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@ -27,11 +27,12 @@ static void rt_hw_timer_init(void)
GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ;
GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ; GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ;
rt_hw_interrupt_enable(1); rt_hw_interrupt_enable(1);
/* set_csr(mie, MIP_MTIP);*/
CLINT_REG(CLINT_MTIME) = 0x0; CLINT_REG(CLINT_MTIME) = 0x0;
CLINT_REG(CLINT_MTIMECMP) = 0x10000; CLINT_REG(CLINT_MTIMECMP) = 0x10000;
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
set_csr(mstatus, MSTATUS_MIE); set_csr(mstatus, MSTATUS_MIE);
*mtimecmp = 0x20000;
return; return;
} }
void rt_hw_board_init(void) void rt_hw_board_init(void)
@ -43,7 +44,7 @@ void rt_hw_board_init(void)
/* initialize the system clock */ /* initialize the system clock */
//rt_hw_clock_init(); //set each pll etc. //rt_hw_clock_init(); //set each pll etc.
/* initialize uart */ /* initialize uart */
rt_hw_uart_init(); rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME); rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

15
bsp/risc-v/drivers/usart.c
View File

@ -1,13 +1,18 @@
#include <rtdevice.h> #include <rtdevice.h>
#include "usart.h" #include "usart.h"
#include <encoding.h>
#include <platform.h>
/** /**
* @brief set uartdbg buard * @brief set uartdbg buard
* *
* @param buard * @param buard
*/ */
static usart_init(int buard) static void usart_init(int buard)
{ {
return; GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / buard - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
} }
static void usart_handler(int vector, void *param) static void usart_handler(int vector, void *param)
{ {
@ -17,6 +22,10 @@ static void usart_handler(int vector, void *param)
static rt_err_t usart_configure(struct rt_serial_device *serial, static rt_err_t usart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg) struct serial_configure *cfg)
{ {
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / 115200 - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
return RT_EOK; return RT_EOK;
} }
static rt_err_t usart_control(struct rt_serial_device *serial, static rt_err_t usart_control(struct rt_serial_device *serial,
@ -33,6 +42,8 @@ static rt_err_t usart_control(struct rt_serial_device *serial,
} }
static int usart_putc(struct rt_serial_device *serial, char c) static int usart_putc(struct rt_serial_device *serial, char c)
{ {
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
UART0_REG(UART_REG_TXFIFO) = c;
return 0; return 0;
} }
static int usart_getc(struct rt_serial_device *serial) static int usart_getc(struct rt_serial_device *serial)

2
bsp/risc-v/rtconfig.h
View File

@ -258,4 +258,6 @@
*/ */
//#define RT_USING_CPU_FFS //#define RT_USING_CPU_FFS
#define RT_USING_COMPONENTS_INIT #define RT_USING_COMPONENTS_INIT
#define IDLE_THREAD_STACK_SIZE 512
#endif #endif

66
libcpu/risc-v/e310/context_gcc.S
View File

@ -32,6 +32,7 @@
rt_hw_interrupt_disable: rt_hw_interrupt_disable:
addi sp, sp, -12 addi sp, sp, -12
sw a5, (sp) sw a5, (sp)
csrr a0, mie
li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP
csrrc a5, mie, a5 csrrc a5, mie, a5
/* csrrc a5, mstatus, MSTATUS_MIE*/ /* csrrc a5, mstatus, MSTATUS_MIE*/
@ -60,18 +61,18 @@ rt_hw_interrupt_enable:
*/ */
.globl rt_hw_context_switch .globl rt_hw_context_switch
rt_hw_context_switch: rt_hw_context_switch:
addi sp, sp, -32*REGBYTES addi sp, sp, -32*REGBYTES
STORE sp, (a0) STORE sp, (a0)
STORE x30, 1*REGBYTES(sp) STORE x30, 1*REGBYTES(sp)
STORE x31, 2*REGBYTES(sp) STORE x31, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp) STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp) STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp) STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp) STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp) STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp) STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp) STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp) STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp) STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp) STORE x12, 12*REGBYTES(sp)
@ -91,17 +92,15 @@ rt_hw_context_switch:
STORE x26, 26*REGBYTES(sp) STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp) STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp) STORE x28, 28*REGBYTES(sp)
STORE x1, 31*REGBYTES(sp) STORE x1, 31*REGBYTES(sp)
STORE x10, 29*REGBYTES(sp) STORE x10, 29*REGBYTES(sp)
STORE x1, 30*REGBYTES(sp) STORE x1, 30*REGBYTES(sp)
csrr a0, mcause
# Remain in M-mode after mret # Remain in M-mode after mret
li t0, MSTATUS_MPP li t0, MSTATUS_MPP
csrs mstatus, t0 csrs mstatus, t0
LOAD sp, (a1) LOAD sp, (a1)
LOAD x30, 1*REGBYTES(sp) LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp) LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp) LOAD x3, 3*REGBYTES(sp)
@ -131,12 +130,11 @@ rt_hw_context_switch:
LOAD x27, 27*REGBYTES(sp) LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp) LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp) LOAD x10, 31*REGBYTES(sp)
csrw mepc, a0 csrw mepc,a0
LOAD x10, 29*REGBYTES(sp) LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp) LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
addi sp, sp, 32*REGBYTES
mret mret
/* /*
@ -145,7 +143,7 @@ rt_hw_context_switch:
*/ */
.globl rt_hw_context_switch_to .globl rt_hw_context_switch_to
rt_hw_context_switch_to: rt_hw_context_switch_to:
LOAD sp, (a0) LOAD sp, (a0)
LOAD x30, 1*REGBYTES(sp) LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp) LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp) LOAD x3, 3*REGBYTES(sp)
@ -175,12 +173,12 @@ rt_hw_context_switch_to:
LOAD x27, 27*REGBYTES(sp) LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp) LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp) LOAD x10, 31*REGBYTES(sp)
csrw mepc, a0 csrw mepc,a0
LOAD x10, 29*REGBYTES(sp) LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp) LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES addi sp, sp, 32*REGBYTES
mret mret
@ -193,21 +191,21 @@ rt_hw_context_switch_to:
.globl rt_hw_context_switch_interrupt .globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt: rt_hw_context_switch_interrupt:
addi sp, sp, -16 addi sp, sp, -16
sw s0, 12(sp) sw s0, 12(sp)
sw a0, 8(sp) sw a0, 8(sp)
sw a5, 4(sp) sw a5, 4(sp)
la a0, rt_thread_switch_interrupt_flag la a0, rt_thread_switch_interrupt_flag
beqz a5, _reswitch beqz a5, _reswitch
li a5, 1 li a5, 1
sw a5, (a0) sw a5, (a0)
la a5, rt_interrupt_from_thread la a5, rt_interrupt_from_thread
lw a0, 8(sp) lw a0, 8(sp)
sw a0, (a5) sw a0, (a5)
_reswitch: _reswitch:
la a5, rt_interrupt_to_thread la a5, rt_interrupt_to_thread
sw a1, (a5) sw a1, (a5)
lw a5, 4(sp) lw a5, 4(sp)
lw a0, 8(sp) lw a0, 8(sp)
lw s0, 12(sp) lw s0, 12(sp)
addi sp, sp, 16 addi sp, sp, 16
ret ret

10
libcpu/risc-v/e310/init.c
View File

@ -175,13 +175,7 @@ unsigned long get_cpu_freq()
return cpu_freq; return cpu_freq;
} }
static void uart_init(size_t baud_rate)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
@ -220,9 +214,7 @@ void _init()
#ifndef NO_INIT #ifndef NO_INIT
use_default_clocks(); use_default_clocks();
use_pll(0, 0, 1, 31, 1); use_pll(0, 0, 1, 31, 1);
uart_init(115200);
printf("core freq at %d Hz\n", get_cpu_freq());
write_csr(mtvec, &trap_entry); write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present

26
libcpu/risc-v/e310/start_gcc.S
View File

@ -17,8 +17,7 @@ _start:
la gp, __global_pointer$ la gp, __global_pointer$
.option pop .option pop
la sp, _sp la sp, _sp
/*disable all interrupt*/ csrrsi a5, mstatus, 0
csrw mie, 0
#if defined(ENABLE_SMP) #if defined(ENABLE_SMP)
smp_pause(t0, t1) smp_pause(t0, t1)
@ -124,13 +123,13 @@ trap_entry:
STORE x30, 1*REGBYTES(sp) STORE x30, 1*REGBYTES(sp)
STORE x31, 2*REGBYTES(sp) STORE x31, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp) STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp) STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp) STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp) STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp) STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp) STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp) STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp) STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp) STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp) STORE x12, 12*REGBYTES(sp)
@ -150,13 +149,11 @@ trap_entry:
STORE x26, 26*REGBYTES(sp) STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp) STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp) STORE x28, 28*REGBYTES(sp)
STORE x1, 31*REGBYTES(sp)
STORE x10, 29*REGBYTES(sp) STORE x10, 29*REGBYTES(sp)
STORE x1, 30*REGBYTES(sp) STORE x1, 30*REGBYTES(sp)
csrr x1, mepc
STORE x1, 31*REGBYTES(sp)
csrr a0, mcause
csrr a1, mepc
csrw mepc, a0
call rt_interrupt_enter call rt_interrupt_enter
call rt_hw_trap_irq call rt_hw_trap_irq
@ -167,7 +164,6 @@ trap_entry:
lw a1, (a0) lw a1, (a0)
beqz a1, rt_hw_context_switch_interrupt_do beqz a1, rt_hw_context_switch_interrupt_do
csrw mepc, a0
# Remain in M-mode after mret # Remain in M-mode after mret
li t0, MSTATUS_MPP li t0, MSTATUS_MPP
csrs mstatus, t0 csrs mstatus, t0