[bsp/cvitek]add adc driver (#8562)
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flyingcys
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@ -32,9 +32,10 @@
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| 驱动 | 支持情况 | 备注 |
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| :--- | :------- | :---------------- |
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| UART | 支持 | 默认波特率115200 |
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| uart | 支持 | 默认波特率115200 |
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| gpio | 支持 | |
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| i2c | 支持 | |
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| adc | 支持 | |
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## 支持开发板
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- milk-v duo: [https://milkv.io/duo](https://milkv.io/duo)
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@ -39,4 +39,10 @@ menu "General Drivers Configuration"
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int
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default 32
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endif
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menuconfig BSP_USING_ADC
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bool "Using ADC"
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select RT_USING_ADC
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default n
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endmenu
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@ -31,5 +31,10 @@ menu "General Drivers Configuration"
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default n
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endif
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menuconfig BSP_USING_ADC
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bool "Using ADC"
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select RT_USING_ADC
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default n
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endmenu
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@ -15,6 +15,9 @@ if GetDepend('BSP_USING_CV1800B'):
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if GetDepend('BSP_USING_I2C'):
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src += ['drv_hw_i2c.c']
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if GetDepend('BSP_USING_ADC'):
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src += ['drv_adc.c']
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CPPDEFINES += ['-DCONFIG_64BIT']
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group = DefineGroup('drivers', src, depend = [''], CPPDEFINES = CPPDEFINES, CPPPATH = CPPPATH)
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/02/22 flyingcys first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "drv_adc.h"
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#ifdef BSP_USING_ADC
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define LOG_TAG "DRV.ADC"
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struct cvi_adc_dev
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{
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struct rt_adc_device device;
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const char *name;
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rt_ubase_t base;
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};
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static struct cvi_adc_dev adc_dev_config[] =
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{
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{
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.name = "adc1",
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.base = SARADC_BASE
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},
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};
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static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
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uint32_t value;
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RT_ASSERT(adc_dev != RT_NULL);
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if (channel > SARADC_CH_MAX)
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return -RT_EINVAL;
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if (enabled)
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{
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//set channel
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cvi_set_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
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//set saradc clock cycle
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cvi_set_cyc(adc_dev->base);
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//start
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cvi_set_saradc_ctrl(adc_dev->base, SARADC_CTRL_START);
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LOG_D("enable saradc...");
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}
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else
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{
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cvi_reset_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
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LOG_D("disable saradc...");
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}
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return RT_EOK;
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}
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static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
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rt_uint32_t result;
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rt_uint32_t cnt = 0;
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RT_ASSERT(adc_dev != RT_NULL);
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if (channel > SARADC_CH_MAX)
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return -RT_EINVAL;
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while (cvi_get_saradc_status(adc_dev->base) & SARADC_STATUS_BUSY)
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{
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rt_thread_delay(10);
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LOG_D("wait saradc ready");
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cnt ++;
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if (cnt > 100)
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return -RT_ETIMEOUT;
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}
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result = mmio_read_32(adc_dev->base + SARADC_RESULT(channel - 1));
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if (result & SARADC_RESULT_VALID)
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{
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*value = result & SARADC_RESULT_MASK;
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LOG_D("saradc channel %d value: %04x", channel, *value);
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}
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else
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{
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LOG_E("saradc channel %d read failed. result:0x%04x", channel, result);
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return -RT_ERROR;
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}
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return RT_EOK;
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}
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static const struct rt_adc_ops _adc_ops =
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{
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.enabled = _adc_enabled,
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.convert = _adc_convert,
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};
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int rt_hw_adc_init(void)
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{
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rt_uint8_t i;
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for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i ++)
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{
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if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK)
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{
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LOG_E("%s register failed!", adc_dev_config[i].name);
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return -RT_ERROR;
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}
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}
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(rt_hw_adc_init);
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#endif /* BSP_USING_ADC */
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024/02/22 flyingcys first version
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*/
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#ifndef __DRV_ADC_H__
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#define __DRV_ADC_H__
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#include "pinctrl.h"
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#include "mmio.h"
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#define SARADC_BASE 0x030F0000
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#define SARADC_CH_MAX 3
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#define SARADC_CTRL_OFFSET 0x04
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#define SARADC_CTRL_START (1 << 0)
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#define SARADC_CTRL_SEL_POS 0x04
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#define SARADC_STATUS_OFFSET 0x08
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#define SARADC_STATUS_BUSY (1 << 0)
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#define SARADC_CYC_SET_OFFSET 0x0C
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#define SARADC_CYC_CLKDIV_DIV_POS (12U)
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#define SARADC_CYC_CLKDIV_DIV_MASK (0xF << SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_1 (0U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_2 (1U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_3 (2U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_4 (3U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_5 (4U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_6 (5U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_7 (6U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_8 (7U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_9 (8U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_10 (9U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_11 (10U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_12 (11U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_13 (12U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_14 (13U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_15 (14U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_CYC_CLKDIV_DIV_16 (15U<< SARADC_CYC_CLKDIV_DIV_POS)
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#define SARADC_RESULT_OFFSET 0x014
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#define SARADC_RESULT(n) (SARADC_RESULT_OFFSET + (n) * 4)
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#define SARADC_RESULT_MASK 0x0FFF
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#define SARADC_RESULT_VALID (1 << 15)
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rt_inline void cvi_set_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value |= mmio_read_32(reg_base + SARADC_CTRL_OFFSET);
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline void cvi_reset_saradc_ctrl(unsigned long reg_base, rt_uint32_t value)
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{
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value = mmio_read_32(reg_base + SARADC_CTRL_OFFSET) & ~value;
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mmio_write_32(reg_base + SARADC_CTRL_OFFSET, value);
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}
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rt_inline rt_uint32_t cvi_get_saradc_status(unsigned long reg_base)
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{
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return((rt_uint32_t)mmio_read_32(reg_base + SARADC_STATUS_OFFSET));
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}
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rt_inline void cvi_set_cyc(unsigned long reg_base)
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{
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rt_uint32_t value;
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value = mmio_read_32(reg_base + SARADC_CYC_SET_OFFSET);
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value &= ~SARADC_CYC_CLKDIV_DIV_16;
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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value |= SARADC_CYC_CLKDIV_DIV_16; //set saradc clock cycle=840ns
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mmio_write_32(reg_base + SARADC_CYC_SET_OFFSET, value);
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}
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int rt_hw_adc_init(void);
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#endif /* __DRV_ADC_H__ */
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