diff --git a/.gitignore b/.gitignore index 14d84ddc79..c35f46609f 100644 --- a/.gitignore +++ b/.gitignore @@ -38,5 +38,7 @@ ncscope.* tags .idea +.vscode +.history CMakeLists.txt cmake-build-debug diff --git a/bsp/tkm32F499/Kconfig b/bsp/tkm32F499/Kconfig new file mode 100644 index 0000000000..450f1a443f --- /dev/null +++ b/bsp/tkm32F499/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "drivers/Kconfig" + diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/cmsis_armcc.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/cmsis_armcc.h new file mode 100644 index 0000000000..74c49c67de --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cm4.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cm4.h new file mode 100644 index 0000000000..dc840ebf22 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cm4.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ +#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1U) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmFunc.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..652a48af07 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmInstr.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..f474b0e6f3 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmSimd.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmSimd.h new file mode 100644 index 0000000000..66bf5c2a72 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/core_cmSimd.h @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/startup_Tk499.s b/bsp/tkm32F499/Libraries/CMSIS_and_startup/startup_Tk499.s new file mode 100644 index 0000000000..96e5f7d11d --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/startup_Tk499.s @@ -0,0 +1,389 @@ +;******************** (C) COPYRIGHT 2016 HOLOCENE ******************** +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +;//============== °æ±¾ EK V1.0 20190801 ==============// + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ;WWDG + DCD 0 ; + DCD TAMPER_IRQHandler ;TAMPER + DCD RTC_IRQHandler ;RTC + DCD 0 ; + DCD RCC_IRQHandler ;RCC + DCD EXTI0_IRQHandler ;EXTI0 + DCD EXTI1_IRQHandler ;EXTI1 + DCD EXTI2_IRQHandler ;EXTI2 + DCD EXTI3_IRQHandler ;EXTI3 + DCD EXTI4_IRQHandler ;EXTI4 + DCD DMA1_Channel1_IRQHandler ;DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ;DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ;DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ;DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ;DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ;DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ;DMA1 Channel 7 + DCD ADC1_IRQHandler ;ADC1 + DCD CAN1_IRQHandler ;CAN1 + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD EXTI9_5_IRQHandler ;EXTI9_5 + DCD TIM1_BRK_IRQHandler ;TIM1_BRK + DCD TIM1_UP_IRQHandler ;TIM1_UP + DCD TIM1_TRG_COM_IRQHandler ;TIM1_TRG_COM + DCD TIM1_CC_IRQHandler ;TIM1_CC + DCD TIM3_IRQHandler ;TIM3 + DCD TIM4_IRQHandler ;TIM4 + DCD TIM5_IRQHandler ;TIM5 + DCD TIM6_IRQHandler ;TIM6 + DCD TIM7_IRQHandler ;TIM7 + DCD I2C1_IRQHandler ;I2C1 + DCD I2C2_IRQHandler ;I2C2 + DCD SPI1_IRQHandler ;SPI1 + DCD SPI2_IRQHandler ;SPI2 + DCD UART1_IRQHandler ;UART1 + DCD UART2_IRQHandler ;UART2 + DCD UART3_IRQHandler ;UART3 + DCD EXTI15_10_IRQHandler ;EXTI15_10 + DCD RTCAlarm_IRQHandler ;RTC_ALARM + DCD USBAwake_IRQHandler ;USBAwake + DCD TIM2_BRK_IRQHandler ;TIM2_BRK + DCD TIM2_UP_IRQHandler ;TIM2_UP + DCD TIM2_TRG_COM_IRQHandler ;TIM2_TRG_COM + DCD TIM2_CC_IRQHandler ;TIM2_CC + DCD DMA1_Channel8_IRQHandler ;DMA1 + DCD TK80_IRQHandler ;TK80 + DCD SDIO1_IRQHandler ;SDIO1 + DCD SDIO2_IRQHandler ;SDIO2 + DCD SPI3_IRQHandler ;SPI3 + DCD UART4_IRQHandler ;UART4 + DCD UART5_IRQHandler ;UART5 + DCD 0 ; + DCD TIM8_IRQHandler ;TIM8 + DCD DMA2_Channel1_IRQHandler ;DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ;DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ;DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ;DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ;DMA2 Channel 5 + DCD TIM9_IRQHandler ;TIM9 + DCD TIM10_IRQHandler ;TIM10 + DCD CAN2_IRQHandler ;CAN2 + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD USB_IRQHandler ;USB + DCD DMA2_Channel6_IRQHandler ;DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ;DMA2 Channel 7 + DCD DMA2_Channel8_IRQHandler ;DMA2 Channel 8 + DCD 0 ; + DCD I2C3_IRQHandler ;I2C3 + DCD I2C4_IRQHandler ;I2C4 + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD 0 ; + DCD FPU_IRQHandler ;FPU + DCD 0 ; + DCD 0 ; + DCD SPI4_IRQHandler ;SPI4 + DCD 0 ; + DCD TOUCHPAD_IRQHandler ;TCHPAD + DCD QSPI_IRQHandler ;QSPI + DCD LTDC_IRQHandler ;LCD-TFT + DCD 0 ; + DCD I2S1_IRQHandler ;I2S1 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =0xE000ED88 ; ʹÄܸ¡µãÔËËã CP10,CP11 + LDR R1,[R0] + ORR R1,R1,#(0xF << 20) + STR R1,[R0] + ;IMPORT SystemInit + ; LDR R0, =SystemInit + ;BLX R0 + + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBAwake_IRQHandler [WEAK] + EXPORT TIM2_BRK_IRQHandler [WEAK] + EXPORT TIM2_UP_IRQHandler [WEAK] + EXPORT TIM2_TRG_COM_IRQHandler [WEAK] + EXPORT TIM2_CC_IRQHandler [WEAK] + EXPORT DMA1_Channel8_IRQHandler [WEAK] + EXPORT TK80_IRQHandler [WEAK] + EXPORT SDIO1_IRQHandler [WEAK] + EXPORT SDIO2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM8_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT TIM9_IRQHandler [WEAK] + EXPORT TIM10_IRQHandler [WEAK] + EXPORT CAN2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT DMA2_Channel8_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT I2C4_IRQHandler [WEAK] + EXPORT TOUCHPAD_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT QSPI_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT I2S1_IRQHandler [WEAK] + +WWDG_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +TIM5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBAwake_IRQHandler +TIM2_BRK_IRQHandler +TIM2_UP_IRQHandler +TIM2_TRG_COM_IRQHandler +TIM2_CC_IRQHandler +DMA1_Channel8_IRQHandler +TK80_IRQHandler +SDIO1_IRQHandler +SDIO2_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM8_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +TIM9_IRQHandler +TIM10_IRQHandler +CAN2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +DMA2_Channel8_IRQHandler +I2C3_IRQHandler +I2C4_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +QSPI_IRQHandler +TOUCHPAD_IRQHandler +LTDC_IRQHandler +I2S1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************** (C) COPYRIGHT 2016 HOLOCENE ******************** diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c b/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c new file mode 100644 index 0000000000..ce76891dcb --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.c @@ -0,0 +1,162 @@ +#include "sys.h" +#include "HAL_misc.h" + +void RemapVtorTable(void) +{ + int i; + RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram + //¹ØROMÇøÖÐ¶Ï + for(i = 0;i<90;i++) + { + NVIC_DisableIRQ((IRQn_Type)i); + } + SCB->VTOR = 0; + SCB->VTOR |= 0x1<<29; + for(i = 0;i < 512;i+=4) + *(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i); + +} + +void AI_Responder_enable(void) +{ + AI_Responder->ADDR1= 0x70807040; +// AI_Responder->ADDR0 = 0x70027080; + AI_Responder->ADDR1 = 0; + AI_Responder->CCR &= ~(0x3<<3); + AI_Responder->CCR |= 1; + while((AI_Responder->SR & 0x3) != 2); +} +void AI_Responder_disable(void) +{ + AI_Responder->CCR &= ~1; +} + + +//ÍⲿÖжÏÅäÖú¯Êý +//Ö»Õë¶ÔGPIOA~E +//²ÎÊý: +//GPIOx:0~4,´ú±íGPIOA~E +//BITx:ÐèҪʹÄܵÄ룬ÀýÈçPB12£¬¾ÍÌî 12; +//TRIM:´¥·¢Ä£Ê½,1,ϽµÑØ;2,ÉÏÉýÑØ;3£¬ÈÎÒâµçƽ´¥·¢ +//¸Ãº¯ÊýÒ»´ÎÖ»ÄÜÅäÖÃ1¸öIO¿Ú,¶à¸öIO¿Ú,Ðè¶à´Îµ÷Óà +//¸Ãº¯Êý»á×Ô¶¯¿ªÆô¶ÔÓ¦ÖжÏ,ÒÔ¼°ÆÁ±ÎÏß +void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM) +{ + u8 EXTOFFSET=(BITx%4)*4; + RCC->APB2ENR|=1<<14; //ʹÄÜSYSCFGʱÖÓ + SYSCFG->EXTICR[BITx/4]&=~(0x000F<EXTICR[BITx/4]|=GPIOx<IMR|=1<FTSR|=1<RTSR|=1<SCR|=1<<2; //ʹÄÜSLEEPDEEPλ (SYS->CTRL) + RCC->APB1ENR|=1<<28;//ʹÄܵçԴʱÖÓ + PWR->CSR|=1<<8; //ÉèÖÃWKUPÓÃÓÚ»½ÐÑ + PWR->CR|=1<<2; //Çå³ýWake-up ±êÖ¾ + PWR->CR|=1<<1; //PDDSÖÃλ + WFI_SET(); //Ö´ÐÐWFIÖ¸Áî,½øÈë´ý»úģʽ +} +//ϵͳÈí¸´Î» +void Sys_Soft_Reset(void) +{ + SCB->AIRCR =0X05FA0000|(u32)0x04; +} + +// TK499_NVIC_Init(2,2,TK80_IRQn,2); +//ÉèÖÃNVIC +//NVIC_PreemptionPriority:ÇÀÕ¼ÓÅÏȼ¶ +//NVIC_SubPriority :ÏìÓ¦ÓÅÏȼ¶ +//NVIC_Channel :ÖжϱàºÅ +//NVIC_Group :ÖжϷÖ×é 0~4 +//×¢ÒâÓÅÏȼ¶²»Äܳ¬¹ýÉ趨µÄ×éµÄ·¶Î§!·ñÔò»áÓÐÒâÏë²»µ½µÄ´íÎó +//×é»®·Ö: +//×é0:0λÇÀÕ¼ÓÅÏȼ¶,4λÏìÓ¦ÓÅÏȼ¶ +//×é1:1λÇÀÕ¼ÓÅÏȼ¶,3λÏìÓ¦ÓÅÏȼ¶ +//×é2:2λÇÀÕ¼ÓÅÏȼ¶,2λÏìÓ¦ÓÅÏȼ¶ +//×é3:3λÇÀÕ¼ÓÅÏȼ¶,1λÏìÓ¦ÓÅÏȼ¶ +//×é4:4λÇÀÕ¼ÓÅÏȼ¶,0λÏìÓ¦ÓÅÏȼ¶ +//NVIC_SubPriorityºÍNVIC_PreemptionPriorityµÄÔ­ÔòÊÇ,ÊýֵԽС,Ô½ÓÅÏÈ +void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group) +{ + u32 temp; + NVIC_SetPriorityGrouping(NVIC_Group);//ÉèÖ÷Ö×é + temp=NVIC_PreemptionPriority<<(4-NVIC_Group); + temp|=NVIC_SubPriority&(0x0f>>NVIC_Group); + temp&=0xf; //È¡µÍËÄλ + NVIC->ISER[NVIC_Channel/32]|=1<IP[NVIC_Channel]|=temp<<4; //ÉèÖÃÏìÓ¦ÓÅÏȼ¶ºÍÇÀ¶ÏÓÅÏȼ¶ +} + +void TK80_IRQHandler(void) +{ + if(TK80->SR & 0x1) + { + + } + if(TK80->SR & 0x2) + { + + } + if(TK80->SR & 0x4) + { + + } + if(TK80->SR & 0x8) + { + + } + TK80->SR |= 0; +} + +//±¸Óú¯Êý +//#define T_SRAM_FUN1 0x20000400 +//copyAtoB((u32)LCD_PutPixel&0xFFFFFFFE,T_SRAM_FUN1,800);//¼ÓÔغ¯Êýµ½SRAM +//void copyAtoB(u32 srcAdd,u32 dstAdd,u16 len) +//{ +// len = (len + 3)/4; +// while(len--) +// { +// *(u32*)dstAdd = *(u32*)srcAdd; +// dstAdd += 4 ; +// srcAdd +=4 ; +// } +//} + + + + + + + + + + + + + + diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.h new file mode 100644 index 0000000000..1d9adacad9 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/sys.h @@ -0,0 +1,39 @@ +#ifndef __SYS_H +#define __SYS_H +#include "tk499.h" +#include "HAL_conf.h" +//λ´ø²Ù×÷,ʵÏÖ51ÀàËƵÄGPIO¿ØÖƹ¦ÄÜ +//¾ßÌåʵÏÖ˼Ïë,²Î¿¼<>µÚÎåÕÂ(87Ò³~92Ò³).M4ͬM3ÀàËÆ,Ö»ÊǼĴæÆ÷µØÖ·±äÁË. +//IO¿Ú²Ù×÷ºê¶¨Òå +//#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) +//#define MEM_ADDR(addr) *((volatile unsigned long *)(addr)) +//#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum)) + +void RemapVtorTable(void); +void AI_Responder_enable(void); +void AI_Responder_disable(void); + +void Sys_Soft_Reset(void); //ϵͳÈí¸´Î» +void Sys_Standby(void); //´ý»úģʽ + +void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group); +void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //ÍⲿÖжÏÅäÖú¯Êý(Ö»¶ÔGPIOA~I) + +//ÒÔÏÂΪ»ã±àº¯Êý +void WFI_SET(void); //Ö´ÐÐWFIÖ¸Áî +void INTX_DISABLE(void);//¹Ø±ÕËùÓÐÖÐ¶Ï +void INTX_ENABLE(void); //¿ªÆôËùÓÐÖÐ¶Ï + +void TIM3_Config(u16 arr,u16 psc); +#endif + + + + + + + + + + + diff --git a/bsp/tkm32F499/Libraries/CMSIS_and_startup/tk499.h b/bsp/tkm32F499/Libraries/CMSIS_and_startup/tk499.h new file mode 100644 index 0000000000..a9c1d4f827 --- /dev/null +++ b/bsp/tkm32F499/Libraries/CMSIS_and_startup/tk499.h @@ -0,0 +1,4699 @@ +/** +****************************************************************************** +* @file TK499.h +* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. +* This file contains all the peripheral register's definitions, bits +* definitions and memory mapping for TK499 High Density, Medium +* Density and Low Density devices. +* @author IC Applications Department +* @version V0.8 +* @date 2019-08-12 +****************************************************************************** +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+****************************************************************************** +*/ + +//============== °æ±¾ EK V1.0 20190818 ==============// + + +#define T_SRAM_BASE 0X20000000 +#define T_SDRAM_BASE 0X70020000 + +#ifndef __TK499_H +#define __TK499_H + +/** @addtogroup Library_configuration_section +* @{ +*/ + + + +#if !defined USE_STDPERIPH_DRIVER +/** +* @brief Comment the line below if you will not use the peripherals drivers. +In this case, these drivers will not be included and the application code will +be based on direct access to peripherals registers +*/ +/*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** +* @brief In the following line adjust the value of External High Speed oscillator (HSE) +used in your application +*/ +#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#define HSE_VALUE HSE_Value +/** +* @brief In the following line adjust the External High Speed oscillator (HSE) Startup +Timeout value +*/ +#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSE_STARTUP_TIMEOUT HSEStartUp_TimeOut + +#define HSI_Value_Pll_ON ((uint32_t)48000000/4) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE_PLL_ON HSI_Value_Pll_ON + +#define HSI_Value_Pll_OFF ((uint32_t)48000000/6) /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE_PLL_OFF HSI_Value_Pll_OFF + + +/** +* @} +*/ + +/** @addtogroup Configuration_section_for_CMSIS +* @{ +*/ + +/** +* @brief Configuration of the Cortex-M3 Processor and Core Peripherals +*/ +#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1 /*!< tk499 provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< tk499 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + + /****** TK499 CM3 specific Interrupt Numbers *********************************************************/ + + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + //PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + //FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 et ADC2 global Interrupt */ + CAN1_IRQn = 19, /*!< USB High Priority or CAN1 TX Interrupts */ + + //CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + + //TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 28, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 29, /*!< TIM4 global Interrupt */ + TIM5_IRQn = 30, /*!< TIM4 global Interrupt */ + TIM6_IRQn = 31, /*!< TIM4 global Interrupt */ + TIM7_IRQn = 32, /*!< TIM4 global Interrupt */ + + I2C1_IRQn = 33, /*!< I2C1 Event Interrupt */ + I2C2_IRQn = 34, /*!< I2C2 Event Interrupt */ + + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + UART1_IRQn = 37, /*!< UART1 global Interrupt */ + UART2_IRQn = 38, /*!< UART2 global Interrupt */ + UART3_IRQn = 39, /*!< UART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBAwake_IRQn = 42, /*!< USB WakeUp from suspend through EXTI Line Interrupt */ + TIM2_BRK_IRQn = 43, /**/ + TIM2_UP_IRQn = 44, /**/ + TIM2_TRG_COM_IRQn = 45, /**/ + TIM2_CC_IRQn = 46, /**/ + DMA1_Channel8_IRQn = 47, /**/ + TK80_IRQn = 48, /**/ + + SDIO1_IRQn = 49, /**/ + SDIO2_IRQn = 50, /**/ + SPI3_IRQn = 51, /**/ + UART4_IRQn = 52, /**/ + UART5_IRQn = 53, /**/ + TIM8_IRQn = 55, /**/ + DMA2_Channel1_IRQn = 56, /**/ + DMA2_Channel2_IRQn = 57, /**/ + DMA2_Channel3_IRQn = 58, /**/ + DMA2_Channel4_IRQn = 59, /**/ + DMA2_Channel5_IRQn = 60, /**/ + TIM9_IRQn = 61, /**/ + TIM10_IRQn = 62, /**/ + CAN2_IRQn = 63, /**/ + USB_IRQn = 67, /**/ + DMA2_Channel6_IRQn = 68, /**/ + DMA2_Channel7_IRQn = 69, /**/ + DMA2_Channel8_IRQn = 70, /**/ + I2C3_IRQn = 72, /**/ + I2C4_IRQn = 73, /**/ + FPU_IRQn = 81, /**/ + SPI4_IRQn = 84, /**/ + TOUCHPAD_IRQn = 86, + QSPI_IRQn = 87, /**/ + LTDC_IRQn = 88, /**/ + I2S1_IRQn = 90, /**/ + +} IRQn_Type; + + + + +/** +* @} +*/ + +#include + +#include + +/** @addtogroup Exported_types +* @{ +*/ + +/*!< TK499 Standard Peripheral Library old types (maintained for legacy prupose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** +* @} +*/ + +/** @addtogroup Peripheral_registers_structures +* @{ +*/ +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t SR; + __IO uint32_t IRQMASKR; + __IO uint32_t IRQSTATR; + __IO uint32_t RESERVED0; + __IO uint32_t CSHR; + __IO uint32_t CSMR; + __IO uint32_t RESERVED1; + __IO uint32_t ADDR0; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t ADDR3; + +} AI_Responder_TypeDef; +/** +* @brief Analog to Digital Converter +*/ + +typedef struct +{ + __IO uint32_t ADDATA; + __IO uint32_t ADCFG; + __IO uint32_t ADCR; + __IO uint32_t ADCHS; + __IO uint32_t ADCMPR; + __IO uint32_t ADSTA; + __IO uint32_t ADDR0; + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; + __IO uint32_t ADDR3; + __IO uint32_t ADDR4; + __IO uint32_t ADDR5; + __IO uint32_t ADDR6; + __IO uint32_t ADDR7; + __IO uint32_t ADDR8; +} ADC_TypeDef; + +/** +* @brief Backup Registers +*/ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; +} BKP_TypeDef; + +/** +* @brief CAN basic +*/ +typedef struct +{ + __IO uint32_t CR; //0x00 + __IO uint32_t CMR; //0x04 + __IO uint32_t SR; //0x08 + __IO uint32_t IR; //0x0c + __IO uint32_t ACR; //0x10 + __IO uint32_t AMR; //0x14 + __IO uint32_t BTR0; //0x18 + __IO uint32_t BTR1; //0x1C + __IO uint32_t RESERVED0; //0x20 + uint32_t RESERVED1; //0x24 + __IO uint32_t TXID0; //0x28 + __IO uint32_t TXID1; //0x2c + __IO uint32_t TXDR0; //0x30 + __IO uint32_t TXDR1; //0x34 + __IO uint32_t TXDR2; //0x38 + __IO uint32_t TXDR3; //0x3c + __IO uint32_t TXDR4; //0x40 + __IO uint32_t TXDR5; //0x44 + __IO uint32_t TXDR6; //0x48 + __IO uint32_t TXDR7; //0x4c + __IO uint32_t RXID0; //0x50 + __IO uint32_t RXID1; //0x54 + __IO uint32_t RXDR0; //0x58 + __IO uint32_t RXDR1; //0x5C + __IO uint32_t RXDR2; //0x60 + __IO uint32_t RXDR3; + __IO uint32_t RXDR4; + __IO uint32_t RXDR5; //0x6c + __IO uint32_t RXDR6; //0x70 + __IO uint32_t RXDR7; //0x74 + uint32_t RESERVED2; + __IO uint32_t CDR; //0x7c +}CAN_TypeDef; + +/** +* @brief CAN Peli +*/ +typedef struct +{ + __IO uint32_t MOD; //00 + __IO uint32_t CMR; //04 + __IO uint32_t SR; //08 + __IO uint32_t IR; //0C + __IO uint32_t IER; //0x10h + uint32_t RESERVED0; //14 + __IO uint32_t BTR0; //18 + __IO uint32_t BTR1; //1C + uint32_t RESERVED1; //0x20h + uint32_t RESERVED2; //24 + uint32_t RESERVED3; //28 + __IO uint32_t ALC; //2C + __IO uint32_t ECC; //0x30h + __IO uint32_t EWLR; //34 + __IO uint32_t RXERR; //38 + __IO uint32_t TXERR; //3C + __IO uint32_t FF; //0x40 + __IO uint32_t ID0; //44 + __IO uint32_t ID1; //48 + __IO uint32_t DATA0; //4C + __IO uint32_t DATA1; //0x50 + __IO uint32_t DATA2; + __IO uint32_t DATA3; + __IO uint32_t DATA4; + __IO uint32_t DATA5; //0x60 + __IO uint32_t DATA6; + __IO uint32_t DATA7; + __IO uint32_t DATA8; + __IO uint32_t DATA9; //0x70 + __IO uint32_t RMC; + __IO uint32_t RBSA; + __IO uint32_t CDR; //7C +}CAN_Peli_TypeDef; + + +/** +* @brief CRC calculation unit +*/ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** +* @brief Digital to Analog Converter +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + + +/** +* @brief Debug MCU +*/ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** +* @brief DMA Controller +*/ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** +* @brief External Interrupt/Event Controller +*/ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** +* @brief FLASH Registers +*/ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +} FLASH_TypeDef; + +/** +* @brief Option Bytes Registers +*/ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + + + +/** +* @brief General Purpose IO +*/ + +//typedef struct +//{ +// __IO uint32_t CRL; +// __IO uint32_t CRH; +// __IO uint32_t IDR; +// __IO uint32_t ODR; +// __IO uint32_t BSRR; +// __IO uint32_t BRR; +// __IO uint32_t LCKR; +//} GPIO_TypeDef; + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; + uint32_t RESERVED; + __IO uint32_t AFRL; + __IO uint32_t AFRH; + __IO uint32_t CRH_EXT; + __IO uint32_t BSRR_EXT; + __IO uint32_t AFRH_EXT; +} GPIO_TypeDef; + +/** +* @brief Alternate Function IO +*/ + +//typedef struct +//{ +// __IO uint32_t EVCR; +// __IO uint32_t MAPR; +// __IO uint32_t EXTICR[4]; +//} AFIO_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t RESERVED0; + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ +} SYSCFG_TypeDef; + +/** +* @brief Inter-integrated Circuit Interface +*/ + +typedef struct +{ + __IO uint16_t IC_CON; + uint16_t RESERVED0; + __IO uint16_t IC_TAR; + uint16_t RESERVED1; + __IO uint16_t IC_SAR; + uint16_t RESERVED2; + __IO uint16_t IC_HS_MADDR; + uint16_t RESERVED3; + __IO uint16_t IC_DATA_CMD; + uint16_t RESERVED4; + __IO uint16_t IC_SS_SCL_HCNT; + uint16_t RESERVED5; + __IO uint16_t IC_SS_SCL_LCNT; + uint16_t RESERVED6; + __IO uint16_t IC_FS_SCL_HCNT; + uint16_t RESERVED7; + __IO uint16_t IC_FS_SCL_LCNT; + uint16_t RESERVED8; + __IO uint16_t IC_HS_SCL_HCNT; + uint16_t RESERVED9; + __IO uint16_t IC_HS_SCL_LCNT; + uint16_t RESERVED10; + __IO uint16_t IC_INTR_STAT; + uint16_t RESERVED11; + __IO uint16_t IC_INTR_MASK; + uint16_t RESERVED12; + __IO uint16_t IC_RAW_INTR_STAT; + uint16_t RESERVED13; + __IO uint16_t IC_RX_TL; + uint16_t RESERVED14; + __IO uint16_t IC_TX_TL; + uint16_t RESERVED15; + __IO uint16_t IC_CLR_INTR; + uint16_t RESERVED16; + __IO uint16_t IC_CLR_RX_UNDER; + uint16_t RESERVED17; + __IO uint16_t IC_CLR_RX_OVER; + uint16_t RESERVED18; + __IO uint16_t IC_CLR_TX_OVER; + uint16_t RESERVED19; + __IO uint16_t IC_CLR_RD_REQ; + uint16_t RESERVED20; + __IO uint16_t IC_CLR_TX_ABRT; + uint16_t RESERVED21; + __IO uint16_t IC_CLR_RX_DONE; + uint16_t RESERVED22; + __IO uint16_t IC_CLR_ACTIVITY; + uint16_t RESERVED23; + __IO uint16_t IC_CLR_STOP_DET; + uint16_t RESERVED24; + __IO uint16_t IC_CLR_START_DET; + uint16_t RESERVED25; + __IO uint16_t IC_CLR_GEN_CALL; + uint16_t RESERVED26; + __IO uint16_t IC_ENABLE; //RESERVED + uint16_t RESERVED27; + + __IO uint32_t IC_STATUS; + __IO uint32_t IC_TXFLR; //RESERVED + __IO uint32_t IC_RXFLR; //RESERVED + __IO uint32_t IC_SDA_HOLD; //RESERVED + __IO uint32_t IC_TX_ABRT_SOURCE; //RESERVED + __IO uint32_t IC_SLV_DATA_NACK_ONLY; //RESERVED + __IO uint32_t IC_DMA_CR; //RESERVED + __IO uint32_t IC_DMA_TDLR; //RESERVED + __IO uint32_t IC_DMA_RDLR; //RESERVED + __IO uint32_t IC_SDA_SETUP; //RESERVED + __IO uint32_t IC_ACK_GENERAL_CALL; //RESERVED + + __IO uint32_t IC_FS_SPKLEN; + __IO uint32_t IC_HS_SPKLEN; + + __IO uint16_t IC_CLR_RESTART_DET; + uint16_t RESERVED28; + __IO uint32_t IC_COMP_PARAM_1; + __IO uint32_t IC_COMP_VERSION; + __IO uint32_t IC_COMP_TYPE; + +} I2C_TypeDef; + +/** +* @brief Independent WATCHDOG +*/ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** +* @brief Power Control +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** +* @brief Reset and Clock Control +*/ + +//typedef struct +//{ +// __IO uint32_t CR; +// __IO uint32_t CFGR; +// __IO uint32_t CIR; +// __IO uint32_t APB2RSTR; +// __IO uint32_t APB1RSTR; +// __IO uint32_t AHBENR; +// __IO uint32_t APB2ENR; +// __IO uint32_t APB1ENR; +// __IO uint32_t BDCR; +// __IO uint32_t CSR; +//} RCC_TypeDef; + + + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB peripheral clock register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC AHB peripheral clock register, Address offset: 0x18 */ + __IO uint32_t APB2RSTR; /*!< RCC AHB peripheral clock register, Address offset: 0x1C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB peripheral clock register, Address offset: 0x20 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB peripheral clock register, Address offset: 0x24 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x28 */ + __IO uint32_t APB2ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x2C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x34 */ + __IO uint32_t PLLLCDCFGR; /*!< RCC clock configuration register 2, Address offset: 0x38 */ + __IO uint32_t PLLDCKCFGR; /*!< RCC clock configuration register 3, Address offset: 0x3C */ +} RCC_TypeDef; + + + +/** +* @brief Real-Time Clock +*/ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + + +/** +* @brief Serial Peripheral Interface +*/ + +typedef struct +{ + __IO uint32_t TXREG; //0 + __IO uint32_t RXREG; + __IO uint32_t CSTAT; //10 + __IO uint32_t INTSTAT;//14 + __IO uint32_t INTEN; + __IO uint32_t INTCLR; + __IO uint32_t GCTL; //20 + __IO uint32_t CCTL; + __IO uint32_t SPBRG; + __IO uint32_t RXDNR; + __IO uint32_t SCSR; //30 + __IO uint32_t TXREGBH; + __IO uint32_t TXREGBL; +} SPI_TypeDef; + + + + +/** +* @brief TIM +*/ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** +* @brief Universal Synchronous Asynchronous Receiver Transmitter +*/ + +typedef struct +{ + __IO uint32_t TDR; + __IO uint32_t RDR; + __IO uint32_t CSR; + __IO uint32_t ISR; + __IO uint32_t IER; + __IO uint32_t ICR; + __IO uint32_t GCR; + __IO uint32_t CCR; + __IO uint32_t BRR; + __IO uint32_t FRABRG; + +} UART_TypeDef; + +/** +* @brief Window WATCHDOG +*/ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + + +/** +* @brief USB +*/ +typedef struct +{ + __IO uint32_t rTOP; /*! Address offset: 0x00 */ + __IO uint32_t rINT_STATE; /*! Address offset: 0x04 */ + __IO uint32_t rEP_INT_STATE; /*! Address offset: 0x08 */ + __IO uint32_t rEP0_INT_STATE; /*! Address offset: 0x0C */ + __IO uint32_t rINT_EN; /*! Address offset: 0x10 */ + __IO uint32_t rEP_INT_EN; /*! Address offset: 0x14 */ + __IO uint32_t rEP0_INT_EN; /*! Address offset: 0x18 */ + + __IO uint32_t RESERVED0; + + //__IO uint32_t rEP1_4_INT_STATE[4]; /*! Address offset: 0x20 */ + + __IO uint32_t rEP1_INT_STATE; /*! Address offset: 0x20 */ + __IO uint32_t rEP2_INT_STATE; /*! Address offset: 0x24 */ + __IO uint32_t rEP3_INT_STATE; /*! Address offset: 0x28 */ + __IO uint32_t rEP4_INT_STATE; /*! Address offset: 0x2C */ + + __IO uint32_t RESERVED1; /*! Address offset: 0x30 */ + __IO uint32_t RESERVED2; /*! Address offset: 0x34 */ + __IO uint32_t RESERVED3; /*! Address offset: 0x38 */ + __IO uint32_t RESERVED4; /*! Address offset: 0x3C */ + + __IO uint32_t rEP1_INT_EN; /*! Address offset: 0x40 */ + __IO uint32_t rEP2_INT_EN; /*! Address offset: 0x44 */ + __IO uint32_t rEP3_INT_EN; /*! Address offset: 0x48 */ + __IO uint32_t rEP4_INT_EN; /*! Address offset: 0x4C */ + + __IO uint32_t RESERVED5; /*! Address offset: 0x50 */ + __IO uint32_t RESERVED6; /*! Address offset: 0x54 */ + __IO uint32_t RESERVED7; /*! Address offset: 0x58 */ + __IO uint32_t RESERVED8; /*! Address offset: 0x5C */ + + __IO uint32_t rADDR; /*! Address offset: 0x60 */ + __IO uint32_t rEP_EN; /*! Address offset: 0x64 */ + + __IO uint32_t RESERVED9; /*! Address offset: 0x68 */ + __IO uint32_t RESERVED10; /*! Address offset: 0x6C */ + __IO uint32_t RESERVED11; /*! Address offset: 0x70 */ + __IO uint32_t RESERVED12; /*! Address offset: 0x74 */ + + __IO uint32_t rTOG_CTRL1_4; /*! Address offset: 0x78 */ + + __IO uint32_t RESERVED13; /*! Address offset: 0x7C */ + + __IO uint32_t rSETUP[8]; /*! Address offset: 0x80 */ + //__IO uint32_t rSETUP0; /*! Address offset: 0x80 */ + //__IO uint32_t rSETUP1; /*! Address offset: 0x84 */ + //__IO uint32_t rSETUP2; /*! Address offset: 0x88 */ + //__IO uint32_t rSETUP3; /*! Address offset: 0x8C */ + //__IO uint32_t rSETUP4; /*! Address offset: 0x90 */ + //__IO uint32_t rSETUP5; /*! Address offset: 0x94 */ + //__IO uint32_t rSETUP6; /*! Address offset: 0x98 */ + //__IO uint32_t rSETUP7; /*! Address offset: 0x9C */ + __IO uint32_t rPAKET_SIZE0; /*! Address offset: 0xA0 */ + __IO uint32_t rPAKET_SIZE1; /*! Address offset: 0xA4 */ + + __IO uint32_t RESERVED14; /*! Address offset: 0xA8 */ + __IO uint32_t RESERVED15; /*! Address offset: 0xAC */ + + __IO uint32_t RESERVED16; /*! Address offset: 0xB0 */ + __IO uint32_t RESERVED17; /*! Address offset: 0xB4 */ + __IO uint32_t RESERVED18; /*! Address offset: 0xB8 */ + __IO uint32_t RESERVED19; /*! Address offset: 0xBC */ + + __IO uint32_t RESERVED20; /*! Address offset: 0xC0 */ + __IO uint32_t RESERVED21; /*! Address offset: 0xC4 */ + __IO uint32_t RESERVED22; /*! Address offset: 0xC8 */ + __IO uint32_t RESERVED23; /*! Address offset: 0xCC */ + + __IO uint32_t RESERVED24; /*! Address offset: 0xD0 */ + __IO uint32_t RESERVED25; /*! Address offset: 0xD4 */ + __IO uint32_t RESERVED26; /*! Address offset: 0xD8 */ + __IO uint32_t RESERVED27; /*! Address offset: 0xDC */ + + __IO uint32_t RESERVED28; /*! Address offset: 0xE0 */ + __IO uint32_t RESERVED29; /*! Address offset: 0xE4 */ + __IO uint32_t RESERVED30; /*! Address offset: 0xE8 */ + __IO uint32_t RESERVED31; /*! Address offset: 0xEC */ + + __IO uint32_t RESERVED32; /*! Address offset: 0xF0 */ + __IO uint32_t RESERVED33; /*! Address offset: 0xF4 */ + __IO uint32_t RESERVED34; /*! Address offset: 0xF8 */ + __IO uint32_t RESERVED35; /*! Address offset: 0xFC */ + + __IO uint32_t rEP0_AVIL; /*! Address offset: 0x100 */ + __IO uint32_t rEP1_AVIL; /*! Address offset: 0x104 */ + __IO uint32_t rEP2_AVIL; /*! Address offset: 0x108 */ + __IO uint32_t rEP3_AVIL; /*! Address offset: 0x10C */ + __IO uint32_t rEP4_AVIL; /*! Address offset: 0x110 */ + + __IO uint32_t RESERVED36; /*! Address offset: 0x114 */ + __IO uint32_t RESERVED37; /*! Address offset: 0x118 */ + __IO uint32_t RESERVED38; /*! Address offset: 0x11C */ + __IO uint32_t RESERVED39; /*! Address offset: 0x120 */ + + __IO uint32_t RESERVED40; /*! Address offset: 0x124 */ + __IO uint32_t RESERVED41; /*! Address offset: 0x128 */ + __IO uint32_t RESERVED42; /*! Address offset: 0x12C */ + __IO uint32_t RESERVED43; /*! Address offset: 0x130 */ + + __IO uint32_t RESERVED44; /*! Address offset: 0x134 */ + __IO uint32_t RESERVED45; /*! Address offset: 0x138 */ + __IO uint32_t RESERVED46; /*! Address offset: 0x13C */ + + __IO uint32_t rEP0_CTRL; /*! Address offset: 0x140 */ + __IO uint32_t rEP1_CTRL; /*! Address offset: 0x144 */ + __IO uint32_t rEP2_CTRL; /*! Address offset: 0x148 */ + __IO uint32_t rEP3_CTRL; /*! Address offset: 0x14C */ + __IO uint32_t rEP4_CTRL; /*! Address offset: 0x150 */ + + __IO uint32_t RESERVED47; /*! Address offset: 0x154 */ + __IO uint32_t RESERVED48; /*! Address offset: 0x158 */ + __IO uint32_t RESERVED49; /*! Address offset: 0x15C */ + //__IO uint32_t RESERVED50; /*! Address offset: 0x15C */ + + //__IO uint32_t rEPn_FIFO[5]; /*! Address offset: 0x160 */ + + __IO uint32_t rEP0_FIFO; /*! Address offset: 0x160 */ + __IO uint32_t rEP1_FIFO; /*! Address offset: 0x164 */ + __IO uint32_t rEP2_FIFO; /*! Address offset: 0x168 */ + __IO uint32_t rEP3_FIFO; /*! Address offset: 0x16C */ + __IO uint32_t rEP4_FIFO; /*! Address offset: 0x170 */ + + __IO uint32_t RESERVED51; /*! Address offset: 0x174 */ + __IO uint32_t RESERVED52; /*! Address offset: 0x178 */ + __IO uint32_t RESERVED53; /*! Address offset: 0x17C */ + + __IO uint32_t RESERVED54; /*! Address offset: 0x180 */ + + __IO uint32_t rEP_DMA; /*! Address offset: 0x184 */ + __IO uint32_t rEP_HALT; /*! Address offset: 0x188 */ + __IO uint32_t RESERVED55; /*! Address offset: 0x18C */ + + __IO uint32_t RESERVED56; /*! Address offset: 0x190 */ + __IO uint32_t RESERVED57; /*! Address offset: 0x194 */ + __IO uint32_t RESERVED58; /*! Address offset: 0x198 */ + __IO uint32_t RESERVED59; /*! Address offset: 0x19C */ + + __IO uint32_t RESERVED60; /*! Address offset: 0x1A0 */ + __IO uint32_t RESERVED61; /*! Address offset: 0x1A4 */ + __IO uint32_t RESERVED62; /*! Address offset: 0x1A8 */ + __IO uint32_t RESERVED63; /*! Address offset: 0x1AC */ + + __IO uint32_t RESERVED64; /*! Address offset: 0x1B0 */ + __IO uint32_t RESERVED65; /*! Address offset: 0x1B4 */ + __IO uint32_t RESERVED66; /*! Address offset: 0x1B8 */ + __IO uint32_t RESERVED67; /*! Address offset: 0x1BC */ + __IO uint32_t rPOWER; /*! Address offset: 0x1C0 */ +} USB_TypeDef; + +typedef struct +{ + u32 sHsyncStart; + u32 sHsyncEnd; + u32 aHorLen; + u32 blkHorEnd; + + u32 sVsyncStart; + u32 sVsyncEnd; + u32 aVerLen; + u32 blkVerEnd; +} LCD_FORM_TypeDef; +//2017 for tk499 ADD +typedef struct +{ + __IO uint32_t DP_ADDR0; + __IO uint32_t DP_ADDR1; + __IO uint32_t P_HOR; + __IO uint32_t HSYNC; + __IO uint32_t A_HOR; + __IO uint32_t A_HOR_LEN; + __IO uint32_t BLK_HOR; + __IO uint32_t P_VER; + __IO uint32_t VSYNC; + __IO uint32_t A_VER; + __IO uint32_t A_VER_LEN; + __IO uint32_t BLK_VER; + __IO uint32_t BLK_DATA; + __IO uint32_t POL_CTL; + __IO uint32_t OUT_EN; + __IO uint32_t INTR_STA; + __IO uint32_t INTR_EN; + __IO uint32_t INTR_CLR; + __IO uint32_t DP_SWT; + __IO uint32_t VI_FORMAT; +} LCD_TypeDef; + +typedef struct +{ + __IO uint32_t IER; + __IO uint32_t IRER; + __IO uint32_t ITER; + __IO uint32_t CER; + __IO uint32_t RXFFR; + __IO uint32_t TXFFR; + __IO uint32_t LRBR0; + __IO uint32_t RRBR0; + __IO uint32_t RER0; + __IO uint32_t TER0; + __IO uint32_t RCR0; + __IO uint32_t TCR0; + __IO uint32_t ISR0; + __IO uint32_t IMR0; + __IO uint32_t ROR0; + __IO uint32_t TOR0; + __IO uint32_t RFCR0; + __IO uint32_t TFCR0; + __IO uint32_t RFF0; + __IO uint32_t TFF0; +} I2S_TypeDef; + + +//typedef struct +//{ + +// __IO uint32_t WR; +// __IO uint32_t RD; +// __IO uint32_t CSR; +// __IO uint32_t GCR; +// __IO uint32_t DFR; +// __IO uint32_t ISR; +// __IO uint32_t IER; +// __IO uint32_t ICR; +//} I2S_TypeDef; + +typedef struct +{ + __IO uint32_t MMC_CTRL; + __IO uint32_t MMC_IO; + __IO uint32_t MMC_BYTECNTL; + __IO uint32_t MMC_TR_BLOCKCNT; + __IO uint32_t MMC_CRCCTL; + __IO uint32_t CMD_CRC; + __IO uint32_t DAT_CRCL; + __IO uint32_t DAT_CRCH; + __IO uint32_t MMC_PORT; + __IO uint32_t MMC_INT_MASK; + __IO uint32_t CLR_MMC_INT; + __IO uint32_t MMC_CARDSEL; + __IO uint32_t MMC_SIG; + __IO uint32_t MMC_IO_MBCTL; + __IO uint32_t MMC_BLOCKCNT; + __IO uint32_t MMC_TIMEOUTCNT; + __IO uint32_t CMD_BUF[16]; + __IO uint32_t BUF_CTL; + __IO uint32_t RESERVED[31]; + __IO uint32_t DATA_BUF0; + __IO uint32_t DATA_BUF1; + __IO uint32_t DATA_BUF2; + __IO uint32_t DATA_BUF3; + __IO uint32_t DATA_BUF4; +} SDIO_TypeDef; + +typedef struct +{ + __IO uint32_t DP_ADDR0;//0 + __IO uint32_t DP_ADDR1;//4 + __IO uint32_t P_HOR;//8 + __IO uint32_t HSYNC;//C + __IO uint32_t A_HOR;//10 + __IO uint32_t A_HOR_LEN;//14 + __IO uint32_t BLK_HOR;//18 + __IO uint32_t P_VER;//1C + __IO uint32_t VSYNC;//20 + __IO uint32_t A_VER;//24 + __IO uint32_t A_VER_LEN;//28 + __IO uint32_t BLK_VER;//2C + __IO uint32_t BLK_DATA;//30 + __IO uint32_t POL_CTL;//34 + __IO uint32_t OUT_EN;//38 + __IO uint32_t INTR_STA;//3C + __IO uint32_t INTR_EN;//40 + __IO uint32_t INTR_CLR;//44 + __IO uint32_t DP_SWT;//48 + __IO uint32_t VI_FORMAT;//4C +} +LTDCTypeDef; + +typedef struct +{ + __IO uint32_t CR;//0 + __IO uint32_t CFGR1;//4 + __IO uint32_t CFGR2;//8 + __IO uint32_t SR;//C + __IO uint32_t CMDIR;//10 + __IO uint32_t DINR;//14 + __IO uint32_t CMDOR;//18 + __IO uint32_t RESERVE0;//1C + __IO uint32_t DOUTR;//20 + __IO uint32_t BRDR;//24 + __IO uint32_t RESERVE1;//28 + __IO uint32_t RESERVE2;//2C + __IO uint32_t CFGR3;//30 +} TK80_TypeDef; + + +typedef struct +{ + uint32_t TXREG; /*!< Reserved, 0x22 */ + uint32_t RXREG; /*!< Reserved, 0x22 */ + uint32_t CSTAT; /*!< Reserved, 0x22 */ + uint32_t INTSTAT; /*!< Reserved, 0x22 */ + uint32_t INTEN; /*!< Reserved, 0x22 */ + uint32_t INTCLR; /*!< Reserved, 0x22 */ + uint32_t GCTL; /*!< Reserved, 0x22 */ + uint32_t CCTL; /*!< Reserved, 0x22 */ + uint32_t SPBRG; /*!< Reserved, 0x22 */ + uint32_t RXDNR; /*!< Reserved, 0x22 */ + uint32_t SCSR; /*!< Reserved, 0x22 */ + uint32_t MODE; /*!< Reserved, 0x22 */ +} QSPI_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +typedef struct +{ + __IO uint32_t ADDATA; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t ADCFG; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t ADCR; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t ADCHS; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t ADCMPR; //10 + __IO uint32_t ADSTA; + __IO uint32_t ADDR0; //18 + __IO uint32_t ADDR1; + __IO uint32_t ADDR2; //20 + __IO uint32_t ADDR3; + __IO uint32_t ADDR4; + __IO uint32_t ADDR5; + __IO uint32_t ADDR6; //30 + __IO uint32_t ADDR7; + __IO uint32_t ADDR8; + __IO uint32_t ADDR9; + __IO uint32_t RESERVED0;//40 + __IO uint32_t RESERVED1; + __IO uint32_t TPXDR; + __IO uint32_t TPYDR; + __IO uint32_t TPCR; + __IO uint32_t TPFR; + __IO uint32_t TPCSR; + +} TOUCHPAD_TypeDef; + +/** +* @} +*/ + +/** @addtogroup Peripheral_memory_map +* @{ +*/ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ + +#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */ + + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) + +#define APB3PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2PERIPH_BASE (0x60000000) +#define AHB3PERIPH_BASE (0xC0000000) + +/*!< AHB1 map */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) //0x40020000 +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) +#define BKP_BASE (AHB1PERIPH_BASE + 0x4000) +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x6008) +#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x601C) +#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x6030) +#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x6044) +#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x6058) +#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x606C) +#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x6080) +#define DMA1_Channel8_BASE (AHB1PERIPH_BASE + 0x6094) + +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) +#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x6408) +#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x641C) +#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x6430) +#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x6444) +#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x6458) +#define DMA2_Channel6_BASE (AHB1PERIPH_BASE + 0x646C) +#define DMA2_Channel7_BASE (AHB1PERIPH_BASE + 0x6480) +#define DMA2_Channel8_BASE (AHB1PERIPH_BASE + 0x6494) + +#define LTDC_BASE (AHB1PERIPH_BASE + 0x20000) + +/*!< AHB2 peripherals */ +#define TK80_BASE (AHB2PERIPH_BASE + 0x00000000) //0x60000000 + +/*!< AHB3 peripherals */ +#define SDRAM_BANK_BASE (AHB3PERIPH_BASE + 0x00000000) //0xc0000000 +#define SDRAM_CONTROL_BASE (0xD0000000) + + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) //0x40010000 +#define TIM2_BASE (APB2PERIPH_BASE + 0x0400) +#define UART1_BASE (APB2PERIPH_BASE + 0x0800) +#define UART2_BASE (APB2PERIPH_BASE + 0x0C00) +#define UART3_BASE (APB2PERIPH_BASE + 0x1000) +#define UART4_BASE (APB2PERIPH_BASE + 0x1400) +#define UART5_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) +#define SDIO1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SDIO2_BASE (APB2PERIPH_BASE + 0x3000) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x5000) +#define SPI2_BASE (APB2PERIPH_BASE + 0x5400) +#define SPI3_BASE (APB2PERIPH_BASE + 0x5800) +#define SPI4_BASE (APB2PERIPH_BASE + 0x5C00) +#define QSPI_BASE (APB2PERIPH_BASE + 0x6000) +#define TOUCHPAD_BASE (APB2PERIPH_BASE + 0x6400) +#define AI_Responder_BASE (APB2PERIPH_BASE + 0x7400) +/*!< APB1 peripherals */ +#define TIM3_BASE (APB1PERIPH_BASE + 0x0000) //0x40000000 +#define TIM4_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM6_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM8_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM9_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM10_BASE (APB1PERIPH_BASE + 0x1C00) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define USB_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define I2S_BASE (APB1PERIPH_BASE + 0x7400) + + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + + +/** +* @} +*/ + +/** @addtogroup Peripheral_declaration +* @{ +*/ + +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define UART1 ((UART_TypeDef *) UART1_BASE) +#define UART2 ((UART_TypeDef *) UART2_BASE) +#define UART3 ((UART_TypeDef *) UART3_BASE) +#define UART4 ((UART_TypeDef *) UART4_BASE) +#define UART5 ((UART_TypeDef *) UART5_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define SDIO1 ((SDIO_TypeDef *) SDIO1_BASE) +#define SDIO2 ((SDIO_TypeDef *) SDIO2_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define QSPI ((QSPI_TypeDef *) QSPI_BASE) +#define TOUCHPAD ((TOUCHPAD_TypeDef *) TOUCHPAD_BASE) + +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN1_PELI ((CAN_Peli_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CAN2_PELI ((CAN_Peli_TypeDef *) CAN2_BASE) +#define USB ((USB_TypeDef*) USB_BASE ) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define I2S ((SPI_TypeDef *) I2S_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define LTDC ((LTDCTypeDef *) LTDC_BASE) +#define TK80 ((TK80_TypeDef *) TK80_BASE) +#define AI_Responder ((AI_Responder_TypeDef*) AI_Responder_BASE) +//#define SDRAM_BANK ((DMA_TypeDef *) SDRAM_BANK_BASE) +//#define SDRAM_CONTROL ((DMA_TypeDef *) SDRAM_CONTROL_BASE) + + +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) + +#define OB ((OB_TypeDef *) OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + + + + + + +/** +* @} +*/ + +/** @addtogroup Exported_constants +* @{ +*/ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ + +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x1E00) /*!< PLS[3:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0400) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0800) /*!< Bit 2 */ +#define PWR_CR_PLS_3 ((uint16_t)0x1000) /*!< Bit 3 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0000) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x0200) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_3V0 ((uint16_t)0x0400) /*!< PVD level 3.0V */ +#define PWR_CR_PLS_3V2 ((uint16_t)0x0600) /*!< PVD level 3.2V */ +#define PWR_CR_PLS_3V4 ((uint16_t)0x0800) /*!< PVD level 3.4V */ +#define PWR_CR_PLS_3V6 ((uint16_t)0x0A00) /*!< PVD level 3.6V */ +#define PWR_CR_PLS_3V8 ((uint16_t)0x0C00) /*!< PVD level 3.8V */ +#define PWR_CR_PLS_4V0 ((uint16_t)0x0E00) /*!< PVD level 4.0V */ +#define PWR_CR_PLS_4V2 ((uint16_t)0x1000) /*!< PVD level 4.2V */ +#define PWR_CR_PLS_4V4 ((uint16_t)0x1200) /*!< PVD level 4.4V */ +#define PWR_CR_PLS_4V6 ((uint16_t)0x1400) /*!< PVD level 4.6V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#define RCC_CR_PLLDN ((uint32_t)0xFC000000) /*!< PLLDN[5:0] bits */ +#define RCC_CR_PLLDN_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define RCC_CR_PLLDN_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define RCC_CR_PLLDN_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define RCC_CR_PLLDN_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define RCC_CR_PLLDN_4 ((uint32_t)0x40000000) /*!< Bit 4 */ +#define RCC_CR_PLLDN_5 ((uint32_t)0x80000000) /*!< Bit 5 */ + +#define RCC_CR_PLLDM ((uint32_t)0x00700000) /*!< PLLDM[2:0] bits */ +#define RCC_CR_PLLDM_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define RCC_CR_PLLDM_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define RCC_CR_PLLDM_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +/******************* Bit definition for RCC_CFGR register *******************/ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +/*!< SW configuration */ +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +#define RCC_CFGR_USBPRE ((uint32_t)0x00C00000) /*!< USB prescaler BIT[1:0] */ +#define RCC_CFGR_USBPRE_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define RCC_CFGR_USBPRE_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +/*!< MCO configuration */ +#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) // +#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) +#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected */ +#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< Internal 48 MHz RC oscillator clock selected */ +#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< External 1-25 MHz oscillator clock selected */ +#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected*/ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< IO port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< IO port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< IO port D reset */ +#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< IO port E reset *///RESERVED +#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< IO port F reset *///RESERVED +#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< IO port G reset *///RESERVED +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_UART1RST ((uint32_t)0x00004000) /*!< UART1 reset */ +#define RCC_APB2RSTR_CPTRST ((uint32_t)0x0008000) /*!< CPT interface reset */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ +#define RCC_APB1RSTR_UART2RST ((uint32_t)0x00020000) /*!< UART 2 reset */ +#define RCC_APB1RSTR_UART3RST ((uint32_t)0x00040000) /*!< UART 3 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ +#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */ +#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ +#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMAEN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable *///RESERVED +#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable *///RESERVED +#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable *///RESERVED +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_UART1EN ((uint32_t)0x00004000) /*!< UART1 clock enable */ + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ +#define RCC_APB1ENR_UART2EN ((uint32_t)0x00020000) /*!< UART 2 clock enable */ +#define RCC_APB1ENR_UART3EN ((uint32_t)0x00040000) /*!< UART 3 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ +#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ +#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ +#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function IO */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/******************************************************************************/ +/* */ +/* System Configuration (SYSCFG) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for SYSCFG_CFGR1 register ****************/ +#define SYSCFG_CFGR_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */ +#define SYSCFG_CFGR_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */ +#define SYSCFG_CFGR_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */ +#define SYSCFG_CFGR_IRDA_ENV_SEL ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */ +#define SYSCFG_CFGR_IRDA_ENV_SEL_0 ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */ +#define SYSCFG_CFGR_IRDA_ENV_SEL_1 ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */ +#define SYSCFG_CFGR_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages */ +#define SYSCFG_CFGR_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */ +#define SYSCFG_CFGR_UART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< UART1 TX DMA remap */ +#define SYSCFG_CFGR_UART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< UART1 RX DMA remap */ +#define SYSCFG_CFGR_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ +#define SYSCFG_CFGR_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ +#define SYSCFG_CFGR_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */ +#define SYSCFG_CFGR_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */ + +/***************** Bit definition for SYSCFG_EXTICR1 register ***************/ +#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/** +* @brief EXTI0 configuration +*/ +#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ + +/** +* @brief EXTI1 configuration +*/ +#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ + +/** +* @brief EXTI2 configuration +*/ +#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ + +/** +* @brief EXTI3 configuration +*/ +#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ + +/***************** Bit definition for SYSCFG_EXTICR2 register *****************/ +#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/** +* @brief EXTI4 configuration +*/ +#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ + +/** +* @brief EXTI5 configuration +*/ +#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ + +/** +* @brief EXTI6 configuration +*/ +#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ + +/** +* @brief EXTI7 configuration +*/ +#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ + +/***************** Bit definition for SYSCFG_EXTICR3 register *****************/ +#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/** +* @brief EXTI8 configuration +*/ +#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ + +/** +* @brief EXTI9 configuration +*/ +#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ + +/** +* @brief EXTI10 configuration +*/ +#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ + +/** +* @brief EXTI11 configuration +*/ +#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ + +/***************** Bit definition for SYSCFG_EXTICR4 register *****************/ +#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/** +* @brief EXTI12 configuration +*/ +#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ + +/** +* @brief EXTI13 configuration +*/ +#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ + +/** +* @brief EXTI14 configuration +*/ +#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ + +/** +* @brief EXTI15 configuration +*/ +#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for NVIC_PRI8 register *******************/ +#define NVIC_IPR7_PRI_32 ((uint32_t)0x000000FF) /*!< Priority of interrupt 32 */ +#define NVIC_IPR7_PRI_33 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 33 */ +#define NVIC_IPR7_PRI_34 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 34 */ +#define NVIC_IPR7_PRI_35 ((uint32_t)0xFF000000) /*!< Priority of interrupt 35 */ + +/****************** Bit definition for NVIC_PRI9 register *******************/ +#define NVIC_IPR7_PRI_36 ((uint32_t)0x000000FF) /*!< Priority of interrupt 36 */ +#define NVIC_IPR7_PRI_37 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 37 */ +#define NVIC_IPR7_PRI_38 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 38 */ +#define NVIC_IPR7_PRI_39 ((uint32_t)0xFF000000) /*!< Priority of interrupt 39 */ + +/****************** Bit definition for NVIC_PRI10 register *******************/ +#define NVIC_IPR7_PRI_40 ((uint32_t)0x000000FF) /*!< Priority of interrupt 40 */ +#define NVIC_IPR7_PRI_41 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 41 */ +#define NVIC_IPR7_PRI_42 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 42 */ +#define NVIC_IPR7_PRI_43 ((uint32_t)0xFF000000) /*!< Priority of interrupt 43 */ + +/****************** Bit definition for NVIC_PRI11 register *******************/ +#define NVIC_IPR7_PRI_44 ((uint32_t)0x000000FF) /*!< Priority of interrupt 44 */ +#define NVIC_IPR7_PRI_45 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 45 */ +#define NVIC_IPR7_PRI_46 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 46 */ +#define NVIC_IPR7_PRI_47 ((uint32_t)0xFF000000) /*!< Priority of interrupt 47 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ +#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ +#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ +#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ +#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Trigger request occurred on the external interrupt line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) +#define EXTI_PR_PR20 ((uint32_t)0x00100000) +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2016 HOLOCENE
+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_ADC_H +#define __HAL_ADC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup ADC +* @{ +*/ + +/** @defgroup ADC_Exported_Types +* @{ +*/ + +/** +* @brief ADC Init structure definition +*/ + +/* +typedef struct +{ +uint32_t ADC_Mode; +FunctionalState ADC_ScanConvMode; +FunctionalState ADC_ContinuousConvMode; +uint32_t ADC_ExternalTrigConv; +uint32_t ADC_DataAlign; +uint8_t ADC_NbrOfChannel; +}ADC_InitTypeDef; +*/ +typedef struct +{ + uint32_t ADC_Resolution; + uint32_t ADC_PRESCARE; + uint32_t ADC_Mode; + FunctionalState ADC_ContinuousConvMode; + uint32_t ADC_TRGEN; + uint32_t ADC_ExternalTrigConv; + uint32_t ADC_DataAlign; +}ADC_InitTypeDef; +/** +* @} +*/ + +/** @defgroup ADC_Exported_Constants +* @{ +*/ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == ADC2_BASE)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == ADC2_BASE)) + +/** @defgroup ADC_Resolution +* @{ +*/ +#define ADC_Resolution_12b ((uint32_t)0x00000000) +#define ADC_Resolution_11b ((uint32_t)0x00000080) +#define ADC_Resolution_10b ((uint32_t)0x00000100) +#define ADC_Resolution_9b ((uint32_t)0x00000180) +#define ADC_Resolution_8b ((uint32_t)0x00000200) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ +((RESOLUTION) == ADC_Resolution_10b) || \ + ((RESOLUTION) == ADC_Resolution_8b) || \ + ((RESOLUTION) == ADC_Resolution_6b)) + +/** +* @brief for ADC1, ADC2 +*/ + +#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000) +#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010) +#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020) +#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030) +#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040) +#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050) +#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060) +#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070) + + + +/** @defgroup ADC_dual_mode +* @{ +*/ + +#define ADC_Mode_Single ((uint32_t)0x00000000) +#define ADC_Mode_Single_Period ((uint32_t)0x00000200) +#define ADC_Mode_Continuous_Scan ((uint32_t)0x00000400) + + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Single) || \ +((MODE) == ADC_Mode_Single_Period) || \ + ((MODE) == ADC_Mode_Continuous_Scan)) +/** +* @} +*/ + +#define ADC_TRG_Disable ((uint32_t)0xfffffffB) +#define ADC_TRG_Enable ((uint32_t)0x00000004) + +/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion +* @{ +*/ + +/** +* @brief for ADC1 +*/ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010) +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060) +#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070) + +/** +* @brief for ADC2 +*/ + +#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC4 ((uint32_t)0x00000010) +#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00000020) +#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00000030) +#define ADC_ExternalTrigConv_T3_CC4 ((uint32_t)0x00000040) +#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x00000050) +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060) +#define ADC_ExternalTrigConv_EXTI_15 ((uint32_t)0x00000070) + + + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ +((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_EXTI_11) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_EXTI_15)) +/** +* @} +*/ + +/** @defgroup ADC_data_align +* @{ +*/ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ +((ALIGN) == ADC_DataAlign_Left)) +/** +* @} +*/ + +/** @defgroup ADC_channels +* @{ +*/ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_All ((uint8_t)0x0f) + + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ +((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All)) +/** +* @} +*/ + +/** +* @} +*/ + +#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */ +#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +/** @defgroup ADC_sampling_times +* @{ +*/ + +#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000) +#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001) +#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002) +#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003) +#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004) +#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005) +#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006) +#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \ +((TIME) == ADC_SampleTime_7_5Cycles) || \ + ((TIME) == ADC_SampleTime_13_5Cycles) || \ + ((TIME) == ADC_SampleTime_28_5Cycles) || \ + ((TIME) == ADC_SampleTime_41_5Cycles) || \ + ((TIME) == ADC_SampleTime_55_5Cycles) || \ + ((TIME) == ADC_SampleTime_71_5Cycles) || \ + ((TIME) == ADC_SampleTime_239_5Cycles)) + + + +/** @defgroup ADC_injected_channel_selection +* @{ +*/ + +#define ADC_InjectedChannel_0 ((uint8_t)0x18) +#define ADC_InjectedChannel_1 ((uint8_t)0x1C) +#define ADC_InjectedChannel_2 ((uint8_t)0x20) +#define ADC_InjectedChannel_3 ((uint8_t)0x24) +#define ADC_InjectedChannel_4 ((uint8_t)0x28) +#define ADC_InjectedChannel_5 ((uint8_t)0x2C) +#define ADC_InjectedChannel_6 ((uint8_t)0x30) +#define ADC_InjectedChannel_7 ((uint8_t)0x34) +#define ADC_InjectedChannel_8 ((uint8_t)0x38) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ +((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4) || \ + ((CHANNEL) == ADC_InjectedChannel_5) || \ + ((CHANNEL) == ADC_InjectedChannel_6) || \ + ((CHANNEL) == ADC_InjectedChannel_7) || \ + ((CHANNEL) == ADC_InjectedChannel_8)) +/** +* @} +*/ + +/** @defgroup ADC_analog_watchdog_selection +* @{ +*/ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00000002) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ +((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** +* @} +*/ + +/** @defgroup ADC_interrupts_definition +* @{ +*/ + +#define ADC_IT_EOC ((uint16_t)0x0001) +#define ADC_IT_AWD ((uint16_t)0x0002) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFFFC) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD)) + +/** +* @} +*/ + +/** @defgroup ADC_flags_definition +* @{ +*/ + +#define ADC_FLAG_AWD ((uint8_t)0x02) //ADWIF ±È½Ï±ê־λ +#define ADC_FLAG_EOC ((uint8_t)0x01) //ADIF ת»»½áÊø±ê־λ +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC)) + +/** +* @} +*/ + +/** @defgroup ADC_thresholds +* @{ +*/ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** +* @} +*/ + +/** @defgroup ADC_injected_offset +* @{ +*/ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** +* @} +*/ + +/** @defgroup ADC_injected_length +* @{ +*/ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** +* @} +*/ + +/** @defgroup ADC_injected_rank +* @{ +*/ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** +* @} +*/ + + +/** @defgroup ADC_regular_length +* @{ +*/ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** +* @} +*/ + +/** @defgroup ADC_regular_rank +* @{ +*/ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** +* @} +*/ + +/** @defgroup ADC_regular_discontinuous_mode_number +* @{ +*/ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Exported_Functions +* @{ +*/ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#endif /*__HAL_ADC_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_can.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_can.h new file mode 100644 index 0000000000..313634a5d0 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_can.h @@ -0,0 +1,391 @@ +/** +****************************************************************************** +* @file HAL_can.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the CAN firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_CAN_H +#define __HAL_CAN_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + + +/** @defgroup CAN_sleep_constants +* @{ +*/ + +#define CANINITFAILED ((uint8_t)0x00) /* CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /* CAN initialization ok */ + +/** +* @} +*/ + + + +/** @defgroup CAN_sleep_constants +* @{ +*/ + +#define CANSLEEPFAILED ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/** +* @} +*/ + + +/** @defgroup CAN_wake_up_constants +* @{ +*/ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Mode +*/ +#define CAN_BASICMode ((uint32_t)0x0) +#define CAN_PELIMode ((uint32_t)0x80) +#define CAN_WorkMode ((uint32_t)0x80) +#define CAN_ResetMode ((uint32_t)0x1) +#define CAN_ListenOnlyMode ((uint32_t)0x2) +#define CAN_SeftTestMode ((uint32_t)0x4) +#define CAN_FilterMode_Singal ((uint32_t)0x8) +#define CAN_FilterMode_Double ((uint32_t)0xf7) +#define CAN_SleepMode ((uint32_t)0x10) + +/** +* @} +*/ + +/** +* @brief parasmeter of BASIC CAN interrupt +*/ +#define CAN_IT_RIE ((uint32_t)0x2) +#define CAN_IT_TIE ((uint32_t)0x4) +#define CAN_IT_EIE ((uint32_t)0x8) +#define CAN_IT_OIE ((uint32_t)0x10) + +/** +* @} +*/ + +/** +* @brief parasmeter of PELI CAN interrupt +*/ +#define CAN_IT_RI ((uint32_t)0x1) +#define CAN_IT_TI ((uint32_t)0x2) +#define CAN_IT_EI ((uint32_t)0x4) +#define CAN_IT_DOI ((uint32_t)0x8) +#define CAN_IT_WUI ((uint32_t)0x10) +#define CAN_IT_EPI ((uint32_t)0x20) +#define CAN_IT_ALI ((uint32_t)0x40) +#define CAN_IT_BEI ((uint32_t)0x80) +#define CAN_IT_ALL ((uint32_t)0xff) + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Status +*/ +#define CAN_STATUS_RBS ((uint32_t)0x1) +#define CAN_STATUS_DOS ((uint32_t)0x2) +#define CAN_STATUS_TBS ((uint32_t)0x4) +#define CAN_STATUS_TCS ((uint32_t)0x8) +#define CAN_STATUS_RS ((uint32_t)0x10) +#define CAN_STATUS_TS ((uint32_t)0x20) +#define CAN_STATUS_ES ((uint32_t)0x40) +#define CAN_STATUS_BS ((uint32_t)0x80) + +/** +* @} +*/ + +/** +* @brief parasmeter of CAN Command register +*/ +#define CAN_TR 0x1 +#define CAN_AT 0x2 +#define CAN_RRB 0x4 +#define CAN_CDO 0x8 + +/** +* @} +*/ + +/** +* @brief CAN_Basic init structure definition +*/ +typedef struct +{ + uint8_t SJW; + uint8_t BRP; + FlagStatus SAM; + uint8_t TESG2; + uint8_t TESG1; + FunctionalState GTS; + uint8_t CDCLK; + uint8_t CLOSE_OPEN_CLK; + uint8_t RXINTEN; + uint8_t CBP; +} CAN_Basic_InitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli init structure definition +*/ +typedef struct +{ + uint8_t SJW; + uint8_t BRP; + FlagStatus SAM; + uint8_t TESG2; + uint8_t TESG1; + FunctionalState LOM; + FunctionalState STM; + FunctionalState SM; + FunctionalState SRR; + uint32_t EWLR; +} CAN_Peli_InitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Basic filter init structure definition +*/ +typedef struct +{ + uint8_t CAN_FilterId; /*!< Specifies the filter identification number . + This parameter can be a value between 0x00 and 0xFF */ + + uint8_t CAN_FilterMaskId; /*!< Specifies the filter mask number or identification number, + This parameter can be a value between 0x00 and 0xFF */ +} CAN_Basic_FilterInitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli filter init structure definition +*/ +typedef struct +{ + uint8_t AFM; + uint8_t CAN_FilterId0; /*!< Specifies the filter identification number + This parameter can be a value between 0x00 and 0xFF */ + uint8_t CAN_FilterId1; + uint8_t CAN_FilterId2; + uint8_t CAN_FilterId3; + + uint8_t CAN_FilterMaskId0; /*!< Specifies the filter mask number or identification number, + This parameter can be a value between 0x00 and 0xFF */ + uint8_t CAN_FilterMaskId1; + uint8_t CAN_FilterMaskId2; + uint8_t CAN_FilterMaskId3; +} CAN_Peli_FilterInitTypeDef; + +/** +* @} +*/ + +/** +* @brief CAN_Peli transmit frame definition +*/ +typedef enum {DataFrame = 0, RemoteFrame = !DataFrame} TransFrame; + +/** +* @} +*/ + +/** +* @brief CAN_Basic Tx message structure definition +*/ +typedef struct +{ + uint8_t IDH; /*!< Specifies the standard high identifier. + This parameter can be a value between 0 to 0xFF. */ + uint8_t IDL; /*!< Specifies the standard low identifier. + This parameter can be a value between 0 to 0x7. */ + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be @TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanBasicTxMsg; + +/** +* @} +*/ + +/** +* @brief CAN_Basic Rx message structure definition +*/ +typedef struct +{ + uint16_t ID; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + +} CanBasicRxMsg; + +/** +* @} +*/ + +/** +* @brief CAN_Peli_Tx message structure definition +*/ +typedef struct +{ + uint8_t IDLL; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0xFF. */ + uint8_t IDLH; + uint8_t IDHL; + uint8_t IDHH; + uint8_t FF; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanPeliTxMsg; + +/** +* @} +*/ + +/** +* @brief CAN Rx message structure definition +*/ +typedef struct +{ + uint32_t ID; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + uint8_t FF; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref TransFrame */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + +} CanPeliRxMsg; + + + + +#define CANTXFAILED ((uint8_t)0x00) /* CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + + +/************************ Basic and Peli Work all need function ********************/ + +void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE); +void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_ClearDataOverflow(CAN_TypeDef* CANx); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx); + + +/************************ Basic Work function ********************/ +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct); +void CAN_FilterInit(CAN_TypeDef* CANx, CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct); +void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage); +void CAN_CancelTransmit(CAN_TypeDef* CANx); +void CAN_FIFORelease(CAN_TypeDef* CANx); +void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); + + +/************************ Peli Work function *********************/ +void CAN_Peli_SleepMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_Peli_Init(CAN_TypeDef* CANx, CAN_Peli_InitTypeDef* CAN_Peli_InitStruct); +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct); +void CAN_Peli_FilterInit(CAN_TypeDef* CANx, CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct); +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct); +void CAN_Peli_Transmit(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage); +void CAN_Peli_TransmitRepeat(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage); +void CAN_Peli_Receive(CAN_TypeDef* CANx, CanPeliRxMsg* PeliRxMessage); +uint32_t CAN_Peli_GetRxFIFOInfo(CAN_TypeDef* CANx); +uint8_t CAN_Peli_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_Peli_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_Peli_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); +void CAN_Peli_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +ITStatus CAN_Peli_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud ); +#endif /* __HAL_CAN_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ + diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_conf.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_conf.h new file mode 100644 index 0000000000..3872b63a37 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_conf.h @@ -0,0 +1,43 @@ +/** +****************************************************************************** +* @file HAL_conf.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains Header file for generic microcontroller. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ +#ifndef __HAL_CONF_H__ +#define __HAL_CONF_H__ + +/*´Ë´¦¿ÉÌí¼Ó»òɾ³ýÍâÉè*/ +#include "HAL_device.h" +#include "HAL_adc.h" +#include "HAL_dma.h" +#include "HAL_exti.h" +#include "HAL_flash.h" +#include "HAL_gpio.h" +#include "HAL_i2c.h" +#include "HAL_iwdg.h" +#include "HAL_pwr.h" +#include "HAL_rcc.h" +#include "HAL_spi.h" +#include "HAL_tim.h" +#include "HAL_uart.h" +#include "HAL_wwdg.h" +#include "HAL_misc.h" +#include "HAL_syscfg.h" +#include "HAL_can.h" +#endif + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_device.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_device.h new file mode 100644 index 0000000000..786a6eafba --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_device.h @@ -0,0 +1,27 @@ +/**************************************************************************//** +* @file HAL_device.h +* @brief CMSIS Cortex-M Peripheral Access Layer for HOLOCENE +* microcontroller devices +* +* This is a convenience header file for defining the part number on the +* build command line, instead of specifying the part specific header file. +* +* Example: Add "-TKM32F499" to your build options, to define part +* Add "#include "HAL_device.h" to your source files +* +* +* @version 1.5.0 +* +* +*****************************************************************************/ + +#ifndef __HAL_device_H +#define __HAL_device_H + + + +#include "tk499.h" + + +#endif /* __HAL_device_H */ +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_dma.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_dma.h new file mode 100644 index 0000000000..897374c914 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_dma.h @@ -0,0 +1,411 @@ +/** +****************************************************************************** +* @file HAL_dma.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the DMA firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_DMA_H +#define __HAL_DMA_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup DMA +* @{ +*/ + +/** @defgroup DMA_Exported_Types +* @{ +*/ + +/** +* @brief DMA Init structure definition +*/ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; + uint32_t DMA_MemoryBaseAddr; + uint32_t DMA_DIR; + uint32_t DMA_BufferSize; + uint32_t DMA_PeripheralInc; + uint32_t DMA_MemoryInc; + uint32_t DMA_PeripheralDataSize; + uint32_t DMA_MemoryDataSize; + uint32_t DMA_Mode; + uint32_t DMA_Priority; + uint32_t DMA_M2M; +}DMA_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Constants +* @{ +*/ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE)) + + + +/** @defgroup DMA_data_transfer_direction +* @{ +*/ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) //mtop +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) //ptom +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ +((DIR) == DMA_DIR_PeripheralSRC)) +/** +* @} +*/ + +/** @defgroup DMA_peripheral_incremented_mode +* @{ +*/ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ +((STATE) == DMA_PeripheralInc_Disable)) +/** +* @} +*/ + +/** @defgroup DMA_memory_incremented_mode +* @{ +*/ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ +((STATE) == DMA_MemoryInc_Disable)) +/** +* @} +*/ + +/** @defgroup DMA_peripheral_data_size +* @{ +*/ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ +((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** +* @} +*/ + +/** @defgroup DMA_memory_data_size +* @{ +*/ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ +((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** +* @} +*/ + +/** @defgroup DMA_circular_normal_mode +* @{ +*/ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** +* @} +*/ + +/** @defgroup DMA_priority_level +* @{ +*/ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ +((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** +* @} +*/ + +/** @defgroup DMA_memory_to_memory +* @{ +*/ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** +* @} +*/ + +/** @defgroup DMA_interrupts_definition +* @{ +*/ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +/** +* @brief For DMA1 +*/ + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) +#define DMA2_IT_GL6 ((uint32_t)0x10100000) +#define DMA2_IT_TC6 ((uint32_t)0x10200000) +#define DMA2_IT_HT6 ((uint32_t)0x10400000) +#define DMA2_IT_TE6 ((uint32_t)0x10800000) +#define DMA2_IT_GL7 ((uint32_t)0x11000000) +#define DMA2_IT_TC7 ((uint32_t)0x12000000) +#define DMA2_IT_HT7 ((uint32_t)0x14000000) +#define DMA2_IT_TE7 ((uint32_t)0x18000000) + +#define DMA2_IT_GL8 ((uint32_t)0x10000001) +#define DMA2_IT_TC8 ((uint32_t)0x20000001) +#define DMA2_IT_HT8 ((uint32_t)0x40000001) +#define DMA2_IT_TE8 ((uint32_t)0x80000001) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ +((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5)) + + +/** +* @} +*/ + +/** @defgroup DMA_flags_definition +* @{ +*/ + +/** +* @brief For DMA1 +*/ + +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) +#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) +#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) +#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) + +#define DMA2_FLAG_GL8 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000001) +#define DMA2_FLAG_HT8 ((uint32_t)0x40000001) +#define DMA2_FLAG_TE8 ((uint32_t)0x80000001) + + + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ +((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5)) + + +/** +* @} +*/ + +/** @defgroup DMA_Buffer_Size +* @{ +*/ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Exported_Functions +* @{ +*/ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#endif /*__HAL_DMA_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*------------------ (C) COPYRIGHT 2016 HOLOCENE ------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_exti.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_exti.h new file mode 100644 index 0000000000..15a807ecee --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_exti.h @@ -0,0 +1,170 @@ +/** +****************************************************************************** +* @file HAL_exti.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the EXTI +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_EXTI_H +#define __HAL_EXTI_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup EXTI +* @{ +*/ + +/** @defgroup EXTI_Exported_Types +* @{ +*/ + +/** +* @brief EXTI mode enumeration +*/ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** +* @brief EXTI Trigger enumeration +*/ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ +((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** +* @brief EXTI Init Structure definition +*/ + +typedef struct +{ + uint32_t EXTI_Line; + EXTIMode_TypeDef EXTI_Mode; + EXTITrigger_TypeDef EXTI_Trigger; + FunctionalState EXTI_LineCmd; +}EXTI_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Constants +* @{ +*/ + +/** @defgroup EXTI_Lines +* @{ +*/ + +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 +Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 +Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 +Connected to the USB Wakeup from +suspend event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00)) + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ +((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Exported_Functions +* @{ +*/ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#endif /* __HAL_EXTI_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_flash.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_flash.h new file mode 100644 index 0000000000..304d423484 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_flash.h @@ -0,0 +1,307 @@ +/** +****************************************************************************** +* @file HAL_flash.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the FLASH +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_FLASH_H +#define __HAL_FLASH_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup FLASH +* @{ +*/ + +/** @defgroup FLASH_Exported_Types +* @{ +*/ + +/** +* @brief FLASH Status +*/ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Constants +* @{ +*/ + +/** @defgroup Flash_Latency +* @{ +*/ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ +#define FLASH_Latency_3 ((uint32_t)0x00000003) /* FLASH Three Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ +((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2) || \ + ((LATENCY) == FLASH_Latency_3)) +/** +* @} +*/ + +/** @defgroup Half_Cycle_Enable_Disable +* @{ +*/ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ +((STATE) == FLASH_HalfCycleAccess_Disable)) +/** +* @} +*/ + +/** @defgroup Prefetch_Buffer_Enable_Disable +* @{ +*/ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ +((STATE) == FLASH_PrefetchBuffer_Disable)) +/** +* @} +*/ + +/** @defgroup Option_Bytes_Write_Protection +* @{ +*/ + +/* Values to be used with microcontroller Medium-density devices: FLASH memory density +ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */ + +/* Values to be used with microcontroller High-density devices: FLASH memory density +ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_IWatchdog +* @{ +*/ + +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_nRST_STOP +* @{ +*/ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** +* @} +*/ + +/** @defgroup Option_Bytes_nRST_STDBY +* @{ +*/ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +/** +* @} +*/ + +/** @defgroup FLASH_Interrupts +* @{ +*/ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) + +/** +* @} +*/ + +/** @defgroup FLASH_Flags +* @{ +*/ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ +((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Exported_Functions +* @{ +*/ + +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG); +void FLASH_ClearFlag(uint16_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +#endif /* __HAL_FLASH_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_gpio.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_gpio.h new file mode 100644 index 0000000000..2c1d4a9ad2 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_gpio.h @@ -0,0 +1,282 @@ +/** +****************************************************************************** +* @file HAL_gpio.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the GPIO +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_GPIO_H +#define __HAL_GPIO_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup GPIO +* @{ +*/ + +/** @defgroup GPIO_Exported_Types +* @{ +*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || \ +((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == GPIOG_BASE)) + +/** +* @brief Output Maximum frequency selection +*/ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ +((SPEED) == GPIO_Speed_50MHz)) + +/** +* @brief Configuration Mode enumeration +*/ + +typedef enum +{ +GPIO_Mode_AIN = 0x0, //Ä£ÄâÊäÈë +GPIO_Mode_IN_FLOATING = 0x04, //¸¡¿ÕÊäÈë +GPIO_Mode_IPD = 0x28, //ÏÂÀ­ÊäÈë +GPIO_Mode_IPU = 0x48, //ÉÏÀ­ÊäÈë +GPIO_Mode_Out_OD = 0x14,//ͨÓÿªÂ©Êä³ö +GPIO_Mode_Out_PP = 0x10,//ͨÓÃÍÆÃâÊä³ö +GPIO_Mode_AF_OD = 0x1C, // ¸´ÓÿªÂ©Êä³ö +GPIO_Mode_AF_PP = 0x18 //¸´ÓÃÍÆÃâÊä³ö +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ +((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** +* @brief GPIO Init structure definition +*/ + +typedef struct +{ + uint32_t GPIO_Pin; + GPIOSpeed_TypeDef GPIO_Speed; + GPIOMode_TypeDef GPIO_Mode; +}GPIO_InitTypeDef; + +/** +* @brief Bit_SET and Bit_RESET enumeration +*/ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Constants +* @{ +*/ + +/** @defgroup GPIO_pins_define +* @{ +*/ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ + +#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ +#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ +#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ +#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ +#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ +#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ +#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ +#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ +#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ +((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** +* @} +*/ + +/** @defgroup GPIO_Remap_define +* @{ +*/ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_UART1 ((uint32_t)0x00000004) /* UART1 Alternate Function mapping */ + + +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ + + +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ + +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ + +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ +((REMAP) == GPIO_Remap_UART1) || ((REMAP) == GPIO_PartialRemap_TIM1) || \ + ((REMAP) == GPIO_FullRemap_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) ||\ + ((REMAP) == GPIO_PartialRemap2_TIM2) || ((REMAP) == GPIO_FullRemap_TIM2) || \ + ((REMAP) == GPIO_PartialRemap_TIM3) || ((REMAP) == GPIO_FullRemap_TIM3) ||\ + ((REMAP) == GPIO_Remap_TIM4) || ((REMAP) == GPIO_Remap_PD01) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \ + ((REMAP) == GPIO_Remap_SWJ_Disable)) + + +/** +* @} +*/ +/** +* @} +*/ + +/** @defgroup GPIO_Alternate_function_selection_define +* @{ +*/ + + +#define GPIO_AF_MCO_SW ((uint8_t)0x00) /* MC0, SWDIO,SWCLK */ +#define GPIO_AF_TIM_1_2 ((uint8_t)0x01) /* TIM 1/2 */ +#define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */ +#define GPIO_AF_I2S ((uint8_t)0x03) +#define GPIO_AF_I2C ((uint8_t)0x04) /* I2C 1/2/3 */ +#define GPIO_AF_SPI ((uint8_t)0x05) /* SPI 1/2/3/4 */ +#define GPIO_AF_QSPI ((uint8_t)0x06) +#define GPIO_AF_UART_2345 ((uint8_t)0x07) /* UART 2/3/4/5 */ +#define GPIO_AF_UART_1 ((uint8_t)0x08) +#define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */ +#define GPIO_AF_USB ((uint8_t)0x0A) +#define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */ +#define GPIO_AF_TK80_SDIO ((uint8_t)0x0C) /* TK80 SDIO 1/2 */ +#define GPIO_AF_Touchpad ((uint8_t)0x0D) +#define GPIO_AF_LTDC ((uint8_t)0x0E) /* RGB_LTDC AF */ + + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ +((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ + ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ + ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7)) + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Exported_Functions +* @{ +*/ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF); +#endif /* __HAL_GPIO_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_i2c.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_i2c.h new file mode 100644 index 0000000000..c184c34333 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_i2c.h @@ -0,0 +1,330 @@ +/** +****************************************************************************** +* @file HAL_i2c.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the I2C firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_I2C_H +#define __HAL_I2C_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup I2C +* @{ +*/ + +/** @defgroup I2C_Exported_Types +* @{ +*/ + +/** +* @brief I2C Init structure definition +*/ +/* +typedef struct +{ +uint16_t I2C_Mode; +uint16_t I2C_DutyCycle; +uint16_t I2C_OwnAddress1; +uint16_t I2C_Ack; +uint16_t I2C_AcknowledgedAddress; +uint32_t I2C_ClockSpeed; +}I2C_InitTypeDef; +*/ +typedef struct +{ + uint16_t I2C_Mode; + uint16_t I2C_Speed; + uint16_t I2C_OwnAddress; + uint32_t I2C_ClockSpeed; +}I2C_InitTypeDef; + +/** +* @} +*/ + + +/** @defgroup I2C_Exported_Constants +* @{ +*/ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == I2C2_BASE)) +/** @defgroup I2C_modes +* @{ +*/ + +#define TX_EMPTY_CTRL (0x0001<<8) +#define IC_SLAVE_DISABLE (0x0001<<6) +#define IC_SLAVE_ENABLE (0x0000<<6) +#define IC_RESTART_EN (0x0001<<5) +#define IC_7BITADDR_MASTER (0x0000<<4) +#define IC_7BITADDR_SLAVE (0x0000<<3) + +#define I2C_Speed_STANDARD ((uint16_t)0x0002) +#define I2C_Speed_FAST ((uint16_t)0x0004) +#define I2C_Mode_MASTER ((uint16_t)0x0001) +#define I2C_Mode_SLAVE ((uint16_t)0x0000) + +#define TDMAE_SET ((uint16_t)0x0002) +#define RDMAE_SET ((uint16_t)0x0001) + +#define CMD_READ ((uint16_t)0x0100) +#define CMD_WRITE ((uint16_t)0x0000) + + + + +#define I2C_Mode_I2C ((uint16_t)0x0000) + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C)) + +/** +* @} +*/ + + +/** @defgroup I2C_transfer_direction +* @{ +*/ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ +((DIRECTION) == I2C_Direction_Receiver)) +/** +* @} +*/ + +/** @defgroup I2C_acknowledged_address_defines +* @{ +*/ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ +((ADDRESS) == I2C_AcknowledgedAddress_10bit)) + +/** +* @} +*/ + +/** @defgroup I2C_interrupts_definition +* @{ +*/ + + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** +* @} +*/ + +/** @defgroup I2C_interrupts_definition +* @{ +*/ + +#define I2C_IT_RX_UNDER ((uint16_t)0x0001) +#define I2C_IT_RX_OVER ((uint16_t)0x0002) +#define I2C_IT_RX_FULL ((uint16_t)0x0004) +#define I2C_IT_TX_OVER ((uint16_t)0x0008) +#define I2C_IT_TX_EMPTY ((uint16_t)0x0010) +#define I2C_IT_RD_REQ ((uint16_t)0x0020) +#define I2C_IT_TX_ABRT ((uint16_t)0x0040) +#define I2C_IT_RX_DONE ((uint16_t)0x0080) +#define I2C_IT_ACTIVITY ((uint16_t)0x0100) +#define I2C_IT_STOP_DET ((uint16_t)0x0200) +#define I2C_IT_START_DET ((uint16_t)0x0400) +#define I2C_IT_GEN_CALL ((uint16_t)0x0800) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || \ +((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || \ + ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || \ + ((IT) == I2C_IT_TX_ABRT) || ((IT) == I2C_IT_RX_DONE) || \ + ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || \ + ((IT) == I2C_IT_START_DET) || ((IT) == I2C_IT_GEN_CALL)) +/** +* @} +*/ + +/** @defgroup I2C_flags_definition +* @{ +*/ + + + +#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001) +#define I2C_FLAG_RX_OVER ((uint16_t)0x0002) +#define I2C_FLAG_RX_FULL ((uint16_t)0x0004) +#define I2C_FLAG_TX_OVER ((uint16_t)0x0008) +#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010) +#define I2C_FLAG_RD_REQ ((uint16_t)0x0020) +#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040) +#define I2C_FLAG_RX_DONE ((uint16_t)0x0080) +#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100) +#define I2C_FLAG_STOP_DET ((uint16_t)0x0200) +#define I2C_FLAG_START_DET ((uint16_t)0x0400) +#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800) + + + + + + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF000) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_RX_UNDER) || ((FLAG) == I2C_FLAG_RX_OVER) || \ +((FLAG) == I2C_FLAG_RX_FULL) || ((FLAG) == I2C_FLAG_TX_OVER) || \ + ((FLAG) == I2C_FLAG_TX_EMPTY) || ((FLAG) == I2C_FLAG_RD_REQ) || \ + ((FLAG) == I2C_FLAG_TX_ABRT) || ((FLAG) == I2C_FLAG_RX_DONE) || \ + ((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_STOP_DET) || \ + ((FLAG) == I2C_FLAG_START_DET) || ((FLAG) == I2C_FLAG_GEN_CALL)) + + +/** @defgroup I2C_Statusflags_definition +* @{ +*/ + +#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001) +#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002) +#define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004) +#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008) +#define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010) +#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020) +#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040) + + +/** +* @} +*/ + +/** @defgroup I2C_Events +* @{ +*/ + + +#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001) +#define I2C_EVENT_RX_OVER ((uint32_t)0x0002) +#define I2C_EVENT_RX_FULL ((uint32_t)0x0004) +#define I2C_EVENT_TX_OVER ((uint32_t)0x0008) +#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010) +#define I2C_EVENT_RD_REQ ((uint32_t)0x0020) +#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040) +#define I2C_EVENT_RX_DONE ((uint32_t)0x0080) +#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100) +#define I2C_EVENT_STOP_DET ((uint32_t)0x0200) +#define I2C_EVENT_START_DET ((uint32_t)0x0400) +#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800) + + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \ +((EVENT) == I2C_EVENT_RX_OVER) || \ + ((EVENT) == I2C_EVENT_RX_FULL) || \ + ((EVENT) == I2C_EVENT_TX_OVER) || \ + ((EVENT) == I2C_EVENT_RD_REQ) || \ + ((EVENT) == I2C_EVENT_TX_ABRT) || \ + ((EVENT) == I2C_EVENT_RX_DONE) || \ + ((EVENT) == (I2C_EVENT_ACTIVITY | I2C_EVENT_STOP_DET)) || \ + ((EVENT) == (I2C_EVENT_START_DET | I2C_EVENT_GEN_CALL))) + +/** +* @} +*/ + +/** @defgroup I2C_own_address1 +* @{ +*/ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** +* @} +*/ + +/** @defgroup I2C_clock_speed +* @{ +*/ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Exported_Functions +* @{ +*/ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); + +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ReadCmd(I2C_TypeDef* I2Cx); + + +#endif /*__HAL_I2C_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_iwdg.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_iwdg.h new file mode 100644 index 0000000000..08d075a7ac --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_iwdg.h @@ -0,0 +1,131 @@ +/** +****************************************************************************** +* @file HAL_iwdg.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the IWDG +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_IWDG_H +#define __HAL_IWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup IWDG +* @{ +*/ + +/** @defgroup IWDG_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Constants +* @{ +*/ + +/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers +* @{ +*/ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ +((ACCESS) == IWDG_WriteAccess_Disable)) +/** +* @} +*/ + +/** @defgroup IWDG_prescaler +* @{ +*/ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ +((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** +* @} +*/ + +/** @defgroup IWDG_Flag +* @{ +*/ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Exported_Functions +* @{ +*/ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#endif /* __HAL_IWDG_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_misc.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_misc.h new file mode 100644 index 0000000000..ab13e67121 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_misc.h @@ -0,0 +1,166 @@ +/** +****************************************************************************** +* @file HAL_misc.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the +* miscellaneous firmware library functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup MISC +* @{ +*/ + +/** @defgroup MISC_Exported_Types +* @{ +*/ + +/** +* @brief NVIC Init Structure definition +*/ + +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Constants +* @{ +*/ + +/** @defgroup Vector_Table_Base +* @{ +*/ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ +((VECTTAB) == NVIC_VectTab_FLASH)) +/** +* @} +*/ + +/** @defgroup System_Low_Power +* @{ +*/ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ +((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** +* @} +*/ + +/** @defgroup Preemption_Priority_Group +* @{ +*/ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority +4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority +3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority +2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority +1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority +0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ +((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF) + +/** +* @} +*/ + +/** @defgroup SysTick_clock_source +* @{ +*/ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ +((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Exported_Functions +* @{ +*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#endif /* __MISC_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_pwr.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_pwr.h new file mode 100644 index 0000000000..db9144da92 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_pwr.h @@ -0,0 +1,152 @@ +/** +****************************************************************************** +* @file HAL_pwr.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the PWR firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_PWR_H +#define __HAL_PWR_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup PWR +* @{ +*/ + +/** @defgroup PWR_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Constants +* @{ +*/ + +/** @defgroup PVD_detection_level +* @{ +*/ + +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V8 ((uint32_t)0x00000200) +#define PWR_PVDLevel_3V0 ((uint32_t)0x00000400) +#define PWR_PVDLevel_3V2 ((uint32_t)0x00000600) +#define PWR_PVDLevel_3V4 ((uint32_t)0x00000800) +#define PWR_PVDLevel_3V6 ((uint32_t)0x00000A00) +#define PWR_PVDLevel_3V8 ((uint32_t)0x00000C00) +#define PWR_PVDLevel_4V0 ((uint32_t)0x00000E00) +#define PWR_PVDLevel_4V2 ((uint32_t)0x00001000) +#define PWR_PVDLevel_4V4 ((uint32_t)0x00001200) +#define PWR_PVDLevel_4V6 ((uint32_t)0x00001400) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V8)|| \ +((LEVEL) == PWR_PVDLevel_3V0) || ((LEVEL) == PWR_PVDLevel_3V2)|| \ + ((LEVEL) == PWR_PVDLevel_3V4) || ((LEVEL) == PWR_PVDLevel_3V6)|| \ + ((LEVEL) == PWR_PVDLevel_3V8) || ((LEVEL) == PWR_PVDLevel_4V0)|| \ + ((LEVEL) == PWR_PVDLevel_4V2) || ((LEVEL) == PWR_PVDLevel_4V4)|| \ + ((LEVEL) == PWR_PVDLevel_4V6)) +/** +* @} +*/ + +/** @defgroup Regulator_state_is_STOP_mode +* @{ +*/ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000002) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ +((REGULATOR) == PWR_Regulator_LowPower)) +/** +* @} +*/ + +/** @defgroup STOP_mode_entry +* @{ +*/ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** +* @} +*/ + +/** @defgroup PWR_Flag +* @{ +*/ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ +((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Exported_Functions +* @{ +*/ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#endif /* __HAL_PWR_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_rcc.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_rcc.h new file mode 100644 index 0000000000..30b80413a0 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_rcc.h @@ -0,0 +1,467 @@ +/** +****************************************************************************** +* @file HAL_rcc.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the RCC firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_RCC_H +#define __HAL_RCC_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup RCC +* @{ +*/ + +/** @defgroup RCC_Exported_Types +* @{ +*/ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t ADCCLK_Frequency; +}RCC_ClocksTypeDef; + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Constants +* @{ +*/ + +/** @defgroup HSE_configuration +* @{ +*/ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ +((HSE) == RCC_HSE_Bypass)) + +/** +* @} +*/ + +/** @defgroup PLL_entry_clock_source +* @{ +*/ + +#define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00420000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00400000) +#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ +((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +/** +* @} +*/ + + +/** @defgroup System_clock_source +* @{ +*/ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ +((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** +* @} +*/ + +/** @defgroup AHB_clock_source +* @{ +*/ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ +((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** +* @} +*/ + +/** @defgroup APB1_APB2_clock_source +* @{ +*/ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ +((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) + +/** +* @} +*/ + +/** @defgroup PLL_multiplication_factor +* @{ +*/ + +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_17 ((uint32_t)0x003C0000) +#define RCC_PLLMul_18 ((uint32_t)0x00400000) +#define RCC_PLLMul_19 ((uint32_t)0x004C0000) +#define RCC_PLLMul_20 ((uint32_t)0x00500000) +#define RCC_PLLMul_21 ((uint32_t)0x00540000) +#define RCC_PLLMul_22 ((uint32_t)0x00580000) +#define RCC_PLLMul_23 ((uint32_t)0x005C0001) +#define RCC_PLLMul_24 ((uint32_t)0x00600002) +#define RCC_PLLMul_25 ((uint32_t)0x00680003) +#define RCC_PLLMul_26 ((uint32_t)0x006C0004) +#define RCC_PLLMul_27 ((uint32_t)0x00700005) +#define RCC_PLLMul_28 ((uint32_t)0x00780006) +#define RCC_PLLMul_29 ((uint32_t)0x007C0007) +#define RCC_PLLMul_30 ((uint32_t)0x00800008) +#define RCC_PLLMul_31 ((uint32_t)0x00880009) +#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ +((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + + +/** +* @} +*/ + +/** @defgroup RCC_Interrupt_source +* @{ +*/ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) +#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) +#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ +((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + +#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +/** +* @} +*/ + +/** @defgroup USB_clock_source +* @{ +*/ + +#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) +#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ +((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** +* @} +*/ + +/** @defgroup ADC_clock_source +* @{ +*/ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ +((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** +* @} +*/ + +/** @defgroup LSE_configuration +* @{ +*/ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ +((LSE) == RCC_LSE_Bypass)) +/** +* @} +*/ + +/** @defgroup RTC_clock_source +* @{ +*/ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ +((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** +* @} +*/ + +/** @defgroup AHB_peripheral +* @{ +*/ + +#define RCC_AHBPeriph_LTDC ((uint32_t)0x80000000) +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00200000) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00400000) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000001<<12) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + +#define RCC_AHBPeriph_GPIOA ((uint32_t)0x00000001) +#define RCC_AHBPeriph_GPIOB ((uint32_t)0x00000002) +#define RCC_AHBPeriph_GPIOC ((uint32_t)0x0000004) +#define RCC_AHBPeriph_GPIOD ((uint32_t)0x0000008) +#define RCC_AHBPeriph_GPIOE ((uint32_t)0x0000010) + +#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup APB2_peripheral +* @{ +*/ + + + +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) +#define RCC_APB2Periph_TIM2 ((uint32_t)0x00000002) + +#define RCC_APB2Periph_UART1 ((uint32_t)0x00000004) +#define RCC_APB2Periph_UART2 ((uint32_t)0x00000008) +#define RCC_APB2Periph_UART3 ((uint32_t)0x00000010) +#define RCC_APB2Periph_UART4 ((uint32_t)0x00000020) +#define RCC_APB2Periph_UART5 ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) + +#define RCC_APB2Periph_SDIO1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SDIO2 ((uint32_t)0x00001000) +#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00100000) +#define RCC_APB2Periph_SPI2 ((uint32_t)0x00200000) +#define RCC_APB2Periph_SPI3 ((uint32_t)0x00400000) +#define RCC_APB2Periph_SPI4 ((uint32_t)0x00800000) +#define RCC_APB2Periph_QSPI ((uint32_t)0x01000000) + +#define RCC_AHB2Periph_TK80 ((uint32_t)0x80000000) + +#define RCC_APB2Periph_ALL ((uint32_t)0x0003FFFD) +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup APB1_peripheral +* @{ +*/ + + +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000001<<0) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000001<<1) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000001<<2) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000001<<3) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000001<<4) +#define RCC_APB1Periph_TIM8 ((uint32_t)0x00000001<<5) +#define RCC_APB1Periph_TIM9 ((uint32_t)0x00000001<<6) +#define RCC_APB1Periph_TIM10 ((uint32_t)0x00000001<<7) + + + + +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) + +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) + +#define RCC_APB1Periph_UART2 ((uint32_t)0x00020000) + +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) + +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) + +#define RCC_APB1Periph_CAN1 ((uint32_t)0x04000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x08000000) + +#define RCC_APB1Periph_USB ((uint32_t)0x10000000) + + + +#define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) +/** +* @} +*/ + +/** @defgroup Clock_source_to_output_on_MCO_pin +* @{ +*/ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) +#define RCC_MCO_LSI ((uint8_t)0x02) +#define RCC_MCO_LSE ((uint8_t)0x03) +#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ +((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\ + ((MCO) == RCC_MCO_LSE)) +/** +* @} +*/ + +/** @defgroup RCC_Flag +* @{ +*/ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ +((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Exported_Functions +* @{ +*/ +void SystemClk_HSEInit(uint32_t PLL_DN); +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void getSystemClock(u32 *sysclk); +#endif /* __HAL_RCC_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_spi.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_spi.h new file mode 100644 index 0000000000..d060cee6de --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_spi.h @@ -0,0 +1,374 @@ +/** +****************************************************************************** +* @file HAL_spi.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the SPI firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_SPI_H +#define __HAL_SPI_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup SPI +* @{ +*/ + +/** @defgroup SPI_Exported_Types +* @{ +*/ + +/** +* @brief SPI Init structure definition +*/ + +typedef struct +{ + uint16_t SPI_Mode; + uint16_t SPI_DataSize; + uint16_t SPI_DataWidth; + uint16_t SPI_CPOL; + uint16_t SPI_CPHA; + uint16_t SPI_NSS; + uint16_t SPI_BaudRatePrescaler; + uint16_t SPI_FirstBit; +}SPI_InitTypeDef; + + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Constants +* @{ +*/ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI0_BASE) || \ +((*(uint32_t*)&(PERIPH)) == SPI1_BASE)) + +#define IS_SPI_2_PERIPH(PERIPH) ((*(uint32_t*)&(PERIPH)) == SPI1_BASE) + + +/** +* @} +*/ + +/** @defgroup SPI_master_slave_mode +* @{ +*/ + +#define SPI_Mode_Master ((uint16_t)0x0004) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ +((MODE) == SPI_Mode_Slave)) +/** +* @} +*/ + +/** @defgroup SPI_data_size +* @{ +*/ + +#define SPI_DataSize_32b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \ +((DATASIZE) == SPI_DataSize_8b)) + +/** +* @} +*/ + + +/** @defgroup SPI_7bit_8bit data width +* @{ +*/ + +#define SPI_DataWidth_7b ((uint16_t)0x0000) +#define SPI_DataWidth_8b ((uint16_t)0x0008) +#define IS_SPI_DATAWIDRH(WIDTH) (((WIDTH) == SPI_DataWidth_7b) || \ +((WIDTH) == SPI_DataWidth_8b)) +/** +* @} +*/ + + +/** @defgroup SPI_Clock_Polarity +* @{ +*/ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ +((CPOL) == SPI_CPOL_High)) +/** +* @} +*/ + +/** @defgroup SPI_Clock_Phase +* @{ +*/ + +#define SPI_CPHA_1Edge ((uint16_t)0x0001) +#define SPI_CPHA_2Edge ((uint16_t)0x0000) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ +((CPHA) == SPI_CPHA_2Edge)) +/** +* @} +*/ + +/** @defgroup SPI_Slave_Select_management +* @{ +*/ + +#define SPI_NSS_Soft ((uint16_t)0x0000) +#define SPI_NSS_Hard ((uint16_t)0x0400) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ +((NSS) == SPI_NSS_Hard)) + + +/** +* @} +*/ + +/** @defgroup SPI_NSS_internal_software_mangement +* @{ +*/ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0001) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFFFE) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ +((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup SPI_BaudRate_Prescaler_ +* @{ +*/ + + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0002) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0004) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0040) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0080) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0100) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ +((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** +* @} +*/ + +/** @defgroup SPI_MSB_LSB_transmission +* @{ +*/ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0004) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ +((BIT) == SPI_FirstBit_LSB)) + + +/** +* @} +*/ + +/** @defgroup SPI_DMA_transfer_requests +* @{ +*/ + +#define SPI_DMAReq_EN ((uint16_t)0x0200) +#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN) + + +/** +* @} +*/ + +/** @defgroup SPI TX Fifo and RX Fifo trigger level +* @{ +*/ +#define SPI_TXTLF ((uint16_t)0x0080) +#define SPI_RXTLF ((uint16_t)0x0020) +#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF)) + + + + + + + +/** +* @} +*/ + +/** @defgroup SPI_NSS_internal_software_mangement +* @{ +*/ + +#define SPI_CS_BIT0 ((uint16_t)0xfffe) +#define SPI_CS_BIT1 ((uint16_t)0xfffd) +#define SPI_CS_BIT2 ((uint16_t)0xfffb) +#define SPI_CS_BIT3 ((uint16_t)0xfff7) +#define SPI_CS_BIT4 ((uint16_t)0xffef) +#define SPI_CS_BIT5 ((uint16_t)0xffdf) +#define SPI_CS_BIT6 ((uint16_t)0xffbf) +#define SPI_CS_BIT7 ((uint16_t)0xff7f) +#define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\ +((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\ + ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\ + ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7)) +/** +* @} +*/ + + +/** @defgroup SPI_direction_transmit_receive +* @{ +*/ + +#define SPI_Direction_Rx ((uint16_t)0x0010) +#define SPI_Direction_Tx ((uint16_t)0x0008) +#define SPI_Disable_Tx ((uint16_t)0xfff7) +#define SPI_Disable_Rx ((uint16_t)0xffef) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ +((DIRECTION) == SPI_Direction_Tx) || \ + ((DIRECTION) == SPI_Disable_Tx) || \ + ((DIRECTION) == SPI_Disable_Rx)) +/** +* @} +*/ + +/** @defgroup SPI_interrupts_definition +* @{ +*/ +#define SPI_INT_EN ((uint16_t)0x0002) + +#define SPI_IT_TX ((uint8_t)0x01) +#define SPI_IT_RX ((uint8_t)0x02) + +#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TX) || \ +((IT) == SPI_IT_RX)) + +#define SPI_IT_UNDERRUN ((uint8_t)0x04) +#define SPI_IT_RXOVER ((uint8_t)0x08) +#define SPI_IT_RXMATCH ((uint8_t)0x10) +#define SPI_IT_RXFULL ((uint8_t)0x20) +#define SPI_IT_TXEPT ((uint8_t)0x40) + +#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \ +((IT) == SPI_IT_UNDERRUN) || ((IT) == SPI_IT_RXOVER) || \ + ((IT) == SPI_IT_RXMATCH) || ((IT) == SPI_IT_RXFULL) || \ + ((IT) == SPI_IT_TXEPT)) +/** +* @} +*/ + +/** @defgroup SPI_flags_definition +* @{ +*/ + + +#define SPI_FLAG_RXAVL ((uint16_t)0x0002) +#define SPI_FLAG_TXEPT ((uint16_t)0x0001) + +#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXAVL) || \ +((FLAG) == SPI_FLAG_TXEPT)) + +/** +* @} +*/ + +/** @defgroup SPI mode tx data transmit phase adjust set +*in slave mode according to txedge bit of CCTL register +* @{ +*/ + + +#define SPI_SlaveAdjust_FAST ((uint16_t)0x0020) +#define SPI_SlaveAdjust_LOW ((uint16_t)0xffdf) + +#define IS_SPI_SlaveAdjust(ADJUST) (((ADJUST) == SPI_SlaveAdjust_FAST) || \ +((ADJUST) == SPI_SlaveAdjust_LOW)) + + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Exported_Functions +* @{ +*/ + +void SPI_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState); +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState); +void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState); +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx); +void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,FunctionalState NewState); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT); +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT); +void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number); +void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue); +#endif /*__HAL_SPI_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_syscfg.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_syscfg.h new file mode 100644 index 0000000000..87d26c1e82 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_syscfg.h @@ -0,0 +1,180 @@ +/** +****************************************************************************** +* @file HAL_syscfg.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the SYSCFG firmware +* library. +****************************************************************************** +* @attention +* +*

© COPYRIGHT 2016 HOLOCENE

+* +*/ + +/*!< Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_SYSCFG_H +#define __HAL_SYSCFG_H + +#ifdef __cplusplus +extern "C" { +#endif + + /*!< Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + + /** @addtogroup StdPeriph_Driver + * @{ + */ + + /** @addtogroup SYSCFG + * @{ + */ + /* Exported types ------------------------------------------------------------*/ + /* Exported constants --------------------------------------------------------*/ + + /** @defgroup SYSCFG_Exported_Constants + * @{ + */ + + /** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOF ((uint8_t)0x05) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOF)) +/** +* @} +*/ + +/** @defgroup SYSCFG_EXTI_Pin_sources +* @{ +*/ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) + +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ +((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** +* @} +*/ + +/** @defgroup SYSCFG_Memory_Remap_Config +* @{ +*/ +#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) +#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + + +#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ +((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM)) + +/** +* @} +*/ + +/** @defgroup SYSCFG_DMA_Remap_Config +* @{ +*/ +#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */ +#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */ +#define SYSCFG_DMARemap_UART1Rx SYSCFG_CFGR1_UART1RX_DMA_RMP /* Remap UART1 Rx DMA requests from channel3 to channel5 */ +#define SYSCFG_DMARemap_UART1Tx SYSCFG_CFGR1_UART1TX_DMA_RMP /* Remap UART1 Tx DMA requests from channel2 to channel4 */ +#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */ + +#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \ +((REMAP) == SYSCFG_DMARemap_TIM16) || \ + ((REMAP) == SYSCFG_DMARemap_UART1Rx) || \ + ((REMAP) == SYSCFG_DMARemap_UART1Tx) || \ + ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_UART3_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_UART2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \ + ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \ + ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \ + ((REMAP) == SYSCFG_DMARemap_ADC1)) + + +/** +* @} +*/ + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the SYSCFG configuration to the default reset state **/ +void SYSCFG_DeInit(void); + +/* SYSCFG configuration functions *********************************************/ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState); +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); +void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine); +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); +FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag); +void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag); + +#ifdef __cplusplus +} +#endif + +#endif /*__HAL_SYSCFG_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_tim.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_tim.h new file mode 100644 index 0000000000..41edfd8ac1 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_tim.h @@ -0,0 +1,1103 @@ +/** +****************************************************************************** +* @file HAL_tim.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the TIM firmware +* library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_TIM_H +#define __HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + + /* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + + /** @addtogroup StdPeriph_Driver + * @{ + */ + + /** @addtogroup TIM + * @{ + */ + + /* Exported types ------------------------------------------------------------*/ + + /** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx. + */ + + typedef struct + { + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; + /*!< Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1. */ + } TIM_TimeBaseInitTypeDef; + + /** + * @brief TIM Output Compare Init structure definition + */ + + typedef struct + { + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1. */ + + uint32_t TIM_Pulse; + uint16_t TIM_OCPolarity; + uint16_t TIM_OCNPolarity; + uint16_t TIM_OCIdleState; + uint16_t TIM_OCNIdleState; +} TIM_OCInitTypeDef; + +/** +* @brief TIM Input Capture Init structure definition +*/ + +typedef struct +{ + uint16_t TIM_Channel; + uint16_t TIM_ICPolarity; + uint16_t TIM_ICSelection; + uint16_t TIM_ICPrescaler; + uint16_t TIM_ICFilter; +} TIM_ICInitTypeDef; + +/** +* @brief BDTR structure definition +*/ + +typedef struct +{ + uint16_t TIM_OSSRState; + uint16_t TIM_OSSIState; + uint16_t TIM_LOCKLevel; + uint16_t TIM_DeadTime; + uint16_t TIM_Break; + uint16_t TIM_BreakPolarity; + uint16_t TIM_AutomaticOutput; +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants +* @{ +*/ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) + +/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14) || \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST6: TIM 1, 2, 3 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3)) + +/* LIST7: TIM 1, 2, 3 and 14 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14)) + +/* LIST8: TIM 1, 2, 3 and 14 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM14)) + +/* LIST9: TIM 1, 2, 3 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3)) + +/* LIST10: TIM 1, 2, 3, 16 and 17 */ +#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ +((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 11 */ +#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14) + + +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_and_PWM_modes +* @{ +*/ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ +((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ +((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** +* @} +*/ + +/** @defgroup TIM_One_Pulse_Mode +* @{ +*/ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ +((MODE) == TIM_OPMode_Repetitive)) +/** +* @} +*/ + +/** @defgroup TIM_Channel +* @{ +*/ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ +((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ +((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ +((CHANNEL) == TIM_Channel_2)) + +/** +* @} +*/ + +/** @defgroup TIM_Clock_Division_CKD +* @{ +*/ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ +((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** +* @} +*/ + +/** @defgroup TIM_Counter_Mode +* @{ +*/ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ +((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Polarity +* @{ +*/ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ +((POLARITY) == TIM_OCPolarity_Low)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_Polarity +* @{ +*/ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ +((POLARITY) == TIM_OCNPolarity_Low)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_state +* @{ +*/ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ +((STATE) == TIM_OutputState_Enable)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_state +* @{ +*/ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ +((STATE) == TIM_OutputNState_Enable)) +/** +* @} +*/ + +/** @defgroup TIM_Capture_Compare_state +* @{ +*/ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ +((CCX) == TIM_CCx_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Capture_Compare_N_state +* @{ +*/ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ +((CCXN) == TIM_CCxN_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Break_Input_enable_disable +* @{ +*/ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ +((STATE) == TIM_Break_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Break_Polarity +* @{ +*/ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ +((POLARITY) == TIM_BreakPolarity_High)) +/** +* @} +*/ + +/** @defgroup TIM_AOE_Bit_Set_Reset +* @{ +*/ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ +((STATE) == TIM_AutomaticOutput_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Lock_level +* @{ +*/ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ +((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** +* @} +*/ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state +* @{ +*/ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ +((STATE) == TIM_OSSIState_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state +* @{ +*/ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ +((STATE) == TIM_OSSRState_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Idle_State +* @{ +*/ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ +((STATE) == TIM_OCIdleState_Reset)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_N_Idle_State +* @{ +*/ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ +((STATE) == TIM_OCNIdleState_Reset)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Polarity +* @{ +*/ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ +((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Selection +* @{ +*/ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be +connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be +connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ +((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** +* @} +*/ + +/** @defgroup TIM_Input_Capture_Prescaler +* @{ +*/ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ +((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** +* @} +*/ + +/** @defgroup TIM_interrupt_sources +* @{ +*/ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ +((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** +* @} +*/ + +/** @defgroup TIM_DMA_Base_address +* @{ +*/ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define TIM_DMABase_OR ((uint16_t)0x0013) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ +((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR) || \ + ((BASE) == TIM_DMABase_OR)) +/** +* @} +*/ + + +/** @defgroup TIM_DMA_Burst_Length +* @{ +*/ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ +((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** +* @} +*/ + +/** @defgroup TIM_DMA_sources +* @{ +*/ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Prescaler +* @{ +*/ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ +((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** +* @} +*/ + +/** @defgroup TIM_Internal_Trigger_Selection +* @{ +*/ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ +((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ +((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** +* @} +*/ + +/** @defgroup TIM_TIx_External_Clock_Source +* @{ +*/ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Polarity +* @{ +*/ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ +((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** +* @} +*/ + +/** @defgroup TIM_Prescaler_Reload_Mode +* @{ +*/ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ +((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** +* @} +*/ + +/** @defgroup TIM_Forced_Action +* @{ +*/ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ +((ACTION) == TIM_ForcedAction_InActive)) +/** +* @} +*/ + +/** @defgroup TIM_Encoder_Mode +* @{ +*/ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ +((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** +* @} +*/ + + +/** @defgroup TIM_Event_Source +* @{ +*/ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** +* @} +*/ + +/** @defgroup TIM_Update_Source +* @{ +*/ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow +or the setting of UG bit, or an update generation +through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ +((SOURCE) == TIM_UpdateSource_Regular)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Preload_State +* @{ +*/ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ +((STATE) == TIM_OCPreload_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Fast_State +* @{ +*/ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ +((STATE) == TIM_OCFast_Disable)) + +/** +* @} +*/ + +/** @defgroup TIM_Output_Compare_Clear_State +* @{ +*/ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ +((STATE) == TIM_OCClear_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Trigger_Output_Source +* @{ +*/ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ +((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** +* @} +*/ + +/** @defgroup TIM_Slave_Mode +* @{ +*/ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ +((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** +* @} +*/ + +/** @defgroup TIM_Master_Slave_Mode +* @{ +*/ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ +((STATE) == TIM_MasterSlaveMode_Disable)) +/** +* @} +*/ + +/** @defgroup TIM_Flags +* @{ +*/ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ +((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** +* @} +*/ + + +/** @defgroup TIM_Input_Capture_Filer_Value +* @{ +*/ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** +* @} +*/ + +/** @defgroup TIM_External_Trigger_Filter +* @{ +*/ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** +* @} +*/ + +/** @defgroup TIM_OCReferenceClear +* @{ +*/ +#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) +#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) +#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ +((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) + +/** +* @} +*/ +/** @defgroup TIM_Remap +* @{ +*/ +#define TIM14_GPIO ((uint16_t)0x0000) +#define TIM14_RTC_CLK ((uint16_t)0x0001) +#define TIM14_HSEDiv32 ((uint16_t)0x0002) +#define TIM14_MCO ((uint16_t)0x0003) + +#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \ +((TIM_REMAP) == TIM14_RTC_CLK) || \ + ((TIM_REMAP) == TIM14_HSEDiv32) || \ + ((TIM_REMAP) == TIM14_MCO)) +/** +* @} +*/ + +/** @defgroup TIM_Legacy +* @{ +*/ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** +* @} +*/ + +/** +* @} +*/ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Advanced-control timers (TIM1) specific features*******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); + + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); + + +#ifdef __cplusplus +} +#endif + +#endif /*__HAL_TIM_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_uart.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_uart.h new file mode 100644 index 0000000000..ae9052cd59 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_uart.h @@ -0,0 +1,246 @@ +/** +****************************************************************************** +* @file HAL_UART.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the UART +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_UART_H +#define __HAL_UART_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup UART +* @{ +*/ + +/** @defgroup UART_Exported_Types +* @{ +*/ + +/** +* @brief UART Init Structure definition +*/ + +typedef struct +{ + uint32_t UART_BaudRate; + uint16_t UART_WordLength; + uint16_t UART_StopBits; + uint16_t UART_Parity; + uint16_t UART_Mode; + uint16_t UART_HardwareFlowControl; +} UART_InitTypeDef; + + +/** +* @} +*/ + +/** @defgroup UART_Exported_Constants +* @{ +*/ + +#define IS_UART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART3_BASE)) +#define IS_UART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \ +((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \ + ((*(uint32_t*)&(PERIPH)) == UART3_BASE)) + +/** @defgroup UART_Word_Length +* @{ +*/ + +#define UART_WordLength_5b ((uint16_t)0x0000) +#define UART_WordLength_6b ((uint16_t)0x0010) +#define UART_WordLength_7b ((uint16_t)0x0020) +#define UART_WordLength_8b ((uint16_t)0x0030) + + +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \ +((LENGTH) == UART_WordLength_6b) || \ + ((LENGTH) == UART_WordLength_7b) || \ + ((LENGTH) == UART_WordLength_8b)) +/** +* @} +*/ + +/** @defgroup UART_Stop_Bits +* @{ +*/ + +#define UART_StopBits_1 ((uint16_t)0x0000) +#define UART_StopBits_2 ((uint16_t)0x0004) + +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ +((STOPBITS) == UART_StopBits_2)) + +/** +* @} +*/ + +/** @defgroup UART_Parity +* @{ +*/ + +#define UART_Parity_No ((uint16_t)0x0000) +#define UART_Parity_Even ((uint16_t)0x0003) +#define UART_Parity_Odd ((uint16_t)0x0001) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ +((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) +/** +* @} +*/ + +/** @defgroup UART_Mode +* @{ +*/ + +#define UART_Mode_Rx ((uint16_t)0x0008) +#define UART_Mode_Tx ((uint16_t)0x0010) +#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFE7) == 0x00) && ((MODE) != (uint16_t)0x00)) + +#define UART_EN ((uint16_t)0x0001) + +/** +* @} +*/ + +/** @defgroup UART_Hardware_Flow_Control +* @{ +*/ +#define UART_HardwareFlowControl_None ((uint16_t)0x0000) + +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ +(((CONTROL) == UART_HardwareFlowControl_None) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS) || \ + ((CONTROL) == UART_HardwareFlowControl_CTS) || \ + ((CONTROL) == UART_HardwareFlowControl_RTS_CTS)) + +/** @defgroup UART_Interrupt_definition +* @{ +*/ + + +#define UART_IT_ERR ((uint16_t)0x0020) +#define UART_IT_PE ((uint16_t)0x0010) +#define UART_OVER_ERR ((uint16_t)0x0008) +#define UART_TIMEOUT_ERR ((uint16_t)0x0004) +#define UART_IT_RXIEN ((uint16_t)0x0002) +#define UART_IT_TXIEN ((uint16_t)0x0001) + +#define IS_UART_CONFIG_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \ +((IT) == UART_IT_RXIEN) || ((IT) == UART_IT_ERR)) + +#define IS_UART_GET_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \ +((IT) == UART_IT_ERR) || ((IT) == UART_IT_RXIEN) || \ + ((IT) == UART_OVER_ERR) || ((IT) == UART_TIMEOUT_ERR)) + +#define IS_UART_CLEAR_IT(IT) ((IT) == UART_IT_RXIEN) + + +/** +* @} +*/ + +/** @defgroup UART_DMA_Requests +* @{ +*/ +#define UART_DMAReq_EN ((uint16_t)0x0002) + +#define IS_UART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFD) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** +* @} +*/ + + +/** @defgroup UART_Flags +* @{ +*/ + + +#define UART_FLAG_TXEMPTY ((uint16_t)0x0008) +#define UART_FLAG_TXFULL ((uint16_t)0x0004) +#define UART_FLAG_RXAVL ((uint16_t)0x0002) +#define UART_FLAG_TXEPT ((uint16_t)0x0001) + + +#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_TXEMPTY) || ((FLAG) == UART_FLAG_TXFULL) || \ +((FLAG) == UART_FLAG_RXAVL) || ((FLAG) == UART_FLAG_TXEPT)) + + +#define IS_UART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x00FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_UART_DATA(DATA) ((DATA) <= 0x1FF) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup UART_Exported_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Exported_Functions +* @{ +*/ + +void UART_DeInit(UART_TypeDef* UARTx); +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState); +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState); +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_ReceiveData(UART_TypeDef* UARTx); +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG); +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG); +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT); +#endif /* __HAL_UART_H */ +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_wwdg.h b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_wwdg.h new file mode 100644 index 0000000000..3d43c7ccad --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/inc/HAL_wwdg.h @@ -0,0 +1,106 @@ +/** +****************************************************************************** +* @file HAL_wwdg.h +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file contains all the functions prototypes for the WWDG +* firmware library. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __HAL_WWDG_H +#define __HAL_WWDG_H + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_device.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @addtogroup WWDG +* @{ +*/ + +/** @defgroup WWDG_Exported_Types +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Constants +* @{ +*/ + +/** @defgroup WWDG_Prescaler +* @{ +*/ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ +((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** +* @} +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Macros +* @{ +*/ +/** +* @} +*/ + +/** @defgroup WWDG_Exported_Functions +* @{ +*/ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#endif /* __HAL_WWDG_H */ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_can.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_can.c new file mode 100644 index 0000000000..578d487c7a --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_can.c @@ -0,0 +1,1267 @@ +/** +****************************************************************************** +* @file HAL_can.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the CAN firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_can.h" +#include "HAL_rcc.h" + +/** +* @brief: Deinitialinzes the CAN registers to their default reset values +* @retval: None +*/ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + break; + case CAN2_BASE: + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + break; + default: + break; + } + +} + +/** +* @brief Initializes the CAN peripheral according to the specified +* parameters in the CAN_InitStruct. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that +* contains the configuration information for the CAN peripheral. +* @retval : Constant indicates initialization succeed which will be +* CANINITFAILED or CANINITOK. +*/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SJW)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->BRP)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SAM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG2)); + assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG1)); + + CANx->BTR0 = ((uint32_t)(CAN_Basic_InitStruct->SJW) << 6) | ((uint32_t)(CAN_Basic_InitStruct->BRP)); + CANx->BTR1 = ((uint32_t)(CAN_Basic_InitStruct->SAM) << 7) | ((uint32_t)(CAN_Basic_InitStruct->TESG2) << 4) | \ + ((uint32_t)(CAN_Basic_InitStruct->TESG1)); + if(CAN_Basic_InitStruct->GTS == ENABLE) + { + CANx->CMR |= (uint32_t)CAN_SleepMode; + } + else + { + CANx->CMR &= ~(uint32_t)CAN_SleepMode; + } + + CANx->CDR |= ((CAN_Basic_InitStruct->CBP) << 6) | ((CAN_Basic_InitStruct->RXINTEN) << 5) | \ + ((CAN_Basic_InitStruct->CLOSE_OPEN_CLK) << 3) | (CAN_Basic_InitStruct->CDCLK); + + InitStatus = CANINITOK; + return InitStatus; +} + +/** +* @brief Configures the CAN_Basic reception filter according to the specified +* parameters in the CAN_Basic_FilterInitStruct. +* @param CAN_Basic_FilterInitStruct: pointer to a CAN_Basic_FilterInitTypeDef structure that +* contains the configuration information. +* @retval None +*/ +void CAN_FilterInit(CAN_TypeDef* CANx, CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct) +{ + /* Filter Mode */ + CANx->ACR = CAN_Basic_FilterInitStruct->CAN_FilterId; + CANx->AMR = CAN_Basic_FilterInitStruct->CAN_FilterMaskId; +} + + +/** +* @brief Fills each CAN_Basic_InitStruct member with its default value. +* @param CAN_Basic_InitStruct : pointer to a CAN_Basic_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct) +{ + /*--------------- Reset CAN_Basic init structure parameters values -----------------*/ + + + /* initialize the BRP member(where can be set with (0..63))*/ + CAN_Basic_InitStruct->BRP = 0x0; + /* initialize the SJW member(where can be set with (0..3)) */ + CAN_Basic_InitStruct->SJW = 0x0; + /* Initialize the TESG1 member(where can be set with (0..15)) */ + CAN_Basic_InitStruct->TESG1 = 0x0; + /* Initialize the TESG2 member(where can be set with(0..7)) */ + CAN_Basic_InitStruct->TESG2 = 0x0; + /* Initialize the SAM member(where can be set (SET or RESET)) */ + CAN_Basic_InitStruct->SAM = RESET; + /* Initialize the GTS member to Sleep Mode(where can be set (ENABLE or DISABLE)) */ + CAN_Basic_InitStruct->GTS = DISABLE; + /* Initialize the external pin CLKOUT frequence */ + CAN_Basic_InitStruct->CDCLK = 0x0; + /* Initialize the external clk is open or close */ + CAN_Basic_InitStruct->CLOSE_OPEN_CLK = 0x0; + /* Initialize the TX1 pin work as rx interrupt output */ + CAN_Basic_InitStruct->RXINTEN = 0x0; + /* Initialize the CBP of CDR register */ + CAN_Basic_InitStruct->CBP = 0x0; +} + +/** +* @brief Enables or disables the specified CAN interrupts. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_IT: specifies the CAN interrupt sources to be enabled or +* disabled. +* This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE, +* CAN_IT_RIE,. +* @param Newstate: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(Newstate)); + if (Newstate != DISABLE) + { + /* Enable the selected CAN interrupt */ + CANx->CR |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CANx->CR &= ~CAN_IT; + } +} + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval CANTXOK if the CAN driver transmits the message +*/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage) +{ + /* TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_RTR(BasicTxMessage->RTR)); + assert_param(IS_CAN_DLC(BasicTxMessage->DLC)); + + CANx->TXID0 = (BasicTxMessage->IDH); + CANx->TXID1 = (BasicTxMessage->IDL << 5) | (BasicTxMessage->RTR << 4) | (BasicTxMessage->DLC); + if((FunctionalState)(BasicTxMessage->RTR) != ENABLE) + { + CANx->TXDR0 = BasicTxMessage->Data[0]; + CANx->TXDR1 = BasicTxMessage->Data[1]; + CANx->TXDR2 = BasicTxMessage->Data[2]; + CANx->TXDR3 = BasicTxMessage->Data[3]; + CANx->TXDR4 = BasicTxMessage->Data[4]; + CANx->TXDR5 = BasicTxMessage->Data[5]; + CANx->TXDR6 = BasicTxMessage->Data[6]; + CANx->TXDR7 = BasicTxMessage->Data[7]; + } + + CANx->CMR = CAN_CMR_TR; + + return state; +} + +/** +* @brief Cancels a transmit request. +* @param CANx: where x can be 1 to select the CAN peripheral. + +* @retval None +*/ +void CAN_CancelTransmit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + CANx->CMR = CAN_AT; + +} + +/** +* @brief Releases the specified receive FIFO. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @retval None +*/ +void CAN_FIFORelease(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Release FIFO */ + CANx->CMR |= (uint32_t)CAN_RRB; + +} + +/** +* @brief Receives a correct CAN frame. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param RxMessage: pointer to a structure receive frame which contains CAN Id, +* CAN DLC, CAN data and FMI number. +* @retval None +*/ +void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage) +{ + uint16_t tempid; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + BasicRxMessage->RTR = (uint8_t)((CANx->RXID1) >> 4) & 0x1; + BasicRxMessage->DLC = (uint8_t)((CANx->RXID1) & 0xf); + tempid = (uint16_t)(((CANx->RXID1) & 0xe0) >> 5); + tempid |= (uint16_t)(CANx->RXID0 << 3); + BasicRxMessage->ID = tempid; + BasicRxMessage->Data[0] = CANx->RXDR0; + BasicRxMessage->Data[1] = CANx->RXDR1; + BasicRxMessage->Data[2] = CANx->RXDR2; + BasicRxMessage->Data[3] = CANx->RXDR3; + BasicRxMessage->Data[4] = CANx->RXDR4; + BasicRxMessage->Data[5] = CANx->RXDR5; + BasicRxMessage->Data[6] = CANx->RXDR6; + BasicRxMessage->Data[7] = CANx->RXDR7; + CAN_FIFORelease( CANx); +} + +/** +* @brief: Select the Sleep mode or not in Basic workmode +* @param: NewState to go into the Sleep mode or go out +* @retval: None +*/ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + CANx->CMR |= CAN_SleepMode; + if((CANx->CMR & 0x10) == CAN_SleepMode) + { + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; + +} + +/** +* @brief Wakes the CAN up. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @retval : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other +* case. +*/ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->CMR &= ~CAN_SleepMode; + + /* Sleep mode status */ + if((CANx->CMR & 0x01) == 0) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + + +/** +* @brief Checks whether the specified CAN flag is set or not. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param CAN_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg CAN_STATUS_RBS: Receive buffer status +* @arg CAN_STATUS_DOS: Data overflow status +* @arg CAN_STATUS_TBS: Transmit buffer status +* @arg CAN_STATUS_TCS: Transmit complete status +* @arg CAN_STATUS_RS: Receiving status +* @arg CAN_STATUS_TS: Transmiting status +* @arg CAN_STATUS_ES: Error status +* @arg CAN_STATUS_BS: bus status, close or open +* @retval The new state of CAN_FLAG (SET or RESET). +*/ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CANx->SR & CAN_FLAG) == CAN_FLAG) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** +* @brief Checks whether the specified CAN interrupt has occurred or not. +* @param CANx: where x can be 1 to select the CAN peripheral. +* @param CAN_IT: specifies the CAN interrupt source to check. +* This parameter can be one of the following values: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_ALL: use it can enble all Interrupt +* @retval The current state of CAN_IT (SET or RESET). +*/ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the interrupt enable bit */ + if((CANx->IR & CAN_IT) != CAN_IT) + { + itstatus = RESET; + } + else + { + itstatus = SET; + } + + return itstatus; +} + + +/** +* @brief: Select the can work as peli mode or basic mode +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode +* @retval: None +*/ +void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + CANx->CDR |= CAN_MODE; +} + + +/** +* @brief: Select the Reset mode or not +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @param: NewState to go into the Reset mode or go out +* @retval: None +*/ +void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if(NewState == ENABLE) + { + CANx->CR |= CAN_ResetMode; + } + else + { + CANx->CR &= ~CAN_ResetMode; + } +} + +/** +* @brief Clear the data overflow. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @retval None +*/ +void CAN_ClearDataOverflow(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + CANx->CMR |= (uint32_t)CAN_CDO; + +} + +/** +* @brief Clears the CAN's IT pending. +* @param CANx: where x can be 1 or 2 to to select the CAN peripheral. +* @retval None +*/ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx) +{ + uint32_t temp = 0; + temp = temp; + temp = CANx->IR; //read this register clear all interrupt + +} + + + +/** +* @brief: Select the Sleep mode or not in Peli workmode +* @param: NewState to go into the Sleep mode or go out +* @retval: None +*/ +void CAN_Peli_SleepMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + if(NewState == ENABLE) + CAN1_PELI->MOD |= CAN_SleepMode; + else + CAN1_PELI->MOD &= ~CAN_SleepMode; + break; + case CAN2_BASE: + if(NewState == ENABLE) + CAN2_PELI->MOD |= CAN_SleepMode; + else + CAN2_PELI->MOD &= ~CAN_SleepMode; + break; + default: + break; + } +} + + +/** +* @brief Fills each CAN1_PELI_InitStruct member with its default value. +* @param CAN_Peli_InitStruct : pointer to a CAN_Peli_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct) +{ + /*--------------- Reset CAN_Peli init structure parameters values -----------------*/ + + /* initialize the BRP member(where can be set with (0..63))*/ + CAN_Peli_InitStruct->BRP = 0x0; + /* initialize the SJW member(where can be set with (0..3)) */ + CAN_Peli_InitStruct->SJW = 0x0; + /* Initialize the TESG1 member(where can be set with (0..15)) */ + CAN_Peli_InitStruct->TESG1 = 0x0; + /* Initialize the TESG2 member(where can be set with(0..7)) */ + CAN_Peli_InitStruct->TESG2 = 0x0; + /* Initialize the SAM member(where can be set (SET or RESET)) */ + CAN_Peli_InitStruct->SAM = RESET; + /* Initialize the LOM member*/ + CAN_Peli_InitStruct->LOM = DISABLE; + /* Initialize the STM member*/ + CAN_Peli_InitStruct->STM = DISABLE; + /* Initialize the SM member*/ + CAN_Peli_InitStruct->SM = DISABLE; + CAN_Peli_InitStruct->SRR = DISABLE; + CAN_Peli_InitStruct->EWLR = 0x96; +} + +/** +* @brief Initializes the CAN_Peli peripheral according to the specified +* parameters in the CAN_Peli_InitStruct. +* @param CAN_Basic_InitStruct: pointer to a CAN_Peli_InitTypeDef structure that contains +* the configuration information for the CAN peripheral in the peli workmode. +* @retval None +*/ +void CAN_Peli_Init(CAN_TypeDef* CANx, CAN_Peli_InitTypeDef* CAN_Peli_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SJW)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->BRP)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SAM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG2)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG1)); + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + CAN1_PELI->BTR0 = ((uint32_t)CAN_Peli_InitStruct->SJW << 6) | ((uint32_t)CAN_Peli_InitStruct->BRP); + CAN1_PELI->BTR1 = ((uint32_t)CAN_Peli_InitStruct->SAM << 7) | ((uint32_t)CAN_Peli_InitStruct->TESG2 << 4) | \ + ((uint32_t)CAN_Peli_InitStruct->TESG1); + if(CAN_Peli_InitStruct->LOM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_ListenOnlyMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_ListenOnlyMode; + if(CAN_Peli_InitStruct->STM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_SeftTestMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_SeftTestMode; + if(CAN_Peli_InitStruct->SM == ENABLE) + CAN1_PELI->MOD |= (uint32_t)CAN_SleepMode; + else + CAN1_PELI->MOD &= ~(uint32_t)CAN_SleepMode; + CAN1_PELI->EWLR = (uint32_t)CAN_Peli_InitStruct->EWLR; + break; + case CAN2_BASE: + CAN2_PELI->BTR0 = ((uint32_t)CAN_Peli_InitStruct->SJW << 6) | ((uint32_t)CAN_Peli_InitStruct->BRP); + CAN2_PELI->BTR1 = ((uint32_t)CAN_Peli_InitStruct->SAM << 7) | ((uint32_t)CAN_Peli_InitStruct->TESG2 << 4) | \ + ((uint32_t)CAN_Peli_InitStruct->TESG1); + if(CAN_Peli_InitStruct->LOM == ENABLE) + CAN2_PELI->MOD |= (uint32_t)CAN_ListenOnlyMode; + else + CAN2_PELI->MOD &= ~(uint32_t)CAN_ListenOnlyMode; + if(CAN_Peli_InitStruct->STM == ENABLE) + CAN2_PELI->MOD |= (uint32_t)CAN_SeftTestMode; + else + CAN2_PELI->MOD &= ~(uint32_t)CAN_SeftTestMode; + if(CAN_Peli_InitStruct->SM == ENABLE) + CAN2_PELI->MOD |= (uint32_t)CAN_SleepMode; + else + CAN2_PELI->MOD &= ~(uint32_t)CAN_SleepMode; + CAN2_PELI->EWLR = (uint32_t)CAN_Peli_InitStruct->EWLR; + break; + default: + break; + } +} + + + +/** +* @brief Configures the CAN_Peli reception filter according to the specified +* parameters in the CAN_Peli_FilterInitStruct. +* @param CAN_Peli_FilterInitStruct: pointer to a CAN_Peli_FilterInitTypeDef structure that +* contains the configuration information. +* @retval None +*/ +void CAN_Peli_FilterInit(CAN_TypeDef* CANx, CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct) +{ + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + if(CAN_Peli_FilterInitStruct->AFM == CAN_FilterMode_Singal) + CAN1_PELI->MOD |= (uint32_t)CAN_FilterMode_Singal; + else + CAN1_PELI->MOD &= (uint32_t)CAN_FilterMode_Double; + + CAN1_PELI->FF = CAN_Peli_FilterInitStruct->CAN_FilterId0; + CAN1_PELI->ID0 = CAN_Peli_FilterInitStruct->CAN_FilterId1; + CAN1_PELI->ID1 = CAN_Peli_FilterInitStruct->CAN_FilterId2; + CAN1_PELI->DATA0 = CAN_Peli_FilterInitStruct->CAN_FilterId3; + + CAN1_PELI->DATA1 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId0; + CAN1_PELI->DATA2 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId1; + CAN1_PELI->DATA3 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId2; + CAN1_PELI->DATA4 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId3; + break; + case CAN2_BASE: + if(CAN_Peli_FilterInitStruct->AFM == CAN_FilterMode_Singal) + CAN2_PELI->MOD |= (uint32_t)CAN_FilterMode_Singal; + else + CAN2_PELI->MOD &= (uint32_t)CAN_FilterMode_Double; + + CAN2_PELI->FF = CAN_Peli_FilterInitStruct->CAN_FilterId0; + CAN2_PELI->ID0 = CAN_Peli_FilterInitStruct->CAN_FilterId1; + CAN2_PELI->ID1 = CAN_Peli_FilterInitStruct->CAN_FilterId2; + CAN2_PELI->DATA0 = CAN_Peli_FilterInitStruct->CAN_FilterId3; + + CAN2_PELI->DATA1 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId0; + CAN2_PELI->DATA2 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId1; + CAN2_PELI->DATA3 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId2; + CAN2_PELI->DATA4 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId3; + break; + default: + break; + } + +} + +/** +* @brief Fills each CAN_Peli_FilterInitStruct member with its default value. +* @param CAN_Peli_FilterInitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. +* @retval None +*/ +void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct) +{ + CAN_Peli_FilterInitStruct->CAN_FilterId0 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId1 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId2 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterId3 = 0; + + CAN_Peli_FilterInitStruct->CAN_FilterMaskId0 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId1 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId2 = 0; + CAN_Peli_FilterInitStruct->CAN_FilterMaskId3 = 0; +} + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval None +*/ +void CAN_Peli_Transmit(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_RTR(PeliTxMessage->RTR)); + assert_param(IS_CAN_DLC(PeliTxMessage->DLC)); + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN1_PELI->ID0 = (PeliTxMessage->IDHH); + // CAN1_PELI->ID1 = ((PeliTxMessage->IDHL)<<5); + CAN1_PELI->ID1 = (PeliTxMessage->IDHL & 0xE0); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN1_PELI->ID0 = PeliTxMessage->IDHH; + CAN1_PELI->ID1 = PeliTxMessage->IDHL; + CAN1_PELI->DATA0 = PeliTxMessage->IDLH; + CAN1_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + if(CAN1_PELI->MOD & CAN_MOD_STM) + { + CANx->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CANx->CMR = CAN_TR | CAN_AT; + } + break; + case CAN2_BASE: + CAN2_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN2_PELI->ID0 = (PeliTxMessage->IDHH); + // CAN2_PELI->ID1 = ((PeliTxMessage->IDHL)<<5); + CAN2_PELI->ID1 = (PeliTxMessage->IDHL & 0xE0); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN2_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN2_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN2_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN2_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN2_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN2_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN2_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN2_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN2_PELI->ID0 = PeliTxMessage->IDHH; + CAN2_PELI->ID1 = PeliTxMessage->IDHL; + CAN2_PELI->DATA0 = PeliTxMessage->IDLH; + CAN2_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN2_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN2_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN2_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN2_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN2_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN2_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN2_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN2_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + if(CAN2_PELI->MOD & CAN_MOD_STM) + { + CANx->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CANx->CMR = CAN_TR | CAN_AT; + } + break; + default: + break; + } +} + + + +/** +* @brief Initiates and transmits a CAN frame message. +* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. +* @retval None +*/ +void CAN_Peli_TransmitRepeat(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_RTR(PeliTxMessage->RTR)); + assert_param(IS_CAN_DLC(PeliTxMessage->DLC)); + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN1_PELI->ID0 = (PeliTxMessage->IDHH); + CAN1_PELI->ID1 = ((PeliTxMessage->IDHL) << 5); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN1_PELI->ID0 = PeliTxMessage->IDHH; + CAN1_PELI->ID1 = PeliTxMessage->IDHL; + CAN1_PELI->DATA0 = PeliTxMessage->IDLH; + CAN1_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN1_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN1_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN1_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN1_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN1_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN1_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN1_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN1_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + + if(CAN1_PELI->MOD & CAN_MOD_STM) + { + CANx->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CANx->CMR = CAN_CMR_TR; + } + break; + case CAN2_BASE: + CAN2_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC); + if(((FunctionalState)PeliTxMessage->FF) != ENABLE) + { + CAN2_PELI->ID0 = (PeliTxMessage->IDHH); + CAN2_PELI->ID1 = ((PeliTxMessage->IDHL) << 5); + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN2_PELI->DATA0 = PeliTxMessage->Data[0]; + CAN2_PELI->DATA1 = PeliTxMessage->Data[1]; + CAN2_PELI->DATA2 = PeliTxMessage->Data[2]; + CAN2_PELI->DATA3 = PeliTxMessage->Data[3]; + CAN2_PELI->DATA4 = PeliTxMessage->Data[4]; + CAN2_PELI->DATA5 = PeliTxMessage->Data[5]; + CAN2_PELI->DATA6 = PeliTxMessage->Data[6]; + CAN2_PELI->DATA7 = PeliTxMessage->Data[7]; + } + } + else + { + CAN2_PELI->ID0 = PeliTxMessage->IDHH; + CAN2_PELI->ID1 = PeliTxMessage->IDHL; + CAN2_PELI->DATA0 = PeliTxMessage->IDLH; + CAN2_PELI->DATA1 = PeliTxMessage->IDLL; + if((FunctionalState)(PeliTxMessage->RTR) != ENABLE) + { + CAN2_PELI->DATA2 = PeliTxMessage->Data[0]; + CAN2_PELI->DATA3 = PeliTxMessage->Data[1]; + CAN2_PELI->DATA4 = PeliTxMessage->Data[2]; + CAN2_PELI->DATA5 = PeliTxMessage->Data[3]; + CAN2_PELI->DATA6 = PeliTxMessage->Data[4]; + CAN2_PELI->DATA7 = PeliTxMessage->Data[5]; + CAN2_PELI->DATA8 = PeliTxMessage->Data[6]; + CAN2_PELI->DATA9 = PeliTxMessage->Data[7]; + } + } + + if(CAN2_PELI->MOD & CAN_MOD_STM) + { + CANx->CMR = CAN_CMR_GTS | CAN_CMR_AT; + } + else + { + CANx->CMR = CAN_CMR_TR; + } + break; + default: + break; + } + +} + +/** @defgroup CAN_Group3 CAN Frames Reception functions +* @brief CAN Frames Reception functions +* +@verbatim +=============================================================================== +##### CAN Frames Reception functions ##### +=============================================================================== +[..] This section provides functions allowing to +(+) Receive a correct CAN frame. +(+) Release a specified receive FIFO +(+) Return the number of the pending received CAN frames. + +@endverbatim +* @{ +*/ + + +/** +* @brief Receives a correct CAN frame. +* @param RxMessage: pointer to a structure receive frame which contains CAN Id, +* CAN DLC, CAN data and FMI number. +* @retval None +*/ +void CAN_Peli_Receive(CAN_TypeDef* CANx, CanPeliRxMsg* PeliRxMessage) +{ + uint32_t tempid; + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + PeliRxMessage->FF = (CAN1_PELI->FF) >> 7; + PeliRxMessage->RTR = ((CAN1_PELI->FF) >> 6) & 0x1; + PeliRxMessage->DLC = (CAN1_PELI->FF) & 0xf; + + if(((FunctionalState)PeliRxMessage->FF) != ENABLE) + { + tempid = (uint32_t)(CAN1_PELI->ID1 >> 5); + tempid |= (uint32_t)(CAN1_PELI->ID0 << 3); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN1_PELI->DATA0; + PeliRxMessage->Data[1] = CAN1_PELI->DATA1; + PeliRxMessage->Data[2] = CAN1_PELI->DATA2; + PeliRxMessage->Data[3] = CAN1_PELI->DATA3; + PeliRxMessage->Data[4] = CAN1_PELI->DATA4; + PeliRxMessage->Data[5] = CAN1_PELI->DATA5; + PeliRxMessage->Data[6] = CAN1_PELI->DATA6; + PeliRxMessage->Data[7] = CAN1_PELI->DATA7; + } + else + { + tempid = (uint32_t)((CAN1_PELI->DATA1 & 0xf8) >> 3); + tempid |= (uint32_t)(CAN1_PELI->DATA0 << 5); + tempid |= (uint32_t)(CAN1_PELI->ID1 << 13); + tempid |= (uint32_t)(CAN1_PELI->ID0 << 21); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN1_PELI->DATA2; + PeliRxMessage->Data[1] = CAN1_PELI->DATA3; + PeliRxMessage->Data[2] = CAN1_PELI->DATA4; + PeliRxMessage->Data[3] = CAN1_PELI->DATA5; + PeliRxMessage->Data[4] = CAN1_PELI->DATA6; + PeliRxMessage->Data[5] = CAN1_PELI->DATA7; + PeliRxMessage->Data[6] = CAN1_PELI->DATA8; + PeliRxMessage->Data[7] = CAN1_PELI->DATA9; + } + CAN_FIFORelease(CANx); + break; + case CAN2_BASE: + PeliRxMessage->FF = (CAN2_PELI->FF) >> 7; + PeliRxMessage->RTR = ((CAN2_PELI->FF) >> 6) & 0x1; + PeliRxMessage->DLC = (CAN2_PELI->FF) & 0xf; + + if(((FunctionalState)PeliRxMessage->FF) != ENABLE) + { + tempid = (uint32_t)(CAN2_PELI->ID1 >> 5); + tempid |= (uint32_t)(CAN2_PELI->ID0 << 3); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN2_PELI->DATA0; + PeliRxMessage->Data[1] = CAN2_PELI->DATA1; + PeliRxMessage->Data[2] = CAN2_PELI->DATA2; + PeliRxMessage->Data[3] = CAN2_PELI->DATA3; + PeliRxMessage->Data[4] = CAN2_PELI->DATA4; + PeliRxMessage->Data[5] = CAN2_PELI->DATA5; + PeliRxMessage->Data[6] = CAN2_PELI->DATA6; + PeliRxMessage->Data[7] = CAN2_PELI->DATA7; + } + else + { + tempid = (uint32_t)((CAN2_PELI->DATA1 & 0xf8) >> 3); + tempid |= (uint32_t)(CAN2_PELI->DATA0 << 5); + tempid |= (uint32_t)(CAN2_PELI->ID1 << 13); + tempid |= (uint32_t)(CAN2_PELI->ID0 << 21); + PeliRxMessage->ID = tempid; + PeliRxMessage->Data[0] = CAN2_PELI->DATA2; + PeliRxMessage->Data[1] = CAN2_PELI->DATA3; + PeliRxMessage->Data[2] = CAN2_PELI->DATA4; + PeliRxMessage->Data[3] = CAN2_PELI->DATA5; + PeliRxMessage->Data[4] = CAN2_PELI->DATA6; + PeliRxMessage->Data[5] = CAN2_PELI->DATA7; + PeliRxMessage->Data[6] = CAN2_PELI->DATA8; + PeliRxMessage->Data[7] = CAN2_PELI->DATA9; + } + CAN_FIFORelease(CANx); + break; + default: + break; + } +} + + +/** +* @brief Get available current informatoin in receive FIFO only in Peli workmode. +* @retval The value in reg RMC +*/ +uint32_t CAN_Peli_GetRxFIFOInfo(CAN_TypeDef* CANx) +{ + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + return CAN1_PELI->RMC; + break; + case CAN2_BASE: + return CAN2_PELI->RMC; + break; + default: + break; + } + +} + + +/** @defgroup CAN_Group5 CAN Bus Error management functions +* @brief CAN Bus Error management functions +* +@verbatim +=============================================================================== +##### CAN Bus Error management functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Returns the CAN's last error code (LEC). +* @retval Error code: +* - CAN_ERRORCODE_NoErr: No Error +* - CAN_ERRORCODE_StuffErr: Stuff Error +* - CAN_ERRORCODE_FormErr: Form Error +* - CAN_ERRORCODE_ACKErr : Acknowledgment Error +* - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error +* - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error +* - CAN_ERRORCODE_CRCErr: CRC Error +* - CAN_ERRORCODE_SoftwareSetErr: Software Set Error +*/ +uint8_t CAN_Peli_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode = 0; + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* Get the error code*/ + errorcode = ((uint8_t)CAN1_PELI->ECC); + break; + case CAN2_BASE: + /* Get the error code*/ + errorcode = ((uint8_t)CAN2_PELI->ECC); + break; + default: + break; + } + /* Return the error code*/ + return errorcode; +} +/** +* @brief Returns the CAN Receive Error Counter (REC). +* @note In case of an error during reception, this counter is incremented +* by 1 or by 8 depending on the error condition as defined by the CAN +* standard. After every successful reception, the counter is +* decremented by 1 or reset to 120 if its value was higher than 128. +* When the counter value exceeds 127, the CAN controller enters the +* error passive state. +* @retval CAN Receive Error Counter. +*/ +uint8_t CAN_Peli_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* Get the Receive Error Counter*/ + counter = (uint8_t)(CAN1_PELI->RXERR); + break; + case CAN2_BASE: + /* Get the Receive Error Counter*/ + counter = (uint8_t)(CAN2_PELI->RXERR); + break; + default: + break; + } + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** +* @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). +* @retval LSB of the 8-bit CAN Transmit Error Counter. +*/ +uint8_t CAN_Peli_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* Get the LSB of the 8-bit CAN Transmit Error Counter(TEC) */ + counter = (uint8_t)(CAN1_PELI->TXERR); + break; + case CAN2_BASE: + /* Get the LSB of the 8-bit CAN Transmit Error Counter(TEC) */ + counter = (uint8_t)(CAN2_PELI->TXERR); + break; + default: + break; + } + + /* Return the LSB of the 8-bit CAN Transmit Error Counter(TEC) */ + return counter; +} +/** @defgroup CAN_Group6 Interrupts and flags management functions +* @brief Interrupts and flags management functions +* +@verbatim +=============================================================================== +##### Interrupts and flags management functions ##### +=============================================================================== +[..] This section provides functions allowing to configure the CAN Interrupts +and to get the status and clear flags and Interrupts pending bits. +[..] The CAN provides 14 Interrupts sources and 15 Flags: + +*** Flags *** +============= +*/ +/** +* @brief Enables or disables the specified CAN interrupts in peli workmode. +* @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. +* This parameter can be: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_EPI(only Peli): passive error Interrupt +* @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +* @arg CAN_IT_BEI(only Peli): bus error Interrupt +@arg CAN_IT_ALL: use it can enble all Interrupt +* @param NewState: new state of the CAN interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void CAN_Peli_ITConfig(CAN_TypeDef* CANx,uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN1_PELI->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN1_PELI->IER &= ~CAN_IT; + } + break; + case CAN2_BASE: + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CAN2_PELI->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CAN2_PELI->IER &= ~CAN_IT; + } + break; + default: + break; + } + +} + + +/** +* @brief Checks whether the specified CAN interrupt has occurred or not. +* @param CAN_IT: specifies the CAN interrupt source to check. +* This parameter can be one of the following values: +* @arg CAN_IT_RI: Receive FIFO not empty Interrupt +* @arg CAN_IT_TI: Transmit Interrupt +* @arg CAN_IT_EI: ERROR Interrupt +* @arg CAN_IT_DOI: Data voerflow Interrupt +* @arg CAN_IT_WUI: Wakeup Interrupt +* @arg CAN_IT_EPI(only Peli): passive error Interrupt +* @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt +* @arg CAN_IT_BEI(only Peli): bus error Interrupt +@arg CAN_IT_ALL: use it can enble all Interrupt +* @retval The current state of CAN_IT (SET or RESET). +*/ +ITStatus CAN_Peli_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_IT(CAN_IT)); + + switch (*(uint32_t*)&CANx) + { + case CAN1_BASE: + /* check the interrupt enable bit */ + if((CAN1_PELI->IR & CAN_IT) != CAN_IT) + { + itstatus = RESET; + } + else + { + itstatus = SET; + } + break; + case CAN2_BASE: + /* check the interrupt enable bit */ + if((CAN2_PELI->IR & CAN_IT) != CAN_IT) + { + itstatus = RESET; + } + else + { + itstatus = SET; + } + break; + default: + break; + } + + return itstatus; +} + +/** +* @brief Config CAN_Peli_InitTypeDef baud parameter. +* @param CAN_Peli_InitTypeDef: CAN struct. +* @param SrcClk: CAN module clock. +* @param baud: specified baud. +* @retval The current state of CAN_IT (SET or RESET). +*/ +void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud ) +{ + unsigned int i, value = baud, record = 1; + unsigned int remain = 0, sumPrescaler = 0; + while(( baud == 0 ) || ( SrcClk == 0 )); //·ÀÖ¹²¨ÌØÂʼ°Ê±ÖÓΪ0 + sumPrescaler = SrcClk / baud; //×Ü·ÖƵ + sumPrescaler = sumPrescaler / 2; // + for( i = 25; i > 3; i -- ) + { + remain = sumPrescaler - ((sumPrescaler / i) * i); + if( remain == 0 ) //Õû³ý + { + record = i; + break; + } + else + { + if(remain < value) + { + value = remain; + record = i; + } + } + } + CAN_Peli_InitStruct->SJW = 0; + CAN_Peli_InitStruct->BRP = (sumPrescaler / record) - 1; + CAN_Peli_InitStruct->TESG2 = (record - 3) / 3; + CAN_Peli_InitStruct->TESG1 = (record - 3) - CAN_Peli_InitStruct->TESG2; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + + + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ + diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma.c new file mode 100644 index 0000000000..72eb78a67f --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma.c @@ -0,0 +1,714 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "hal_dma.h" +#include "hal_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000001) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR1_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMAy_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + /* DMAy_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMAy_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMAy_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMAy_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; + } + else + { + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); + + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; + } + else + { + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c new file mode 100644 index 0000000000..8e4d885de3 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c @@ -0,0 +1,539 @@ +/** +****************************************************************************** +* @file HAL_dma.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the DMA firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_dma.h" + +//?? +#ifdef 0 + + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup DMA +* @brief DMA driver modules +* @{ +*/ + +/** @defgroup DMA_Private_TypesDefinitions +* @{ +*/ +/** +* @} +*/ + +/** @defgroup DMA_Private_Defines +* @{ +*/ + +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((uint32_t)0x00000001) +#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) + + + + + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** +* @} +*/ + +/** @defgroup DMA_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the DMAy Channelx registers to their default reset +* values. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @retval : None +*/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + switch (*(uint32_t*)&DMAy_Channelx) + { + case DMA1_Channel1_BASE: + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + break; + case DMA1_Channel2_BASE: + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + break; + case DMA1_Channel3_BASE: + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + break; + case DMA1_Channel4_BASE: + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + break; + case DMA1_Channel5_BASE: + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + break; + + + default: + break; + } +} + +/** +* @brief Initializes the DMAy Channelx according to the specified +* parameters in the DMA_InitStruct. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that +* contains the configuration information for the specified +* DMA Channel. +* @retval : None +*/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** +* @brief Fills each DMA_InitStruct member with its default value. +* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** +* @brief Enables or disables the specified DMAy Channelx. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param NewState: new state of the DMAy Channelx. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/** +* @brief Enables or disables the specified DMAy Channelx interrupts. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @param DMA_IT: specifies the DMA interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg DMA_IT_TC: Transfer complete interrupt mask +* @arg DMA_IT_HT: Half transfer interrupt mask +* @arg DMA_IT_TE: Transfer error interrupt mask +* @param NewState: new state of the specified DMA interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** +* @brief Returns the number of remaining data units in the current +* DMAy Channelx transfer. +* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and +* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the +* DMA Channel. +* @retval : The number of remaining data units in the current DMAy Channelx +* transfer. +*/ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** +* @brief Checks whether the specified DMAy Channelx flag is set or not. +* @param DMA_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* @retval : The new state of DMA_FLAG (SET or RESET). +*/ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** +* @brief Clears the DMAy Channelx's pending flags. +* @param DMA_FLAG: specifies the flag to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. +* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. +* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. +* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. +* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. +* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. +* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. +* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. +* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. +* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. +* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. +* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. +* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. +* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. +* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. +* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. +* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. +* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. +* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. +* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. +* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. +* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. +* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. +* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. +* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. +* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. +* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. +* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. +* @retval : None +*/ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; +} + +/** +* @brief Checks whether the specified DMAy Channelx interrupt has +* occurred or not. +* @param DMA_IT: specifies the DMA interrupt source to check. +* This parameter can be one of the following values: +* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* @retval : The new state of DMA_IT (SET or RESET). +*/ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** +* @brief Clears the DMAy Channelx’s interrupt pending bits. +* @param DMA_IT: specifies the DMA interrupt pending bit to clear. +* This parameter can be any combination (for the same DMA) of +* the following values: +* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. +* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. +* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. +* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. +* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. +* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. +* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. +* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. +* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. +* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. +* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. +* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. +* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. +* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. +* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. +* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. +* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. +* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. +* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. +* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. +* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. +* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. +* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. +* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. +* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. +* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. +* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. +* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. +* @retval : None +*/ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +#endif // 0 +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_exti.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_exti.c new file mode 100644 index 0000000000..087e3b993b --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_exti.c @@ -0,0 +1,272 @@ +/** +****************************************************************************** +* @file HAL_exti.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the EXTI firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_exti.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup EXTI +* @brief EXTI driver modules +* @{ +*/ + +/** @defgroup EXTI_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Defines +* @{ +*/ + +#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup EXTI_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the EXTI peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x001FFFFF; +} + +/** +* @brief Initializes the EXTI peripheral according to the specified +* parameters in the EXTI_InitStruct. +* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* that contains the configuration information for the EXTI +* peripheral. +* @retval : None +*/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Mode; + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** +* @brief Fills each EXTI_InitStruct member with its reset value. +* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** +* @brief Generates a Software interrupt. +* @param EXTI_Line: specifies the EXTI lines to be enabled or +* disabled. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** +* @brief Checks whether the specified EXTI line flag is set or not. +* @param EXTI_Line: specifies the EXTI line flag to check. +* This parameter can be: +* @arg EXTI_Linex: External interrupt line x where x(0..18) +* @retval : The new state of EXTI_Line (SET or RESET). +*/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the EXTI’s line pending flags. +* @param EXTI_Line: specifies the EXTI lines flags to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** +* @brief Checks whether the specified EXTI line is asserted or not. +* @param EXTI_Line: specifies the EXTI line to check. +* This parameter can be: +* @arg EXTI_Linex: External interrupt line x where x(0..18) +* @retval : The new state of EXTI_Line (SET or RESET). +*/ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the EXTI’s line pending bits. +* @param EXTI_Line: specifies the EXTI lines to clear. +* This parameter can be any combination of EXTI_Linex where +* x can be (0..18). +* @retval : None +*/ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_gpio.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_gpio.c new file mode 100644 index 0000000000..a6842f9607 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_gpio.c @@ -0,0 +1,548 @@ +/** +****************************************************************************** +* @file HAL_gpio.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the GPIO firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_gpio.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup GPIO +* @brief GPIO driver modules +* @{ +*/ + +/** @defgroup GPIO_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Defines +* @{ +*/ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the GPIOx peripheral registers to their default +* reset values. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : None +*/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + switch (*(uint32_t*)&GPIOx) + { + case GPIOA_BASE: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, DISABLE); + break; + case GPIOB_BASE: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, DISABLE); + break; + case GPIOC_BASE: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, DISABLE); + break; + case GPIOD_BASE: + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, DISABLE); + break; + default: + break; + } +} + + +/** +* @brief Initializes the GPIOx peripheral according to the specified +* parameters in the GPIO_InitStruct. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that +* contains the configuration information for the specified GPIO +* peripheral. +* @retval : None +*/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + + /*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + /*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } + /*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } + /*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/ + if(GPIO_InitStruct->GPIO_Pin>>16) //˵Ã÷ÊÇGPIOEµÄ16~23λ + { + GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16; + tmpreg = GPIOE->CRH_EXT; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOE->CRH_EXT = tmpreg; + } +} + +/** +* @brief Fills each GPIO_InitStruct member with its default value. +* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** +* @brief Reads the specified input port pin. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* @retval : The input port pin value. +*/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** +* @brief Reads the specified GPIO input data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : GPIO input data port value. +*/ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** +* @brief Reads the specified output data port bit. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to read. +* This parameter can be GPIO_Pin_x where x can be (0..15). +* @retval : The output port pin value. +*/ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** +* @brief Reads the specified GPIO output data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @retval : GPIO output data port value. +*/ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** +* @brief Sets the selected data port bits. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + if(GPIO_Pin>GPIO_Pin_15)GPIOE->BSRR_EXT=GPIO_Pin>>16; + else + GPIOx->BSRR = GPIO_Pin; + +} + +/** +* @brief Clears the selected data port bits. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bits to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + GPIOx->BRR = GPIO_Pin; +} + +/** +* @brief Sets or clears the selected data port bit. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to be written. +* This parameter can be one of GPIO_Pin_x where x can be (0..15). +* @param BitVal: specifies the value to be written to the selected bit. +* This parameter can be one of the BitAction enum values: +* @arg Bit_RESET: to clear the port pin +* @arg Bit_SET: to set the port pin +* @retval : None +*/ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** +* @brief Writes data to the specified GPIO data port. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param PortVal: specifies the value to be written to the port output +* data register. +* @retval : None +*/ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** +* @brief Locks GPIO Pins configuration registers. +* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. +* @param GPIO_Pin: specifies the port bit to be written. +* This parameter can be any combination of GPIO_Pin_x where +* x can be (0..15). +* @retval : None +*/ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + + +/** +* @brief Writes data to the specified GPIO data port. +* @param GPIOx: where x can be (A, B, C, D ) to select the GPIO peripheral. +* @param GPIO_PinSource: specifies the pin for the Alternate function. +* This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD +* and (0..12) for GPIOC . +* @param GPIO_AF: selects the pin to used as Alternate function. +* This parameter can be one of the following value: +* @arg GPIO_AF_0: SPI1, MC0, TIM17_BKIN, SWDIO,SWCLK, +UART1 +* @arg GPIO_AF_1: UART1, TIM3_CH1, TIM3_CH2, TIM3_CH3, +TIM3_CH4, I2C1 +* @arg GPIO_AF_2: TIM2_CH1_ETR, TIM2_CH2, TIM2_CH3, +TIM2_CH3, TIM2_CH4, TIM1_BKIN, +TIM1_CH1N, TIM1_CH1, TIM1_CH2, +TIM1_CH3, TIM1_CH4, TIM1_ETR, +TIM1_CH2N, TIM1_CH3N, TIM2_CH2, +TIM1 6_BKIN, TIM16_CH1N, TIM17_CH1N, +TIM1 6_CH1, TIM17_CH1 +* @arg GPIO_AF_4: TIM14_CH1, I2C1 +* @note The pin should already been configured in Alternate Function mode(AF) +* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF +* @note Refer to the Alternate function mapping table in the device datasheet +* for the detailed mapping of the system and peripherals'alternate +* function I/O pins. +* @retval None +*/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF) +{ + uint32_t temp; + unsigned char i; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + if(GPIO_Pin>>16) //˵Ã÷ÊÇGPIOEµÄ16~23λ + { + temp = GPIO_Pin>>16; + for(i=0;i<8;i++) + { + if(temp&0x01) + { + GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AFÅäÖÃÕ¼°ë×Ö½Ú£¬Òªx4,¼´<<2 + GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); + } + temp = temp>>1; + } + } + if(GPIO_Pin&0XFF00) //˵Ã÷ÊÇGPIOEµÄ8~15λ + { + temp = GPIO_Pin>>8; + for(i=0;i<8;i++) + { + if(temp&0x01) + { + GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AFÅäÖÃÕ¼°ë×Ö½Ú£¬Òªx4,¼´<<2 + GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); + } + temp = temp>>1; + } + } + if(GPIO_Pin&0XFF) //˵Ã÷ÊÇGPIOEµÄ0~7λ + { + for(i=0;i<8;i++) + { + if(temp&0x01) + { + GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AFÅäÖÃÕ¼°ë×Ö½Ú£¬Òªx4,¼´<<2 + GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2))); + } + temp = temp>>1; + } + } +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c new file mode 100644 index 0000000000..73cd8d2205 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c @@ -0,0 +1,848 @@ +/** +****************************************************************************** +* @file HAL_i2c.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the I2C firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_i2c.h" +#include "HAL_rcc.h" + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup I2C +* @brief I2C driver modules +* @{ +*/ + +/** @defgroup I2C_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Defines +* @{ +*/ + +/*I2c Enable disable*/ +#define IC_ENABLE_Reset ((uint16_t)0xFFFE) +#define IC_ENABLE_Set ((uint16_t)0x0001) +#define IC_CON_RESET ((uint16_t)0xFE8A) +#define INTR_MASK ((uint16_t)0xC000) + +/*I2c DMA reset*/ +#define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC) + +/* I2C START mask */ +#define IC_CON_START_Set ((uint16_t)0x0020) +#define IC_CON_START_Reset ((uint16_t)0xFFDF) + +/* I2C STOP mask */ +#define IC_DATA_CMD_STOP_Set ((uint16_t)0x0200) +#define IC_DATA_CMD_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ADD2 mask */ +#define IC_TAR_Reset ((uint16_t)0xFF00) + +/* I2C IC_10BITADDR_MASTER bit mask */ +#define IC_TAR_ENDUAL_Set ((uint16_t)0x1000) +#define IC_TAR_ENDUAL_Reset ((uint16_t)0xEFFF) + +/* I2C SPECIAL¡¢GC_OR_START bits mask */ +#define IC_TAR_GC_Set ((uint16_t)0x0800) +#define IC_TAR_GC_Reset ((uint16_t)0xF7FF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00793FFF) + +//static + uint8_t I2C_CMD_DIR = 0; + +/*ÐÂÔö¼ÓµÄÓû§±äÁ¿£¬Íⲿµ÷ÓÃʱÐèÒª¸üиñäÁ¿Öµ*/ +uint16_t I2C_DMA_DIR = 0; + +/** +* @} +*/ + +/** @defgroup I2C_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup I2C_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the I2Cx peripheral registers to their default +* reset values. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : None +*/ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + switch (*(uint32_t*)&I2Cx) + { + case I2C1_BASE: + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + break; + + default: + break; + } +} + +/** +* @brief Initializes the I2Cx peripheral according to the specified +* parameters in the I2C_InitStruct. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that +* contains the configuration information for the specified +* I2C peripheral. +* @retval : None +*/ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + + uint16_t tmpreg = 0; + uint32_t pclk1 = 8000000; + uint32_t minSclLowTime = 0; + uint32_t i2cPeriod = 0; + uint32_t pclk1Period = 0; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + /*---------------------------- I2Cx IC_ENABLE Configuration ------------------------*/ + /* Disable the selected I2C peripheral */ + I2Cx->IC_ENABLE &= IC_ENABLE_Reset; + + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + + /* Set pclk1 period value */ + pclk1Period = 1000000000/pclk1; + + i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit + tmpreg = 0; + + /*Get the I2Cx IC_CON value */ + tmpreg = I2Cx->IC_CON; + /*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ + tmpreg &= IC_CON_RESET; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + minSclLowTime = i2cPeriod/pclk1Period; + I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2; + I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT; + I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD; + } + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + minSclLowTime = i2cPeriod/pclk1Period; + I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2; + I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT; + I2C_InitStruct->I2C_Speed = I2C_Speed_FAST; + } + + + /*Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/ + tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN |IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode; + /* Write to I2Cx IC_CON */ + I2Cx->IC_CON = tmpreg; + + /*---------------------------- I2Cx IC_INTR_MASK Configuration ------------------------*/ + /* Get the I2Cx IC_INTR_MASK value */ + tmpreg = I2Cx->IC_INTR_MASK; + /* clear the I2Cx IC_INTR_MASK value */ + tmpreg &= INTR_MASK; + /* Write to IC_INTR_MASK */ + I2Cx->IC_INTR_MASK = tmpreg; + + /* Write to IC_RX_TL */ + I2Cx->IC_RX_TL = 0x0; //rxfifo depth is 1 + /* Write to IC_TX_TL */ + I2Cx->IC_TX_TL = 0x1; //tcfifo depth is 1 + +} + +/** +* @brief Fills each I2C_InitStruct member with its default value. +* @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_MASTER; + /* Initialize the I2C_OwnAddress member */ + I2C_InitStruct->I2C_OwnAddress = 0xA8; + /* Initialize the I2C_Speed member */ + I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD; + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 100000; +} + +/** +* @brief Enables or disables the specified I2C peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2Cx peripheral. This parameter +* can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->IC_ENABLE |= IC_ENABLE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->IC_ENABLE &= IC_ENABLE_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C DMA requests. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param DMA_Direcction : TDMAE_SET,RDMAE_SET +* This parameter can be any combination of the following values: +* @arg TDMAE_SET :DMA TX set +* @arg RDMAE_SET :DMA RX set +* @param NewState: new state of the I2C DMA transfer. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + if(I2C_DMA_DIR==TDMAE_SET) + { + /* Enable the selected I2C TX DMA requests */ + I2Cx->IC_DMA_CR |= TDMAE_SET; + } + else if(I2C_DMA_DIR==RDMAE_SET) + { + /* Enable the selected I2C TX DMA requests */ + I2Cx->IC_DMA_CR |= RDMAE_SET; + } + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->IC_DMA_CR &= DMA_CR_TDMAE_RDMAE_Reset; + } +} + + +/** +* @brief Generates I2Cx communication START condition. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C START condition generation. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->IC_CON |= IC_CON_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->IC_CON &= IC_CON_START_Reset; + } +} + +/** +* @brief Generates I2Cx communication STOP condition. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C STOP condition generation. +* This parameter can be: ENABLE or DISABLE. +* @retval : None. +*/ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->IC_DATA_CMD |= IC_DATA_CMD_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->IC_DATA_CMD &= IC_DATA_CMD_STOP_Reset; + } +} + +/** +* @brief Configures the specified I2C own address2. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Address: specifies the 7bit I2C own address2. +* @retval : None. +*/ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +//void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Get the old register value */ + tmpreg = I2Cx->IC_TAR; + /* Reset I2Cx Own address2 bit [7:0] */ + tmpreg &= IC_TAR_Reset; + /* Set I2Cx Own address2 */ + tmpreg |= Address>>1; + /* Store the new register value */ + I2Cx->IC_TAR = tmpreg; +} + +/** +* @brief Enables or disables the specified I2C dual addressing mode. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C dual addressing mode. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->IC_TAR |= IC_TAR_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->IC_TAR &= IC_TAR_ENDUAL_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C general call feature. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param NewState: new state of the I2C General call. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->IC_TAR |= IC_TAR_GC_Set; + } + else + { + /* Disable generall call */ + I2Cx->IC_TAR &= IC_TAR_GC_Reset; + } +} + +/** +* @brief Enables or disables the specified I2C interrupts. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the I2C interrupts sources to be enabled +* or disabled. +* This parameter can be any combination of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt mask +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask +* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask +* @arg I2C_IT_STOP_DET : stop condition interrupt mask +* @arg I2C_IT_START_DET : start condition interrupt mask +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask +* @param NewState: new state of the specified I2C interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if(I2C_IT == I2C_IT_RX_FULL) + { + I2C1->IC_DATA_CMD = CMD_READ; + } + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->IC_INTR_MASK |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; + } +} + +/** +* @brief Sends a data byte through the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Data: Byte to be transmitted.. +* @retval : None +*/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the IC_DATA_CMD register the data to be sent */ + I2Cx->IC_DATA_CMD = CMD_WRITE | Data; +} + +/** +* @brief Returns the most recent received data by the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The value of the received data. + +*/ +void I2C_ReadCmd(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + I2Cx->IC_DATA_CMD = CMD_READ; +} + +/** +* @brief Returns the most recent received data by the I2Cx peripheral. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The value of the received data. +*/ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + I2C_CMD_DIR= 0; + /* Return the data in the IC_DATA_CMD register */ + return (uint8_t)I2Cx->IC_DATA_CMD; +} + +/** +* @brief Transmits the address byte to select the slave device. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param Address: specifies the slave address which will be transmitted +* @param I2C_Direction: specifies whether the I2C device will be a +* Transmitter or a Receiver. +* This parameter can be one of the following values +* @arg I2C_Direction_Transmitter: Transmitter mode +* @arg I2C_Direction_Receiver: Receiver mode +* @retval : None. +*/ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Store the new register value */ + I2Cx->IC_TAR = Address>>1; +} + +/** +* @brief Reads the specified I2C register and returns its value. +* @param I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* @retval : The value of the read register. +*/ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + /* Return the selected register value */ + return (*(__IO uint16_t *)(*((__IO uint32_t *)&I2Cx) + I2C_Register)); +} + +/** +* @brief Returns the last I2Cx Event. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @retval : The last event +*/ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Read the I2Cx status register */ + flag1 = I2Cx->IC_RAW_INTR_STAT; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 ) & FLAG_Mask; + /* Return status */ + return lastevent; +} + + + +/** +* @brief Checks whether the last I2Cx Event is equal to the one passed +* as parameter. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_EVENT: specifies the event to be checked. +* This parameter can be one of the following values: +* @arg I2C_EVENT_RX_UNDER: Rx Buffer is empty event +* @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event +* @arg I2C_EVENTT_RX_FULL : Rx buffer full event +* @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event +* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event +* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event +* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode) +* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode) +* @arg I2C_EVENT_ACTIVITY : I2C activity event +* @arg I2C_EVENT_STOP_DET : stop condition event +* @arg I2C_EVENT_START_DET : start condition event +* @arg I2C_EVENT_GEN_CALL : a general call address and ack event +* - SUCCESS: Last event is equal to the I2C_EVENT +* - ERROR: Last event is different from the I2C_EVENT +*/ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0; + ErrorStatus status = ERROR; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + if((I2C_EVENT == I2C_EVENT_RX_FULL)&&(I2C_CMD_DIR==0)) + { + I2C1->IC_DATA_CMD = CMD_READ; + I2C_CMD_DIR = 1; + } + /* Read the I2Cx status register */ + flag1 = I2Cx->IC_RAW_INTR_STAT; + //flag1 = I2Cx->IC_INTR_STAT; + /* Get the last event value from I2C status register */ + lastevent = (flag1 ) & I2C_EVENT; + + /* Check whether the last event is equal to I2C_EVENT */ + if (lastevent == I2C_EVENT ) + //if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; + +} + +/** +* @brief Checks whether the specified I2C flag is set or not. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag +* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +* @arg I2C_FLAG_RX_FULL : Rx buffer full flag +* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag +* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +* @arg I2C_FLAG_ACTIVITY: I2C activity flag +* @arg I2C_FLAG_STOP_DET: stop condition flag +* @arg I2C_FLAG_START_DET: start condition flag +* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +* @retval : The new state of I2C_FLAG (SET or RESET). +*/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + /* Check the status of the specified I2C flag and set I2C direction*/ + if((I2C_FLAG == I2C_FLAG_RX_FULL)&&(I2C_CMD_DIR==0)) + { + I2Cx->IC_DATA_CMD = CMD_READ; + I2C_CMD_DIR = 1; + } + + /* Check the status of the specified I2C flag */ + if((I2Cx->IC_RAW_INTR_STAT & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + +/** +* @brief Clears the I2Cx's pending flags. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag +* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag +* @arg I2C_FLAG_RX_FULL : Rx buffer full flag +* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag +* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag +* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag +* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode) +* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode) +* @arg I2C_FLAG_ACTIVITY: I2C activity flag +* @arg I2C_FLAG_STOP_DET: stop condition flag +* @arg I2C_FLAG_START_DET: start condition flag +* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag +* @retval : None +*/ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + __IO uint32_t i2creg = 0, i2cxbase = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2Cx peripheral base address */ + i2cxbase = (*(uint32_t*)&(I2Cx)); + + if(I2C_FLAG==I2C_FLAG_RX_UNDER) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x44; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_RX_UNDER = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_RX_OVER) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x48; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_RX_OVER = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_TX_OVER) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x4C; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_TX_OVER = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_RD_REQ) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x50; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_RD_REQ = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_TX_ABRT) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x54; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_TX_ABRT = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_RX_DONE) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x58; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_RX_DONE = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_ACTIVITY) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x5C; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_ACTIVITY = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_STOP_DET) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x60; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_STOP_DET = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_START_DET) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x64; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_START_DET = (uint16_t)I2C_FLAG; + } + if(I2C_FLAG==I2C_FLAG_GEN_CALL) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x68; + /* Clear the selected I2C flag */ + I2Cx->IC_CLR_GEN_CALL = (uint16_t)I2C_FLAG; + } +} + +/** +* @brief Checks whether the specified I2C interrupt has occurred or not. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the interrupt source to check. +* This parameter can be one of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt +* @arg I2C_IT_STOP_DET : stop condition interrupt +* @arg I2C_IT_START_DET : start condition interrupt +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +* @retval : The new state of I2C_IT (SET or RESET). +*/ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check the status of the specified I2C flag */ + if((I2Cx->IC_RAW_INTR_STAT & I2C_IT) != (uint32_t)RESET) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + + /* Return the I2C_IT status */ + return bitstatus; +} + +/** +* @brief Clears the I2Cx interrupt pending bits. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. +* @param I2C_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt +* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt +* @arg I2C_IT_RX_FULL : Rx buffer full interrupt +* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt +* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt +* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt +* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode) +* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode) +* @arg I2C_IT_ACTIVITY : I2C activity interrupt +* @arg I2C_IT_STOP_DET : stop condition interrupt +* @arg I2C_IT_START_DET : start condition interrupt +* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt +* @retval : None +*/ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Clear the selected I2C flag */ + I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_iwdg.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_iwdg.c new file mode 100644 index 0000000000..657e843ffc --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_iwdg.c @@ -0,0 +1,198 @@ +/** +****************************************************************************** +* @file HAL_iwdg.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the IWDG firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_iwdg.h" + +//IWDG_BASE 未定义 +#ifdef 0 + + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup IWDG +* @brief IWDG driver modules +* @{ +*/ + +/** @defgroup IWDG_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Defines +* @{ +*/ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup IWDG_Private_Functions +* @{ +*/ + +/** +* @brief Enables or disables write access to IWDG_PR and IWDG_RLR +* registers. +* @param IWDG_WriteAccess: new state of write access to IWDG_PR and +* IWDG_RLR registers. +* This parameter can be one of the following values: +* @arg IWDG_WriteAccess_Enable: Enable write access to +* IWDG_PR and IWDG_RLR registers +* @arg IWDG_WriteAccess_Disable: Disable write access to +* IWDG_PR and IWDG_RLR registers +* @retval : None +*/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** +* @brief Sets IWDG Prescaler value. +* @param IWDG_Prescaler: specifies the IWDG Prescaler value. +* This parameter can be one of the following values: +* @arg IWDG_Prescaler_4: IWDG prescaler set to 4 +* @arg IWDG_Prescaler_8: IWDG prescaler set to 8 +* @arg IWDG_Prescaler_16: IWDG prescaler set to 16 +* @arg IWDG_Prescaler_32: IWDG prescaler set to 32 +* @arg IWDG_Prescaler_64: IWDG prescaler set to 64 +* @arg IWDG_Prescaler_128: IWDG prescaler set to 128 +* @arg IWDG_Prescaler_256: IWDG prescaler set to 256 +* @retval : None +*/ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** +* @brief Sets IWDG Reload value. +* @param Reload: specifies the IWDG Reload value. +* This parameter must be a number between 0 and 0x0FFF. +* @retval : None +*/ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** +* @brief Reloads IWDG counter with value defined in the reload register +* (write access to IWDG_PR and IWDG_RLR registers disabled). +* @param None +* @retval : None +*/ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** +* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers +* disabled). +* @param None +* @retval : None +*/ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** +* @brief Checks whether the specified IWDG flag is set or not. +* @param IWDG_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg IWDG_FLAG_PVU: Prescaler Value Update on going +* @arg IWDG_FLAG_RVU: Reload Value Update on going +* @retval : The new state of IWDG_FLAG (SET or RESET). +*/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +#endif // 0 +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_misc.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_misc.c new file mode 100644 index 0000000000..22a53d11d9 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_misc.c @@ -0,0 +1,256 @@ +/** +****************************************************************************** +* @file HAL_misc.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the miscellaneous firmware functions (add-on +* to CMSIS functions). +****************************************************************************** +* @attention +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_misc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup MISC +* @brief MISC driver modules +* @{ +*/ + +/** @defgroup MISC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Defines +* @{ +*/ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** +* @} +*/ + +/** @defgroup MISC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup MISC_Private_Functions +* @{ +*/ + +/** +* @brief Configures the priority grouping: pre-emption priority and subpriority. +* @param NVIC_PriorityGroup: specifies the priority grouping bits length. +* This parameter can be one of the following values: +* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority +* 4 bits for subpriority +* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority +* 3 bits for subpriority +* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority +* 2 bits for subpriority +* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority +* 1 bits for subpriority +* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority +* 0 bits for subpriority +* @retval None +*/ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} +//void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +//{ +// /* Check the parameters */ +// assert_param(IS_TIM_ALL_PERIPH(TIMx)); +// assert_param(IS_TIM_IT(TIM_IT)); +// assert_param(IS_FUNCTIONAL_STATE(NewState)); +// +// if (NewState != DISABLE) +// { +// /* Enable the Interrupt sources */ +// TIMx->DIER |= TIM_IT; +// } +// else +// { +// /* Disable the Interrupt sources */ +// TIMx->DIER &= (uint16_t)~TIM_IT; +// } +//} + +//void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +//{ +// /* Check the parameters */ +// assert_param(IS_TIM_ALL_PERIPH(TIMx)); +// assert_param(IS_FUNCTIONAL_STATE(NewState)); +// +// if (NewState != DISABLE) +// { +// /* Enable the TIM Counter */ +// TIMx->CR1 |= TIM_CR1_CEN; +// } +// else +// { +// /* Disable the TIM Counter */ +// TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); +// } +//} + +/** +* @brief Initializes the NVIC peripheral according to the specified +* parameters in the NVIC_InitStruct. +* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains +* the configuration information for the specified NVIC peripheral. +* @retval None +*/ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + + tmppre = NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05]; + //printf("NVIC->ISER = 0x%x\r\n",tmppre); +} + +/** +* @brief Sets the vector table location and Offset. +* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. +* This parameter can be one of the following values: +* @arg NVIC_VectTab_RAM +* @arg NVIC_VectTab_FLASH +* @param Offset: Vector Table base offset field. This value must be a multiple +* of 0x200. +* @retval None +*/ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + + + //SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** +* @brief Selects the condition for the system to enter low power mode. +* @param LowPowerMode: Specifies the new mode for the system to enter low power mode. +* This parameter can be one of the following values: +* @arg NVIC_LP_SEVONPEND +* @arg NVIC_LP_SLEEPDEEP +* @arg NVIC_LP_SLEEPONEXIT +* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** +* @brief Configures the SysTick clock source. +* @param SysTick_CLKSource: specifies the SysTick clock source. +* This parameter can be one of the following values: +* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. +* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. +* @retval None +*/ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_pwr.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_pwr.c new file mode 100644 index 0000000000..2bcdab6193 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_pwr.c @@ -0,0 +1,346 @@ +/** +****************************************************************************** +* @file HAL_pwr.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the PWR firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_pwr.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup PWR +* @brief PWR driver modules +* @{ +*/ + +/** @defgroup PWR_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Defines +* @{ +*/ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_PDDS_Set ((uint32_t)0x00000002) +#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) +#define CR_CWUF_Set ((uint32_t)0x00000004) +#define CR_PLS_Mask ((uint32_t)0xFFFFE1FF) + +/* --------- Cortex System Control register bit mask ---------------- */ + +/* Cortex System Control register address */ +#define SCB_SysCtrl ((uint32_t)0xE000ED10) + +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +/** +* @} +*/ + +/** @defgroup PWR_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PWR_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the PWR peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** +* @brief Enables or disables access to the RTC and backup registers. +* @param NewState: new state of the access to the RTC and backup +* registers. This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; + if(NewState!=DISABLE) + { + PWR->CR |= 0x00000100; + } + else + { + PWR->CR &= 0xfffffeff; + } + +} + +/** +* @brief Enables or disables the Power Voltage Detector(PVD). +* @param NewState: new state of the PVD. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState==ENABLE) + { + PWR->CR |= 0x00000010; + } + else + { + PWR->CR &= 0xffffffef; + } + +} + +/** +* @brief Configures the voltage threshold detected by the Power Voltage +* Detector(PVD). +* @param PWR_PVDLevel: specifies the PVD detection level +* This parameter can be one of the following values: +* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V +* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V +* @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V +* @arg PWR_PVDLevel_3V2: PVD detection level set to 3.2V +* @arg PWR_PVDLevel_3V4: PVD detection level set to 3.4V +* @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V +* @arg PWR_PVDLevel_3V8: PVD detection level set to 3.8V +* @arg PWR_PVDLevel_4V0: PVD detection level set to 4.0V +* @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V +* @arg PWR_PVDLevel_4V4: PVD detection level set to 4.4V +* @arg PWR_PVDLevel_4V6: PVD detection level set to 4.6V +* @retval : None +*/ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** +* @brief Enables or disables the WakeUp Pin functionality. +* @param NewState: new state of the WakeUp Pin functionality. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState!=DISABLE) + { + PWR->CSR |= 0x00000100; + } + else + { + PWR->CSR &= 0xfffffeff; + } +} + +/** +* @brief Enters STOP mode. +* @param PWR_Regulator: specifies the regulator state in STOP mode. +* This parameter can be one of the following values: +* @arg PWR_Regulator_ON: STOP mode with regulator ON +* @arg PWR_Regulator_LowPower: STOP mode with +* regulator in low power mode +* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or +* WFE instruction. +* This parameter can be one of the following values: +* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction +* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction +* @retval : None +*/ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + SCB->SCR |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } +} + +/** +* @brief Enters STANDBY mode. +* @param None +* @retval : None +*/ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + + SCB->SCR |= SysCtrl_SLEEPDEEP_Set; + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** +* @brief Checks whether the specified PWR flag is set or not. +* @param PWR_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg PWR_FLAG_WU: Wake Up flag +* @arg PWR_FLAG_SB: StandBy flag +* @arg PWR_FLAG_PVDO: PVD Output +* @retval : The new state of PWR_FLAG (SET or RESET). +*/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @brief Clears the PWR's pending flags. +* @param PWR_FLAG: specifies the flag to clear. +* This parameter can be one of the following values: +* @arg PWR_FLAG_WU: Wake Up flag +* @arg PWR_FLAG_SB: StandBy flag +* @retval : None +*/ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c new file mode 100644 index 0000000000..1e9b7f8947 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_rcc.c @@ -0,0 +1,1305 @@ +/** +****************************************************************************** +* @file HAL_rcc.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the RCC firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_rcc.h" + +u32 TK499_SYS_CLK = 48000000; +u32 TK499_PLL_FACTOR = 0x00004; +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup RCC +* @brief RCC driver modules +* @{ +*/ + +/** @defgroup RCC_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Defines +* @{ +*/ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) +#define USBPRE_BitNumber 0x16 +#define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00400000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* Typical Value of the HSI in Hz */ +#define HSI_Value ((uint32_t)8000000) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ +#define HSEStartUp_TimeOut ((uint16_t)0x0500) +#endif + +/** +* @} +*/ + +/** @defgroup RCC_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Variables +* @{ +*/ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** +* @} +*/ + +/** @defgroup RCC_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup RCC_Private_Functions +* @{ +*/ +void SystemClk_HSEInit(uint32_t PLL_DN) +{ + RCC_DeInit(); + //HSE on + //CR¼Ä´æÆ÷BIT16루HSEON룩ÖÃ1£¬×÷ÓÃÊÇÁ¬½ÓÍⲿʱÖÓHSE×÷ΪϵͳʱÖÓ + RCC_HSEConfig(RCC_HSE_ON); + + while(1) + { + if(RCC_WaitForHSEStartUp()!=0) + { + break; + } + } + RCC_PLLCmd(DISABLE); + RCC_PLLConfig(RCC_PLLSource_HSE_Div1,PLL_DN); + RCC_PLLCmd(ENABLE); + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);//Ñ¡ÔñÍⲿʱÖÓ×÷ΪϵͳʱÖÓ +} +/** +* @brief Resets the RCC clock configuration to the default reset state. +* @param None +* @retval : None +*/ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FF0000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** +* @brief Configures the External High Speed oscillator (HSE). +* HSE can not be stopped if it is used directly or through the +* PLL as system clock. +* @param RCC_HSE: specifies the new state of the HSE. +* This parameter can be one of the following values: +* @arg RCC_HSE_OFF: HSE oscillator OFF +* @arg RCC_HSE_ON: HSE oscillator ON +* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external +* clock +* @retval : None +*/ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** +* @brief Waits for HSE start-up. +* @param None +* @retval : An ErrorStatus enumuration value: +* - SUCCESS: HSE oscillator is stable and ready to use +* - ERROR: HSE oscillator not yet ready +*/ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut)); + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** +* @brief Adjusts the Internal High Speed oscillator (HSI) calibration +* value. +* @param HSICalibrationValue: specifies the calibration trimming value. +* This parameter must be a number between 0 and 0x1F. +* @retval : None +*/ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** +* @brief Enables or disables the Internal High Speed oscillator (HSI). +* HSI can not be stopped if it is used directly or through the +* PLL as system clock. +* @param NewState: new state of the HSI. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState==ENABLE) + { + RCC->CR |= 0x01; + } + else + { + RCC->CR &= 0xfffffffe; + } +} +/** +* @brief Configures the PLL clock source and DM DN factor. +* This function must be used only when the PLL is disabled. +* @param RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* @param RCC_PLLDN: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[31:26] +* @param RCC_PLLDM: specifies the PLL Divsior factor. +* This parameter can be RCC_Divsior_x where x:[22:20] +* @retval : None +*/ +void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN,uint32_t RCC_PLLDP, uint32_t RCC_PLLDM) +{ + uint32_t tmpreg0 = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + if(RCC_PLLSource == 0) + { + tmpreg0 &= ~(1<<22); + } + else + { + TK499_PLL_FACTOR |= 0x10000; + tmpreg0 |= (1<<22); + } + + RCC_PLLDN &= 0x7f; + RCC_PLLDP &= 0x3; + RCC_PLLDM &= 0xf; + /* Set the PLL configuration bits */ + tmpreg0 |= (u32)((u32)(RCC_PLLDN<<6))|((u32)(RCC_PLLDP<<4))|((u32)RCC_PLLDM); + + RCC->PLLCFGR = tmpreg0; +// RCC->PLLCFGR = 0x4004d1; +} + + +/** +* @brief Configures the PLL clock source and multiplication factor. +* This function must be used only when the PLL is disabled. +* @param RCC_PLLSource: specifies the PLL entry clock source. +* This parameter can be one of the following values: +* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided +* by 2 selected as PLL clock entry +* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected +* as PLL clock entry +* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided +* by 2 selected as PLL clock entry +* @param RCC_PLLMul: specifies the PLL multiplication factor. +* This parameter can be RCC_PLLMul_x where x:[31:26][22:20] +* @retval : None +*/ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource; + /* Store the new value */ + RCC->CFGR = tmpreg; + + if(RCC_PLLMul==RCC_PLLMul_2) + { + TK499_PLL_FACTOR = 2; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000001, 0x00000000,0x00000000); //Frclk*8/4 + } + if(RCC_PLLMul==RCC_PLLMul_3) + { + TK499_PLL_FACTOR = 3; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000002, 0x00000000,0x00000000);//Frclk*6/2 + } + if(RCC_PLLMul==RCC_PLLMul_4) + { + TK499_PLL_FACTOR = 4; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000003, 0x00000000,0x00000000);//Frclk*8/2 + } + if(RCC_PLLMul==RCC_PLLMul_5) + { + TK499_PLL_FACTOR = 5; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001,0x00000001);//Frclk*10/2 + } + if(RCC_PLLMul==RCC_PLLMul_6) + { + TK499_PLL_FACTOR = 6; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000000,0x00000000);//Frclk*12/2 + } + if(RCC_PLLMul==RCC_PLLMul_7) + { + TK499_PLL_FACTOR = 7; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000006, 0x00000000,0x00000000);//Frclk*14/2 + } + if(RCC_PLLMul==RCC_PLLMul_8) + { + TK499_PLL_FACTOR = 8; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000000,0x00000000);//Frclk*16/2 + } + if(RCC_PLLMul==RCC_PLLMul_9) + { + TK499_PLL_FACTOR = 9; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000008, 0x00000000,0x00000000);//Frclk*18/2 + } + if(RCC_PLLMul==RCC_PLLMul_10) + { + TK499_PLL_FACTOR = 10; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000000,0x00000000);//Frclk*20/2 + } + if(RCC_PLLMul==RCC_PLLMul_11) + { + TK499_PLL_FACTOR = 11; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000a, 0x00000000,0x00000000);//Frclk*22/2 + } + if(RCC_PLLMul==RCC_PLLMul_12) + { + TK499_PLL_FACTOR = 12; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000b, 0x00000000,0x00000000);//Frclk*24/2 + } + if(RCC_PLLMul==RCC_PLLMul_13) + { + TK499_PLL_FACTOR = 13; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000c, 0x00000000,0x00000000);//Frclk*26/2 + } + if(RCC_PLLMul==RCC_PLLMul_14) + { + TK499_PLL_FACTOR = 14; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000d, 0x00000000,0x00000000);//Frclk*28/2 + } + if(RCC_PLLMul==RCC_PLLMul_15) + { + TK499_PLL_FACTOR = 15; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000e, 0x00000000,0x00000000);//Frclk*30/2 + } + if(RCC_PLLMul==RCC_PLLMul_16) + { + TK499_PLL_FACTOR = 16; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000f, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_17) + { + TK499_PLL_FACTOR = 17; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000010, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_18) + { + TK499_PLL_FACTOR = 18; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_19) + { + TK499_PLL_FACTOR = 19; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000012, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_20) + { + TK499_PLL_FACTOR = 20; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_21) + { + TK499_PLL_FACTOR = 21; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000014, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_22) + { + TK499_PLL_FACTOR = 22; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_23) + { + TK499_PLL_FACTOR = 23; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000016, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_24) + { + TK499_PLL_FACTOR = 24; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_25) + { + TK499_PLL_FACTOR = 25; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000018, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_26) + { + TK499_PLL_FACTOR = 26; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_27) + { + TK499_PLL_FACTOR = 27; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000020, 0x00000000,0x00000000);//Frclk*32/2 + } + if(RCC_PLLMul==RCC_PLLMul_28) + { + TK499_PLL_FACTOR = 28; + RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000021, 0x00000000,0x00000000);//Frclk*32/2 + } +} + + +/** +* @brief Enables or disables the PLL. +* The PLL can not be disabled if it is used as system clock. +* @param NewState: new state of the PLL. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= 0x01000000; + } + else + { + RCC->CR &= 0xfeffffff; + } +} + +/** +* @brief Configures the system clock (SYSCLK). +* @param RCC_SYSCLKSource: specifies the clock source used as system +* clock. This parameter can be one of the following values: +* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock +* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock +* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock +* @retval : None +*/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; + if(RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK) + { + if(TK499_PLL_FACTOR&0x10000)//hse as pll src + { + TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSE_VALUE; + } + else + { + TK499_SYS_CLK = (TK499_PLL_FACTOR&0xff)*HSI_Value_Pll_ON; + } + } + else if(RCC_SYSCLKSource == RCC_SYSCLKSource_HSE) + { + TK499_SYS_CLK = HSE_VALUE; + } + else + { + TK499_SYS_CLK = HSI_Value_Pll_OFF; + } +} + +/** +* @brief Returns the clock source used as system clock. +* @param None +* @retval : The clock source used as system clock. The returned value can +* be one of the following: +* - 0x00: HSI/6 used as system clock +* - 0x04: HSE used as system clock +* - 0x08: PLL used as system clock +*/ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** +* @brief Configures the AHB clock (HCLK). +* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from +* the system clock (SYSCLK). +* This parameter can be one of the following values: +* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK +* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 +* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 +* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 +* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 +* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 +* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 +* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 +* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 +* @retval : None +*/ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the Low Speed APB clock (PCLK1). +* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from +* the AHB clock (HCLK). +* This parameter can be one of the following values: +* @arg RCC_HCLK_Div1: APB1 clock = HCLK +* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 +* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 +* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 +* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 +* @retval : None +*/ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the High Speed APB clock (PCLK2). +* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from +* the AHB clock (HCLK). +* This parameter can be one of the following values: +* @arg RCC_HCLK_Div1: APB2 clock = HCLK +* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 +* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 +* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 +* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 +* @retval : None +*/ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Enables or disables the specified RCC interrupts. +* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @param NewState: new state of the specified RCC interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ + + RCC->CIR |= ((uint32_t)RCC_IT)<<8; + } + else + { + /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ + + RCC->CIR &= ~((uint32_t)RCC_IT<<8); + } +} + +/** +* @brief Configures the USB clock (USBCLK). +* @param RCC_USBCLKSource: specifies the USB clock source. This clock is +* derived from the PLL output. +* This parameter can be one of the following values: +* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB +* clock source +* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source +* @retval : None +*/ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + RCC->CFGR |= RCC_USBCLKSource; +} + +/** +* @brief Configures the ADC clock (ADCCLK). +* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from +* the APB2 clock (PCLK2). +* This parameter can be one of the following values: +* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 +* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 +* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 +* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 +* @retval : None +*/ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** +* @brief Configures the External Low Speed oscillator (LSE). +* @param RCC_LSE: specifies the new state of the LSE. +* This parameter can be one of the following values: +* @arg RCC_LSE_OFF: LSE oscillator OFF +* @arg RCC_LSE_ON: LSE oscillator ON +* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external +* clock +* @retval : None +*/ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + RCC->BDCR &= ~((uint32_t)RCC_LSE_ON); + /* Reset LSEBYP bit */ + RCC->BDCR &= ~((uint32_t)RCC_LSE_ON); + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + RCC->BDCR |= RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + RCC->BDCR |= RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** +* @brief Enables or disables the Internal Low Speed oscillator (LSI). +* LSI can not be disabled if the IWDG is running. +* @param NewState: new state of the LSI. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CSR |= 0x00000001; + } + else + { + RCC->CSR &= 0xfffffffe; + } +} + +/** +* @brief Configures the RTC clock (RTCCLK). +* Once the RTC clock is selected it can’t be changed unless the +* Backup domain is reset. +* @param RCC_RTCCLKSource: specifies the RTC clock source. +* This parameter can be one of the following values: +* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock +* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock +* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 +* selected as RTC clock +* @retval : None +*/ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** +* @brief Enables or disables the RTC clock. +* This function must be used only after the RTC clock was +* selected using the RCC_RTCCLKConfig function. +* @param NewState: new state of the RTC clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= 0x00008000; + } + else + { + RCC->BDCR &= 0xffff7fff; + } +} +void getSystemClock(u32 *sysclk) +{ + u32 tempreg0 = RCC->CFGR; + u32 tempreg1; + u8 dn,dp,dm; + if((tempreg0 & 0xC) == 0x00) + { + *sysclk = 8000000; + } + else if((tempreg0 & 0xC) ==0x04) + { + *sysclk = 12000000; + } + else + { + tempreg1 = RCC->PLLCFGR; + dn = (tempreg1 >> 6) & 0x7F; + dn ++; + dp = (tempreg1 >> 4) & 0x3; + if(dp == 0) + dp = 1; + else if(dp == 1) + dp = 2; + else if(dp == 2) + dp = 4; + else if(dp == 3) + dp = 8; + dm = (tempreg1 >> 0) & 0xF; + dm++; + if(tempreg1 & (1 << 22)) + { + if(tempreg0 & (1 << 16)) + *sysclk = 6000000* dn/( dm * dp); + else + *sysclk = 12000000* dn/( dm * dp); + } + else + { + *sysclk = 12000000* dn/( dm * dp); + } + } +} + +/** +* @brief Returns the frequencies of different on chip clocks. +* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which +* will hold the clocks frequencies. +* @retval : None +*/ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, presc = 0; + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + + RCC_Clocks->SYSCLK_Frequency = TK499_SYS_CLK; + getSystemClock( & (RCC_Clocks->SYSCLK_Frequency )); + break; + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF; + break; + } + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** +* @brief Enables or disables the AHB peripheral clock. +* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. +* This parameter can be any combination of the following values: +* @arg RCC_AHBPeriph_DMA1 +* @arg RCC_AHBPeriph_DMA2 +* @arg RCC_AHBPeriph_SRAM +* @arg RCC_AHBPeriph_FLITF +* @arg RCC_AHBPeriph_CRC +* @arg RCC_AHBPeriph_FSMC +* @arg RCC_AHBPeriph_SDIO +* SRAM and FLITF clock can be disabled only during sleep mode. +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHBPeriph; + } + else + { + RCC->AHB1ENR &= ~RCC_AHBPeriph; + } +} + +/** +* @brief Enables or disables the High Speed APB (APB2) peripheral clock. +* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* @arg RCC_APB2Periph_SYSCFG, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, +* RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, +* RCC_APB2Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + + +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** +* @brief Enables or disables the Low Speed APB (APB1) peripheral clock. +* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its +* clock. +* This parameter can be any combination of the following values: +* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4, +* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** +* @brief Forces or releases High Speed APB (APB2) peripheral reset. +* @param RCC_APB2Periph: specifies the APB2 peripheral to reset. +* This parameter can be any combination of the following values: +* @arg RCC_APB2Periph_AFIO, RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, +* RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_APB2Periph_ADC1, +* RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, +* RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, RCC_APB2Periph_ADC3, +* RCC_APB2Periph_ALL +* @param NewState: new state of the specified peripheral reset. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** +* @brief Forces or releases Low Speed APB (APB1) peripheral reset. +* @param RCC_APB1Periph: specifies the APB1 peripheral to reset. +* This parameter can be any combination of the following values: +* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, +* RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, +* RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, +* RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4, +* RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, +* RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, +* RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL +* @param NewState: new state of the specified peripheral clock. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + + + +/** +* @brief Enables or disables the Clock Security System. +* @param NewState: new state of the Clock Security System.. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + // *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; + if(NewState==ENABLE) + { + RCC->CR |= (uint32_t)0x00080000; + } + else + { + RCC->CR &= (uint32_t)0xfff7ffff; + } +} + +/** +* @brief Selects the clock source to output on MCO pin. +* @param RCC_MCO: specifies the clock source to output. +* This parameter can be one of the following values: +* @arg RCC_MCO_NoClock: No clock selected +* @arg RCC_MCO_SYSCLK: System clock selected +* @arg RCC_MCO_HSI: HSI oscillator clock selected +* @arg RCC_MCO_HSE: HSE oscillator clock selected +* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected +* @retval : None +*/ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + /* Perform Byte access to MCO[2:0] bits to select the MCO source */ + + RCC->CFGR |= (RCC_MCO<<24); +} + +/** +* @brief Checks whether the specified RCC flag is set or not. +* @param RCC_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready +* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready +* @arg RCC_FLAG_PLLRDY: PLL clock ready +* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready +* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready +* @arg RCC_FLAG_PINRST: Pin reset +* @arg RCC_FLAG_PORRST: POR/PDR reset +* @arg RCC_FLAG_SFTRST: Software reset +* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset +* @arg RCC_FLAG_WWDGRST: Window Watchdog reset +* @arg RCC_FLAG_LPWRRST: Low Power reset +* @retval : The new state of RCC_FLAG (SET or RESET). +*/ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** +* @brief Clears the RCC reset flags. +* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, +* RCC_FLAG_LPWRRST +* @param None +* @retval : None +*/ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** +* @brief Checks whether the specified RCC interrupt has occurred or not. +* @param RCC_IT: specifies the RCC interrupt source to check. +* This parameter can be one of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @arg RCC_IT_CSS: Clock Security System interrupt +* @retval : The new state of RCC_IT (SET or RESET). +*/ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the RCC_IT status */ + return bitstatus; +} + +/** +* @brief Clears the RCC’s interrupt pending bits. +* @param RCC_IT: specifies the interrupt pending bit to clear. +* This parameter can be any combination of the following values: +* @arg RCC_IT_LSIRDY: LSI ready interrupt +* @arg RCC_IT_LSERDY: LSE ready interrupt +* @arg RCC_IT_HSIRDY: HSI ready interrupt +* @arg RCC_IT_HSERDY: HSE ready interrupt +* @arg RCC_IT_PLLRDY: PLL ready interrupt +* @arg RCC_IT_CSS: Clock Security System interrupt +* @retval : None +*/ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + + RCC->CIR |= (uint32_t)RCC_IT<<16; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_spi.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_spi.c new file mode 100644 index 0000000000..14381c040d --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_spi.c @@ -0,0 +1,616 @@ +/** +****************************************************************************** +* @file HAL_spi.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the SPI firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_spi.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup SPI +* @brief SPI driver modules +* @{ +*/ + +/** @defgroup SPI_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup SPI_Private_Defines +* @{ +*/ + + + +/* SPI SPIENE mask */ +#define GCTL_SPIEN_Set ((uint16_t)0x0001) +#define GCTL_SPIEN_Reset ((uint16_t)0xFFFE) +/* SPI registers Masks */ +#define GCTL_CLEAR_Mask ((uint16_t)0xF000) +#define CCTL_CLEAR_Mask ((uint16_t)0xFFC0) +#define SPBRG_CLEAR_Mask ((uint16_t)0x0000) +#define SPI_DataSize_Mask ((uint16_t)0xFCFF) +/** +* @} +*/ + +/** @defgroup SPI_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the SPIx peripheral registers to their default +* reset values . +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @retval : None +*/ +void SPI_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + switch (*(uint32_t*)&SPIx) + { + case SPI1_BASE: + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + break; + default: + break; + } +} + +/** +* @brief Initializes the SPIx peripheral according to the specified +* parameters in the SPI_InitStruct. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that +* contains the configuration information for the specified +* SPI peripheral. +* @retval : None +*/ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint32_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_DATAWIDRH(SPI_InitStruct->SPI_DataWidth)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + /*---------------------------- SPIx GCTL Configuration ------------------------*/ + /* Get the SPIx GCTL value */ + tmpreg = SPIx->GCTL; + /* Clear csn_sel, dmamode, txtlf, rxtlf,data_sel, rxen, txen, mm, int_en, spien bits */ + tmpreg &= GCTL_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set dat_sel bits according to SPI_DataSize value */ + /* Set csn and csn_sel bits according to SPI_NSS value */ + /* Set mm bit according to SPI_Mode value */ + tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_Mode ); + /* Write to SPIx GCTL */ +// if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000; + SPIx->GCTL = tmpreg; + /*---------------------------- SPIx CCTL Configuration ------------------------*/ + tmpreg = SPIx->CCTL; + /* Clear spilen, lsbfe, CPOL, CPHA bits */ + tmpreg &= CCTL_CLEAR_Mask; + /* Set Spilen bit according to SPI_DataWidth value */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint16_t) SPI_InitStruct->SPI_DataWidth | SPI_InitStruct->SPI_FirstBit | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA ); + + /* Write to SPIx CCTL */ + SPIx->CCTL = tmpreg; + + /*---------------------------- SPIx SPBRG Configuration ------------------------*/ + tmpreg = SPIx->SPBRG; + /* Clear spbrg bits */ + tmpreg &= (uint16_t)SPBRG_CLEAR_Mask; + /* Set BR bits according to SPI_BaudRatePrescaler value */ + tmpreg |= (uint16_t) SPI_InitStruct->SPI_BaudRatePrescaler; + /* Write to SPIx SPBRG */ + SPIx->SPBRG = tmpreg; + +} + +/** +* @brief Fills each SPI_InitStruct member with its default value. +* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPILEN member */ + SPI_InitStruct->SPI_DataWidth = SPI_DataWidth_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Soft; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + +} + + +/** +* @brief Enables or disables the specified SPI peripheral. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param NewState: new state of the SPIx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->GCTL |= GCTL_SPIEN_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->GCTL &= GCTL_SPIEN_Reset; + } +} + + +/** +* @brief Enables or disables the specified SPIinterrupts. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt source to be +* enabled or disabled. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Tx buffer empty interrupt mask +* @arg SPI_IT_RX: Rx buffer interrupt mask +* @arg SPI_IT_UNDERRUN: under Error interrupt mask in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt mask +* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask +* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask +* @param NewState: new state of the specified SPI interrupt. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_CONFIG_IT(SPI_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI Global interrupt */ + SPIx->GCTL |= SPI_INT_EN; + /* Enable the selected SPI interrupt */ + SPIx->INTEN |= SPI_IT; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->INTEN &= (uint16_t)~SPI_IT; + /* Disable the selected SPI Global interrupt */ + SPIx->GCTL &= (uint16_t)~SPI_INT_EN; + } + +} + +/** +* @brief Enables or disables the SPIx DMA interface. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_DMAReq: specifies the SPI DMA transfer request +* to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg SPI_DMAReq_EN: DMA transfer request enable +* @param NewState: new state of the selected SPI DMA transfer +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->GCTL |= SPI_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->GCTL &= (uint32_t)~SPI_DMAReq; + } +} + +/** +* @brief configure tn Fifo trigger level bit. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_FifoTriggerValue: specifies the Fifo trigger level +* This parameter can be any combination of the following values: +* SPI_TXTLF : SPI TX FIFO Trigger value set +* SPI_RXTLF : SPI RX FIFO Trigger value set +* @param NewState: new state of the selected SPI DMA transfer +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_FIFOTRIGGER(SPI_FifoTriggerValue)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->GCTL |= SPI_FifoTriggerValue; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->GCTL &= (uint32_t)~SPI_FifoTriggerValue; + } +} + +/** +* @brief Transmits a Data through the SPIx peripheral. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param Data : Data to be transmitted.. +* @retval : None +*/ +void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the TXREG register the data to be sent */ + SPIx->TXREG = Data; +} + +/** +* @brief Returns the most recent received data by the SPIx peripheral. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @retval : The value of the received data. +*/ +uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the RXREG register */ + return SPIx->RXREG; +} + +/** +* @brief Slave chip csn single by selected +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_CSInternalSelected: specifies the SPI CS internal selected. +* This parameter can be one of the following values: +* @arg SPI_CS_BIT0: cs bit 0 selected +* @arg SPI_CS_BIT1: cs bit 1 selected +* @arg SPI_CS_BIT2: cs bit 2 selected +* @arg SPI_CS_BIT3: cs bit 3 selected +* @arg SPI_CS_BIT4: cs bit 4 selected +* @arg SPI_CS_BIT5: cs bit 5 selected +* @arg SPI_CS_BIT6: cs bit 6 selected +* @arg SPI_CS_BIT7: cs bit 7 selected +* @param NewState: new state of the selected SPI CS pin +* request. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CS(SPI_CSInternalSelected)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + if (NewState != DISABLE) + { + /* selected cs pin according SCSR Value */ + SPIx->SCSR &= SPI_CSInternalSelected; + } + else + { + /* release cs pin according SCSR Value*/ + SPIx->SCSR |= ~SPI_CSInternalSelected; + } +} + +/** +* @brief Configures the data size for the selected SPI. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_DataSize: specifies the SPI data size. +* This parameter can be one of the following values: +* @arg SPI_DataSize_32b: Set data frame format to 32bit +* @arg SPI_DataSize_16b: Set data frame format to 16bit +* @arg SPI_DataSize_8b: Set data frame format to 8bit +* @retval : None +*/ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear data_sel bit */ + SPIx->GCTL &= SPI_DataSize_Mask; + /* Set new data_sel bit value */ + SPIx->GCTL |= SPI_DataSize; +} + + + +/** +* @brief Selects the data transfer direction in bi-directional mode +* for the specified SPI. +* @param SPIx: where x can be 0, 1 to select the SPI peripheral. +* @param SPI_Direction: specifies the data transfer direction in +* bi-directional mode. +* This parameter can be one of the following values: +* @arg SPI_Direction_Tx: Selects Tx transmission direction +* @arg SPI_Direction_Rx: Selects Rx receive direction +@arg SPI_Disable_Tx: Selects Rx receive direction +@arg SPI_Disable_Rx: Selects Rx receive direction +* @retval : None +*/ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + + /* Set the Tx only mode */ + if(SPI_Direction==SPI_Direction_Tx) + { + SPIx->GCTL |= SPI_Direction_Tx; + } + /* Set the Rx only mode */ + if(SPI_Direction==SPI_Direction_Rx) + { + SPIx->GCTL |= SPI_Direction_Rx; + } + /* Disable the Tx only mode */ + if(SPI_Direction==SPI_Disable_Tx) + { + SPIx->GCTL &= SPI_Disable_Tx; + } + /* Disable the Rx only mode */ + if(SPI_Direction==SPI_Disable_Rx) + { + SPIx->GCTL &= SPI_Disable_Rx; + } +} + +/** +* @brief Checks whether the specified SPI flag is set or not. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_FLAG: specifies the SPI flag to check. +* This parameter can be one of the following values: +* @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag +* @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag +* @retval : The new state of SPI_FLAG (SET or RESET). +*/ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_FLAG(SPI_FLAG)); + /* Check the status of the specified SPI flag */ + if ((SPIx->CSTAT & SPI_FLAG) != (uint16_t)RESET) + { + /* SPI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_FLAG status */ + return bitstatus; +} + +/** +* @brief Checks whether the specified SPI interrupt has occurred or not. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt source to check. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Tx buffer empty interrupt +* @arg SPI_IT_RX: Rx buffer interrupt +* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +* @arg SPI_IT_RXFULL: Rx buffer full interrupt +* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +* @retval : The new state of SPI_IT (SET or RESET). +*/ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_IT(SPI_IT)); + /* Check the status of the specified SPI interrupt */ + if ((SPIx->INTSTAT & SPI_IT) != (uint16_t)RESET) + { + /* SPI_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_IT status */ + return bitstatus; +} + +/** +* @brief Clears the SPIx Error interrupt pending bit. +* @param SPIx: where x can be : +* 0, 1 in SPI mode +* @param SPI_IT: specifies the SPI interrupt pending bit to clear. +* @arg SPI_IT_TX: Tx buffer empty interrupt +* @arg SPI_IT_RX: Rx buffer interrupt +* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode +* @arg SPI_IT_RXOVER: RX OVER Error interrupt +* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt +* @arg SPI_IT_RXFULL: Rx buffer full interrupt +* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt +* This function clears only ERR intetrrupt pending bit. +* @retval : None +*/ +void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + + /* Clear the selected SPI IT INTERRUPT */ + SPIx->INTCLR |= (uint16_t)SPI_IT; +} + + +/** +* @brief SPI Hole a count Received bytes in next receive process. +* @param SPIx: where x can be 0, 1 in SPI mode +* @param Number: specifies the SPI receive Number. +* This parament can be 1-65535. +* This function can use only in SPI master single receive mode. +* @retval : None +*/ +void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + /*set the received bytes in next receive process */ + SPIx->RXDNR = Number; +} + +/** +* @brief slave mode tx data transmit phase adjust set. +* @param SPIx: where x can be 0, 1 in SPI mode +* @param AdjustValue: specifies the SPI receive Number. +* This parament can be : +* SPI_SlaveAdjust_FAST: fast speed use +* SPI_SlaveAdjust_LOW: low speed use +* This function can use only in SPI master single receive mode. +* @retval : None +*/ +void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_SlaveAdjust(AdjustValue)); + /*set the AdjustValue according to txedge bit of CCTL register*/ + SPIx->CCTL |= AdjustValue; +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_syscfg.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_syscfg.c new file mode 100644 index 0000000000..53f1046851 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_syscfg.c @@ -0,0 +1,199 @@ +/** +****************************************************************************** +* @file HAL_syscfg.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides firmware functions to manage the following +* functionalities of the SYSCFG peripheral: +* + Remapping the memory mapped at 0x00000000 +* + Remapping the DMA channels +* + Enabling I2C fast mode plus driving capability for I2C pins +* + Configuring the EXTI lines connection to the GPIO port +* + Configuring the CFGR2 features (Connecting some internal signal +* to the break input of TIM1) +* +* @verbatim +=============================================================================== +##### How to use this driver ##### +=============================================================================== +[..] +The SYSCFG registers can be accessed only when the SYSCFG +interface APB clock is enabled. +To enable SYSCFG APB clock use: +RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE). +* @endverbatim +* +****************************************************************************** +* @attention +* +*

© COPYRIGHT 2016 HOLOCENE

+****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_syscfg.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup SYSCFG +* @brief SYSCFG driver modules +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Functions +* @{ +*/ + +/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions +* @brief SYSCFG Initialization and Configuration functions +* +@verbatim +=============================================================================== +##### SYSCFG Initialization and Configuration functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Deinitializes the SYSCFG registers to their default reset values. +* @param None +* @retval None +* @note MEM_MODE bits are not affected by APB reset. +* @note MEM_MODE bits took the value from the user option bytes. +* @note CFGR2 register is not affected by APB reset. +* @note CLABBB configuration bits are locked when set. +* @note To unlock the configuration, perform a system reset. +*/ +void SYSCFG_DeInit(void) +{ + /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ + SYSCFG->CFGR &= SYSCFG_CFGR_MEM_MODE; + /* Set EXTICRx registers to reset value */ + SYSCFG->EXTICR[0] = 0; + SYSCFG->EXTICR[1] = 0; + SYSCFG->EXTICR[2] = 0; + SYSCFG->EXTICR[3] = 0; + +} + +/** +* @brief Configures the memory mapping at address 0x00000000. +* @param SYSCFG_MemoryRemap: selects the memory remapping. +* This parameter can be one of the following values: +* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 +* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 +* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 +* @retval None +*/ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) +{ + uint32_t tmpctrl = 0; + + /* Check the parameter */ + assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); + + /* Get CFGR1 register value */ + tmpctrl = SYSCFG->CFGR; + + /* Clear MEM_MODE bits */ + tmpctrl &= (uint32_t) (~SYSCFG_CFGR_MEM_MODE); + + /* Set the new MEM_MODE bits value */ + tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; + + /* Set CFGR1 register with the new memory remap configuration */ + SYSCFG->CFGR = tmpctrl; +} + +/** +* @brief Configure the DMA channels remapping. +* @param SYSCFG_DMARemap: selects the DMA channels remap. +* This parameter can be one of the following values: +* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 +* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 +* @arg SYSCFG_DMARemap_UART1Rx: Remap UART1 Rx DMA requests from channel3 to channel5 +* @arg SYSCFG_DMARemap_UART1Tx: Remap UART1 Tx DMA requests from channel2 to channel4 +* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 +* @param NewState: new state of the DMA channel remapping. +* This parameter can be: ENABLE or DISABLE. +* @note When enabled, DMA channel of the selected peripheral is remapped +* @note When disabled, Default DMA channel is mapped to the selected peripheral +* @note By default TIM17 DMA requests is mapped to channel 1, +* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap +* TIM17 DMA requests to channel 2 and use +* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map +* TIM17 DMA requests to channel 1 (default mapping) +* @retval None +*/ +void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Remap the DMA channel */ + SYSCFG->CFGR |= (uint32_t)SYSCFG_DMARemap; + } + else + { + /* use the default DMA channel mapping */ + SYSCFG->CFGR &= (uint32_t)(~SYSCFG_DMARemap); + } +} + + + +/** +* @brief Selects the GPIO pin used as EXTI Line. +* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source +* for EXTI lines where x can be (A, B, C, D, E or F). +* @param EXTI_PinSourcex: specifies the EXTI line to be configured. +* @note This parameter can be EXTI_PinSourcex where x can be: +* For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD. +* @retval None +*/ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_tim.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_tim.c new file mode 100644 index 0000000000..639d0e7fa1 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_tim.c @@ -0,0 +1,3306 @@ +/** +****************************************************************************** +* @file HAL_tim.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides firmware functions to manage the following +* functionalities of the TIM peripheral: +* + TimeBase management +* + Output Compare management +* + Input Capture management +* + Interrupts, DMA and flags management +* + Clocks management +* + Synchronization management +* + Specific interface management +* + Specific remapping management +* +* @verbatim + +=============================================================================== +##### How to use this driver ##### +=============================================================================== +[..] This driver provides functions to configure and program the TIM +of all M0 series devices These functions are split in 8 groups: +(#) TIM TimeBase management: this group includes all needed functions +to configure the TM Timebase unit: +(++) Set/Get Prescaler. +(++) Set/Get Autoreload. +(++) Counter modes configuration. +(++) Set Clock division. +(++) Select the One Pulse mode. +(++) Update Request Configuration. +(++) Update Disable Configuration. +(++) Auto-Preload Configuration. +(++) Enable/Disable the counter. + +(#) TIM Output Compare management: this group includes all needed +functions to configure the Capture/Compare unit used in Output +compare mode: +(++) Configure each channel, independently, in Output Compare mode. +(++) Select the output compare modes. +(++) Select the Polarities of each channel. +(++) Set/Get the Capture/Compare register values. +(++) Select the Output Compare Fast mode. +(++) Select the Output Compare Forced mode. +(++) Output Compare-Preload Configuration. +(++) Clear Output Compare Reference. +(++) Select the OCREF Clear signal. +(++) Enable/Disable the Capture/Compare Channels. + +(#) TIM Input Capture management: this group includes all needed +functions to configure the Capture/Compare unit used in +Input Capture mode: +(++) Configure each channel in input capture mode. +(++) Configure Channel1/2 in PWM Input mode. +(++) Set the Input Capture Prescaler. +(++) Get the Capture/Compare values. + +(#) Advanced-control timers (TIM1) specific features +(++) Configures the Break input, dead time, Lock level, the OSSI, +the OSSR State and the AOE(automatic output enable) +(++) Enable/Disable the TIM peripheral Main Outputs +(++) Select the Commutation event +(++) Set/Reset the Capture Compare Preload Control bit + +(#) TIM interrupts, DMA and flags management. +(++) Enable/Disable interrupt sources. +(++) Get flags status. +(++) Clear flags/ Pending bits. +(++) Enable/Disable DMA requests. +(++) Configure DMA burst mode. +(++) Select CaptureCompare DMA request. + +(#) TIM clocks management: this group includes all needed functions +to configure the clock controller unit: +(++) Select internal/External clock. +(++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. + +(#) TIM synchronization management: this group includes all needed. +functions to configure the Synchronization unit: +(++) Select Input Trigger. +(++) Select Output Trigger. +(++) Select Master Slave Mode. +(++) ETR Configuration when used as external trigger. + +(#) TIM specific interface management, this group includes all +needed functions to use the specific TIM interface: +(++) Encoder Interface Configuration. +(++) Select Hall Sensor. + +(#) TIM specific remapping management includes the Remapping +configuration of specific timers + +@endverbatim +* +****************************************************************************** +* @attention +* +*

© COPYRIGHT 2016 HOLOCENE

+* +****************************************************************************** +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_tim.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup TIM +* @brief TIM driver modules +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_MASK ((uint16_t)0x00FF) +#define CCMR_OFFSET ((uint16_t)0x0018) +#define CCER_CCE_SET ((uint16_t)0x0001) +#define CCER_CCNE_SET ((uint16_t)0x0004) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup TIM_Private_Functions +* @{ +*/ + +/** @defgroup TIM_Group1 TimeBase management functions +* @brief TimeBase management functions +* +@verbatim +=============================================================================== +##### TimeBase management functions ##### +=============================================================================== + +*** TIM Driver: how to use it in Timing(Time base) Mode *** +=============================================================================== +[..] To use the Timer in Timing(Time base) mode, the following steps are +mandatory: +(#) Enable TIM clock using +RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. +(#) Fill the TIM_TimeBaseInitStruct with the desired parameters. +(#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure +the Time Base unit with the corresponding configuration. +(#) Enable the NVIC if you need to generate the update interrupt. +(#) Enable the corresponding interrupt using the function +TIM_ITConfig(TIMx, TIM_IT_Update). +(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. +[..] +(@) All other functions can be used seperatly to modify, if needed, +a specific feature of the Timer. + +@endverbatim +* @{ +*/ + +/** +* @brief Deinitializes the TIMx peripheral registers to their default reset values. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + + + +* @retval None +* +*/ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + + else if (TIMx == TIM6) + { + RCC_APB2PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else + { + if (TIMx == TIM7) + { + RCC_APB2PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + } + +} + +/** +* @brief Initializes the TIMx Time Base Unit peripheral according to +* the specified parameters in the TIM_TimeBaseInitStruct. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef +* structure that contains the configuration information for +* the specified TIM peripheral. +* @retval None +*/ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1)|| (TIMx == TIM6) || (TIMx == TIM7)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** +* @brief Fills each TIM_TimeBaseInitStruct member with its default value. +* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure +* which will be initialized. +* @retval None +*/ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** +* @brief Configures the TIMx Prescaler. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + + + +* @param Prescaler: specifies the Prescaler Register value +* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode +* This parameter can be one of the following values: +* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. +* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. +* @retval None +*/ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** +* @brief Specifies the TIMx Counter Mode to be used. +* @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. + +* @param TIM_CounterMode: specifies the Counter Mode to be used +* This parameter can be one of the following values: +* @arg TIM_CounterMode_Up: TIM Up Counting Mode +* @arg TIM_CounterMode_Down: TIM Down Counting Mode +* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 +* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 +* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 +* @retval None +*/ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** +* @brief Sets the TIMx Counter Register value +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param Counter: specifies the Counter register new value. +* @retval None +*/ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** +* @brief Sets the TIMx Autoreload Register value +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. + + + +* @param Autoreload: specifies the Autoreload register new value. +* @retval None +*/ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** +* @brief Gets the TIMx Counter value. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @retval Counter Register value. +*/ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** +* @brief Gets the TIMx Prescaler value. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @retval Prescaler Register value. +*/ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** +* @brief Enables or Disables the TIMx Update event. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param NewState: new state of the TIMx UDIS bit +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** +* @brief Configures the TIMx Update Request Interrupt source. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param TIM_UpdateSource: specifies the Update source. +* This parameter can be one of the following values: +* @arg TIM_UpdateSource_Regular: Source of update is the counter +* overflow/underflow or the setting of UG bit, or an update +* generation through the slave mode controller. +* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. +* @retval None +*/ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** +* @brief Enables or disables TIMx peripheral Preload register on ARR. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param NewState: new state of the TIMx peripheral Preload register +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** +* @brief Selects the TIMx's One Pulse Mode. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM +* peripheral. + + + +* @param TIM_OPMode: specifies the OPM Mode to be used. +* This parameter can be one of the following values: +* @arg TIM_OPMode_Single +* @arg TIM_OPMode_Repetitive +* @retval None +*/ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** +* @brief Sets the TIMx Clock Division value. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + +* @param TIM_CKD: specifies the clock division value. +* This parameter can be one of the following value: +* @arg TIM_CKD_DIV1: TDTS = Tck_tim +* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim +* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim +* @retval None +*/ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** +* @brief Enables or disables the specified TIM peripheral. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx +* peripheral. + + + +* @param NewState: new state of the TIMx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** +* @} +*/ + +/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features +* @brief Advanced-control timers (TIM1) specific features +* +@verbatim +=============================================================================== +##### Advanced-control timers (TIM1) specific features ##### +=============================================================================== + +=================================================================== +*** TIM Driver: how to use the Break feature *** +=================================================================== +[..] After configuring the Timer channel(s) in the appropriate Output Compare mode: + +(#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer +Break Polarity, dead time, Lock level, the OSSI/OSSR State and the +AOE(automatic output enable). + +(#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer + +(#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) + +(#) Once the break even occurs, the Timer's output signals are put in reset +state or in a known state (according to the configuration made in +TIM_BDTRConfig() function). + +@endverbatim +* @{ +*/ +/** +* @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State +* and the AOE(automatic output enable). +* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM +* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that +* contains the BDTR Register configuration information for the TIM peripheral. +* @retval None +*/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** +* @brief Fills each TIM_BDTRInitStruct member with its default value. +* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which +* will be initialized. +* @retval None +*/ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** +* @brief Enables or disables the TIM peripheral Main Outputs. +* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. +* @param NewState: new state of the TIM peripheral Main Outputs. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** +* @} +*/ + +/** @defgroup TIM_Group3 Output Compare management functions +* @brief Output Compare management functions +* +@verbatim +=============================================================================== +##### Output Compare management functions ##### +=============================================================================== +*** TIM Driver: how to use it in Output Compare Mode *** +=============================================================================== +[..] To use the Timer in Output Compare mode, the following steps are mandatory: +(#) Enable TIM clock using +RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. +(#) Configure the TIM pins by configuring the corresponding GPIO pins +(#) Configure the Time base unit as described in the first part of this +driver, if needed, else the Timer will run with the default +configuration: +(++) Autoreload value = 0xFFFF. +(++) Prescaler value = 0x0000. +(++) Counter mode = Up counting. +(++) Clock Division = TIM_CKD_DIV1. +(#) Fill the TIM_OCInitStruct with the desired parameters including: +(++) The TIM Output Compare mode: TIM_OCMode. +(++) TIM Output State: TIM_OutputState. +(++) TIM Pulse value: TIM_Pulse. +(++) TIM Output Compare Polarity : TIM_OCPolarity. +(#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired +channel with the corresponding configuration. +(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. +[..] +(@) All other functions can be used separately to modify, if needed, +a specific feature of the Timer. +(@) In case of PWM mode, this function is mandatory: +TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). +(@) If the corresponding interrupt or DMA request are needed, the user should: +(#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). +(#@) Enable the corresponding interrupt (or DMA request) using the function +TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). + +@endverbatim +* @{ +*/ + +/** +* @brief Initializes the TIMx Channel1 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM6) || (TIMx == TIM7)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel2 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2, 3 to select the TIM peripheral. + +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1)) + { + /* Check the parameters */ + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + + if (TIMx == TIM1) + { + /* Check the parameters */ + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel3 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Initializes the TIMx Channel4 according to the specified +* parameters in the TIM_OCInitStruct. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Fills each TIM_OCInitStruct member with its default value. +* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will +* be initialized. +* @retval None +*/ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** +* @brief Selects the TIM Output Compare Mode. +* @note This function disables the selected channel before changing the Output +* Compare Mode. +* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_Channel: specifies the TIM Channel +* This parameter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @arg TIM_Channel_4: TIM Channel 4 +* @param TIM_OCMode: specifies the TIM Output Compare Mode. +* This parameter can be one of the following values: +* @arg TIM_OCMode_Timing +* @arg TIM_OCMode_Active +* @arg TIM_OCMode_Toggle +* @arg TIM_OCMode_PWM1 +* @arg TIM_OCMode_PWM2 +* @arg TIM_ForcedAction_Active +* @arg TIM_ForcedAction_InActive +* @retval None +*/ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** +* @brief Sets the TIMx Capture Compare1 Register value +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param Compare1: specifies the Capture Compare1 register new value. +* @retval None +*/ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** +* @brief Sets the TIMx Capture Compare2 Register value +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param Compare2: specifies the Capture Compare2 register new value. +* @retval None +*/ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** +* @brief Sets the TIMx Capture Compare3 Register value +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. +* @param Compare3: specifies the Capture Compare3 register new value. +* @retval None +*/ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** +* @brief Sets the TIMx Capture Compare4 Register value +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param Compare4: specifies the Capture Compare4 register new value. +* @retval None +*/ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** +* @brief Forces the TIMx output 1 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC1REF +* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. +* @retval None +*/ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Forces the TIMx output 2 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC2REF +* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. +* @retval None +*/ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Forces the TIMx output 3 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC3REF +* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. +* @retval None +*/ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Forces the TIMx output 4 waveform to active or inactive level. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. +* This parameter can be one of the following values: +* @arg TIM_ForcedAction_Active: Force active level on OC4REF +* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. +* @retval None +*/ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral + +* @param NewState: new state of the Capture Compare Preload Control bit +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR1. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. + +* @param TIM_OCPreload: new state of the TIMx peripheral Preload register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval None +*/ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR2. +* @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. + +* @param TIM_OCPreload: new state of the TIMx peripheral Preload register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval None +*/ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR3. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCPreload: new state of the TIMx peripheral Preload register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval None +*/ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Enables or disables the TIMx peripheral Preload register on CCR4. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCPreload: new state of the TIMx peripheral Preload register +* This parameter can be one of the following values: +* @arg TIM_OCPreload_Enable +* @arg TIM_OCPreload_Disable +* @retval None +*/ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx Output Compare 1 Fast feature. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval None +*/ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Configures the TIMx Output Compare 2 Fast feature. +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval None +*/ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Configures the TIMx Output Compare 3 Fast feature. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval None +*/ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx Output Compare 4 Fast feature. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCFast_Enable: TIM output compare fast enable +* @arg TIM_OCFast_Disable: TIM output compare fast disable +* @retval None +*/ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Clears or safeguards the OCREF1 signal on an external event +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval None +*/ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Clears or safeguards the OCREF2 signal on an external event +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval None +*/ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** +* @brief Clears or safeguards the OCREF3 signal on an external event +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval None +*/ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Clears or safeguards the OCREF4 signal on an external event +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. +* This parameter can be one of the following values: +* @arg TIM_OCClear_Enable: TIM Output clear enable +* @arg TIM_OCClear_Disable: TIM Output clear disable +* @retval None +*/ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** +* @brief Configures the TIMx channel 1 polarity. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_OCPolarity: specifies the OC1 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 1N polarity. +* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC1N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 2 polarity. +* @param TIMx: where x can be 1, 2, 3 to select the TIM peripheral. + +* @param TIM_OCPolarity: specifies the OC2 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 2N polarity. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC2N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 3 polarity. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCPolarity: specifies the OC3 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx Channel 3N polarity. +* @param TIMx: where x can be 1 to select the TIM peripheral. +* @param TIM_OCNPolarity: specifies the OC3N Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCNPolarity_High: Output Compare active high +* @arg TIM_OCNPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Configures the TIMx channel 4 polarity. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCPolarity: specifies the OC4 Polarity +* This parmeter can be one of the following values: +* @arg TIM_OCPolarity_High: Output Compare active high +* @arg TIM_OCPolarity_Low: Output Compare active low +* @retval None +*/ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Selects the OCReference Clear source. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_OCReferenceClear: specifies the OCReference Clear source. +* This parameter can be one of the following values: +* @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. +* @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. +* @retval None +*/ +//void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) +//{ +// /* Check the parameters */ +// assert_param(IS_TIM_LIST3_PERIPH(TIMx)); +// assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); +// +// /* Set the TIM_OCReferenceClear source */ +// TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); +// TIMx->SMCR |= TIM_OCReferenceClear; +//} + +/** +* @brief Enables or disables the TIM Capture Compare Channel x. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_Channel: specifies the TIM Channel +* This parameter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @arg TIM_Channel_4: TIM Channel 4 +* @param TIM_CCx: specifies the TIM Channel CCxE bit new state. +* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. +* @retval None +*/ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** +* @brief Enables or disables the TIM Capture Compare Channel xN. +* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. +* @param TIM_Channel: specifies the TIM Channel +* This parmeter can be one of the following values: +* @arg TIM_Channel_1: TIM Channel 1 +* @arg TIM_Channel_2: TIM Channel 2 +* @arg TIM_Channel_3: TIM Channel 3 +* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. +* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. +* @retval None +*/ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** +* @brief Selects the TIM peripheral Commutation event. +* @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral +* @param NewState: new state of the Commutation event. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** +* @} +*/ + +/** @defgroup TIM_Group4 Input Capture management functions +* @brief Input Capture management functions +* +@verbatim +=============================================================================== +##### Input Capture management functions ##### +=============================================================================== + +*** TIM Driver: how to use it in Input Capture Mode *** +=============================================================================== +[..] To use the Timer in Input Capture mode, the following steps are mandatory: +(#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) +function. +(#) Configure the TIM pins by configuring the corresponding GPIO pins. +(#) Configure the Time base unit as described in the first part of this +driver, if needed, else the Timer will run with the default configuration: +(++) Autoreload value = 0xFFFF. +(++) Prescaler value = 0x0000. +(++) Counter mode = Up counting. +(++) Clock Division = TIM_CKD_DIV1. +(#) Fill the TIM_ICInitStruct with the desired parameters including: +(++) TIM Channel: TIM_Channel. +(++) TIM Input Capture polarity: TIM_ICPolarity. +(++) TIM Input Capture selection: TIM_ICSelection. +(++) TIM Input Capture Prescaler: TIM_ICPrescaler. +(++) TIM Input CApture filter value: TIM_ICFilter. +(#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired +channel with the corresponding configuration and to measure only +frequency or duty cycle of the input signal,or, Call +TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired +channels with the corresponding configuration and to measure the +frequency and the duty cycle of the input signal. +(#) Enable the NVIC or the DMA to read the measured frequency. +(#) Enable the corresponding interrupt (or DMA request) to read +the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) +(or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). +(#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. +(#) Use TIM_GetCapturex(TIMx); to read the captured value. +[..] +(@) All other functions can be used separately to modify, if needed, +a specific feature of the Timer. + +@endverbatim +* @{ +*/ + +/** +* @brief Initializes the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** +* @brief Fills each TIM_ICInitStruct member with its default value. +* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will +* be initialized. +* @retval None +*/ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** +* @brief Configures the TIM peripheral according to the specified +* parameters in the TIM_ICInitStruct to measure an external PWM signal. +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure +* that contains the configuration information for the specified TIM +* peripheral. +* @retval None +*/ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** +* @brief Gets the TIMx Input Capture 1 value. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @retval Capture Compare 1 Register value. +*/ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** +* @brief Gets the TIMx Input Capture 2 value. +* @param TIMx: where x can be 1, 2, 3 to select the TIM peripheral. +* @retval Capture Compare 2 Register value. +*/ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** +* @brief Gets the TIMx Input Capture 3 value. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @retval Capture Compare 3 Register value. +*/ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** +* @brief Gets the TIMx Input Capture 4 value. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @retval Capture Compare 4 Register value. +*/ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** +* @brief Sets the TIMx Input Capture 1 prescaler. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval None +*/ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** +* @brief Sets the TIMx Input Capture 2 prescaler. +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval None +*/ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** +* @brief Sets the TIMx Input Capture 3 prescaler. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval None +*/ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** +* @brief Sets the TIMx Input Capture 4 prescaler. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. +* This parameter can be one of the following values: +* @arg TIM_ICPSC_DIV1: no prescaler +* @arg TIM_ICPSC_DIV2: capture is done once every 2 events +* @arg TIM_ICPSC_DIV4: capture is done once every 4 events +* @arg TIM_ICPSC_DIV8: capture is done once every 8 events +* @retval None +*/ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** +* @} +*/ + +/** @defgroup TIM_Group5 Interrupts DMA and flags management functions +* @brief Interrupts, DMA and flags management functions +* +@verbatim +=============================================================================== +##### Interrupts, DMA and flags management functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Enables or disables the specified TIM interrupts. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral. + + + +* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg TIM_IT_Update: TIM update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* +* @note TIM6 and TIM7 can only generate an update interrupt. +* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. +* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. +* @note TIM_IT_Break is used only with TIM1 and TIM15. +* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. +* +* @param NewState: new state of the TIM interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** +* @brief Configures the TIMx event to be generate by software. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the +* TIM peripheral. + + + +* @param TIM_EventSource: specifies the event source. +* This parameter can be one or more of the following values: +* @arg TIM_EventSource_Update: Timer update Event source +* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source +* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source +* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source +* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source +* @arg TIM_EventSource_COM: Timer COM event source +* @arg TIM_EventSource_Trigger: Timer Trigger Event source +* @arg TIM_EventSource_Break: Timer Break event source +* +* @note TIM6 and TIM7 can only generate an update event. +* @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. +* +* @retval None +*/ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** +* @brief Checks whether the specified TIM flag is set or not. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + + + +* @param TIM_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg TIM_FLAG_Update: TIM update Flag +* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* @arg TIM_FLAG_COM: TIM Commutation Flag +* @arg TIM_FLAG_Trigger: TIM Trigger Flag +* @arg TIM_FLAG_Break: TIM Break Flag +* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* +* @note TIM6 and TIM7 can have only one update flag. +* @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger. +* @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. +* @note TIM_FLAG_Break is used only with TIM1 and TIM15. +* @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. +* +* @retval The new state of TIM_FLAG (SET or RESET). +*/ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the TIMx's pending flags. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + + + +* @param TIM_FLAG: specifies the flag bit to clear. +* This parameter can be any combination of the following values: +* @arg TIM_FLAG_Update: TIM update Flag +* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag +* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag +* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag +* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag +* @arg TIM_FLAG_COM: TIM Commutation Flag +* @arg TIM_FLAG_Trigger: TIM Trigger Flag +* @arg TIM_FLAG_Break: TIM Break Flag +* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag +* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag +* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag +* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag +* +* @note TIM6 and TIM7 can have only one update flag. +* @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or +* TIM_FLAG_Trigger. +* @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. +* @note TIM_FLAG_Break is used only with TIM1 and TIM15. +* @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. +* +* @retval None +*/ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** +* @brief Checks whether the TIM interrupt has occurred or not. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + + + +* @param TIM_IT: specifies the TIM interrupt source to check. +* This parameter can be one of the following values: +* @arg TIM_IT_Update: TIM update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* +* @note TIM6 and TIM7 can generate only an update interrupt. +* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. +* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. +* @note TIM_IT_Break is used only with TIM1 and TIM15. +* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. +* +* @retval The new state of the TIM_IT(SET or RESET). +*/ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the TIMx's interrupt pending bits. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. + + + +* @param TIM_IT: specifies the pending bit to clear. +* This parameter can be any combination of the following values: +* @arg TIM_IT_Update: TIM1 update Interrupt source +* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source +* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source +* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source +* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source +* @arg TIM_IT_COM: TIM Commutation Interrupt source +* @arg TIM_IT_Trigger: TIM Trigger Interrupt source +* @arg TIM_IT_Break: TIM Break Interrupt source +* +* @note TIM6 and TIM7 can generate only an update interrupt. +* @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. +* @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. +* @note TIM_IT_Break is used only with TIM1 and TIM15. +* @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. +* +* @retval None +*/ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** +* @brief Configures the TIMx's DMA interface. +* @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_DMABase: DMA Base address. +* This parameter can be one of the following values: +* @arg TIM_DMABase_CR1 +* @arg TIM_DMABase_CR2 +* @arg TIM_DMABase_SMCR +* @arg TIM_DMABase_DIER +* @arg TIM_DMABase_SR +* @arg TIM_DMABase_EGR +* @arg TIM_DMABase_CCMR1 +* @arg TIM_DMABase_CCMR2 +* @arg TIM_DMABase_CCER +* @arg TIM_DMABase_CNT +* @arg TIM_DMABase_PSC +* @arg TIM_DMABase_ARR +* @arg TIM_DMABase_CCR1 +* @arg TIM_DMABase_CCR2 +* @arg TIM_DMABase_CCR3 +* @arg TIM_DMABase_CCR4 +* @arg TIM_DMABase_DCR +* @arg TIM_DMABase_OR +* @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value +* between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. +* @retval None +*/ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** +* @brief Enables or disables the TIMx's DMA Requests. +* @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. + + + +* @param TIM_DMASource: specifies the DMA Request sources. +* This parameter can be any combination of the following values: +* @arg TIM_DMA_Update: TIM update Interrupt source +* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +* @arg TIM_DMA_COM: TIM Commutation DMA source +* @arg TIM_DMA_Trigger: TIM Trigger DMA source +* @param NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST10_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** +* @brief Selects the TIMx peripheral Capture Compare DMA source. +* @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. + +* @param NewState: new state of the Capture Compare DMA source +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** +* @} +*/ + +/** @defgroup TIM_Group6 Clocks management functions +* @brief Clocks management functions +* +@verbatim +=============================================================================== +##### Clocks management functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Configures the TIMx internal Clock +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @retval None +*/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** +* @brief Configures the TIMx Internal Trigger as External Clock +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @param TIM_ITRSource: Trigger source. +* This parameter can be one of the following values: +* @arg TIM_TS_ITR0: Internal Trigger 0 +* @arg TIM_TS_ITR1: Internal Trigger 1 +* @arg TIM_TS_ITR2: Internal Trigger 2 +* @arg TIM_TS_ITR3: Internal Trigger 3 +* @retval None +*/ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** +* @brief Configures the TIMx Trigger as External Clock +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @param TIM_TIxExternalCLKSource: Trigger source. +* This parameter can be one of the following values: +* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector +* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 +* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 +* @param TIM_ICPolarity: specifies the TIx Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param ICFilter: specifies the filter value. +* This parameter must be a value between 0x0 and 0xF. +* @retval None +*/ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** +* @brief Configures the External clock Mode1 +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* @retval None +*/ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @brief Configures the External clock Mode2 +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* @retval None +*/ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** +* @} +*/ + +/** @defgroup TIM_Group7 Synchronization management functions +* @brief Synchronization management functions +* +@verbatim +=============================================================================== +##### Synchronization management functions ##### +=============================================================================== +*** TIM Driver: how to use it in synchronization Mode *** +=============================================================================== +[..] Case of two/several Timers +(#) Configure the Master Timers using the following functions: +(++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, +uint16_t TIM_TRGOSource). +(++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, +uint16_t TIM_MasterSlaveMode); +(#) Configure the Slave Timers using the following functions: +(++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, +uint16_t TIM_InputTriggerSource); +(++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +[..] Case of Timers and external trigger(ETR pin) +(#) Configure the Etrenal trigger using this function: +(++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, +uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +(#) Configure the Slave Timers using the following functions: +(++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, +uint16_t TIM_InputTriggerSource); +(++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); + +@endverbatim +* @{ +*/ +/** +* @brief Selects the Input Trigger source +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_InputTriggerSource: The Input Trigger source. +* This parameter can be one of the following values: +* @arg TIM_TS_ITR0: Internal Trigger 0 +* @arg TIM_TS_ITR1: Internal Trigger 1 +* @arg TIM_TS_ITR2: Internal Trigger 2 +* @arg TIM_TS_ITR3: Internal Trigger 3 +* @arg TIM_TS_TI1F_ED: TI1 Edge Detector +* @arg TIM_TS_TI1FP1: Filtered Timer Input 1 +* @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +* @arg TIM_TS_ETRF: External Trigger input +* @retval None +*/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @brief Selects the TIMx Trigger Output Mode. +* @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral. + + + +* @param TIM_TRGOSource: specifies the Trigger Output source. +* This parameter can be one of the following values: +* +* - For all TIMx +* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). +* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). +* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). +* +* - For all TIMx except TIM6 and TIM7 +* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag +* is to be set, as soon as a capture or compare match occurs (TRGO). +* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). +* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). +* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). +* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). +* +* @retval None +*/ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** +* @brief Selects the TIMx Slave Mode. +* @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. + +* @param TIM_SlaveMode: specifies the Timer Slave Mode. +* This parameter can be one of the following values: +* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes +* the counter and triggers an update of the registers. +* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. +* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. +* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. +* @retval None +*/ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** +* @brief Sets or Resets the TIMx Master/Slave Mode. +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. +* This parameter can be one of the following values: +* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer +* and its slaves (through TRGO). +* @arg TIM_MasterSlaveMode_Disable: No action +* @retval None +*/ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** +* @brief Configures the TIMx External Trigger (ETR). +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. +* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. +* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. +* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. +* @param TIM_ExtTRGPolarity: The external Trigger Polarity. +* This parameter can be one of the following values: +* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. +* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. +* @param ExtTRGFilter: External Trigger Filter. +* This parameter must be a value between 0x00 and 0x0F +* @retval None +*/ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** +* @} +*/ + +/** @defgroup TIM_Group8 Specific interface management functions +* @brief Specific interface management functions +* +@verbatim +=============================================================================== +##### Specific interface management functions ##### +=============================================================================== + +@endverbatim +* @{ +*/ + +/** +* @brief Configures the TIMx Encoder Interface. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_EncoderMode: specifies the TIMx Encoder Mode. +* This parameter can be one of the following values: +* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. +* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. +* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending +* on the level of the other input. +* @param TIM_IC1Polarity: specifies the IC1 Polarity +* This parmeter can be one of the following values: +* @arg TIM_ICPolarity_Falling: IC Falling edge. +* @arg TIM_ICPolarity_Rising: IC Rising edge. +* @param TIM_IC2Polarity: specifies the IC2 Polarity +* This parmeter can be one of the following values: +* @arg TIM_ICPolarity_Falling: IC Falling edge. +* @arg TIM_ICPolarity_Rising: IC Rising edge. +* @retval None +*/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** +* @brief Enables or disables the TIMx's Hall sensor interface. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param NewState: new state of the TIMx Hall sensor interface. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** +* @} +*/ + +/** @defgroup TIM_Group9 Specific remapping management function +* @brief Specific remapping management function +* +@verbatim +=============================================================================== +##### Specific remapping management function ##### +=============================================================================== + +@endverbatim +* @{ +*/ +/** +* @brief Configures the TIM14 Remapping input Capabilities. +* @param TIMx: where x can be 14 to select the TIM peripheral. +* @param TIM_Remap: specifies the TIM input reampping source. +* This parameter can be one of the following values: +* @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO. +* @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock. +* RTC input clock can be LSE, LSI or HSE/div128. +* @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock. +* @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock. +* MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. +* @retval None +*/ +//void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) +//{ +// /* Check the parameters */ +// assert_param(IS_TIM_LIST11_PERIPH(TIMx)); +// assert_param(IS_TIM_REMAP(TIM_Remap)); +// +// /* Set the Timer remapping configuration */ +// TIMx->OR = TIM_Remap; +//} + +/** +* @} +*/ + +/** +* @brief Configure the TI1 as Input. +* @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. + +* @param TIM_ICPolarity: The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. +* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. +* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval None +*/ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI2 as Input. +* @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. + +* @param TIM_ICPolarity: The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. +* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. +* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval None +*/ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI3 as Input. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ICPolarity: The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. +* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. +* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval None +*/ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** +* @brief Configure the TI4 as Input. +* @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. + +* @param TIM_ICPolarity: The Input Polarity. +* This parameter can be one of the following values: +* @arg TIM_ICPolarity_Rising +* @arg TIM_ICPolarity_Falling +* @param TIM_ICSelection: specifies the input to be used. +* This parameter can be one of the following values: +* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. +* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. +* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. +* @param TIM_ICFilter: Specifies the Input Capture Filter. +* This parameter must be a value between 0x00 and 0x0F. +* @retval None +*/ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_uart.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_uart.c new file mode 100644 index 0000000000..224dd38f49 --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_uart.c @@ -0,0 +1,438 @@ +/** +****************************************************************************** +* @file HAL_UART.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the UART firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_uart.h" +#include "HAL_rcc.h" + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup UART +* @brief UART driver modules +* @{ +*/ + +/** @defgroup UART_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Defines +* @{ +*/ + + + +/* UART UE Mask */ +#define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */ +#define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */ + +#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */ +#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */ +/** +* @} +*/ + +/** @defgroup UART_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup UART_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the UARTx peripheral registers to their +* default reset values. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @retval : None +*/ +void UART_DeInit(UART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + switch (*(uint32_t*)&UARTx) + { + case UART1_BASE: + RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, DISABLE); + break; + default: + break; + } +} + +/** +* @brief Initializes the UARTx peripheral according to the specified +* parameters in the UART_InitStruct . +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_InitStruct: pointer to a UART_InitTypeDef structure +* that contains the configuration information for the +* specified UART peripheral. +* @retval : None +*/ +void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + uint32_t tmpreg = 0x00; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + /*---------------------------- UART CCR Configuration -----------------------*/ + /* get UART CCR values */ + tmpreg = UARTx->CCR; + /* Clear spb,psel,pen bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure the UART Word Length,the UART Stop Bits,Parity ------------*/ + /* Set the char bits according to UART_WordLength value */ + /* Set spb bit according to UART_StopBits value */ + /* Set PEN bit according to UART_Parity value */ + tmpreg |= (uint32_t)UART_InitStruct->UART_WordLength |(uint32_t)UART_InitStruct->UART_StopBits |UART_InitStruct->UART_Parity; + + /* Write to UART CCR */ + UARTx->CCR = tmpreg; + + /*---------------------------- UART GCR Configuration -----------------------*/ + /* get UART GCR values */ + tmpreg = UARTx->GCR; + /* Clear TXEN and RXEN ,autoflowen, mode ,uarten bits */ + tmpreg &= GCR_CLEAR_Mask; + /* Set autorlowen bit according to UART_HardwareFlowControl value */ + /* Set rxen,txen bits according to UART_Mode value */ + tmpreg |= UART_InitStruct->UART_HardwareFlowControl | UART_InitStruct->UART_Mode ; + /* Write to UART GCR */ + UARTx->GCR = tmpreg; + /*---------------------------- UART BRR Configuration -----------------------*/ + /* Configure the UART Baud Rate -------------------------------------------RCC_ClocksStatus.PCLK1_Frequency;*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + /* Determine the UART_baud*/ + tmpreg = ((RCC_ClocksStatus.PCLK1_Frequency)/(UART_InitStruct->UART_BaudRate)/16) ; + /* Write to UART BRR */ + UARTx->BRR = tmpreg; +} + +/** +* @brief Fills each UART_InitStruct member with its default value. +* @param UART_InitStruct: pointer to a UART_InitTypeDef structure +* which will be initialized. +* @retval : None +*/ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 9600; + UART_InitStruct->UART_WordLength = UART_WordLength_8b; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No ; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; +} + + +/** +* @brief Enables or disables the specified UART peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param NewState: new state of the UARTx peripheral. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected UART by setting the uarten bit in the GCR register */ + UARTx->GCR |= GCR_UE_Set; + } + else + { + /* Disable the selected UART by clearing the uarten bit in the GCR register */ + UARTx->GCR &= GCR_UE_Reset; + } +} + +/** +* @brief Enables or disables the specified UART interrupts. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_IT: specifies the UART interrupt sources to be +* enabled or disabled. +* This parameter can be one of the following values: +* +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +* @param NewState: new state of the specified UARTx interrupts. +* This parameter can be: ENABLE or DISABLE. +* @retval : None +*/ +void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CONFIG_IT(UART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the UART_IT interrupt */ + UARTx->IER |= UART_IT; + } + else + { + /* Disable the UART_IT interrupt */ + UARTx->IER &= ~ UART_IT; + } +} + +/** +* @brief Enables or disables the UART’s DMA interface. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3 . +* @param UART_DMAReq: specifies the DMA request. +* This parameter can be any combination of the following values: +* @arg UART_DMAReq_EN: UART DMA transmit request +* +* @param NewState: new state of the DMA Request sources. +* This parameter can be: ENABLE or DISABLE. +* @note The DMA mode is not available for UART5. +* @retval : None +*/ +void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_1234_PERIPH(UARTx)); + assert_param(IS_UART_DMAREQ(UART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer */ + UARTx->GCR |= UART_DMAReq; + } + else + { + /* Disable the DMA transfer */ + UARTx->GCR &= ~UART_DMAReq; + } +} + + +/** +* @brief Transmits single data through the UARTx peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param Data: the data to transmit. +* @retval : None +*/ +void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_DATA(Data)); + + /* Transmit Data */ + UARTx->TDR = (Data & (uint16_t)0x00FF); +} + +/** +* @brief Returns the most recent received data by the UARTx peripheral. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @retval : The received data. +*/ +uint16_t UART_ReceiveData(UART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + /* Receive Data */ + return (uint16_t)(UARTx->RDR & (uint16_t)0x00FF); +} + + +/** +* @brief Checks whether the specified UART flag is set or not. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_FLAG: specifies the flag to check. +* This parameter can be one of the following values: +* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag +* @arg UART_FLAG_TXFULL:Transmit data buffer full +* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag +* @arg UART_FLAG_OVER:OverRun Error flag +* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag +* @retval : The new state of UART_FLAG (SET or RESET). +*/ +FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + if ((UARTx->CSR & UART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the UARTx's pending flags. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3, UART4 or UART5. +* @param UART_FLAG: specifies the flag to clear. +* This parameter can be any combination of the following values: +* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag +* @arg UART_FLAG_TXFULL:Transmit data buffer full +* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag +* @arg UART_FLAG_OVER:OverRun Error flag +* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag +* @retval : None +*/ +void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) +{ + +} + +/** +* @brief Checks whether the specified UART interrupt has occurred or not. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3. +* @param UART_IT: specifies the UART interrupt source to check. +* This parameter can be one of the following values: +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt +* @retval : The new state of UART_IT (SET or RESET). +*/ +ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_FLAG(UART_FLAG)); + assert_param(IS_UART_PERIPH_FLAG(UARTx, UART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ + if ((UARTx->ISR & UART_IT) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** +* @brief Clears the UARTx’s interrupt pending bits. +* @param UARTx: Select the UART or the UART peripheral. +* This parameter can be one of the following values: +* UART1, UART2, UART3, UART4 or UART5. +* @param UART_IT: specifies the interrupt pending bit to clear. +* This parameter can be one of the following values: +* @arg UART_IT_ERR: Error interrupt(Frame error,) +* @arg UART_IT_PE: Parity Error interrupt +* @arg UART_OVER_ERR: overrun Error interrupt +* @arg UART_TIMEOUT_ERR: timeout Error interrupt +* @arg UART_IT_RXIEN: Receive Data register interrupt +* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt + +* @retval : None +*/ +void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) +{ + + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_IT(UART_IT)); + assert_param(IS_UART_PERIPH_IT(UARTx, UART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ + /*clear UART_IT pendings bit*/ + UARTx->ICR = UART_IT; +} +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_wwdg.c b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_wwdg.c new file mode 100644 index 0000000000..6f2cb9b54b --- /dev/null +++ b/bsp/tkm32F499/Libraries/Hal_lib/src/HAL_wwdg.c @@ -0,0 +1,224 @@ +/** +****************************************************************************** +* @file HAL_wwdg.c +* @author IC Applications Department +* @version V0.8 +* @date 2019_08_02 +* @brief This file provides all the WWDG firmware functions. +****************************************************************************** +* @copy +* +* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE +* TIME. AS A RESULT,HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY +* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING +* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE +* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +* +*

© COPYRIGHT 2016 HOLOCENE

+*/ + +/* Includes ------------------------------------------------------------------*/ +#include "HAL_wwdg.h" +#include "HAL_rcc.h" + +//WWDG_BASE 未定义 +#ifdef 0 + +/** @addtogroup StdPeriph_Driver +* @{ +*/ + +/** @defgroup WWDG +* @brief WWDG driver modules +* @{ +*/ + +/** @defgroup WWDG_Private_TypesDefinitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Defines +* @{ +*/ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_FunctionPrototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup WWDG_Private_Functions +* @{ +*/ + +/** +* @brief Deinitializes the WWDG peripheral registers to their default +* reset values. +* @param None +* @retval : None +*/ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** +* @brief Sets the WWDG Prescaler. +* @param WWDG_Prescaler: specifies the WWDG Prescaler. +* This parameter can be one of the following values: +* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 +* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 +* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 +* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 +* @retval : None +*/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** +* @brief Sets the WWDG window value. +* @param WindowValue: specifies the window value to be compared to +* the downcounter. +* This parameter value must be lower than 0x80. +* @retval : None +*/ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + tmpreg = WWDG->CFR & CFR_W_Mask; + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & BIT_Mask; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** +* @brief Enables the WWDG Early Wakeup interrupt(EWI). +* @param None +* @retval : None +*/ +void WWDG_EnableIT(void) +{ + WWDG->CFR |= (uint32_t)0x200; +} + +/** +* @brief Sets the WWDG counter value. +* @param Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* @retval : None +*/ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** +* @brief Enables WWDG and load the counter value. +* @param Counter: specifies the watchdog counter value. +* This parameter must be a number between 0x40 and 0x7F. +* @retval : None +*/ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** +* @brief Checks whether the Early Wakeup interrupt flag is set or not. +* @param None +* @retval : The new state of the Early Wakeup interrupt flag (SET or RESET) +*/ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** +* @brief Clears Early Wakeup interrupt flag. +* @param None +* @retval : None +*/ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ +#endif // 0 +/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/ diff --git a/bsp/tkm32F499/Libraries/SConscript b/bsp/tkm32F499/Libraries/SConscript new file mode 100644 index 0000000000..6eaca5636e --- /dev/null +++ b/bsp/tkm32F499/Libraries/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Glob('Hal_lib/src/*.c') +src += [cwd + '/CMSIS_and_startup/sys.c'] +src += [cwd + '/CMSIS_and_startup/startup_Tk499.s'] + +path = [ + cwd + '/CMSIS_and_startup/CMSIS', + cwd + '/CMSIS_and_startup', + cwd + '/Hal_lib/inc',] + +CPPDEFINES = [] + +group = DefineGroup('TKM32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/tkm32F499/README.md b/bsp/tkm32F499/README.md new file mode 100644 index 0000000000..7a9bd347d4 --- /dev/null +++ b/bsp/tkm32F499/README.md @@ -0,0 +1,116 @@ +# TKM32F499 + +## 简介 + +本文档为 TKM32F499 液晶å±è¯„ä¼°æ¿çš„ BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚在进阶使用指å—章节，将会介ç»æ›´å¤šé«˜çº§åŠŸèƒ½ï¼Œå¸®åŠ©å¼€å‘者利用 RT-Thread 驱动更多æ¿è½½èµ„æºã€‚ + +## å¼€å‘æ¿ä»‹ç» + +TKM32F499 液晶å±è¯„ä¼°æ¿æ˜¯æ·±åœ³å¸‚好钜润科技有é™å…¬å¸å®˜æ–¹æŽ¨å‡ºçš„å¼€å‘æ¿ï¼Œæ­è½½ TKM32F499 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的æ¿è½½èµ„æºï¼Œå¯ä»¥å……分å‘挥 TKM32F499 的芯片性能。 + +å¼€å‘æ¿å¤–观如下图所示： + +![board](figures/board.jpg) + +该开å‘æ¿å¸¸ç”¨ **æ¿è½½èµ„æº** 如下： + +- MCU：TKM32F499，主频 240MHz ，8MB RAM，带FPU，DMA å•æ¬¡ 42 亿点 +- 常用外设 + - LED：3个，LD1（PD8），LD2（PB14），LD3（PB15） + - 按键：5 å‘按键 1 个，RESET +- 常用接å£ï¼šTK80接å£ï¼ˆå‘下兼容è€å¼8080接å£ï¼‰ + +官方资料：[TKM32F499评估æ¿å‚考资料](http://hjrkj.com/companyfile/1.html) + +*更多相关信æ¯èµ„æ–™è§å®˜ç½‘详情页：[TKM32F499芯片åŠè¯„测](http://hjrkj.com/product/13.html)* + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **片上外设** | **支æŒæƒ…况** | **备注** | +| :----------- | :----------: | :----------- | +| GPIO | æ”¯æŒ | | +| UART | æ”¯æŒ | UART1ã€UART2 | +| SPI | æš‚ä¸æ”¯æŒ | | +| I2C | æš‚ä¸æ”¯æŒ | | +| RTC | æš‚ä¸æ”¯æŒ | | +| PWM | æš‚ä¸æ”¯æŒ | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + +- 进阶使用 + + 本章节是为需è¦åœ¨ RT-Thread æ“作系统上使用更多开å‘æ¿èµ„æºçš„å¼€å‘者准备的。通过使用 ENV 工具对 BSP 进行é…置，å¯ä»¥å¼€å¯æ›´å¤šæ¿è½½èµ„æºï¼Œå®žçŽ°æ›´å¤šé«˜çº§åŠŸèƒ½ã€‚ + + +### 快速上手 + +本 BSP 为开å‘者æä¾› MDK5 工程。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + +使用数æ®çº¿è¿žæŽ¥å¼€å‘æ¿åˆ° PC，连接串å£1到 PC，打开电æºå¼€å…³ã€‚ + +#### 编译下载 + +åŒå‡» project.uvprojx 文件，打开 MDK5 工程，编译并下载程åºåˆ°å¼€å‘æ¿ã€‚ + +> å¯ä»¥é€šè¿‡ bootloader 自带 usb下载，通过 u 盘方å¼ä¸‹è½½ï¼š +> +> * 方法一：五å‘按键å‘上推（按下 PA1 按键，åˆå APP 键） ，åŒæ—¶æŒ‰ä¸€ä¸‹å¤ä½ï¼ˆæ³¨æ„，æ¾æ‰‹æ—¶ï¼Œå…ˆæ¾å¤ä½ï¼Œå†æ¾äº”å‘按键），然åŽç‚¹ä¸€ä¸‹ KEIL 的下载按钮å³å¯ +> * 方法二：å‘上推， åŒæ—¶æŒ‰ä¸€ä¸‹å¤ä½ï¼Œç„¶åŽå…ˆæ¾å¼€å¤ä½å†æ¾å¼€å‘上按键， 就会进入程åºä¸‹è½½æ¨¡å¼ï¼Œ 电脑会弹出一个 TK499_V2 盘符的 U 盘，把 KEIL 工程目录下生æˆçš„ bin 程åºæ‹–è¿› U盘就行 +> +> 本工程下自带官方的 bootloader ，通过把五å‘按键å‘左推（按下 PA13 按键，åˆå BOOT 键） ， åŒæ—¶å†æŒ‰ä¸€ä¸‹å¤ä½ï¼Œç„¶åŽå…ˆæ¾å¼€å¤ä½å†æ¾å¼€å‘上按键就进入了 Bootloader 下载模å¼ã€‚这时会弹出一个盘符为 TK499 çš„ U 盘，把本工程下的 Bootloader.bin 拖进去å³å¯é‡æ–°çƒ§å½• bootloader +> +> 注æ„： +> +> * bootloader 默认的波特率为460800，所以会在å¯åŠ¨ rtthread æ—¶å­˜åœ¨ä¹±ç  +> * 该芯片有个致命问题：å¤ä½å¼•è„šä¸èƒ½æ­£å¸¸å¤ä½ï¼Œæ–­ç”µé‡å¯äº†æ‰å¯ä»¥ã€‚如有莫å其妙的问题请断电é‡å¯ã€‚出处https://www.amobbs.com/thread-5748003-1-1.html + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼Œæ©˜é»„色 LD2 会周期性闪çƒã€‚ + +USB 虚拟 COM 端å£é»˜è®¤è¿žæŽ¥ä¸²å£ 1，在终端工具里打开相应的串å£ï¼ˆ115200-8-1-N），å¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +```bash + \ | / +- RT - Thread Operating System + / | \ 4.0.4 build Oct 14 2021 + 2006 - 2021 Copyright by rt-thread team +msh > +``` + +* 注æ„：官方 bootloader 使用的是串å£1，且波特率为460800ï¼Œæ‰€ä»¥ä¼šåœ¨ä¸€å¼€å§‹æœ‰ä¸€æ®µä¹±ç  + +### 进阶使用 + +æ­¤ BSP 默认åªå¼€å¯äº† GPIO å’Œ 串å£1 的功能，更多高级功能需è¦åˆ©ç”¨ ENV 工具对 BSP 进行é…置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令é…置工程，é…置好之åŽä¿å­˜é€€å‡ºã€‚ + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5` 命令é‡æ–°ç”Ÿæˆå·¥ç¨‹ã€‚ + + +## è”ç³»äººä¿¡æ¯ + +维护人：[NU-LL](https://github.com/NU-LL) diff --git a/bsp/tkm32F499/SConscript b/bsp/tkm32F499/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/tkm32F499/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/tkm32F499/SConstruct b/bsp/tkm32F499/SConstruct new file mode 100644 index 0000000000..1b8b45907e --- /dev/null +++ b/bsp/tkm32F499/SConstruct @@ -0,0 +1,40 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread-tkm32f4xx.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/tkm32F499/applications/SConscript b/bsp/tkm32F499/applications/SConscript new file mode 100644 index 0000000000..ca2395451a --- /dev/null +++ b/bsp/tkm32F499/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/tkm32F499/applications/main.c b/bsp/tkm32F499/applications/main.c new file mode 100644 index 0000000000..539f6e55f7 --- /dev/null +++ b/bsp/tkm32F499/applications/main.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ + +#include +#include +#include +#include +#include "board.h" +#include "drv_gpio.h" + + +#define LED_PIN GET_PIN(D, 8) +#define LED0_PIN GET_PIN(B, 14) +#define LED1_PIN GET_PIN(B, 15) + + +int main(void) +{ + /* set LED pin mode to output */ + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + rt_pin_write(LED_PIN, PIN_LOW); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_pin_write(LED1_PIN, PIN_LOW); + + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } + + return RT_EOK; +} diff --git a/bsp/tkm32F499/drivers/Kconfig b/bsp/tkm32F499/drivers/Kconfig new file mode 100644 index 0000000000..870c473f9b --- /dev/null +++ b/bsp/tkm32F499/drivers/Kconfig @@ -0,0 +1,146 @@ +menu "Hardware Drivers Config" + +config SOC_SERIES_TKM32F4 + bool + default y + +config SOC_TKM32F499 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select SOC_SERIES_TKM32F4 + default y + +menu "Onboard Peripheral Drivers" + + config BSP_USING_USB_TO_USART + bool "Enable USB TO USART (uart1)" + select BSP_USING_UART + select BSP_USING_UART1 + default y + + config BSP_USING_SDCARD + bool "Enable SDCARD (sdio)" + select BSP_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1 PA9/10(T/R)" + default y + + config BSP_USING_UART2 + bool "Enable UART2 PA2/3(T/R)" + default n + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 0 175 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 23 + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM2 + bool "Enable TIM2" + default n + + config BSP_USING_TIM3 + bool "Enable TIM3" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/tkm32F499/drivers/SConscript b/bsp/tkm32F499/drivers/SConscript new file mode 100644 index 0000000000..861b449735 --- /dev/null +++ b/bsp/tkm32F499/drivers/SConscript @@ -0,0 +1,24 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +""") + +# add serial driver code +if GetDepend('RT_USING_SERIAL'): + src += ['drv_uart.c'] + +# add gpio driver code +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/tkm32F499/drivers/board.c b/bsp/tkm32F499/drivers/board.c new file mode 100644 index 0000000000..b11afa8f16 --- /dev/null +++ b/bsp/tkm32F499/drivers/board.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2017-2019, MindMotion AE Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ +#include +#include +#include +#include +// extern uint32_t SystemCoreClock; +// extern void SystemInit(void); + +#ifdef RT_USING_FINSH +#include +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +static void bsp_clock_config(void) +{ + RemapVtorTable(); + SystemClk_HSEInit(RCC_PLLMul_20);//å¯åŠ¨PLL时钟，12MHz*20=240MHz + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次 + + uint32_t sysclk = 0; + getSystemClock(&sysclk); + + SysTick_Config(sysclk / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +void rt_hw_board_init() +{ + bsp_clock_config(); +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + // volatile uint16_t i=0; + // rt_hw_uart_init(); + // i = UINT16_MAX; + // while(i--); //wait for a while after uart initiated. +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/tkm32F499/drivers/board.h b/bsp/tkm32F499/drivers/board.h new file mode 100644 index 0000000000..eb5390829a --- /dev/null +++ b/bsp/tkm32F499/drivers/board.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017-2019, MindMotion AE Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ +#include +#include +#include +#include "sys.h" + + + +#define SRAM_SIZE (8 * 1024 * 1024) +// #define SRAM_BASE ((uint32_t)0x70000000) + + +#define SRAM_END (T_SDRAM_BASE + SRAM_SIZE) +#ifdef __CC_ARM + extern int Image$$RW_IRAM1$$ZI$$Limit; + #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ + #pragma section = "HEAP" + #define HEAP_BEGIN (__segment_end("HEAP")) +#else + extern int __bss_end; + #define HEAP_BEGIN ((void *)&__bss_end) +#endif +#define HEAP_END SRAM_END +#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) +extern void rt_hw_board_init(void); +#endif diff --git a/bsp/tkm32F499/drivers/drv_gpio.c b/bsp/tkm32F499/drivers/drv_gpio.c new file mode 100644 index 0000000000..2fe9418d72 --- /dev/null +++ b/bsp/tkm32F499/drivers/drv_gpio.c @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ +#include +#include +#include +#include +#include + +#ifdef RT_USING_PIN + +#define TKM32_PIN(index, rcc, gpio, gpio_index) { index, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, \ + ((rt_base_t)__TKM32_PORT(gpio)-(rt_base_t)GPIOA_BASE)/(0x0400UL), gpio_index} +#define TKM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0} +/* TKM32 GPIO driver */ +struct pin_index +{ + int index; + uint32_t rcc; + GPIO_TypeDef *gpio; + uint32_t pin; + uint8_t port_source; + uint8_t pin_source; +}; +static const struct pin_index tkm32_pin_map[] = +{ + TKM32_PIN_DEFAULT, + TKM32_PIN(0, AHB, A, 0), + TKM32_PIN(1, AHB, A, 1), + TKM32_PIN(2, AHB, A, 2), + TKM32_PIN(3, AHB, A, 3), + TKM32_PIN(4, AHB, A, 4), + TKM32_PIN(5, AHB, A, 5), + TKM32_PIN(6, AHB, A, 6), + TKM32_PIN(7, AHB, A, 7), + TKM32_PIN(8, AHB, A, 8), + TKM32_PIN(9, AHB, A, 9), + TKM32_PIN(10, AHB, A, 10), + TKM32_PIN(11, AHB, A, 11), + TKM32_PIN(12, AHB, A, 12), + TKM32_PIN(13, AHB, A, 13), + TKM32_PIN(14, AHB, A, 14), + TKM32_PIN(15, AHB, A, 15), + TKM32_PIN(16, AHB, B, 0), + TKM32_PIN(17, AHB, B, 1), + TKM32_PIN(18, AHB, B, 2), + TKM32_PIN(19, AHB, B, 3), + TKM32_PIN(20, AHB, B, 4), + TKM32_PIN(21, AHB, B, 5), + TKM32_PIN(22, AHB, B, 6), + TKM32_PIN(23, AHB, B, 7), + TKM32_PIN(24, AHB, B, 8), + TKM32_PIN(25, AHB, B, 9), + TKM32_PIN(26, AHB, B, 10), + TKM32_PIN(27, AHB, B, 11), + TKM32_PIN(28, AHB, B, 12), + TKM32_PIN(29, AHB, B, 13), + TKM32_PIN(30, AHB, B, 14), + TKM32_PIN(31, AHB, B, 15), + TKM32_PIN(32, AHB, C, 0), + TKM32_PIN(33, AHB, C, 1), + TKM32_PIN(34, AHB, C, 2), + TKM32_PIN(35, AHB, C, 3), + TKM32_PIN(36, AHB, C, 4), + TKM32_PIN(37, AHB, C, 5), + TKM32_PIN(38, AHB, C, 6), + TKM32_PIN(39, AHB, C, 7), + TKM32_PIN(40, AHB, C, 8), + TKM32_PIN(41, AHB, C, 9), + TKM32_PIN(42, AHB, C, 10), + TKM32_PIN(43, AHB, C, 11), + TKM32_PIN(44, AHB, C, 12), + TKM32_PIN(45, AHB, C, 13), + TKM32_PIN(46, AHB, C, 14), + TKM32_PIN(47, AHB, C, 15), + TKM32_PIN(48, AHB, D, 0), + TKM32_PIN(49, AHB, D, 1), + TKM32_PIN(50, AHB, D, 2), + TKM32_PIN(51, AHB, D, 3), + TKM32_PIN(52, AHB, D, 4), + TKM32_PIN(53, AHB, D, 5), + TKM32_PIN(54, AHB, D, 6), + TKM32_PIN(55, AHB, D, 7), + TKM32_PIN(56, AHB, D, 8), + TKM32_PIN(57, AHB, D, 9), + TKM32_PIN(58, AHB, D, 10), + TKM32_PIN(59, AHB, D, 11), + TKM32_PIN(60, AHB, D, 12), + TKM32_PIN(61, AHB, D, 13), + TKM32_PIN(62, AHB, D, 14), + TKM32_PIN(63, AHB, D, 15), + TKM32_PIN(64, AHB, E, 0), + TKM32_PIN(65, AHB, E, 1), + TKM32_PIN(66, AHB, E, 2), + TKM32_PIN(67, AHB, E, 3), + TKM32_PIN(68, AHB, E, 4), + TKM32_PIN(69, AHB, E, 5), + TKM32_PIN(70, AHB, E, 6), + TKM32_PIN(71, AHB, E, 7), + TKM32_PIN(72, AHB, E, 8), + TKM32_PIN(73, AHB, E, 9), + TKM32_PIN(74, AHB, E, 10), + TKM32_PIN(75, AHB, E, 11), + TKM32_PIN(76, AHB, E, 12), + TKM32_PIN(77, AHB, E, 13), + TKM32_PIN(78, AHB, E, 14), + TKM32_PIN(79, AHB, E, 15), + TKM32_PIN(80, AHB, E, 16), + TKM32_PIN(81, AHB, E, 17), + TKM32_PIN(82, AHB, E, 18), + TKM32_PIN(83, AHB, E, 19), + TKM32_PIN(84, AHB, E, 20), + TKM32_PIN(85, AHB, E, 21), + TKM32_PIN(86, AHB, E, 22), + TKM32_PIN(87, AHB, E, 23), +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + rt_uint32_t irqbit; + enum IRQn irqno; +}; +const struct pin_irq_map tkm32_pin_irq_map[] = +{ + {GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn }, + {GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn }, + {GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn }, + {GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn }, + {GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn }, + {GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn }, + {GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn }, + {GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn }, + {GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn }, + {GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn }, + {GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn}, + {GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn}, + {GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn}, + {GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn}, + {GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn}, + {GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr tkm32_pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin+1 < ITEM_NUM(tkm32_pin_map)) + { + index = &tkm32_pin_map[pin+1]; + if (index->gpio == 0) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + if (value == PIN_LOW) + { + GPIO_ResetBits(index->gpio, index->pin); + } + else + { + GPIO_SetBits(index->gpio, index->pin); + } +} + +int tkm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + index = get_pin(pin); + if (index == RT_NULL) + { + return PIN_LOW; + } + if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + return value; +} + +void tkm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + /* GPIO Periph clock enable */ + RCC_AHBPeriphClockCmd(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + } + else + { + /* input setting:default. */ + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + } + GPIO_Init( index->gpio, &GPIO_InitStructure); + GPIO_PinAFConfig(index->gpio, index->pin, GPIO_AF_GPIO); +} +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(tkm32_pin_irq_map)) + { + return RT_NULL; + } + return &tkm32_pin_irq_map[mapindex]; +}; +rt_err_t tkm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map)) + { + return -RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (tkm32_pin_irq_hdr_tab[irqindex].pin == pin && + tkm32_pin_irq_hdr_tab[irqindex].hdr == hdr && + tkm32_pin_irq_hdr_tab[irqindex].mode == mode && + tkm32_pin_irq_hdr_tab[irqindex].args == args + ) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (tkm32_pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + tkm32_pin_irq_hdr_tab[irqindex].pin = pin; + tkm32_pin_irq_hdr_tab[irqindex].hdr = hdr; + tkm32_pin_irq_hdr_tab[irqindex].mode = mode; + tkm32_pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t tkm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (tkm32_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + tkm32_pin_irq_hdr_tab[irqindex].pin = -1; + tkm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + tkm32_pin_irq_hdr_tab[irqindex].mode = 0; + tkm32_pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t tkm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + EXTI_InitTypeDef EXTI_InitStructure; + + index = get_pin(pin); + if (index == RT_NULL) + { + return -RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map)) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (tkm32_pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + irqmap = &tkm32_pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + RCC_AHBPeriphClockCmd(index->rcc, ENABLE); + /* Configure GPIO_InitStructure */ + GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(index->gpio, &GPIO_InitStructure); + + NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + // GPIO_EXTILineConfig(index->port_source, index->pin_source); + // EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + // EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + switch (tkm32_pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + Ex_NVIC_Config(index->port_source, index->pin_source, 2); + // EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + break; + case PIN_IRQ_MODE_FALLING: + Ex_NVIC_Config(index->port_source, index->pin_source, 1); + // EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; + break; + case PIN_IRQ_MODE_RISING_FALLING: + Ex_NVIC_Config(index->port_source, index->pin_source, 3); + // EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling; + break; + } + // EXTI_InitStructure.EXTI_LineCmd = ENABLE; + // EXTI_Init(&EXTI_InitStructure); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return -RT_ENOSYS; + } + EXTI_InitStructure.EXTI_Line = irqmap->irqbit; + EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; + EXTI_InitStructure.EXTI_LineCmd = DISABLE; + EXTI_Init(&EXTI_InitStructure); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _tkm32_pin_ops = +{ + tkm32_pin_mode, + tkm32_pin_write, + tkm32_pin_read, + tkm32_pin_attach_irq, + tkm32_pin_detach_irq, + tkm32_pin_irq_enable, + RT_NULL, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_tkm32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + EXTI_ClearITPendingBit(tkm32_pin_irq_map[irqno].irqbit); + if (tkm32_pin_irq_hdr_tab[irqno].hdr) + { + tkm32_pin_irq_hdr_tab[irqno].hdr(tkm32_pin_irq_hdr_tab[irqno].args); + } +} +void EXTI0_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(0); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(1); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(2); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(3); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + pin_irq_hdr(4); + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line5) != RESET) + { + pin_irq_hdr(5); + } + if (EXTI_GetITStatus(EXTI_Line6) != RESET) + { + pin_irq_hdr(6); + } + if (EXTI_GetITStatus(EXTI_Line7) != RESET) + { + pin_irq_hdr(7); + } + if (EXTI_GetITStatus(EXTI_Line8) != RESET) + { + pin_irq_hdr(8); + } + if (EXTI_GetITStatus(EXTI_Line9) != RESET) + { + pin_irq_hdr(9); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + if (EXTI_GetITStatus(EXTI_Line10) != RESET) + { + pin_irq_hdr(10); + } + if (EXTI_GetITStatus(EXTI_Line11) != RESET) + { + pin_irq_hdr(11); + } + if (EXTI_GetITStatus(EXTI_Line12) != RESET) + { + pin_irq_hdr(12); + } + if (EXTI_GetITStatus(EXTI_Line13) != RESET) + { + pin_irq_hdr(13); + } + if (EXTI_GetITStatus(EXTI_Line14) != RESET) + { + pin_irq_hdr(14); + } + if (EXTI_GetITStatus(EXTI_Line15) != RESET) + { + pin_irq_hdr(15); + } + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_PIN */ diff --git a/bsp/tkm32F499/drivers/drv_gpio.h b/bsp/tkm32F499/drivers/drv_gpio.h new file mode 100644 index 0000000000..50eac81e17 --- /dev/null +++ b/bsp/tkm32F499/drivers/drv_gpio.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ +#ifndef DRV_GPIO_H__ +#define DRV_GPIO_H__ + +#define __TKM32_PORT(port) GPIO##port##_BASE + +#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__TKM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN) + + + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/tkm32F499/drivers/drv_log.h b/bsp/tkm32F499/drivers/drv_log.h new file mode 100644 index 0000000000..3fe511789b --- /dev/null +++ b/bsp/tkm32F499/drivers/drv_log.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-11-15 SummerGift first version + */ + +/* + * NOTE: DO NOT include this file on the header file. + */ + +#ifndef LOG_TAG +#define DBG_TAG "drv" +#else +#define DBG_TAG LOG_TAG +#endif /* LOG_TAG */ + +#ifdef DRV_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_INFO +#endif /* DRV_DEBUG */ + +#include diff --git a/bsp/tkm32F499/drivers/drv_uart.c b/bsp/tkm32F499/drivers/drv_uart.c new file mode 100644 index 0000000000..336367d9be --- /dev/null +++ b/bsp/tkm32F499/drivers/drv_uart.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ +#include +#include +#include +#include "drv_uart.h" + +#ifdef RT_USING_SERIAL + +//#define DRV_DEBUG +#define LOG_TAG "drv.uart" +#include + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) +#error "Please define at least one BSP_USING_UARTx" +/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ +#endif + + +/* UART1 */ +#define UART1_GPIO_TX GPIO_Pin_9 +#define UART1_GPIO_RX GPIO_Pin_10 +#define UART1_GPIO_AF GPIO_AF_UART_1 +#define UART1_GPIO GPIOA + +/* UART2 */ +#define UART2_GPIO_TX GPIO_Pin_2 +#define UART2_GPIO_RX GPIO_Pin_3 +#define UART2_GPIO_AF GPIO_AF_UART_2345 +#define UART2_GPIO GPIOA + + +static rt_err_t tkm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct tkm32_uart *uart; + UART_InitTypeDef UART_InitStructure; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct tkm32_uart *)serial->parent.user_data; + UART_InitStructure.UART_BaudRate = cfg->baud_rate; + if (cfg->data_bits == DATA_BITS_8) + UART_InitStructure.UART_WordLength = UART_WordLength_8b; + if (cfg->stop_bits == STOP_BITS_1) + UART_InitStructure.UART_StopBits = UART_StopBits_1; + else if (cfg->stop_bits == STOP_BITS_2) + UART_InitStructure.UART_StopBits = UART_StopBits_2; + UART_InitStructure.UART_Parity = UART_Parity_No; + UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_Init(uart->uart, &UART_InitStructure); + /* Enable UART */ + UART_Cmd(uart->uart, ENABLE); + return RT_EOK; +} + +static rt_err_t tkm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct tkm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct tkm32_uart *)serial->parent.user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE); + break; + } + return RT_EOK; +} + +static int tkm32_uart_putc(struct rt_serial_device *serial, char c) +{ + struct tkm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct tkm32_uart *)serial->parent.user_data; + while ((uart->uart->CSR & UART_IT_TXIEN) == 0); + uart->uart->TDR = (c & (uint16_t)0x00FF); + return 1; +} + +static int tkm32_uart_getc(struct rt_serial_device *serial) +{ + int ch; + struct tkm32_uart *uart; + RT_ASSERT(serial != RT_NULL); + uart = (struct tkm32_uart *)serial->parent.user_data; + ch = -1; + if (uart->uart->CSR & UART_FLAG_RXAVL) + { + ch = uart->uart->RDR & 0xff; + } + return ch; +} + +static const struct rt_uart_ops tkm32_uart_ops = +{ + tkm32_uart_configure, + tkm32_uart_control, + tkm32_uart_putc, + tkm32_uart_getc, +}; + +#if defined(BSP_USING_UART1) +/* UART1 device driver structure */ +static struct tkm32_uart uart1; +struct rt_serial_device serial1; +void UART1_IRQHandler(void) +{ + struct tkm32_uart *uart; + uart = &uart1; + /* enter interrupt */ + rt_interrupt_enter(); + if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET) + { + UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + } + if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET) + { + /* clear interrupt */ + UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +/* UART2 device driver structure */ +static struct tkm32_uart uart2; +struct rt_serial_device serial2; +void UART2_IRQHandler(void) +{ + struct tkm32_uart *uart; + uart = &uart2; + /* enter interrupt */ + rt_interrupt_enter(); + if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET) + { + UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + } + if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET) + { + /* clear interrupt */ + UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN); + } + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART2 */ + +#ifdef BSP_USING_UART1 +static void UART1PINconfigStepA(void) +{ + /* Enable UART clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE); +} + +static void UART1PINconfigStepB(void) +{ + + GPIO_InitTypeDef GPIO_InitStructure; + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(UART1_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(UART1_GPIO, UART1_GPIO_TX | UART1_GPIO_RX, UART1_GPIO_AF); + UART_ClearITPendingBit(UART1, 0xFF); +} +#endif + +#ifdef BSP_USING_UART2 +static void UART2PINconfigStepA(void) +{ + /* Enable UART clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); +} + +static void UART2PINconfigStepB(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + /* Configure USART Rx/tx PIN */ + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(UART2_GPIO, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(UART2_GPIO, &GPIO_InitStructure); + GPIO_PinAFConfig(UART2_GPIO, UART2_GPIO_TX | UART2_GPIO_RX, UART2_GPIO_AF); + UART_ClearITPendingBit(UART2, 0xFF); +} +#endif + +int rt_hw_uart_init(void) +{ + struct tkm32_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; +#ifdef BSP_USING_UART1 + UART1PINconfigStepA(); + uart = &uart1; + uart->uart = UART1; + uart->irq = UART1_IRQn; + config.baud_rate = BAUD_RATE_115200; + serial1.ops = &tkm32_uart_ops; + serial1.config = config; + /* register UART1 device */ + rt_hw_serial_register(&serial1, "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX, + uart); + UART1PINconfigStepB(); +#endif /* BSP_USING_UART1 */ + +#ifdef BSP_USING_UART2 + UART2PINconfigStepA(); + uart = &uart2; + uart->uart = UART2; + uart->irq = UART2_IRQn; + config.baud_rate = BAUD_RATE_115200; + serial2.ops = &tkm32_uart_ops; + serial2.config = config; + /* register UART2 device */ + rt_hw_serial_register(&serial2, "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX, + uart); + UART2PINconfigStepB(); +#endif /* BSP_USING_UART2 */ + return 0; +} +INIT_BOARD_EXPORT(rt_hw_uart_init); + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/tkm32F499/drivers/drv_uart.h b/bsp/tkm32F499/drivers/drv_uart.h new file mode 100644 index 0000000000..4615c9db3d --- /dev/null +++ b/bsp/tkm32F499/drivers/drv_uart.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-02 spaceman first version + */ + +#ifndef DRV_UART_H__ +#define DRV_UART_H__ + +#include +#include "rtdevice.h" +#include + + +int rt_hw_uart_init(void); + +/* uart driver */ +struct tkm32_uart +{ + UART_TypeDef *uart; + IRQn_Type irq; +}; + + + +#endif diff --git a/bsp/tkm32F499/drivers/linker_scripts/link.icf b/bsp/tkm32F499/drivers/linker_scripts/link.icf new file mode 100644 index 0000000000..a2e05e53a6 --- /dev/null +++ b/bsp/tkm32F499/drivers/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_IROM_end__ = 0x0001FFFF; +define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x0800; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0800; +/**** End of ICF editor section. ###ICF###*/ +define memory mem with size = 4G; +define region IROM_region = mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in IROM_region { readonly }; +place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP }; diff --git a/bsp/tkm32F499/drivers/linker_scripts/link.lds b/bsp/tkm32F499/drivers/linker_scripts/link.lds new file mode 100644 index 0000000000..aad42bdb39 --- /dev/null +++ b/bsp/tkm32F499/drivers/linker_scripts/link.lds @@ -0,0 +1,137 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */ + DATA (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 8K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x200; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + .stack : + { + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/tkm32F499/drivers/linker_scripts/link.sct b/bsp/tkm32F499/drivers/linker_scripts/link.sct new file mode 100644 index 0000000000..b2d98ef44a --- /dev/null +++ b/bsp/tkm32F499/drivers/linker_scripts/link.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x70020000 0x00200000 { ; load region size_region + ER_IROM1 0x70020000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x70220000 0x005DFFFF { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/tkm32F499/figures/board.jpg b/bsp/tkm32F499/figures/board.jpg new file mode 100644 index 0000000000..1faf3029c4 Binary files /dev/null and b/bsp/tkm32F499/figures/board.jpg differ diff --git a/bsp/tkm32F499/project.uvprojx b/bsp/tkm32F499/project.uvprojx new file mode 100644 index 0000000000..05c2ffc586 --- /dev/null +++ b/bsp/tkm32F499/project.uvprojx @@ -0,0 +1,788 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin -o .//@L.bin ./build/@L.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "flash_download" (.//@L.bin TK499_V2) + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x70020000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x70220000 + 0x5dffff + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + + applications;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m4;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;drivers;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\finsh;.;rt-thread\include;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;rt-thread\components\libc\compilers\common\nogcc;Libraries\CMSIS_and_startup\CMSIS;Libraries\CMSIS_and_startup;Libraries\Hal_lib\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + CPU + + + backtrace.c + 1 + rt-thread\libcpu\arm\common\backtrace.c + + + showmem.c + 1 + rt-thread\libcpu\arm\common\showmem.c + + + div0.c + 1 + rt-thread\libcpu\arm\common\div0.c + + + cpuport.c + 1 + rt-thread\libcpu\arm\cortex-m4\cpuport.c + + + context_rvds.S + 2 + rt-thread\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + rt-thread\components\drivers\misc\pin.c + + + serial.c + 1 + rt-thread\components\drivers\serial\serial.c + + + waitqueue.c + 1 + rt-thread\components\drivers\src\waitqueue.c + + + workqueue.c + 1 + rt-thread\components\drivers\src\workqueue.c + + + ringbuffer.c + 1 + rt-thread\components\drivers\src\ringbuffer.c + + + pipe.c + 1 + rt-thread\components\drivers\src\pipe.c + + + ringblk_buf.c + 1 + rt-thread\components\drivers\src\ringblk_buf.c + + + completion.c + 1 + rt-thread\components\drivers\src\completion.c + + + dataqueue.c + 1 + rt-thread\components\drivers\src\dataqueue.c + + + + + Drivers + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + drv_uart.c + 1 + drivers\drv_uart.c + + + board.c + 1 + drivers\board.c + + + + + Filesystem + + + dfs_posix.c + 1 + rt-thread\components\dfs\src\dfs_posix.c + + + dfs_poll.c + 1 + rt-thread\components\dfs\src\dfs_poll.c + + + dfs_file.c + 1 + rt-thread\components\dfs\src\dfs_file.c + + + dfs.c + 1 + rt-thread\components\dfs\src\dfs.c + + + dfs_fs.c + 1 + rt-thread\components\dfs\src\dfs_fs.c + + + dfs_select.c + 1 + rt-thread\components\dfs\src\dfs_select.c + + + devfs.c + 1 + rt-thread\components\dfs\filesystems\devfs\devfs.c + + + + + Finsh + + + shell.c + 1 + rt-thread\components\finsh\shell.c + + + msh.c + 1 + rt-thread\components\finsh\msh.c + + + msh_file.c + 1 + rt-thread\components\finsh\msh_file.c + + + cmd.c + 1 + rt-thread\components\finsh\cmd.c + + + + + Kernel + + + ipc.c + 1 + rt-thread\src\ipc.c + + + irq.c + 1 + rt-thread\src\irq.c + + + mem.c + 1 + rt-thread\src\mem.c + + + scheduler.c + 1 + rt-thread\src\scheduler.c + + + device.c + 1 + rt-thread\src\device.c + + + components.c + 1 + rt-thread\src\components.c + + + mempool.c + 1 + rt-thread\src\mempool.c + + + idle.c + 1 + rt-thread\src\idle.c + + + timer.c + 1 + rt-thread\src\timer.c + + + object.c + 1 + rt-thread\src\object.c + + + clock.c + 1 + rt-thread\src\clock.c + + + kservice.c + 1 + rt-thread\src\kservice.c + + + thread.c + 1 + rt-thread\src\thread.c + + + + + libc + + + syscalls.c + 1 + rt-thread\components\libc\compilers\armlibc\syscalls.c + + + mem_std.c + 1 + rt-thread\components\libc\compilers\armlibc\mem_std.c + + + libc.c + 1 + rt-thread\components\libc\compilers\armlibc\libc.c + + + stdio.c + 1 + rt-thread\components\libc\compilers\armlibc\stdio.c + + + time.c + 1 + rt-thread\components\libc\compilers\common\time.c + + + stdlib.c + 1 + rt-thread\components\libc\compilers\common\stdlib.c + + + unistd.c + 1 + rt-thread\components\libc\compilers\common\unistd.c + + + delay.c + 1 + rt-thread\components\libc\compilers\common\delay.c + + + + + TKM32_Lib + + + HAL_dma_bak.c + 1 + Libraries\Hal_lib\src\HAL_dma_bak.c + + + HAL_exti.c + 1 + Libraries\Hal_lib\src\HAL_exti.c + + + startup_Tk499.s + 2 + Libraries\CMSIS_and_startup\startup_Tk499.s + + + HAL_dma.c + 1 + Libraries\Hal_lib\src\HAL_dma.c + + + HAL_can.c + 1 + Libraries\Hal_lib\src\HAL_can.c + + + HAL_uart.c + 1 + Libraries\Hal_lib\src\HAL_uart.c + + + HAL_rcc.c + 1 + Libraries\Hal_lib\src\HAL_rcc.c + + + HAL_tim.c + 1 + Libraries\Hal_lib\src\HAL_tim.c + + + HAL_misc.c + 1 + Libraries\Hal_lib\src\HAL_misc.c + + + HAL_spi.c + 1 + Libraries\Hal_lib\src\HAL_spi.c + + + HAL_wwdg.c + 1 + Libraries\Hal_lib\src\HAL_wwdg.c + + + HAL_pwr.c + 1 + Libraries\Hal_lib\src\HAL_pwr.c + + + HAL_iwdg.c + 1 + Libraries\Hal_lib\src\HAL_iwdg.c + + + HAL_syscfg.c + 1 + Libraries\Hal_lib\src\HAL_syscfg.c + + + sys.c + 1 + Libraries\CMSIS_and_startup\sys.c + + + HAL_gpio.c + 1 + Libraries\Hal_lib\src\HAL_gpio.c + + + HAL_i2c.c + 1 + Libraries\Hal_lib\src\HAL_i2c.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/bsp/tkm32F499/rtconfig.h b/bsp/tkm32F499/rtconfig.h new file mode 100644 index 0000000000..bb0d92cc87 --- /dev/null +++ b/bsp/tkm32F499/rtconfig.h @@ -0,0 +1,189 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define RT_USING_MSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX +#define RT_LIBC_USING_TIME +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + + +/* Hardware Drivers Config */ + +#define SOC_SERIES_TKM32F4 +#define SOC_TKM32F499 + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_USB_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/tkm32F499/rtconfig.py b/bsp/tkm32F499/rtconfig.py new file mode 100644 index 0000000000..4f537ccd48 --- /dev/null +++ b/bsp/tkm32F499/rtconfig.py @@ -0,0 +1,167 @@ +import os +import sys +# toolchains options +CROSS_TOOL = 'gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +# device options +ARCH = 'arm' +CPU = 'cortex-m4' +CROSS_TOOL = 'keil' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:/Keil/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wall' + CFLAGS = DEVICE + ' -std=c99' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + # CC = 'armcc' + # CXX = 'armcc' + # AS = 'armasm' + # AR = 'armar' + # LINK = 'armlink' + # TARGET_EXT = 'axf' + + # DEVICE = ' --cpu Cortex-M4.fp.sp' + # CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + # AFLAGS = DEVICE + ' --apcs=interwork ' + # LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + + # CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + # LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + # CFLAGS += ' -D__MICROLIB ' + # AFLAGS += ' --pd "__MICROLIB SETA 1" ' + # LFLAGS += ' --library_type=microlib ' + # EXEC_PATH += '/ARM/ARMCC/bin/' + + # if BUILD == 'debug': + # CFLAGS += ' -g -O0' + # AFLAGS += ' -g' + # else: + # CFLAGS += ' -O2' + + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp.sp --li' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + CFLAGS += ' -I' + EXEC_PATH + '../Arm/Packs/ARM/CMSIS/5.7.0/Device/ARM/ARMCM4/Include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + # CFLAGS += ' -D__MICROLIB ' + CFLAGS += ' -DARMCM4_FP ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + # LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + # CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' # + ' -D' + PART_TYPE + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "drivers/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + #LFLAGS += ' --silent' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/tkm32F499/template.uvprojx b/bsp/tkm32F499/template.uvprojx new file mode 100644 index 0000000000..82994d0c9d --- /dev/null +++ b/bsp/tkm32F499/template.uvprojx @@ -0,0 +1,406 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 1 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin -o .//@L.bin ./build/@L.axf + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 0 + 1 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "flash_download" (.//@L.bin TK499_V2) + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x70020000 + 0x200000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x70220000 + 0x5dffff + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\drivers\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +