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add tkm32f499 bsp

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NU-LL 2021-10-14 18:50:35 +08:00
parent 92ea0ec8c7
commit 37b29862f6
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2
.gitignore vendored
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@ -38,5 +38,7 @@ ncscope.*
tags
.idea
.vscode
.history
CMakeLists.txt
cmake-build-debug

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bsp/tkm32F499/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "drivers/Kconfig"

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bsp/tkm32F499/Libraries/CMSIS_and_startup/CMSIS/cmsis_armcc.h Normal file
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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;******************** (C) COPYRIGHT 2016 HOLOCENE ********************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
;//============== °æ±¾ EK V1.0 20190801 ==============//
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ;WWDG
DCD 0 ;
DCD TAMPER_IRQHandler ;TAMPER
DCD RTC_IRQHandler ;RTC
DCD 0 ;
DCD RCC_IRQHandler ;RCC
DCD EXTI0_IRQHandler ;EXTI0
DCD EXTI1_IRQHandler ;EXTI1
DCD EXTI2_IRQHandler ;EXTI2
DCD EXTI3_IRQHandler ;EXTI3
DCD EXTI4_IRQHandler ;EXTI4
DCD DMA1_Channel1_IRQHandler ;DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ;DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ;DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ;DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ;DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ;DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ;DMA1 Channel 7
DCD ADC1_IRQHandler ;ADC1
DCD CAN1_IRQHandler ;CAN1
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD EXTI9_5_IRQHandler ;EXTI9_5
DCD TIM1_BRK_IRQHandler ;TIM1_BRK
DCD TIM1_UP_IRQHandler ;TIM1_UP
DCD TIM1_TRG_COM_IRQHandler ;TIM1_TRG_COM
DCD TIM1_CC_IRQHandler ;TIM1_CC
DCD TIM3_IRQHandler ;TIM3
DCD TIM4_IRQHandler ;TIM4
DCD TIM5_IRQHandler ;TIM5
DCD TIM6_IRQHandler ;TIM6
DCD TIM7_IRQHandler ;TIM7
DCD I2C1_IRQHandler ;I2C1
DCD I2C2_IRQHandler ;I2C2
DCD SPI1_IRQHandler ;SPI1
DCD SPI2_IRQHandler ;SPI2
DCD UART1_IRQHandler ;UART1
DCD UART2_IRQHandler ;UART2
DCD UART3_IRQHandler ;UART3
DCD EXTI15_10_IRQHandler ;EXTI15_10
DCD RTCAlarm_IRQHandler ;RTC_ALARM
DCD USBAwake_IRQHandler ;USBAwake
DCD TIM2_BRK_IRQHandler ;TIM2_BRK
DCD TIM2_UP_IRQHandler ;TIM2_UP
DCD TIM2_TRG_COM_IRQHandler ;TIM2_TRG_COM
DCD TIM2_CC_IRQHandler ;TIM2_CC
DCD DMA1_Channel8_IRQHandler ;DMA1
DCD TK80_IRQHandler ;TK80
DCD SDIO1_IRQHandler ;SDIO1
DCD SDIO2_IRQHandler ;SDIO2
DCD SPI3_IRQHandler ;SPI3
DCD UART4_IRQHandler ;UART4
DCD UART5_IRQHandler ;UART5
DCD 0 ;
DCD TIM8_IRQHandler ;TIM8
DCD DMA2_Channel1_IRQHandler ;DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ;DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ;DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ;DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ;DMA2 Channel 5
DCD TIM9_IRQHandler ;TIM9
DCD TIM10_IRQHandler ;TIM10
DCD CAN2_IRQHandler ;CAN2
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD USB_IRQHandler ;USB
DCD DMA2_Channel6_IRQHandler ;DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ;DMA2 Channel 7
DCD DMA2_Channel8_IRQHandler ;DMA2 Channel 8
DCD 0 ;
DCD I2C3_IRQHandler ;I2C3
DCD I2C4_IRQHandler ;I2C4
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD 0 ;
DCD FPU_IRQHandler ;FPU
DCD 0 ;
DCD 0 ;
DCD SPI4_IRQHandler ;SPI4
DCD 0 ;
DCD TOUCHPAD_IRQHandler ;TCHPAD
DCD QSPI_IRQHandler ;QSPI
DCD LTDC_IRQHandler ;LCD-TFT
DCD 0 ;
DCD I2S1_IRQHandler ;I2S1
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
LDR R0, =0xE000ED88 ; ʹÄܸ¡µãÔËËã CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
;IMPORT SystemInit
; LDR R0, =SystemInit
;BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBAwake_IRQHandler [WEAK]
EXPORT TIM2_BRK_IRQHandler [WEAK]
EXPORT TIM2_UP_IRQHandler [WEAK]
EXPORT TIM2_TRG_COM_IRQHandler [WEAK]
EXPORT TIM2_CC_IRQHandler [WEAK]
EXPORT DMA1_Channel8_IRQHandler [WEAK]
EXPORT TK80_IRQHandler [WEAK]
EXPORT SDIO1_IRQHandler [WEAK]
EXPORT SDIO2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM8_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT TIM10_IRQHandler [WEAK]
EXPORT CAN2_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT DMA2_Channel6_IRQHandler [WEAK]
EXPORT DMA2_Channel7_IRQHandler [WEAK]
EXPORT DMA2_Channel8_IRQHandler [WEAK]
EXPORT I2C3_IRQHandler [WEAK]
EXPORT I2C4_IRQHandler [WEAK]
EXPORT TOUCHPAD_IRQHandler [WEAK]
EXPORT SPI4_IRQHandler [WEAK]
EXPORT QSPI_IRQHandler [WEAK]
EXPORT LTDC_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
WWDG_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
CAN1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
TIM5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBAwake_IRQHandler
TIM2_BRK_IRQHandler
TIM2_UP_IRQHandler
TIM2_TRG_COM_IRQHandler
TIM2_CC_IRQHandler
DMA1_Channel8_IRQHandler
TK80_IRQHandler
SDIO1_IRQHandler
SDIO2_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM8_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
TIM9_IRQHandler
TIM10_IRQHandler
CAN2_IRQHandler
USB_IRQHandler
DMA2_Channel6_IRQHandler
DMA2_Channel7_IRQHandler
DMA2_Channel8_IRQHandler
I2C3_IRQHandler
I2C4_IRQHandler
FPU_IRQHandler
SPI4_IRQHandler
QSPI_IRQHandler
TOUCHPAD_IRQHandler
LTDC_IRQHandler
I2S1_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************** (C) COPYRIGHT 2016 HOLOCENE ********************

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#include "sys.h"
#include "HAL_misc.h"
void RemapVtorTable(void)
{
int i;
RCC->AHB1ENR |= 1<<13;//bkp clk,enable sram
//关ROM区中断
for(i = 0;i<90;i++)
{
NVIC_DisableIRQ((IRQn_Type)i);
}
SCB->VTOR = 0;
SCB->VTOR |= 0x1<<29;
for(i = 0;i < 512;i+=4)
*(u32*)(T_SRAM_BASE + i) = *(u32*)(T_SDRAM_BASE+i);
}
void AI_Responder_enable(void)
{
AI_Responder->ADDR1= 0x70807040;
// AI_Responder->ADDR0 = 0x70027080;
AI_Responder->ADDR1 = 0;
AI_Responder->CCR &= ~(0x3<<3);
AI_Responder->CCR |= 1;
while((AI_Responder->SR & 0x3) != 2);
}
void AI_Responder_disable(void)
{
AI_Responder->CCR &= ~1;
}
//外部中断配置函数
//只针对GPIOA~E
//参数:
//GPIOx:0~4,代表GPIOA~E
//BITx:需要使能的位，例如PB12，就填 12;
//TRIM:触发模式,1,下降沿;2,上升沿;3，任意电平触发
//该函数一次只能配置1个IO口,多个IO口,需多次调用
//该函数会自动开启对应中断,以及屏蔽线
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM)
{
u8 EXTOFFSET=(BITx%4)*4;
RCC->APB2ENR|=1<<14; //使能SYSCFG时钟
SYSCFG->EXTICR[BITx/4]&=~(0x000F<<EXTOFFSET);//清除原来设置！！！
SYSCFG->EXTICR[BITx/4]|=GPIOx<<EXTOFFSET; //EXTI.BITx映射到GPIOx.BITx
//自动设置
EXTI->IMR|=1<<BITx; //开启line BITx上的中断(如果要禁止中断，则反操作即可)
if(TRIM&0x01)EXTI->FTSR|=1<<BITx; //line BITx事件下降沿触发
if(TRIM&0x02)EXTI->RTSR|=1<<BITx; //line BITx事件上升沿触发
}
//THUMB指令不支持汇编内联
//采用如下方法实现执行汇编指令WFI
void WFI_SET(void)
{
__ASM volatile("wfi");
}
//关闭所有中断(但是不包括fault和NMI中断)
void INTX_DISABLE(void)
{
__ASM volatile("cpsid i");
}
//开启所有中断
void INTX_ENABLE(void)
{
__ASM volatile("cpsie i");
}
//设置栈顶地址 __set_MSP(0x70002000);
//进入待机模式
void Sys_Standby(void)
{
SCB->SCR|=1<<2; //使能SLEEPDEEP位 (SYS->CTRL)
RCC->APB1ENR|=1<<28;//使能电源时钟
PWR->CSR|=1<<8; //设置WKUP用于唤醒
PWR->CR|=1<<2; //清除Wake-up 标志
PWR->CR|=1<<1; //PDDS置位
WFI_SET(); //执行WFI指令,进入待机模式
}
//系统软复位
void Sys_Soft_Reset(void)
{
SCB->AIRCR =0X05FA0000|(u32)0x04;
}
// TK499_NVIC_Init(2,2,TK80_IRQn,2);
//设置NVIC
//NVIC_PreemptionPriority:抢占优先级
//NVIC_SubPriority :响应优先级
//NVIC_Channel :中断编号
//NVIC_Group :中断分组 0~4
//注意优先级不能超过设定的组的范围!否则会有意想不到的错误
//组划分:
//组0:0位抢占优先级,4位响应优先级
//组1:1位抢占优先级,3位响应优先级
//组2:2位抢占优先级,2位响应优先级
//组3:3位抢占优先级,1位响应优先级
//组4:4位抢占优先级,0位响应优先级
//NVIC_SubPriority和NVIC_PreemptionPriority的原则是,数值越小,越优先
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group)
{
u32 temp;
NVIC_SetPriorityGrouping(NVIC_Group);//设置分组
temp=NVIC_PreemptionPriority<<(4-NVIC_Group);
temp|=NVIC_SubPriority&(0x0f>>NVIC_Group);
temp&=0xf; //取低四位
NVIC->ISER[NVIC_Channel/32]|=1<<NVIC_Channel%32;//使能中断位(要清除的话,设置ICER对应位为1即可)
NVIC->IP[NVIC_Channel]|=temp<<4; //设置响应优先级和抢断优先级
}
void TK80_IRQHandler(void)
{
if(TK80->SR & 0x1)
{
}
if(TK80->SR & 0x2)
{
}
if(TK80->SR & 0x4)
{
}
if(TK80->SR & 0x8)
{
}
TK80->SR |= 0;
}
//备用函数
//#define T_SRAM_FUN1 0x20000400
//copyAtoB((u32)LCD_PutPixel&0xFFFFFFFE,T_SRAM_FUN1,800);//加载函数到SRAM
//void copyAtoB(u32 srcAdd,u32 dstAdd,u16 len)
//{
// len = (len + 3)/4;
// while(len--)
// {
// *(u32*)dstAdd = *(u32*)srcAdd;
// dstAdd += 4 ;
// srcAdd +=4 ;
// }
//}

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#ifndef __SYS_H
#define __SYS_H
#include "tk499.h"
#include "HAL_conf.h"
//位带操作,实现51类似的GPIO控制功能
//具体实现思想,参考<<CM3权威指南>>第五章(87页~92页).M4同M3类似,只是寄存器地址变了.
//IO口操作宏定义
//#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2))
//#define MEM_ADDR(addr) *((volatile unsigned long *)(addr))
//#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum))
void RemapVtorTable(void);
void AI_Responder_enable(void);
void AI_Responder_disable(void);
void Sys_Soft_Reset(void); //系统软复位
void Sys_Standby(void); //待机模式
void TK499_NVIC_Init(u8 NVIC_PreemptionPriority,u8 NVIC_SubPriority,u8 NVIC_Channel,u8 NVIC_Group);
void Ex_NVIC_Config(u8 GPIOx,u8 BITx,u8 TRIM); //外部中断配置函数(只对GPIOA~I)
//以下为汇编函数
void WFI_SET(void); //执行WFI指令
void INTX_DISABLE(void);//关闭所有中断
void INTX_ENABLE(void); //开启所有中断
void TIM3_Config(u16 arr,u16 psc);
#endif

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/**
******************************************************************************
* @file HAL_adc.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_ADC_H
#define __HAL_ADC_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_Exported_Types
* @{
*/
/**
* @brief ADC Init structure definition
*/
/*
typedef struct
{
uint32_t ADC_Mode;
FunctionalState ADC_ScanConvMode;
FunctionalState ADC_ContinuousConvMode;
uint32_t ADC_ExternalTrigConv;
uint32_t ADC_DataAlign;
uint8_t ADC_NbrOfChannel;
}ADC_InitTypeDef;
*/
typedef struct
{
uint32_t ADC_Resolution;
uint32_t ADC_PRESCARE;
uint32_t ADC_Mode;
FunctionalState ADC_ContinuousConvMode;
uint32_t ADC_TRGEN;
uint32_t ADC_ExternalTrigConv;
uint32_t ADC_DataAlign;
}ADC_InitTypeDef;
/**
* @}
*/
/** @defgroup ADC_Exported_Constants
* @{
*/
#define IS_ADC_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
((*(uint32_t*)&(PERIPH)) == ADC2_BASE))
#define IS_ADC_DMA_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
((*(uint32_t*)&(PERIPH)) == ADC2_BASE))
/** @defgroup ADC_Resolution
* @{
*/
#define ADC_Resolution_12b ((uint32_t)0x00000000)
#define ADC_Resolution_11b ((uint32_t)0x00000080)
#define ADC_Resolution_10b ((uint32_t)0x00000100)
#define ADC_Resolution_9b ((uint32_t)0x00000180)
#define ADC_Resolution_8b ((uint32_t)0x00000200)
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
((RESOLUTION) == ADC_Resolution_10b) || \
((RESOLUTION) == ADC_Resolution_8b) || \
((RESOLUTION) == ADC_Resolution_6b))
/**
* @brief for ADC1, ADC2
*/
#define ADC_PCLK2_PRESCARE_2 ((uint32_t)0x00000000)
#define ADC_PCLK2_PRESCARE_4 ((uint32_t)0x00000010)
#define ADC_PCLK2_PRESCARE_6 ((uint32_t)0x00000020)
#define ADC_PCLK2_PRESCARE_8 ((uint32_t)0x00000030)
#define ADC_PCLK2_PRESCARE_10 ((uint32_t)0x00000040)
#define ADC_PCLK2_PRESCARE_12 ((uint32_t)0x00000050)
#define ADC_PCLK2_PRESCARE_14 ((uint32_t)0x00000060)
#define ADC_PCLK2_PRESCARE_16 ((uint32_t)0x00000070)
/** @defgroup ADC_dual_mode
* @{
*/
#define ADC_Mode_Single ((uint32_t)0x00000000)
#define ADC_Mode_Single_Period ((uint32_t)0x00000200)
#define ADC_Mode_Continuous_Scan ((uint32_t)0x00000400)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Single) || \
((MODE) == ADC_Mode_Single_Period) || \
((MODE) == ADC_Mode_Continuous_Scan))
/**
* @}
*/
#define ADC_TRG_Disable ((uint32_t)0xfffffffB)
#define ADC_TRG_Enable ((uint32_t)0x00000004)
/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
* @{
*/
/**
* @brief for ADC1
*/
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00000010)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00000020)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00000030)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00000040)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x00000050)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060)
#define ADC_ExternalTrigConv_EXTI_11 ((uint32_t)0x00000070)
/**
* @brief for ADC2
*/
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC4 ((uint32_t)0x00000010)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00000020)
#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00000030)
#define ADC_ExternalTrigConv_T3_CC4 ((uint32_t)0x00000040)
#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x00000050)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000060)
#define ADC_ExternalTrigConv_EXTI_15 ((uint32_t)0x00000070)
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_EXTI_11) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T1_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T2_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \
((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
((REGTRIG) == ADC_ExternalTrigConv_EXTI_15))
/**
* @}
*/
/** @defgroup ADC_data_align
* @{
*/
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
((ALIGN) == ADC_DataAlign_Left))
/**
* @}
*/
/** @defgroup ADC_channels
* @{
*/
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_All ((uint8_t)0x0f)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All))
/**
* @}
*/
/**
* @}
*/
#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
/** @defgroup ADC_sampling_times
* @{
*/
#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
((TIME) == ADC_SampleTime_7_5Cycles) || \
((TIME) == ADC_SampleTime_13_5Cycles) || \
((TIME) == ADC_SampleTime_28_5Cycles) || \
((TIME) == ADC_SampleTime_41_5Cycles) || \
((TIME) == ADC_SampleTime_55_5Cycles) || \
((TIME) == ADC_SampleTime_71_5Cycles) || \
((TIME) == ADC_SampleTime_239_5Cycles))
/** @defgroup ADC_injected_channel_selection
* @{
*/
#define ADC_InjectedChannel_0 ((uint8_t)0x18)
#define ADC_InjectedChannel_1 ((uint8_t)0x1C)
#define ADC_InjectedChannel_2 ((uint8_t)0x20)
#define ADC_InjectedChannel_3 ((uint8_t)0x24)
#define ADC_InjectedChannel_4 ((uint8_t)0x28)
#define ADC_InjectedChannel_5 ((uint8_t)0x2C)
#define ADC_InjectedChannel_6 ((uint8_t)0x30)
#define ADC_InjectedChannel_7 ((uint8_t)0x34)
#define ADC_InjectedChannel_8 ((uint8_t)0x38)
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
((CHANNEL) == ADC_InjectedChannel_2) || \
((CHANNEL) == ADC_InjectedChannel_3) || \
((CHANNEL) == ADC_InjectedChannel_4) || \
((CHANNEL) == ADC_InjectedChannel_5) || \
((CHANNEL) == ADC_InjectedChannel_6) || \
((CHANNEL) == ADC_InjectedChannel_7) || \
((CHANNEL) == ADC_InjectedChannel_8))
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_selection
* @{
*/
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00000002)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
((WATCHDOG) == ADC_AnalogWatchdog_None))
/**
* @}
*/
/** @defgroup ADC_interrupts_definition
* @{
*/
#define ADC_IT_EOC ((uint16_t)0x0001)
#define ADC_IT_AWD ((uint16_t)0x0002)
#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFFFC) == 0x00) && ((IT) != 0x00))
#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD))
/**
* @}
*/
/** @defgroup ADC_flags_definition
* @{
*/
#define ADC_FLAG_AWD ((uint8_t)0x02) //ADWIF ±È½Ï±ê־λ
#define ADC_FLAG_EOC ((uint8_t)0x01) //ADIF ת»»½áÊø±ê־λ
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF0) == 0x00) && ((FLAG) != 0x00))
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC))
/**
* @}
*/
/** @defgroup ADC_thresholds
* @{
*/
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_offset
* @{
*/
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
/**
* @}
*/
/** @defgroup ADC_injected_length
* @{
*/
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_injected_rank
* @{
*/
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
/**
* @}
*/
/** @defgroup ADC_regular_length
* @{
*/
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_rank
* @{
*/
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
/**
* @}
*/
/** @defgroup ADC_regular_discontinuous_mode_number
* @{
*/
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup ADC_Exported_Functions
* @{
*/
void ADC_DeInit(ADC_TypeDef* ADCx);
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
#endif /*__HAL_ADC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_can.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the CAN firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_CAN_H
#define __HAL_CAN_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @defgroup CAN_sleep_constants
* @{
*/
#define CANINITFAILED ((uint8_t)0x00) /* CAN initialization failed */
#define CANINITOK ((uint8_t)0x01) /* CAN initialization ok */
/**
* @}
*/
/** @defgroup CAN_sleep_constants
* @{
*/
#define CANSLEEPFAILED ((uint8_t)0x00) /* CAN did not enter the sleep mode */
#define CANSLEEPOK ((uint8_t)0x01) /* CAN entered the sleep mode */
/**
* @}
*/
/** @defgroup CAN_wake_up_constants
* @{
*/
#define CANWAKEUPFAILED ((uint8_t)0x00) /* CAN did not leave the sleep mode */
#define CANWAKEUPOK ((uint8_t)0x01) /* CAN leaved the sleep mode */
/**
* @}
*/
/**
* @brief parasmeter of CAN Mode
*/
#define CAN_BASICMode ((uint32_t)0x0)
#define CAN_PELIMode ((uint32_t)0x80)
#define CAN_WorkMode ((uint32_t)0x80)
#define CAN_ResetMode ((uint32_t)0x1)
#define CAN_ListenOnlyMode ((uint32_t)0x2)
#define CAN_SeftTestMode ((uint32_t)0x4)
#define CAN_FilterMode_Singal ((uint32_t)0x8)
#define CAN_FilterMode_Double ((uint32_t)0xf7)
#define CAN_SleepMode ((uint32_t)0x10)
/**
* @}
*/
/**
* @brief parasmeter of BASIC CAN interrupt
*/
#define CAN_IT_RIE ((uint32_t)0x2)
#define CAN_IT_TIE ((uint32_t)0x4)
#define CAN_IT_EIE ((uint32_t)0x8)
#define CAN_IT_OIE ((uint32_t)0x10)
/**
* @}
*/
/**
* @brief parasmeter of PELI CAN interrupt
*/
#define CAN_IT_RI ((uint32_t)0x1)
#define CAN_IT_TI ((uint32_t)0x2)
#define CAN_IT_EI ((uint32_t)0x4)
#define CAN_IT_DOI ((uint32_t)0x8)
#define CAN_IT_WUI ((uint32_t)0x10)
#define CAN_IT_EPI ((uint32_t)0x20)
#define CAN_IT_ALI ((uint32_t)0x40)
#define CAN_IT_BEI ((uint32_t)0x80)
#define CAN_IT_ALL ((uint32_t)0xff)
/**
* @}
*/
/**
* @brief parasmeter of CAN Status
*/
#define CAN_STATUS_RBS ((uint32_t)0x1)
#define CAN_STATUS_DOS ((uint32_t)0x2)
#define CAN_STATUS_TBS ((uint32_t)0x4)
#define CAN_STATUS_TCS ((uint32_t)0x8)
#define CAN_STATUS_RS ((uint32_t)0x10)
#define CAN_STATUS_TS ((uint32_t)0x20)
#define CAN_STATUS_ES ((uint32_t)0x40)
#define CAN_STATUS_BS ((uint32_t)0x80)
/**
* @}
*/
/**
* @brief parasmeter of CAN Command register
*/
#define CAN_TR 0x1
#define CAN_AT 0x2
#define CAN_RRB 0x4
#define CAN_CDO 0x8
/**
* @}
*/
/**
* @brief CAN_Basic init structure definition
*/
typedef struct
{
uint8_t SJW;
uint8_t BRP;
FlagStatus SAM;
uint8_t TESG2;
uint8_t TESG1;
FunctionalState GTS;
uint8_t CDCLK;
uint8_t CLOSE_OPEN_CLK;
uint8_t RXINTEN;
uint8_t CBP;
} CAN_Basic_InitTypeDef;
/**
* @}
*/
/**
* @brief CAN_Peli init structure definition
*/
typedef struct
{
uint8_t SJW;
uint8_t BRP;
FlagStatus SAM;
uint8_t TESG2;
uint8_t TESG1;
FunctionalState LOM;
FunctionalState STM;
FunctionalState SM;
FunctionalState SRR;
uint32_t EWLR;
} CAN_Peli_InitTypeDef;
/**
* @}
*/
/**
* @brief CAN_Basic filter init structure definition
*/
typedef struct
{
uint8_t CAN_FilterId; /*!< Specifies the filter identification number .
This parameter can be a value between 0x00 and 0xFF */
uint8_t CAN_FilterMaskId; /*!< Specifies the filter mask number or identification number,
This parameter can be a value between 0x00 and 0xFF */
} CAN_Basic_FilterInitTypeDef;
/**
* @}
*/
/**
* @brief CAN_Peli filter init structure definition
*/
typedef struct
{
uint8_t AFM;
uint8_t CAN_FilterId0; /*!< Specifies the filter identification number
This parameter can be a value between 0x00 and 0xFF */
uint8_t CAN_FilterId1;
uint8_t CAN_FilterId2;
uint8_t CAN_FilterId3;
uint8_t CAN_FilterMaskId0; /*!< Specifies the filter mask number or identification number,
This parameter can be a value between 0x00 and 0xFF */
uint8_t CAN_FilterMaskId1;
uint8_t CAN_FilterMaskId2;
uint8_t CAN_FilterMaskId3;
} CAN_Peli_FilterInitTypeDef;
/**
* @}
*/
/**
* @brief CAN_Peli transmit frame definition
*/
typedef enum {DataFrame = 0, RemoteFrame = !DataFrame} TransFrame;
/**
* @}
*/
/**
* @brief CAN_Basic Tx message structure definition
*/
typedef struct
{
uint8_t IDH; /*!< Specifies the standard high identifier.
This parameter can be a value between 0 to 0xFF. */
uint8_t IDL; /*!< Specifies the standard low identifier.
This parameter can be a value between 0 to 0x7. */
uint8_t RTR; /*!< Specifies the type of frame for the message that will
be transmitted. This parameter can be @TransFrame */
uint8_t DLC; /*!< Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanBasicTxMsg;
/**
* @}
*/
/**
* @brief CAN_Basic Rx message structure definition
*/
typedef struct
{
uint16_t ID; /*!< Specifies the standard identifier.
This parameter can be a value between 0 to 0x7FF. */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of
@ref TransFrame */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
0xFF. */
} CanBasicRxMsg;
/**
* @}
*/
/**
* @brief CAN_Peli_Tx message structure definition
*/
typedef struct
{
uint8_t IDLL; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0xFF. */
uint8_t IDLH;
uint8_t IDHL;
uint8_t IDHH;
uint8_t FF; /*!< Specifies the type of identifier for the message that
will be transmitted. This parameter can be a value
of @ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the message that will
be transmitted. This parameter can be a value of
@ref TransFrame */
uint8_t DLC; /*!< Specifies the length of the frame that will be
transmitted. This parameter can be a value between
0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
to 0xFF. */
} CanPeliTxMsg;
/**
* @}
*/
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t ID; /*!< Specifies the extended identifier.
This parameter can be a value between 0 to 0x1FFFFFFF. */
uint8_t FF; /*!< Specifies the type of identifier for the message that
will be received. This parameter can be a value of
@ref CAN_identifier_type */
uint8_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of
@ref TransFrame */
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter can be a value between 0 to 8 */
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
0xFF. */
} CanPeliRxMsg;
#define CANTXFAILED ((uint8_t)0x00) /* CAN transmission failed */
#define CANTXOK ((uint8_t)0x01) /* CAN transmission succeeded */
#define CANTXPENDING ((uint8_t)0x02) /* CAN transmission pending */
#define CAN_NO_MB ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
/************************ Basic and Peli Work all need function ********************/
void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE);
void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_ClearDataOverflow(CAN_TypeDef* CANx);
void CAN_ClearITPendingBit(CAN_TypeDef* CANx);
/************************ Basic Work function ********************/
void CAN_DeInit(CAN_TypeDef* CANx);
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct);
void CAN_FilterInit(CAN_TypeDef* CANx, CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct);
void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct);
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate);
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage);
void CAN_CancelTransmit(CAN_TypeDef* CANx);
void CAN_FIFORelease(CAN_TypeDef* CANx);
void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage);
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
/************************ Peli Work function *********************/
void CAN_Peli_SleepMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_Peli_Init(CAN_TypeDef* CANx, CAN_Peli_InitTypeDef* CAN_Peli_InitStruct);
void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct);
void CAN_Peli_FilterInit(CAN_TypeDef* CANx, CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct);
void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct);
void CAN_Peli_Transmit(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage);
void CAN_Peli_TransmitRepeat(CAN_TypeDef* CANx, CanPeliTxMsg* PeliTxMessage);
void CAN_Peli_Receive(CAN_TypeDef* CANx, CanPeliRxMsg* PeliRxMessage);
uint32_t CAN_Peli_GetRxFIFOInfo(CAN_TypeDef* CANx);
uint8_t CAN_Peli_GetLastErrorCode(CAN_TypeDef* CANx);
uint8_t CAN_Peli_GetReceiveErrorCounter(CAN_TypeDef* CANx);
uint8_t CAN_Peli_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
void CAN_Peli_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
ITStatus CAN_Peli_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud );
#endif /* __HAL_CAN_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_conf.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains Header file for generic microcontroller.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
#ifndef __HAL_CONF_H__
#define __HAL_CONF_H__
/*´Ë´¦¿ÉÌí¼Ó»òɾ³ýÍâÉè*/
#include "HAL_device.h"
#include "HAL_adc.h"
#include "HAL_dma.h"
#include "HAL_exti.h"
#include "HAL_flash.h"
#include "HAL_gpio.h"
#include "HAL_i2c.h"
#include "HAL_iwdg.h"
#include "HAL_pwr.h"
#include "HAL_rcc.h"
#include "HAL_spi.h"
#include "HAL_tim.h"
#include "HAL_uart.h"
#include "HAL_wwdg.h"
#include "HAL_misc.h"
#include "HAL_syscfg.h"
#include "HAL_can.h"
#endif
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**************************************************************************//**
* @file HAL_device.h
* @brief CMSIS Cortex-M Peripheral Access Layer for HOLOCENE
* microcontroller devices
*
* This is a convenience header file for defining the part number on the
* build command line, instead of specifying the part specific header file.
*
* Example: Add "-TKM32F499" to your build options, to define part
* Add "#include "HAL_device.h" to your source files
*
*
* @version 1.5.0
*
*
*****************************************************************************/
#ifndef __HAL_device_H
#define __HAL_device_H
#include "tk499.h"
#endif /* __HAL_device_H */
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_dma.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_DMA_H
#define __HAL_DMA_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_Exported_Types
* @{
*/
/**
* @brief DMA Init structure definition
*/
typedef struct
{
uint32_t DMA_PeripheralBaseAddr;
uint32_t DMA_MemoryBaseAddr;
uint32_t DMA_DIR;
uint32_t DMA_BufferSize;
uint32_t DMA_PeripheralInc;
uint32_t DMA_MemoryInc;
uint32_t DMA_PeripheralDataSize;
uint32_t DMA_MemoryDataSize;
uint32_t DMA_Mode;
uint32_t DMA_Priority;
uint32_t DMA_M2M;
}DMA_InitTypeDef;
/**
* @}
*/
/** @defgroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \
((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \
((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE) || \
((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE) || \
((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE))
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) //mtop
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) //ptom
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
((DIR) == DMA_DIR_PeripheralSRC))
/**
* @}
*/
/** @defgroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
((STATE) == DMA_PeripheralInc_Disable))
/**
* @}
*/
/** @defgroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
((STATE) == DMA_MemoryInc_Disable))
/**
* @}
*/
/** @defgroup DMA_peripheral_data_size
* @{
*/
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
((SIZE) == DMA_PeripheralDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/** @defgroup DMA_circular_normal_mode
* @{
*/
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
/**
* @}
*/
/** @defgroup DMA_priority_level
* @{
*/
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
((PRIORITY) == DMA_Priority_High) || \
((PRIORITY) == DMA_Priority_Medium) || \
((PRIORITY) == DMA_Priority_Low))
/**
* @}
*/
/** @defgroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
/**
* @}
*/
/** @defgroup DMA_interrupts_definition
* @{
*/
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
/**
* @brief For DMA1
*/
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
#define DMA2_IT_GL6 ((uint32_t)0x10100000)
#define DMA2_IT_TC6 ((uint32_t)0x10200000)
#define DMA2_IT_HT6 ((uint32_t)0x10400000)
#define DMA2_IT_TE6 ((uint32_t)0x10800000)
#define DMA2_IT_GL7 ((uint32_t)0x11000000)
#define DMA2_IT_TC7 ((uint32_t)0x12000000)
#define DMA2_IT_HT7 ((uint32_t)0x14000000)
#define DMA2_IT_TE7 ((uint32_t)0x18000000)
#define DMA2_IT_GL8 ((uint32_t)0x10000001)
#define DMA2_IT_TC8 ((uint32_t)0x20000001)
#define DMA2_IT_HT8 ((uint32_t)0x40000001)
#define DMA2_IT_TE8 ((uint32_t)0x80000001)
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
/**
* @}
*/
/** @defgroup DMA_flags_definition
* @{
*/
/**
* @brief For DMA1
*/
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
#define DMA2_FLAG_GL6 ((uint32_t)0x10100000)
#define DMA2_FLAG_TC6 ((uint32_t)0x10200000)
#define DMA2_FLAG_HT6 ((uint32_t)0x10400000)
#define DMA2_FLAG_TE6 ((uint32_t)0x10800000)
#define DMA2_FLAG_GL7 ((uint32_t)0x11000000)
#define DMA2_FLAG_TC7 ((uint32_t)0x12000000)
#define DMA2_FLAG_HT7 ((uint32_t)0x14000000)
#define DMA2_FLAG_TE7 ((uint32_t)0x18000000)
#define DMA2_FLAG_GL8 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC8 ((uint32_t)0x20000001)
#define DMA2_FLAG_HT8 ((uint32_t)0x40000001)
#define DMA2_FLAG_TE8 ((uint32_t)0x80000001)
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
/**
* @}
*/
/** @defgroup DMA_Buffer_Size
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/**
* @}
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Exported_Functions
* @{
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
void DMA_ClearFlag(uint32_t DMA_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMA_IT);
void DMA_ClearITPendingBit(uint32_t DMA_IT);
#endif /*__HAL_DMA_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*------------------ (C) COPYRIGHT 2016 HOLOCENE ------------------*/

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/**
******************************************************************************
* @file HAL_exti.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the EXTI
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_EXTI_H
#define __HAL_EXTI_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line;
EXTIMode_TypeDef EXTI_Mode;
EXTITrigger_TypeDef EXTI_Trigger;
FunctionalState EXTI_LineCmd;
}EXTI_InitTypeDef;
/**
* @}
*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16
Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17
Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18
Connected to the USB Wakeup from
suspend event */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18))
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#endif /* __HAL_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_flash.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_FLASH_H
#define __HAL_FLASH_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_Exported_Types
* @{
*/
/**
* @brief FLASH Status
*/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
}FLASH_Status;
/**
* @}
*/
/** @defgroup FLASH_Exported_Constants
* @{
*/
/** @defgroup Flash_Latency
* @{
*/
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
#define FLASH_Latency_3 ((uint32_t)0x00000003) /* FLASH Three Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((LATENCY) == FLASH_Latency_1) || \
((LATENCY) == FLASH_Latency_2) || \
((LATENCY) == FLASH_Latency_3))
/**
* @}
*/
/** @defgroup Half_Cycle_Enable_Disable
* @{
*/
#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
((STATE) == FLASH_HalfCycleAccess_Disable))
/**
* @}
*/
/** @defgroup Prefetch_Buffer_Enable_Disable
* @{
*/
#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
((STATE) == FLASH_PrefetchBuffer_Disable))
/**
* @}
*/
/** @defgroup Option_Bytes_Write_Protection
* @{
*/
/* Values to be used with microcontroller Medium-density devices: FLASH memory density
ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */
#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */
#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */
#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */
#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */
#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */
#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */
#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */
#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */
#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */
#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */
#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */
#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */
#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */
#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */
#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */
/* Values to be used with microcontroller High-density devices: FLASH memory density
ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
/**
* @}
*/
/** @defgroup Option_Bytes_IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STOP
* @{
*/
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
/**
* @}
*/
/** @defgroup Option_Bytes_nRST_STDBY
* @{
*/
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
*/
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
/**
* @}
*/
/** @defgroup FLASH_Flags
* @{
*/
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
((FLAG) == FLASH_FLAG_OPTERR))
/**
* @}
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions
* @{
*/
void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
FlagStatus FLASH_GetPrefetchBufferStatus(void);
void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
void FLASH_ClearFlag(uint16_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
#endif /* __HAL_FLASH_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_gpio.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_GPIO_H
#define __HAL_GPIO_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/** @defgroup GPIO_Exported_Types
* @{
*/
#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || \
((*(uint32_t*)&(PERIPH)) == GPIOG_BASE))
/**
* @brief Output Maximum frequency selection
*/
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
}GPIOSpeed_TypeDef;
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
((SPEED) == GPIO_Speed_50MHz))
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_AIN = 0x0, //模拟输入
GPIO_Mode_IN_FLOATING = 0x04, //浮空输入
GPIO_Mode_IPD = 0x28, //下拉输入
GPIO_Mode_IPU = 0x48, //上拉输入
GPIO_Mode_Out_OD = 0x14,//通用开漏输出
GPIO_Mode_Out_PP = 0x10,//通用推免输出
GPIO_Mode_AF_OD = 0x1C, // 复用开漏输出
GPIO_Mode_AF_PP = 0x18 //复用推免输出
}GPIOMode_TypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin;
GPIOSpeed_TypeDef GPIO_Speed;
GPIOMode_TypeDef GPIO_Mode;
}GPIO_InitTypeDef;
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
/**
* @}
*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */
#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */
#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */
#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */
#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */
#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */
#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */
#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */
#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
/** @defgroup GPIO_Remap_define
* @{
*/
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_UART1 ((uint32_t)0x00000004) /* UART1 Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
((REMAP) == GPIO_Remap_UART1) || ((REMAP) == GPIO_PartialRemap_TIM1) || \
((REMAP) == GPIO_FullRemap_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) ||\
((REMAP) == GPIO_PartialRemap2_TIM2) || ((REMAP) == GPIO_FullRemap_TIM2) || \
((REMAP) == GPIO_PartialRemap_TIM3) || ((REMAP) == GPIO_FullRemap_TIM3) ||\
((REMAP) == GPIO_Remap_TIM4) || ((REMAP) == GPIO_Remap_PD01) || \
((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
((REMAP) == GPIO_Remap_SWJ_Disable))
/**
* @}
*/
/**
* @}
*/
/** @defgroup GPIO_Alternate_function_selection_define
* @{
*/
#define GPIO_AF_MCO_SW ((uint8_t)0x00) /* MC0, SWDIO,SWCLK */
#define GPIO_AF_TIM_1_2 ((uint8_t)0x01) /* TIM 1/2 */
#define GPIO_AF_TIM_34567 ((uint8_t)0x02) /* TIM 3/4/5/6/7 */
#define GPIO_AF_I2S ((uint8_t)0x03)
#define GPIO_AF_I2C ((uint8_t)0x04) /* I2C 1/2/3 */
#define GPIO_AF_SPI ((uint8_t)0x05) /* SPI 1/2/3/4 */
#define GPIO_AF_QSPI ((uint8_t)0x06)
#define GPIO_AF_UART_2345 ((uint8_t)0x07) /* UART 2/3/4/5 */
#define GPIO_AF_UART_1 ((uint8_t)0x08)
#define GPIO_AF_CAN ((uint8_t)0x09) /* CAN 1/2 */
#define GPIO_AF_USB ((uint8_t)0x0A)
#define GPIO_AF_GPIO ((uint8_t)0x0B) /* Normal GPIO */
#define GPIO_AF_TK80_SDIO ((uint8_t)0x0C) /* TK80 SDIO 1/2 */
#define GPIO_AF_Touchpad ((uint8_t)0x0D)
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* RGB_LTDC AF */
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
/**
* @}
*/
/** @defgroup GPIO_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF);
#endif /* __HAL_GPIO_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_i2c.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_I2C_H
#define __HAL_I2C_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/** @defgroup I2C_Exported_Types
* @{
*/
/**
* @brief I2C Init structure definition
*/
/*
typedef struct
{
uint16_t I2C_Mode;
uint16_t I2C_DutyCycle;
uint16_t I2C_OwnAddress1;
uint16_t I2C_Ack;
uint16_t I2C_AcknowledgedAddress;
uint32_t I2C_ClockSpeed;
}I2C_InitTypeDef;
*/
typedef struct
{
uint16_t I2C_Mode;
uint16_t I2C_Speed;
uint16_t I2C_OwnAddress;
uint32_t I2C_ClockSpeed;
}I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup I2C_Exported_Constants
* @{
*/
#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \
((*(uint32_t*)&(PERIPH)) == I2C2_BASE))
/** @defgroup I2C_modes
* @{
*/
#define TX_EMPTY_CTRL (0x0001<<8)
#define IC_SLAVE_DISABLE (0x0001<<6)
#define IC_SLAVE_ENABLE (0x0000<<6)
#define IC_RESTART_EN (0x0001<<5)
#define IC_7BITADDR_MASTER (0x0000<<4)
#define IC_7BITADDR_SLAVE (0x0000<<3)
#define I2C_Speed_STANDARD ((uint16_t)0x0002)
#define I2C_Speed_FAST ((uint16_t)0x0004)
#define I2C_Mode_MASTER ((uint16_t)0x0001)
#define I2C_Mode_SLAVE ((uint16_t)0x0000)
#define TDMAE_SET ((uint16_t)0x0002)
#define RDMAE_SET ((uint16_t)0x0001)
#define CMD_READ ((uint16_t)0x0100)
#define CMD_WRITE ((uint16_t)0x0000)
#define I2C_Mode_I2C ((uint16_t)0x0000)
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C))
/**
* @}
*/
/** @defgroup I2C_transfer_direction
* @{
*/
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01)
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
((DIRECTION) == I2C_Direction_Receiver))
/**
* @}
*/
/** @defgroup I2C_acknowledged_address_defines
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup I2C_interrupts_definition
* @{
*/
#define I2C_IT_RX_UNDER ((uint16_t)0x0001)
#define I2C_IT_RX_OVER ((uint16_t)0x0002)
#define I2C_IT_RX_FULL ((uint16_t)0x0004)
#define I2C_IT_TX_OVER ((uint16_t)0x0008)
#define I2C_IT_TX_EMPTY ((uint16_t)0x0010)
#define I2C_IT_RD_REQ ((uint16_t)0x0020)
#define I2C_IT_TX_ABRT ((uint16_t)0x0040)
#define I2C_IT_RX_DONE ((uint16_t)0x0080)
#define I2C_IT_ACTIVITY ((uint16_t)0x0100)
#define I2C_IT_STOP_DET ((uint16_t)0x0200)
#define I2C_IT_START_DET ((uint16_t)0x0400)
#define I2C_IT_GEN_CALL ((uint16_t)0x0800)
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || \
((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || \
((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || \
((IT) == I2C_IT_TX_ABRT) || ((IT) == I2C_IT_RX_DONE) || \
((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || \
((IT) == I2C_IT_START_DET) || ((IT) == I2C_IT_GEN_CALL))
/**
* @}
*/
/** @defgroup I2C_flags_definition
* @{
*/
#define I2C_FLAG_RX_UNDER ((uint16_t)0x0001)
#define I2C_FLAG_RX_OVER ((uint16_t)0x0002)
#define I2C_FLAG_RX_FULL ((uint16_t)0x0004)
#define I2C_FLAG_TX_OVER ((uint16_t)0x0008)
#define I2C_FLAG_TX_EMPTY ((uint16_t)0x0010)
#define I2C_FLAG_RD_REQ ((uint16_t)0x0020)
#define I2C_FLAG_TX_ABRT ((uint16_t)0x0040)
#define I2C_FLAG_RX_DONE ((uint16_t)0x0080)
#define I2C_FLAG_ACTIVITY ((uint16_t)0x0100)
#define I2C_FLAG_STOP_DET ((uint16_t)0x0200)
#define I2C_FLAG_START_DET ((uint16_t)0x0400)
#define I2C_FLAG_GEN_CALL ((uint16_t)0x0800)
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF000) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_RX_UNDER) || ((FLAG) == I2C_FLAG_RX_OVER) || \
((FLAG) == I2C_FLAG_RX_FULL) || ((FLAG) == I2C_FLAG_TX_OVER) || \
((FLAG) == I2C_FLAG_TX_EMPTY) || ((FLAG) == I2C_FLAG_RD_REQ) || \
((FLAG) == I2C_FLAG_TX_ABRT) || ((FLAG) == I2C_FLAG_RX_DONE) || \
((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_STOP_DET) || \
((FLAG) == I2C_FLAG_START_DET) || ((FLAG) == I2C_FLAG_GEN_CALL))
/** @defgroup I2C_Statusflags_definition
* @{
*/
#define I2C_STATUS_FLAG_ACTIVITY ((uint16_t)0x0001)
#define I2C_STATUS_FLAG_TFNF ((uint16_t)0x0002)
#define I2C_STATUS_FLAG_TFE ((uint16_t)0x0004)
#define I2C_STATUS_FLAG_RFNE ((uint16_t)0x0008)
#define I2C_STATUS_FLAG_RFF ((uint16_t)0x0010)
#define I2C_STATUS_FLAG_M_ACTIVITY ((uint16_t)0x0020)
#define I2C_STATUS_FLAG_S_ACTIVITY ((uint16_t)0x0040)
/**
* @}
*/
/** @defgroup I2C_Events
* @{
*/
#define I2C_EVENT_RX_UNDER ((uint32_t)0x0001)
#define I2C_EVENT_RX_OVER ((uint32_t)0x0002)
#define I2C_EVENT_RX_FULL ((uint32_t)0x0004)
#define I2C_EVENT_TX_OVER ((uint32_t)0x0008)
#define I2C_EVENT_TX_EMPTY ((uint32_t)0x0010)
#define I2C_EVENT_RD_REQ ((uint32_t)0x0020)
#define I2C_EVENT_TX_ABRT ((uint32_t)0x0040)
#define I2C_EVENT_RX_DONE ((uint32_t)0x0080)
#define I2C_EVENT_ACTIVITY ((uint32_t)0x0100)
#define I2C_EVENT_STOP_DET ((uint32_t)0x0200)
#define I2C_EVENT_START_DET ((uint32_t)0x0400)
#define I2C_EVENT_GEN_CALL ((uint32_t)0x0800)
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_RX_UNDER) || \
((EVENT) == I2C_EVENT_RX_OVER) || \
((EVENT) == I2C_EVENT_RX_FULL) || \
((EVENT) == I2C_EVENT_TX_OVER) || \
((EVENT) == I2C_EVENT_RD_REQ) || \
((EVENT) == I2C_EVENT_TX_ABRT) || \
((EVENT) == I2C_EVENT_RX_DONE) || \
((EVENT) == (I2C_EVENT_ACTIVITY | I2C_EVENT_STOP_DET)) || \
((EVENT) == (I2C_EVENT_START_DET | I2C_EVENT_GEN_CALL)))
/**
* @}
*/
/** @defgroup I2C_own_address1
* @{
*/
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
/**
* @}
*/
/** @defgroup I2C_clock_speed
* @{
*/
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
/**
* @}
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Exported_Functions
* @{
*/
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
void I2C_ReadCmd(I2C_TypeDef* I2Cx);
#endif /*__HAL_I2C_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_iwdg.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_IWDG_H
#define __HAL_IWDG_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers
* @{
*/
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
((ACCESS) == IWDG_WriteAccess_Disable))
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
((PRESCALER) == IWDG_Prescaler_8) || \
((PRESCALER) == IWDG_Prescaler_16) || \
((PRESCALER) == IWDG_Prescaler_32) || \
((PRESCALER) == IWDG_Prescaler_64) || \
((PRESCALER) == IWDG_Prescaler_128)|| \
((PRESCALER) == IWDG_Prescaler_256))
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions
* @{
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#endif /* __HAL_IWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_misc.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MISC_H
#define __MISC_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @defgroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
((LP) == NVIC_LP_SLEEPDEEP) || \
((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @defgroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /* 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /* 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /* 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /* 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /* 4 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3) || \
((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)
/**
* @}
*/
/** @defgroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_pwr.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_PWR_H
#define __HAL_PWR_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PVD_detection_level
* @{
*/
#define PWR_PVDLevel_2V6 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V8 ((uint32_t)0x00000200)
#define PWR_PVDLevel_3V0 ((uint32_t)0x00000400)
#define PWR_PVDLevel_3V2 ((uint32_t)0x00000600)
#define PWR_PVDLevel_3V4 ((uint32_t)0x00000800)
#define PWR_PVDLevel_3V6 ((uint32_t)0x00000A00)
#define PWR_PVDLevel_3V8 ((uint32_t)0x00000C00)
#define PWR_PVDLevel_4V0 ((uint32_t)0x00000E00)
#define PWR_PVDLevel_4V2 ((uint32_t)0x00001000)
#define PWR_PVDLevel_4V4 ((uint32_t)0x00001200)
#define PWR_PVDLevel_4V6 ((uint32_t)0x00001400)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V8)|| \
((LEVEL) == PWR_PVDLevel_3V0) || ((LEVEL) == PWR_PVDLevel_3V2)|| \
((LEVEL) == PWR_PVDLevel_3V4) || ((LEVEL) == PWR_PVDLevel_3V6)|| \
((LEVEL) == PWR_PVDLevel_3V8) || ((LEVEL) == PWR_PVDLevel_4V0)|| \
((LEVEL) == PWR_PVDLevel_4V2) || ((LEVEL) == PWR_PVDLevel_4V4)|| \
((LEVEL) == PWR_PVDLevel_4V6))
/**
* @}
*/
/** @defgroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000002)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
((REGULATOR) == PWR_Regulator_LowPower))
/**
* @}
*/
/** @defgroup STOP_mode_entry
* @{
*/
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
#endif /* __HAL_PWR_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_rcc.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the RCC firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_RCC_H
#define __HAL_RCC_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/** @defgroup RCC_Exported_Types
* @{
*/
typedef struct
{
uint32_t SYSCLK_Frequency;
uint32_t HCLK_Frequency;
uint32_t PCLK1_Frequency;
uint32_t PCLK2_Frequency;
uint32_t ADCCLK_Frequency;
}RCC_ClocksTypeDef;
/**
* @}
*/
/** @defgroup RCC_Exported_Constants
* @{
*/
/** @defgroup HSE_configuration
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
((HSE) == RCC_HSE_Bypass))
/**
* @}
*/
/** @defgroup PLL_entry_clock_source
* @{
*/
#define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00420000)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00400000)
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \
((SOURCE) == RCC_PLLSource_HSE_Div1) || \
((SOURCE) == RCC_PLLSource_HSE_Div2))
/**
* @}
*/
/** @defgroup System_clock_source
* @{
*/
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
/**
* @}
*/
/** @defgroup AHB_clock_source
* @{
*/
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
((HCLK) == RCC_SYSCLK_Div512))
/**
* @}
*/
/** @defgroup APB1_APB2_clock_source
* @{
*/
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
((PCLK) == RCC_HCLK_Div16))
/**
* @}
*/
/** @defgroup PLL_multiplication_factor
* @{
*/
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define RCC_PLLMul_17 ((uint32_t)0x003C0000)
#define RCC_PLLMul_18 ((uint32_t)0x00400000)
#define RCC_PLLMul_19 ((uint32_t)0x004C0000)
#define RCC_PLLMul_20 ((uint32_t)0x00500000)
#define RCC_PLLMul_21 ((uint32_t)0x00540000)
#define RCC_PLLMul_22 ((uint32_t)0x00580000)
#define RCC_PLLMul_23 ((uint32_t)0x005C0001)
#define RCC_PLLMul_24 ((uint32_t)0x00600002)
#define RCC_PLLMul_25 ((uint32_t)0x00680003)
#define RCC_PLLMul_26 ((uint32_t)0x006C0004)
#define RCC_PLLMul_27 ((uint32_t)0x00700005)
#define RCC_PLLMul_28 ((uint32_t)0x00780006)
#define RCC_PLLMul_29 ((uint32_t)0x007C0007)
#define RCC_PLLMul_30 ((uint32_t)0x00800008)
#define RCC_PLLMul_31 ((uint32_t)0x00880009)
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
((MUL) == RCC_PLLMul_16))
/**
* @}
*/
/** @defgroup RCC_Interrupt_source
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
/**
* @}
*/
/** @defgroup USB_clock_source
* @{
*/
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
/**
* @}
*/
/** @defgroup ADC_clock_source
* @{
*/
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
/**
* @}
*/
/** @defgroup LSE_configuration
* @{
*/
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
((LSE) == RCC_LSE_Bypass))
/**
* @}
*/
/** @defgroup RTC_clock_source
* @{
*/
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
((SOURCE) == RCC_RTCCLKSource_LSI) || \
((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
/**
* @}
*/
/** @defgroup AHB_peripheral
* @{
*/
#define RCC_AHBPeriph_LTDC ((uint32_t)0x80000000)
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000001<<12)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_GPIOA ((uint32_t)0x00000001)
#define RCC_AHBPeriph_GPIOB ((uint32_t)0x00000002)
#define RCC_AHBPeriph_GPIOC ((uint32_t)0x0000004)
#define RCC_AHBPeriph_GPIOD ((uint32_t)0x0000008)
#define RCC_AHBPeriph_GPIOE ((uint32_t)0x0000010)
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup APB2_peripheral
* @{
*/
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
#define RCC_APB2Periph_TIM2 ((uint32_t)0x00000002)
#define RCC_APB2Periph_UART1 ((uint32_t)0x00000004)
#define RCC_APB2Periph_UART2 ((uint32_t)0x00000008)
#define RCC_APB2Periph_UART3 ((uint32_t)0x00000010)
#define RCC_APB2Periph_UART4 ((uint32_t)0x00000020)
#define RCC_APB2Periph_UART5 ((uint32_t)0x00000040)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
#define RCC_APB2Periph_SDIO1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SDIO2 ((uint32_t)0x00001000)
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00100000)
#define RCC_APB2Periph_SPI2 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SPI3 ((uint32_t)0x00400000)
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00800000)
#define RCC_APB2Periph_QSPI ((uint32_t)0x01000000)
#define RCC_AHB2Periph_TK80 ((uint32_t)0x80000000)
#define RCC_APB2Periph_ALL ((uint32_t)0x0003FFFD)
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup APB1_peripheral
* @{
*/
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000001<<0)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000001<<1)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000001<<2)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000001<<3)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000001<<4)
#define RCC_APB1Periph_TIM8 ((uint32_t)0x00000001<<5)
#define RCC_APB1Periph_TIM9 ((uint32_t)0x00000001<<6)
#define RCC_APB1Periph_TIM10 ((uint32_t)0x00000001<<7)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_UART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x04000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x08000000)
#define RCC_APB1Periph_USB ((uint32_t)0x10000000)
#define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F)
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @defgroup Clock_source_to_output_on_MCO_pin
* @{
*/
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#define RCC_MCO_LSI ((uint8_t)0x02)
#define RCC_MCO_LSE ((uint8_t)0x03)
#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \
((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\
((MCO) == RCC_MCO_LSE))
/**
* @}
*/
/** @defgroup RCC_Flag
* @{
*/
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
((FLAG) == RCC_FLAG_LPWRRST))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
/**
* @}
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup RCC_Exported_Functions
* @{
*/
void SystemClk_HSEInit(uint32_t PLL_DN);
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void getSystemClock(u32 *sysclk);
#endif /* __HAL_RCC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_spi.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the SPI firmware
* library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_SPI_H
#define __HAL_SPI_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t SPI_Mode;
uint16_t SPI_DataSize;
uint16_t SPI_DataWidth;
uint16_t SPI_CPOL;
uint16_t SPI_CPHA;
uint16_t SPI_NSS;
uint16_t SPI_BaudRatePrescaler;
uint16_t SPI_FirstBit;
}SPI_InitTypeDef;
/**
* @}
*/
/** @defgroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI0_BASE) || \
((*(uint32_t*)&(PERIPH)) == SPI1_BASE))
#define IS_SPI_2_PERIPH(PERIPH) ((*(uint32_t*)&(PERIPH)) == SPI1_BASE)
/**
* @}
*/
/** @defgroup SPI_master_slave_mode
* @{
*/
#define SPI_Mode_Master ((uint16_t)0x0004)
#define SPI_Mode_Slave ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/**
* @}
*/
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_32b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/** @defgroup SPI_7bit_8bit data width
* @{
*/
#define SPI_DataWidth_7b ((uint16_t)0x0000)
#define SPI_DataWidth_8b ((uint16_t)0x0008)
#define IS_SPI_DATAWIDRH(WIDTH) (((WIDTH) == SPI_DataWidth_7b) || \
((WIDTH) == SPI_DataWidth_8b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint16_t)0x0001)
#define SPI_CPHA_2Edge ((uint16_t)0x0000)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_Soft ((uint16_t)0x0000)
#define SPI_NSS_Hard ((uint16_t)0x0400)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
((NSS) == SPI_NSS_Hard))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0001)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFFFE)
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
((INTERNAL) == SPI_NSSInternalSoft_Reset))
/**
* @}
*/
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler_
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0002)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0004)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0040)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0080)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0100)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0004)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
((BIT) == SPI_FirstBit_LSB))
/**
* @}
*/
/** @defgroup SPI_DMA_transfer_requests
* @{
*/
#define SPI_DMAReq_EN ((uint16_t)0x0200)
#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ) == SPI_DMAReq_EN)
/**
* @}
*/
/** @defgroup SPI TX Fifo and RX Fifo trigger level
* @{
*/
#define SPI_TXTLF ((uint16_t)0x0080)
#define SPI_RXTLF ((uint16_t)0x0020)
#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER) == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF))
/**
* @}
*/
/** @defgroup SPI_NSS_internal_software_mangement
* @{
*/
#define SPI_CS_BIT0 ((uint16_t)0xfffe)
#define SPI_CS_BIT1 ((uint16_t)0xfffd)
#define SPI_CS_BIT2 ((uint16_t)0xfffb)
#define SPI_CS_BIT3 ((uint16_t)0xfff7)
#define SPI_CS_BIT4 ((uint16_t)0xffef)
#define SPI_CS_BIT5 ((uint16_t)0xffdf)
#define SPI_CS_BIT6 ((uint16_t)0xffbf)
#define SPI_CS_BIT7 ((uint16_t)0xff7f)
#define IS_SPI_CS(CS) (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\
((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
/**
* @}
*/
/** @defgroup SPI_direction_transmit_receive
* @{
*/
#define SPI_Direction_Rx ((uint16_t)0x0010)
#define SPI_Direction_Tx ((uint16_t)0x0008)
#define SPI_Disable_Tx ((uint16_t)0xfff7)
#define SPI_Disable_Rx ((uint16_t)0xffef)
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
((DIRECTION) == SPI_Direction_Tx) || \
((DIRECTION) == SPI_Disable_Tx) || \
((DIRECTION) == SPI_Disable_Rx))
/**
* @}
*/
/** @defgroup SPI_interrupts_definition
* @{
*/
#define SPI_INT_EN ((uint16_t)0x0002)
#define SPI_IT_TX ((uint8_t)0x01)
#define SPI_IT_RX ((uint8_t)0x02)
#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TX) || \
((IT) == SPI_IT_RX))
#define SPI_IT_UNDERRUN ((uint8_t)0x04)
#define SPI_IT_RXOVER ((uint8_t)0x08)
#define SPI_IT_RXMATCH ((uint8_t)0x10)
#define SPI_IT_RXFULL ((uint8_t)0x20)
#define SPI_IT_TXEPT ((uint8_t)0x40)
#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \
((IT) == SPI_IT_UNDERRUN) || ((IT) == SPI_IT_RXOVER) || \
((IT) == SPI_IT_RXMATCH) || ((IT) == SPI_IT_RXFULL) || \
((IT) == SPI_IT_TXEPT))
/**
* @}
*/
/** @defgroup SPI_flags_definition
* @{
*/
#define SPI_FLAG_RXAVL ((uint16_t)0x0002)
#define SPI_FLAG_TXEPT ((uint16_t)0x0001)
#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXAVL) || \
((FLAG) == SPI_FLAG_TXEPT))
/**
* @}
*/
/** @defgroup SPI mode tx data transmit phase adjust set
*in slave mode according to txedge bit of CCTL register
* @{
*/
#define SPI_SlaveAdjust_FAST ((uint16_t)0x0020)
#define SPI_SlaveAdjust_LOW ((uint16_t)0xffdf)
#define IS_SPI_SlaveAdjust(ADJUST) (((ADJUST) == SPI_SlaveAdjust_FAST) || \
((ADJUST) == SPI_SlaveAdjust_LOW))
/**
* @}
*/
/** @defgroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Exported_Functions
* @{
*/
void SPI_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState);
void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState);
void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState);
void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx);
void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,FunctionalState NewState);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT);
void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number);
void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue);
#endif /*__HAL_SPI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_syscfg.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*
*/
/*!< Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_SYSCFG_H
#define __HAL_SYSCFG_H
#ifdef __cplusplus
extern "C" {
#endif
/*!< Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup SYSCFG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants
* @{
*/
/** @defgroup SYSCFG_EXTI_Port_Sources
* @{
*/
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
((PORTSOURCE) == EXTI_PortSourceGPIOF))
/**
* @}
*/
/** @defgroup SYSCFG_EXTI_Pin_sources
* @{
*/
#define EXTI_PinSource0 ((uint8_t)0x00)
#define EXTI_PinSource1 ((uint8_t)0x01)
#define EXTI_PinSource2 ((uint8_t)0x02)
#define EXTI_PinSource3 ((uint8_t)0x03)
#define EXTI_PinSource4 ((uint8_t)0x04)
#define EXTI_PinSource5 ((uint8_t)0x05)
#define EXTI_PinSource6 ((uint8_t)0x06)
#define EXTI_PinSource7 ((uint8_t)0x07)
#define EXTI_PinSource8 ((uint8_t)0x08)
#define EXTI_PinSource9 ((uint8_t)0x09)
#define EXTI_PinSource10 ((uint8_t)0x0A)
#define EXTI_PinSource11 ((uint8_t)0x0B)
#define EXTI_PinSource12 ((uint8_t)0x0C)
#define EXTI_PinSource13 ((uint8_t)0x0D)
#define EXTI_PinSource14 ((uint8_t)0x0E)
#define EXTI_PinSource15 ((uint8_t)0x0F)
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
((PINSOURCE) == EXTI_PinSource1) || \
((PINSOURCE) == EXTI_PinSource2) || \
((PINSOURCE) == EXTI_PinSource3) || \
((PINSOURCE) == EXTI_PinSource4) || \
((PINSOURCE) == EXTI_PinSource5) || \
((PINSOURCE) == EXTI_PinSource6) || \
((PINSOURCE) == EXTI_PinSource7) || \
((PINSOURCE) == EXTI_PinSource8) || \
((PINSOURCE) == EXTI_PinSource9) || \
((PINSOURCE) == EXTI_PinSource10) || \
((PINSOURCE) == EXTI_PinSource11) || \
((PINSOURCE) == EXTI_PinSource12) || \
((PINSOURCE) == EXTI_PinSource13) || \
((PINSOURCE) == EXTI_PinSource14) || \
((PINSOURCE) == EXTI_PinSource15))
/**
* @}
*/
/** @defgroup SYSCFG_Memory_Remap_Config
* @{
*/
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
/**
* @}
*/
/** @defgroup SYSCFG_DMA_Remap_Config
* @{
*/
#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
#define SYSCFG_DMARemap_UART1Rx SYSCFG_CFGR1_UART1RX_DMA_RMP /* Remap UART1 Rx DMA requests from channel3 to channel5 */
#define SYSCFG_DMARemap_UART1Tx SYSCFG_CFGR1_UART1TX_DMA_RMP /* Remap UART1 Tx DMA requests from channel2 to channel4 */
#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
((REMAP) == SYSCFG_DMARemap_TIM16) || \
((REMAP) == SYSCFG_DMARemap_UART1Rx) || \
((REMAP) == SYSCFG_DMARemap_UART1Tx) || \
((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_UART3_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_UART2_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
((REMAP) == SYSCFG_DMARemap_ADC1))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/* Function used to set the SYSCFG configuration to the default reset state **/
void SYSCFG_DeInit(void);
/* SYSCFG configuration functions *********************************************/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
void SYSCFG_IRDAEnvSelection(uint32_t SYSCFG_IRDAEnv);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
uint32_t SYSCFG_GetPendingIT(uint32_t ITSourceLine);
void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
#ifdef __cplusplus
}
#endif
#endif /*__HAL_SYSCFG_H */
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_UART.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_UART_H
#define __HAL_UART_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup UART
* @{
*/
/** @defgroup UART_Exported_Types
* @{
*/
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t UART_BaudRate;
uint16_t UART_WordLength;
uint16_t UART_StopBits;
uint16_t UART_Parity;
uint16_t UART_Mode;
uint16_t UART_HardwareFlowControl;
} UART_InitTypeDef;
/**
* @}
*/
/** @defgroup UART_Exported_Constants
* @{
*/
#define IS_UART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART3_BASE))
#define IS_UART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
((*(uint32_t*)&(PERIPH)) == UART3_BASE))
/** @defgroup UART_Word_Length
* @{
*/
#define UART_WordLength_5b ((uint16_t)0x0000)
#define UART_WordLength_6b ((uint16_t)0x0010)
#define UART_WordLength_7b ((uint16_t)0x0020)
#define UART_WordLength_8b ((uint16_t)0x0030)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \
((LENGTH) == UART_WordLength_6b) || \
((LENGTH) == UART_WordLength_7b) || \
((LENGTH) == UART_WordLength_8b))
/**
* @}
*/
/** @defgroup UART_Stop_Bits
* @{
*/
#define UART_StopBits_1 ((uint16_t)0x0000)
#define UART_StopBits_2 ((uint16_t)0x0004)
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_2))
/**
* @}
*/
/** @defgroup UART_Parity
* @{
*/
#define UART_Parity_No ((uint16_t)0x0000)
#define UART_Parity_Even ((uint16_t)0x0003)
#define UART_Parity_Odd ((uint16_t)0x0001)
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
/** @defgroup UART_Mode
* @{
*/
#define UART_Mode_Rx ((uint16_t)0x0008)
#define UART_Mode_Tx ((uint16_t)0x0010)
#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFE7) == 0x00) && ((MODE) != (uint16_t)0x00))
#define UART_EN ((uint16_t)0x0001)
/**
* @}
*/
/** @defgroup UART_Hardware_Flow_Control
* @{
*/
#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
(((CONTROL) == UART_HardwareFlowControl_None) || \
((CONTROL) == UART_HardwareFlowControl_RTS) || \
((CONTROL) == UART_HardwareFlowControl_CTS) || \
((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/** @defgroup UART_Interrupt_definition
* @{
*/
#define UART_IT_ERR ((uint16_t)0x0020)
#define UART_IT_PE ((uint16_t)0x0010)
#define UART_OVER_ERR ((uint16_t)0x0008)
#define UART_TIMEOUT_ERR ((uint16_t)0x0004)
#define UART_IT_RXIEN ((uint16_t)0x0002)
#define UART_IT_TXIEN ((uint16_t)0x0001)
#define IS_UART_CONFIG_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \
((IT) == UART_IT_RXIEN) || ((IT) == UART_IT_ERR))
#define IS_UART_GET_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \
((IT) == UART_IT_ERR) || ((IT) == UART_IT_RXIEN) || \
((IT) == UART_OVER_ERR) || ((IT) == UART_TIMEOUT_ERR))
#define IS_UART_CLEAR_IT(IT) ((IT) == UART_IT_RXIEN)
/**
* @}
*/
/** @defgroup UART_DMA_Requests
* @{
*/
#define UART_DMAReq_EN ((uint16_t)0x0002)
#define IS_UART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFD) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup UART_Flags
* @{
*/
#define UART_FLAG_TXEMPTY ((uint16_t)0x0008)
#define UART_FLAG_TXFULL ((uint16_t)0x0004)
#define UART_FLAG_RXAVL ((uint16_t)0x0002)
#define UART_FLAG_TXEPT ((uint16_t)0x0001)
#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_TXEMPTY) || ((FLAG) == UART_FLAG_TXFULL) || \
((FLAG) == UART_FLAG_RXAVL) || ((FLAG) == UART_FLAG_TXEPT))
#define IS_UART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x00FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_UART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/** @defgroup UART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup UART_Exported_Functions
* @{
*/
void UART_DeInit(UART_TypeDef* UARTx);
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState);
void UART_SendData(UART_TypeDef* UARTx, uint16_t Data);
uint16_t UART_ReceiveData(UART_TypeDef* UARTx);
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG);
void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG);
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT);
#endif /* __HAL_UART_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_wwdg.h
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file contains all the functions prototypes for the WWDG
* firmware library.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __HAL_WWDG_H
#define __HAL_WWDG_H
/* Includes ------------------------------------------------------------------*/
#include "HAL_device.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_Prescaler
* @{
*/
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
((PRESCALER) == WWDG_Prescaler_2) || \
((PRESCALER) == WWDG_Prescaler_4) || \
((PRESCALER) == WWDG_Prescaler_8))
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void);
#endif /* __HAL_WWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file stm32f10x_dma.c
* @author MCD Application Team
* @version V3.5.0
* @date 11-March-2011
* @brief This file provides all the DMA firmware functions.
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "hal_dma.h"
#include "hal_rcc.h"
/** @addtogroup STM32F10x_StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/** @defgroup DMA_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Defines
* @{
*/
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
/* DMA2 Channelx interrupt pending bit masks */
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000001)
/* DMA registers Masks */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/**
* @}
*/
/** @defgroup DMA_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DMAy Channelx registers to their default reset
* values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
if (DMAy_Channelx == DMA1_Channel1)
{
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel2)
{
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel3)
{
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel4)
{
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel5)
{
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel6)
{
/* Reset interrupt pending bits for DMA1 Channel6 */
DMA1->IFCR |= DMA1_Channel6_IT_Mask;
}
else if (DMAy_Channelx == DMA1_Channel7)
{
/* Reset interrupt pending bits for DMA1 Channel7 */
DMA1->IFCR |= DMA1_Channel7_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel1)
{
/* Reset interrupt pending bits for DMA2 Channel1 */
DMA2->IFCR |= DMA2_Channel1_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel2)
{
/* Reset interrupt pending bits for DMA2 Channel2 */
DMA2->IFCR |= DMA2_Channel2_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel3)
{
/* Reset interrupt pending bits for DMA2 Channel3 */
DMA2->IFCR |= DMA2_Channel3_IT_Mask;
}
else if (DMAy_Channelx == DMA2_Channel4)
{
/* Reset interrupt pending bits for DMA2 Channel4 */
DMA2->IFCR |= DMA2_Channel4_IT_Mask;
}
else
{
if (DMAy_Channelx == DMA2_Channel5)
{
/* Reset interrupt pending bits for DMA2 Channel5 */
DMA2->IFCR |= DMA2_Channel5_IT_Mask;
}
}
}
/**
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified DMA Channel.
* @retval None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_Mask;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= DMA_CCR1_EN;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
}
}
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/**
* @brief Sets the number of data units in the current DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @param DataNumber: The number of data units in the current DMAy Channelx
* transfer.
* @note This function can only be used when the DMAy_Channelx is disabled.
* @retval None.
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DataNumber;
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
* @retval The number of remaining data units in the current DMAy Channelx
* transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((uint16_t)(DMAy_Channelx->CNDTR));
}
/**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
* @param DMAy_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* @retval The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR ;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
}
/* Check the status of the specified DMAy flag */
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
/* DMAy_FLAG is set */
bitstatus = SET;
}
else
{
/* DMAy_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMAy_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
* @param DMAy_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
* @retval None
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
/* Calculate the used DMAy */
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy flags */
DMA2->IFCR = DMAy_FLAG;
}
else
{
/* Clear the selected DMAy flags */
DMA1->IFCR = DMAy_FLAG;
}
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
* @param DMAy_IT: specifies the DMAy interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMAy_IT));
/* Calculate the used DMA */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Get DMA2 ISR register value */
tmpreg = DMA2->ISR;
}
else
{
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR;
}
/* Check the status of the specified DMAy interrupt */
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
/* DMAy_IT is set */
bitstatus = SET;
}
else
{
/* DMAy_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's interrupt pending bits.
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
* @retval None
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
/* Calculate the used DMAy */
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
{
/* Clear the selected DMAy interrupt pending bits */
DMA2->IFCR = DMAy_IT;
}
else
{
/* Clear the selected DMAy interrupt pending bits */
DMA1->IFCR = DMAy_IT;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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bsp/tkm32F499/Libraries/Hal_lib/src/HAL_dma_bak.c Normal file
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@ -0,0 +1,539 @@
/**
******************************************************************************
* @file HAL_dma.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the DMA firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_dma.h"
//??
#ifdef 0
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup DMA
* @brief DMA driver modules
* @{
*/
/** @defgroup DMA_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Defines
* @{
*/
/* DMA ENABLE mask */
#define CCR_ENABLE_Set ((uint32_t)0x00000001)
#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
/* DMA registers Masks */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/**
* @}
*/
/** @defgroup DMA_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup DMA_Private_Functions
* @{
*/
/**
* @brief Deinitializes the DMAy Channelx registers to their default reset
* values.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* @retval : None
*/
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
/* Reset DMAy Channelx control register */
DMAy_Channelx->CCR = 0;
/* Reset DMAy Channelx remaining bytes register */
DMAy_Channelx->CNDTR = 0;
/* Reset DMAy Channelx peripheral address register */
DMAy_Channelx->CPAR = 0;
/* Reset DMAy Channelx memory address register */
DMAy_Channelx->CMAR = 0;
switch (*(uint32_t*)&DMAy_Channelx)
{
case DMA1_Channel1_BASE:
/* Reset interrupt pending bits for DMA1 Channel1 */
DMA1->IFCR |= DMA1_Channel1_IT_Mask;
break;
case DMA1_Channel2_BASE:
/* Reset interrupt pending bits for DMA1 Channel2 */
DMA1->IFCR |= DMA1_Channel2_IT_Mask;
break;
case DMA1_Channel3_BASE:
/* Reset interrupt pending bits for DMA1 Channel3 */
DMA1->IFCR |= DMA1_Channel3_IT_Mask;
break;
case DMA1_Channel4_BASE:
/* Reset interrupt pending bits for DMA1 Channel4 */
DMA1->IFCR |= DMA1_Channel4_IT_Mask;
break;
case DMA1_Channel5_BASE:
/* Reset interrupt pending bits for DMA1 Channel5 */
DMA1->IFCR |= DMA1_Channel5_IT_Mask;
break;
default:
break;
}
}
/**
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
* contains the configuration information for the specified
* DMA Channel.
* @retval : None
*/
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
/* Get the DMAy_Channelx CCR value */
tmpreg = DMAy_Channelx->CCR;
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmpreg &= CCR_CLEAR_Mask;
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
/* Set DIR bit according to DMA_DIR value */
/* Set CIRC bit according to DMA_Mode value */
/* Set PINC bit according to DMA_PeripheralInc value */
/* Set MINC bit according to DMA_MemoryInc value */
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
/* Set MSIZE bits according to DMA_MemoryDataSize value */
/* Set PL bits according to DMA_Priority value */
/* Set the MEM2MEM bit according to DMA_M2M value */
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
/* Write to DMAy Channelx CCR */
DMAy_Channelx->CCR = tmpreg;
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
/* Write to DMAy Channelx CNDTR */
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
/* Write to DMAy Channelx CPAR */
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
/* Write to DMAy Channelx CMAR */
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/**
* @brief Fills each DMA_InitStruct member with its default value.
* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
{
/*-------------- Reset DMA init structure parameters values ------------------*/
/* Initialize the DMA_PeripheralBaseAddr member */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
/* Initialize the DMA_MemoryBaseAddr member */
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
/* Initialize the DMA_DIR member */
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
/* Initialize the DMA_BufferSize member */
DMA_InitStruct->DMA_BufferSize = 0;
/* Initialize the DMA_PeripheralInc member */
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
/* Initialize the DMA_MemoryInc member */
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
/* Initialize the DMA_PeripheralDataSize member */
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
/* Initialize the DMA_MemoryDataSize member */
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
/* Initialize the DMA_Mode member */
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
/* Initialize the DMA_Priority member */
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
/* Initialize the DMA_M2M member */
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/**
* @brief Enables or disables the specified DMAy Channelx.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* @param NewState: new state of the DMAy Channelx.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMAy Channelx */
DMAy_Channelx->CCR |= CCR_ENABLE_Set;
}
else
{
/* Disable the selected DMAy Channelx */
DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
}
}
/**
* @brief Enables or disables the specified DMAy Channelx interrupts.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @param NewState: new state of the specified DMA interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected DMA interrupts */
DMAy_Channelx->CCR |= DMA_IT;
}
else
{
/* Disable the selected DMA interrupts */
DMAy_Channelx->CCR &= ~DMA_IT;
}
}
/**
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
* DMA Channel.
* @retval : The number of remaining data units in the current DMAy Channelx
* transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
{
/* Check the parameters */
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
/* Return the number of remaining data units for DMAy Channelx */
return ((uint16_t)(DMAy_Channelx->CNDTR));
}
/**
* @brief Checks whether the specified DMAy Channelx flag is set or not.
* @param DMA_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @retval : The new state of DMA_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
/* Check the status of the specified DMA flag */
if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
{
/* DMA_FLAG is set */
bitstatus = SET;
}
else
{
/* DMA_FLAG is reset */
bitstatus = RESET;
}
/* Return the DMA_FLAG status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx's pending flags.
* @param DMA_FLAG: specifies the flag to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
* @retval : None
*/
void DMA_ClearFlag(uint32_t DMA_FLAG)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
/* Clear the selected DMA flags */
DMA1->IFCR = DMA_FLAG;
}
/**
* @brief Checks whether the specified DMAy Channelx interrupt has
* occurred or not.
* @param DMA_IT: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @retval : The new state of DMA_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMA_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DMA_GET_IT(DMA_IT));
/* Get DMA1 ISR register value */
tmpreg = DMA1->ISR ;
/* Check the status of the specified DMA interrupt */
if ((tmpreg & DMA_IT) != (uint32_t)RESET)
{
/* DMA_IT is set */
bitstatus = SET;
}
else
{
/* DMA_IT is reset */
bitstatus = RESET;
}
/* Return the DMA_IT status */
return bitstatus;
}
/**
* @brief Clears the DMAy Channelx’s interrupt pending bits.
* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
* This parameter can be any combination (for the same DMA) of
* the following values:
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
* @retval : None
*/
void DMA_ClearITPendingBit(uint32_t DMA_IT)
{
/* Check the parameters */
assert_param(IS_DMA_CLEAR_IT(DMA_IT));
/* Clear the selected DMA interrupt pending bits */
DMA1->IFCR = DMA_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif // 0
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_exti.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the EXTI firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_exti.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/** @defgroup EXTI_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Defines
* @{
*/
#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */
/**
* @}
*/
/** @defgroup EXTI_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/**
* @brief Deinitializes the EXTI peripheral registers to their default
* reset values.
* @param None
* @retval : None
*/
void EXTI_DeInit(void)
{
EXTI->IMR = 0x00000000;
EXTI->EMR = 0x00000000;
EXTI->RTSR = 0x00000000;
EXTI->FTSR = 0x00000000;
EXTI->PR = 0x001FFFFF;
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI
* peripheral.
* @retval : None
*/
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
tmp = (uint32_t)EXTI_BASE;
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
/* Clear EXTI line configuration */
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
/* Select the trigger for the selected external interrupts */
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Mode;
/* Disable the selected external lines */
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
* @brief Generates a Software interrupt.
* @param EXTI_Line: specifies the EXTI lines to be enabled or
* disabled.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* @retval : None
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->SWIER |= EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param EXTI_Line: specifies the EXTI line flag to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..18)
* @retval : The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI’s line pending flags.
* @param EXTI_Line: specifies the EXTI lines flags to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* @retval : None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param EXTI_Line: specifies the EXTI line to check.
* This parameter can be:
* @arg EXTI_Linex: External interrupt line x where x(0..18)
* @retval : The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
/* Check the parameters */
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
enablestatus = EXTI->IMR & EXTI_Line;
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the EXTI’s line pending bits.
* @param EXTI_Line: specifies the EXTI lines to clear.
* This parameter can be any combination of EXTI_Linex where
* x can be (0..18).
* @retval : None
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_LINE(EXTI_Line));
EXTI->PR = EXTI_Line;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_gpio.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the GPIO firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_gpio.h"
#include "HAL_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup GPIO
* @brief GPIO driver modules
* @{
*/
/** @defgroup GPIO_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Defines
* @{
*/
/* ------------ RCC registers bit address in the alias region ----------------*/
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
/* --- EVENTCR Register -----*/
/* Alias word address of EVOE bit */
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
#define EVOE_BitNumber ((uint8_t)0x07)
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup GPIO_Private_Functions
* @{
*/
/**
* @brief Deinitializes the GPIOx peripheral registers to their default
* reset values.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval : None
*/
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
switch (*(uint32_t*)&GPIOx)
{
case GPIOA_BASE:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, DISABLE);
break;
case GPIOB_BASE:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, DISABLE);
break;
case GPIOC_BASE:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, DISABLE);
break;
case GPIOD_BASE:
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, DISABLE);
break;
default:
break;
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified
* parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO
* peripheral.
* @retval : None
*/
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
/*---------------------------- GPIO Mode Configuration -----------------------*/
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
{
/* Check the parameters */
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
/* Output mode */
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
}
/*---------------------------- GPIO CRL Configuration ------------------------*/
/* Configure the eight low port pins */
if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CRL;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
}
else
{
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOx->CRL = tmpreg;
}
/*---------------------------- GPIO CRH Configuration ------------------------*/
/* Configure the eight high port pins */
if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CRH;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x08));
/* Get the port pins position */
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding high control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
}
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CRH = tmpreg;
}
/*---------------------------- GPIOE_CRH_EXT Configuration ------------------------*/
if(GPIO_InitStruct->GPIO_Pin>>16) //说明是GPIOE的16~23位
{
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin>>16;
tmpreg = GPIOE->CRH_EXT;
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
/* Get the port pins position */
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if (currentpin == pos)
{
pos = pinpos << 2;
/* Clear the corresponding low control register bits */
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
/* Write the mode configuration in the corresponding bits */
tmpreg |= (currentmode << pos);
/* Reset the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BRR = (((uint32_t)0x01) << pinpos);
}
else
{
/* Set the corresponding ODR bit */
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOE->CRH_EXT = tmpreg;
}
}
/**
* @brief Fills each GPIO_InitStruct member with its default value.
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval : The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval : GPIO input data port value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->IDR);
}
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval : The output port pin value.
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @retval : GPIO output data port value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->ODR);
}
/**
* @brief Sets the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* @retval : None
*/
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
if(GPIO_Pin>GPIO_Pin_15)GPIOE->BSRR_EXT=GPIO_Pin>>16;
else
GPIOx->BSRR = GPIO_Pin;
}
/**
* @brief Clears the selected data port bits.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* @retval : None
*/
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->BRR = GPIO_Pin;
}
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit.
* This parameter can be one of the BitAction enum values:
* @arg Bit_RESET: to clear the port pin
* @arg Bit_SET: to set the port pin
* @retval : None
*/
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
if (BitVal != Bit_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BRR = GPIO_Pin;
}
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param PortVal: specifies the value to be written to the port output
* data register.
* @retval : None
*/
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->ODR = PortVal;
}
/**
* @brief Locks GPIO Pins configuration registers.
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where
* x can be (0..15).
* @retval : None
*/
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
tmp |= GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Reset LCKK bit */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKK bit */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
}
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A, B, C, D ) to select the GPIO peripheral.
* @param GPIO_PinSource: specifies the pin for the Alternate function.
* This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD
* and (0..12) for GPIOC .
* @param GPIO_AF: selects the pin to used as Alternate function.
* This parameter can be one of the following value:
* @arg GPIO_AF_0: SPI1, MC0, TIM17_BKIN, SWDIO,SWCLK,
UART1
* @arg GPIO_AF_1: UART1, TIM3_CH1, TIM3_CH2, TIM3_CH3,
TIM3_CH4, I2C1
* @arg GPIO_AF_2: TIM2_CH1_ETR, TIM2_CH2, TIM2_CH3,
TIM2_CH3, TIM2_CH4, TIM1_BKIN,
TIM1_CH1N, TIM1_CH1, TIM1_CH2,
TIM1_CH3, TIM1_CH4, TIM1_ETR,
TIM1_CH2N, TIM1_CH3N, TIM2_CH2,
TIM1 6_BKIN, TIM16_CH1N, TIM17_CH1N,
TIM1 6_CH1, TIM17_CH1
* @arg GPIO_AF_4: TIM14_CH1, I2C1
* @note The pin should already been configured in Alternate Function mode(AF)
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
* @note Refer to the Alternate function mapping table in the device datasheet
* for the detailed mapping of the system and peripherals'alternate
* function I/O pins.
* @retval None
*/
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint32_t GPIO_Pin, uint8_t GPIO_AF)
{
uint32_t temp;
unsigned char i;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
assert_param(IS_GPIO_AF(GPIO_AF));
if(GPIO_Pin>>16) //说明是GPIOE的16~23位
{
temp = GPIO_Pin>>16;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOE->AFRH_EXT &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOE->AFRH_EXT |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF00) //说明是GPIOE的8~15位
{
temp = GPIO_Pin>>8;
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRH &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRH |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
if(GPIO_Pin&0XFF) //说明是GPIOE的0~7位
{
for(i=0;i<8;i++)
{
if(temp&0x01)
{
GPIOx->AFRL &= ~((uint32_t)0xF << ((uint32_t)(i<<2))); //AF配置占半字节，要x4,即<<2
GPIOx->AFRL |= ((uint32_t)GPIO_AF << ((uint32_t)(i<<2)));
}
temp = temp>>1;
}
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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bsp/tkm32F499/Libraries/Hal_lib/src/HAL_i2c.c Normal file
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@ -0,0 +1,848 @@
/**
******************************************************************************
* @file HAL_i2c.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the I2C firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_i2c.h"
#include "HAL_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup I2C
* @brief I2C driver modules
* @{
*/
/** @defgroup I2C_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Private_Defines
* @{
*/
/*I2c Enable disable*/
#define IC_ENABLE_Reset ((uint16_t)0xFFFE)
#define IC_ENABLE_Set ((uint16_t)0x0001)
#define IC_CON_RESET ((uint16_t)0xFE8A)
#define INTR_MASK ((uint16_t)0xC000)
/*I2c DMA reset*/
#define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC)
/* I2C START mask */
#define IC_CON_START_Set ((uint16_t)0x0020)
#define IC_CON_START_Reset ((uint16_t)0xFFDF)
/* I2C STOP mask */
#define IC_DATA_CMD_STOP_Set ((uint16_t)0x0200)
#define IC_DATA_CMD_STOP_Reset ((uint16_t)0xFDFF)
/* I2C ADD2 mask */
#define IC_TAR_Reset ((uint16_t)0xFF00)
/* I2C IC_10BITADDR_MASTER bit mask */
#define IC_TAR_ENDUAL_Set ((uint16_t)0x1000)
#define IC_TAR_ENDUAL_Reset ((uint16_t)0xEFFF)
/* I2C SPECIAL、GC_OR_START bits mask */
#define IC_TAR_GC_Set ((uint16_t)0x0800)
#define IC_TAR_GC_Reset ((uint16_t)0xF7FF)
/* I2C FLAG mask */
#define FLAG_Mask ((uint32_t)0x00793FFF)
//static
uint8_t I2C_CMD_DIR = 0;
/*新增加的用户变量，外部调用时需要更新该变量值*/
uint16_t I2C_DMA_DIR = 0;
/**
* @}
*/
/** @defgroup I2C_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup I2C_Private_Functions
* @{
*/
/**
* @brief Deinitializes the I2Cx peripheral registers to their default
* reset values.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @retval : None
*/
void I2C_DeInit(I2C_TypeDef* I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
switch (*(uint32_t*)&I2Cx)
{
case I2C1_BASE:
/* Enable I2C1 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
/* Release I2C1 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
break;
default:
break;
}
}
/**
* @brief Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
* contains the configuration information for the specified
* I2C peripheral.
* @retval : None
*/
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
{
uint16_t tmpreg = 0;
uint32_t pclk1 = 8000000;
uint32_t minSclLowTime = 0;
uint32_t i2cPeriod = 0;
uint32_t pclk1Period = 0;
RCC_ClocksTypeDef rcc_clocks;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
/*---------------------------- I2Cx IC_ENABLE Configuration ------------------------*/
/* Disable the selected I2C peripheral */
I2Cx->IC_ENABLE &= IC_ENABLE_Reset;
/* Get pclk1 frequency value */
RCC_GetClocksFreq(&rcc_clocks);
pclk1 = rcc_clocks.PCLK1_Frequency;
/* Set pclk1 period value */
pclk1Period = 1000000000/pclk1;
i2cPeriod = 1000000000/I2C_InitStruct->I2C_ClockSpeed; //ns unit
tmpreg = 0;
/*Get the I2Cx IC_CON value */
tmpreg = I2Cx->IC_CON;
/*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
tmpreg &= IC_CON_RESET;
/* Configure speed in standard mode */
if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
{
minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_SS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_SS_SCL_HCNT = minSclLowTime - I2Cx->IC_SS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
}
else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
{
minSclLowTime = i2cPeriod/pclk1Period;
I2Cx->IC_FS_SCL_LCNT = minSclLowTime/2;
I2Cx->IC_FS_SCL_HCNT = minSclLowTime - I2Cx->IC_FS_SCL_LCNT;
I2C_InitStruct->I2C_Speed = I2C_Speed_FAST;
}
/*Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN |IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode;
/* Write to I2Cx IC_CON */
I2Cx->IC_CON = tmpreg;
/*---------------------------- I2Cx IC_INTR_MASK Configuration ------------------------*/
/* Get the I2Cx IC_INTR_MASK value */
tmpreg = I2Cx->IC_INTR_MASK;
/* clear the I2Cx IC_INTR_MASK value */
tmpreg &= INTR_MASK;
/* Write to IC_INTR_MASK */
I2Cx->IC_INTR_MASK = tmpreg;
/* Write to IC_RX_TL */
I2Cx->IC_RX_TL = 0x0; //rxfifo depth is 1
/* Write to IC_TX_TL */
I2Cx->IC_TX_TL = 0x1; //tcfifo depth is 1
}
/**
* @brief Fills each I2C_InitStruct member with its default value.
* @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
{
/*---------------- Reset I2C init structure parameters values ----------------*/
/* Initialize the I2C_Mode member */
I2C_InitStruct->I2C_Mode = I2C_Mode_MASTER;
/* Initialize the I2C_OwnAddress member */
I2C_InitStruct->I2C_OwnAddress = 0xA8;
/* Initialize the I2C_Speed member */
I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
/* initialize the I2C_ClockSpeed member */
I2C_InitStruct->I2C_ClockSpeed = 100000;
}
/**
* @brief Enables or disables the specified I2C peripheral.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2Cx peripheral. This parameter
* can be: ENABLE or DISABLE.
* @retval : None
*/
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected I2C peripheral */
I2Cx->IC_ENABLE |= IC_ENABLE_Set;
}
else
{
/* Disable the selected I2C peripheral */
I2Cx->IC_ENABLE &= IC_ENABLE_Reset;
}
}
/**
* @brief Enables or disables the specified I2C DMA requests.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param DMA_Direcction : TDMAE_SET,RDMAE_SET
* This parameter can be any combination of the following values:
* @arg TDMAE_SET :DMA TX set
* @arg RDMAE_SET :DMA RX set
* @param NewState: new state of the I2C DMA transfer.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected I2C DMA requests */
if(I2C_DMA_DIR==TDMAE_SET)
{
/* Enable the selected I2C TX DMA requests */
I2Cx->IC_DMA_CR |= TDMAE_SET;
}
else if(I2C_DMA_DIR==RDMAE_SET)
{
/* Enable the selected I2C TX DMA requests */
I2Cx->IC_DMA_CR |= RDMAE_SET;
}
}
else
{
/* Disable the selected I2C DMA requests */
I2Cx->IC_DMA_CR &= DMA_CR_TDMAE_RDMAE_Reset;
}
}
/**
* @brief Generates I2Cx communication START condition.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2C START condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval : None.
*/
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Generate a START condition */
I2Cx->IC_CON |= IC_CON_START_Set;
}
else
{
/* Disable the START condition generation */
I2Cx->IC_CON &= IC_CON_START_Reset;
}
}
/**
* @brief Generates I2Cx communication STOP condition.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2C STOP condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval : None.
*/
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Generate a STOP condition */
I2Cx->IC_DATA_CMD |= IC_DATA_CMD_STOP_Set;
}
else
{
/* Disable the STOP condition generation */
I2Cx->IC_DATA_CMD &= IC_DATA_CMD_STOP_Reset;
}
}
/**
* @brief Configures the specified I2C own address2.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param Address: specifies the 7bit I2C own address2.
* @retval : None.
*/
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
//void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address)
{
uint16_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Get the old register value */
tmpreg = I2Cx->IC_TAR;
/* Reset I2Cx Own address2 bit [7:0] */
tmpreg &= IC_TAR_Reset;
/* Set I2Cx Own address2 */
tmpreg |= Address>>1;
/* Store the new register value */
I2Cx->IC_TAR = tmpreg;
}
/**
* @brief Enables or disables the specified I2C dual addressing mode.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2C dual addressing mode.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable dual addressing mode */
I2Cx->IC_TAR |= IC_TAR_ENDUAL_Set;
}
else
{
/* Disable dual addressing mode */
I2Cx->IC_TAR &= IC_TAR_ENDUAL_Reset;
}
}
/**
* @brief Enables or disables the specified I2C general call feature.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param NewState: new state of the I2C General call.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable generall call */
I2Cx->IC_TAR |= IC_TAR_GC_Set;
}
else
{
/* Disable generall call */
I2Cx->IC_TAR &= IC_TAR_GC_Reset;
}
}
/**
* @brief Enables or disables the specified I2C interrupts.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_IT: specifies the I2C interrupts sources to be enabled
* or disabled.
* This parameter can be any combination of the following values:
* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt mask
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt mask
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt mask
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt mask
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt mask
* @arg I2C_IT_TX_ABRT : TX error interrupt mask(Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt mask(slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt mask
* @arg I2C_IT_STOP_DET : stop condition interrupt mask
* @arg I2C_IT_START_DET : start condition interrupt mask
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt mask
* @param NewState: new state of the specified I2C interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_I2C_CONFIG_IT(I2C_IT));
if(I2C_IT == I2C_IT_RX_FULL)
{
I2C1->IC_DATA_CMD = CMD_READ;
}
if (NewState != DISABLE)
{
/* Enable the selected I2C interrupts */
I2Cx->IC_INTR_MASK |= I2C_IT;
}
else
{
/* Disable the selected I2C interrupts */
I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT;
}
}
/**
* @brief Sends a data byte through the I2Cx peripheral.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param Data: Byte to be transmitted..
* @retval : None
*/
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Write in the IC_DATA_CMD register the data to be sent */
I2Cx->IC_DATA_CMD = CMD_WRITE | Data;
}
/**
* @brief Returns the most recent received data by the I2Cx peripheral.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @retval : The value of the received data.
*/
void I2C_ReadCmd(I2C_TypeDef* I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2Cx->IC_DATA_CMD = CMD_READ;
}
/**
* @brief Returns the most recent received data by the I2Cx peripheral.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @retval : The value of the received data.
*/
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
I2C_CMD_DIR= 0;
/* Return the data in the IC_DATA_CMD register */
return (uint8_t)I2Cx->IC_DATA_CMD;
}
/**
* @brief Transmits the address byte to select the slave device.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param Address: specifies the slave address which will be transmitted
* @param I2C_Direction: specifies whether the I2C device will be a
* Transmitter or a Receiver.
* This parameter can be one of the following values
* @arg I2C_Direction_Transmitter: Transmitter mode
* @arg I2C_Direction_Receiver: Receiver mode
* @retval : None.
*/
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
{
/* Store the new register value */
I2Cx->IC_TAR = Address>>1;
}
/**
* @brief Reads the specified I2C register and returns its value.
* @param I2C_Register: specifies the register to read.
* This parameter can be one of the following values:
* @retval : The value of the read register.
*/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_REGISTER(I2C_Register));
/* Return the selected register value */
return (*(__IO uint16_t *)(*((__IO uint32_t *)&I2Cx) + I2C_Register));
}
/**
* @brief Returns the last I2Cx Event.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @retval : The last event
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
/* Read the I2Cx status register */
flag1 = I2Cx->IC_RAW_INTR_STAT;
/* Get the last event value from I2C status register */
lastevent = (flag1 ) & FLAG_Mask;
/* Return status */
return lastevent;
}
/**
* @brief Checks whether the last I2Cx Event is equal to the one passed
* as parameter.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_EVENT: specifies the event to be checked.
* This parameter can be one of the following values:
* @arg I2C_EVENT_RX_UNDER: Rx Buffer is empty event
* @arg I2C_EVENT_RX_OVER : RX Buffer Overrun event
* @arg I2C_EVENTT_RX_FULL : Rx buffer full event
* @arg I2C_EVENT_TX_OVER : TX Buffer Overrun event
* @arg I2C_EVENT_TX_EMPTY : TX_FIFO empty event
* @arg I2C_EVENT_RD_REQ : I2C work as slave or master event
* @arg I2C_EVENT_TX_ABRT : TX error event(Master mode)
* @arg I2C_EVENT_RX_DONE : Master not ack event(slave mode)
* @arg I2C_EVENT_ACTIVITY : I2C activity event
* @arg I2C_EVENT_STOP_DET : stop condition event
* @arg I2C_EVENT_START_DET : start condition event
* @arg I2C_EVENT_GEN_CALL : a general call address and ack event
* - SUCCESS: Last event is equal to the I2C_EVENT
* - ERROR: Last event is different from the I2C_EVENT
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
{
uint32_t lastevent = 0;
uint32_t flag1 = 0;
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_EVENT(I2C_EVENT));
if((I2C_EVENT == I2C_EVENT_RX_FULL)&&(I2C_CMD_DIR==0))
{
I2C1->IC_DATA_CMD = CMD_READ;
I2C_CMD_DIR = 1;
}
/* Read the I2Cx status register */
flag1 = I2Cx->IC_RAW_INTR_STAT;
//flag1 = I2Cx->IC_INTR_STAT;
/* Get the last event value from I2C status register */
lastevent = (flag1 ) & I2C_EVENT;
/* Check whether the last event is equal to I2C_EVENT */
if (lastevent == I2C_EVENT )
//if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET)
{
/* SUCCESS: last event is equal to I2C_EVENT */
status = SUCCESS;
}
else
{
/* ERROR: last event is different from I2C_EVENT */
status = ERROR;
}
/* Return status */
return status;
}
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag
* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag
* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
* @retval : The new state of I2C_FLAG (SET or RESET).
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
{
FlagStatus bitstatus = RESET;
__IO uint32_t i2creg = 0, i2cxbase = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
/* Check the status of the specified I2C flag and set I2C direction*/
if((I2C_FLAG == I2C_FLAG_RX_FULL)&&(I2C_CMD_DIR==0))
{
I2Cx->IC_DATA_CMD = CMD_READ;
I2C_CMD_DIR = 1;
}
/* Check the status of the specified I2C flag */
if((I2Cx->IC_RAW_INTR_STAT & I2C_FLAG) != (uint32_t)RESET)
{
/* I2C_FLAG is set */
bitstatus = SET;
}
else
{
/* I2C_FLAG is reset */
bitstatus = RESET;
}
/* Return the I2C_FLAG status */
return bitstatus;
}
/**
* @brief Clears the I2Cx's pending flags.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag
* @arg I2C_FLAG_RX_OVER : RX Buffer Overrun flag
* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
* @arg I2C_FLAG_TX_OVER : TX Buffer Overrun flag
* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
* @arg I2C_FLAG_RD_REQ : I2C work as slave or master flag
* @arg I2C_FLAG_TX_ABRT : TX error flag(Master mode)
* @arg I2C_FLAG_RX_DONE : Master not ack flag(slave mode)
* @arg I2C_FLAG_ACTIVITY: I2C activity flag
* @arg I2C_FLAG_STOP_DET: stop condition flag
* @arg I2C_FLAG_START_DET: start condition flag
* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
* @retval : None
*/
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
{
__IO uint32_t i2creg = 0, i2cxbase = 0;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
/* Get the I2Cx peripheral base address */
i2cxbase = (*(uint32_t*)&(I2Cx));
if(I2C_FLAG==I2C_FLAG_RX_UNDER)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x44;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_RX_UNDER = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_RX_OVER)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x48;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_RX_OVER = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_TX_OVER)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x4C;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_TX_OVER = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_RD_REQ)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x50;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_RD_REQ = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_TX_ABRT)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x54;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_TX_ABRT = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_RX_DONE)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x58;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_RX_DONE = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_ACTIVITY)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x5C;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_ACTIVITY = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_STOP_DET)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x60;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_STOP_DET = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_START_DET)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x64;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_START_DET = (uint16_t)I2C_FLAG;
}
if(I2C_FLAG==I2C_FLAG_GEN_CALL)
{
/* Get the I2Cx SR1 register address */
i2cxbase += 0x68;
/* Clear the selected I2C flag */
I2Cx->IC_CLR_GEN_CALL = (uint16_t)I2C_FLAG;
}
}
/**
* @brief Checks whether the specified I2C interrupt has occurred or not.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_IT: specifies the interrupt source to check.
* This parameter can be one of the following values:
* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : The new state of I2C_IT (SET or RESET).
*/
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_GET_IT(I2C_IT));
/* Check the status of the specified I2C flag */
if((I2Cx->IC_RAW_INTR_STAT & I2C_IT) != (uint32_t)RESET)
{
/* I2C_IT is set */
bitstatus = SET;
}
else
{
/* I2C_IT is reset */
bitstatus = RESET;
}
/* Return the I2C_IT status */
return bitstatus;
}
/**
* @brief Clears the I2Cx interrupt pending bits.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_IT: specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt
* @arg I2C_IT_RX_OVER : RX Buffer Overrun interrupt
* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
* @arg I2C_IT_TX_OVER : TX Buffer Overrun interrupt
* @arg I2C_IT_TX_EMPTY : TX_FIFO empty interrupt
* @arg I2C_IT_RD_REQ : I2C work as slave or master interrupt
* @arg I2C_IT_TX_ABRT : TX error interrupt (Master mode)
* @arg I2C_IT_RX_DONE : Master not ack interrupt (slave mode)
* @arg I2C_IT_ACTIVITY : I2C activity interrupt
* @arg I2C_IT_STOP_DET : stop condition interrupt
* @arg I2C_IT_START_DET : start condition interrupt
* @arg I2C_IT_GEN_CALL : a general call address and ack interrupt
* @retval : None
*/
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_PERIPH(I2Cx));
assert_param(IS_I2C_CLEAR_IT(I2C_IT));
/* Clear the selected I2C flag */
I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_iwdg.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the IWDG firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_iwdg.h"
//IWDG_BASE 未定义
#ifdef 0
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/** @defgroup IWDG_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Defines
* @{
*/
/* ---------------------- IWDG registers bit mask ----------------------------*/
/* KR register bit mask */
#define KR_KEY_Reload ((uint16_t)0xAAAA)
#define KR_KEY_Enable ((uint16_t)0xCCCC)
/**
* @}
*/
/** @defgroup IWDG_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/**
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR
* registers.
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and
* IWDG_RLR registers.
* This parameter can be one of the following values:
* @arg IWDG_WriteAccess_Enable: Enable write access to
* IWDG_PR and IWDG_RLR registers
* @arg IWDG_WriteAccess_Disable: Disable write access to
* IWDG_PR and IWDG_RLR registers
* @retval : None
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
/* Check the parameters */
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
IWDG->KR = IWDG_WriteAccess;
}
/**
* @brief Sets IWDG Prescaler value.
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
* @retval : None
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
/* Check the parameters */
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
IWDG->PR = IWDG_Prescaler;
}
/**
* @brief Sets IWDG Reload value.
* @param Reload: specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
* @retval : None
*/
void IWDG_SetReload(uint16_t Reload)
{
/* Check the parameters */
assert_param(IS_IWDG_RELOAD(Reload));
IWDG->RLR = Reload;
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param None
* @retval : None
*/
void IWDG_ReloadCounter(void)
{
IWDG->KR = KR_KEY_Reload;
}
/**
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
* disabled).
* @param None
* @retval : None
*/
void IWDG_Enable(void)
{
IWDG->KR = KR_KEY_Enable;
}
/**
* @brief Checks whether the specified IWDG flag is set or not.
* @param IWDG_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
* @arg IWDG_FLAG_RVU: Reload Value Update on going
* @retval : The new state of IWDG_FLAG (SET or RESET).
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif // 0
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_misc.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_misc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
* 0 bits for subpriority
* @retval None
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
//void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
//{
// /* Check the parameters */
// assert_param(IS_TIM_ALL_PERIPH(TIMx));
// assert_param(IS_TIM_IT(TIM_IT));
// assert_param(IS_FUNCTIONAL_STATE(NewState));
//
// if (NewState != DISABLE)
// {
// /* Enable the Interrupt sources */
// TIMx->DIER |= TIM_IT;
// }
// else
// {
// /* Disable the Interrupt sources */
// TIMx->DIER &= (uint16_t)~TIM_IT;
// }
//}
//void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
//{
// /* Check the parameters */
// assert_param(IS_TIM_ALL_PERIPH(TIMx));
// assert_param(IS_FUNCTIONAL_STATE(NewState));
//
// if (NewState != DISABLE)
// {
// /* Enable the TIM Counter */
// TIMx->CR1 |= TIM_CR1_CEN;
// }
// else
// {
// /* Disable the TIM Counter */
// TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
// }
//}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
* the configuration information for the specified NVIC peripheral.
* @retval None
*/
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
tmppre = NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05];
//printf("NVIC->ISER = 0x%x\r\n",tmppre);
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset: Vector Table base offset field. This value must be a multiple
* of 0x200.
* @retval None
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
//SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
{
if (NewState != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_pwr.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the PWR firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_pwr.h"
#include "HAL_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup PWR
* @brief PWR driver modules
* @{
*/
/** @defgroup PWR_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Defines
* @{
*/
/* --------- PWR registers bit address in the alias region ---------- */
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
/* --- CR Register ---*/
/* Alias word address of DBP bit */
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
/* Alias word address of PVDE bit */
#define PVDE_BitNumber 0x04
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
/* --- CSR Register ---*/
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
/* ------------------ PWR registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_PDDS_Set ((uint32_t)0x00000002)
#define CR_DS_Mask ((uint32_t)0xFFFFFFFC)
#define CR_CWUF_Set ((uint32_t)0x00000004)
#define CR_PLS_Mask ((uint32_t)0xFFFFE1FF)
/* --------- Cortex System Control register bit mask ---------------- */
/* Cortex System Control register address */
#define SCB_SysCtrl ((uint32_t)0xE000ED10)
/* SLEEPDEEP bit mask */
#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004)
/**
* @}
*/
/** @defgroup PWR_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup PWR_Private_Functions
* @{
*/
/**
* @brief Deinitializes the PWR peripheral registers to their default
* reset values.
* @param None
* @retval : None
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/**
* @brief Enables or disables access to the RTC and backup registers.
* @param NewState: new state of the access to the RTC and backup
* registers. This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
//*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
if(NewState!=DISABLE)
{
PWR->CR |= 0x00000100;
}
else
{
PWR->CR &= 0xfffffeff;
}
}
/**
* @brief Enables or disables the Power Voltage Detector(PVD).
* @param NewState: new state of the PVD.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void PWR_PVDCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState==ENABLE)
{
PWR->CR |= 0x00000010;
}
else
{
PWR->CR &= 0xffffffef;
}
}
/**
* @brief Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
* @param PWR_PVDLevel: specifies the PVD detection level
* This parameter can be one of the following values:
* @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
* @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
* @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V
* @arg PWR_PVDLevel_3V2: PVD detection level set to 3.2V
* @arg PWR_PVDLevel_3V4: PVD detection level set to 3.4V
* @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V
* @arg PWR_PVDLevel_3V8: PVD detection level set to 3.8V
* @arg PWR_PVDLevel_4V0: PVD detection level set to 4.0V
* @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V
* @arg PWR_PVDLevel_4V4: PVD detection level set to 4.4V
* @arg PWR_PVDLevel_4V6: PVD detection level set to 4.6V
* @retval : None
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
tmpreg = PWR->CR;
/* Clear PLS[7:5] bits */
tmpreg &= CR_PLS_Mask;
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
tmpreg |= PWR_PVDLevel;
/* Store the new value */
PWR->CR = tmpreg;
}
/**
* @brief Enables or disables the WakeUp Pin functionality.
* @param NewState: new state of the WakeUp Pin functionality.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if(NewState!=DISABLE)
{
PWR->CSR |= 0x00000100;
}
else
{
PWR->CSR &= 0xfffffeff;
}
}
/**
* @brief Enters STOP mode.
* @param PWR_Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_Regulator_ON: STOP mode with regulator ON
* @arg PWR_Regulator_LowPower: STOP mode with
* regulator in low power mode
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or
* WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
* @retval : None
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_Mask;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
}
/**
* @brief Enters STANDBY mode.
* @param None
* @retval : None
*/
void PWR_EnterSTANDBYMode(void)
{
/* Clear Wake-up flag */
PWR->CR |= CR_CWUF_Set;
/* Select STANDBY mode */
PWR->CR |= CR_PDDS_Set;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM )
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief Checks whether the specified PWR flag is set or not.
* @param PWR_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_PVDO: PVD Output
* @retval : The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
/* Return the flag status */
return bitstatus;
}
/**
* @brief Clears the PWR's pending flags.
* @param PWR_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
* @retval : None
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
/* Check the parameters */
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
PWR->CR |= PWR_FLAG << 2;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_spi.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the SPI firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_spi.h"
#include "HAL_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup SPI
* @brief SPI driver modules
* @{
*/
/** @defgroup SPI_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Defines
* @{
*/
/* SPI SPIENE mask */
#define GCTL_SPIEN_Set ((uint16_t)0x0001)
#define GCTL_SPIEN_Reset ((uint16_t)0xFFFE)
/* SPI registers Masks */
#define GCTL_CLEAR_Mask ((uint16_t)0xF000)
#define CCTL_CLEAR_Mask ((uint16_t)0xFFC0)
#define SPBRG_CLEAR_Mask ((uint16_t)0x0000)
#define SPI_DataSize_Mask ((uint16_t)0xFCFF)
/**
* @}
*/
/** @defgroup SPI_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup SPI_Private_Functions
* @{
*/
/**
* @brief Deinitializes the SPIx peripheral registers to their default
* reset values .
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @retval : None
*/
void SPI_DeInit(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
switch (*(uint32_t*)&SPIx)
{
case SPI1_BASE:
/* Enable SPI1 reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
/* Release SPI1 from reset state */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
break;
default:
break;
}
}
/**
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified
* SPI peripheral.
* @retval : None
*/
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
{
uint32_t tmpreg = 0;
/* check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Check the SPI parameters */
assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
assert_param(IS_SPI_DATAWIDRH(SPI_InitStruct->SPI_DataWidth));
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
/*---------------------------- SPIx GCTL Configuration ------------------------*/
/* Get the SPIx GCTL value */
tmpreg = SPIx->GCTL;
/* Clear csn_sel, dmamode, txtlf, rxtlf,data_sel, rxen, txen, mm, int_en, spien bits */
tmpreg &= GCTL_CLEAR_Mask;
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
master/salve mode, CPOL and CPHA */
/* Set dat_sel bits according to SPI_DataSize value */
/* Set csn and csn_sel bits according to SPI_NSS value */
/* Set mm bit according to SPI_Mode value */
tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_Mode );
/* Write to SPIx GCTL */
// if(SPI_InitStruct->SPI_DataSize==SPI_DataSize_8b) tmpreg |= 0x1000;
SPIx->GCTL = tmpreg;
/*---------------------------- SPIx CCTL Configuration ------------------------*/
tmpreg = SPIx->CCTL;
/* Clear spilen, lsbfe, CPOL, CPHA bits */
tmpreg &= CCTL_CLEAR_Mask;
/* Set Spilen bit according to SPI_DataWidth value */
/* Set LSBFirst bit according to SPI_FirstBit value */
/* Set CPOL bit according to SPI_CPOL value */
/* Set CPHA bit according to SPI_CPHA value */
tmpreg |= (uint16_t)((uint16_t) SPI_InitStruct->SPI_DataWidth | SPI_InitStruct->SPI_FirstBit | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA );
/* Write to SPIx CCTL */
SPIx->CCTL = tmpreg;
/*---------------------------- SPIx SPBRG Configuration ------------------------*/
tmpreg = SPIx->SPBRG;
/* Clear spbrg bits */
tmpreg &= (uint16_t)SPBRG_CLEAR_Mask;
/* Set BR bits according to SPI_BaudRatePrescaler value */
tmpreg |= (uint16_t) SPI_InitStruct->SPI_BaudRatePrescaler;
/* Write to SPIx SPBRG */
SPIx->SPBRG = tmpreg;
}
/**
* @brief Fills each SPI_InitStruct member with its default value.
* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
{
/*--------------- Reset SPI init structure parameters values -----------------*/
/* initialize the SPI_Mode member */
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
/* initialize the SPI_DataSize member */
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
/* Initialize the SPILEN member */
SPI_InitStruct->SPI_DataWidth = SPI_DataWidth_8b;
/* Initialize the SPI_CPOL member */
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
/* Initialize the SPI_CPHA member */
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
/* Initialize the SPI_NSS member */
SPI_InitStruct->SPI_NSS = SPI_NSS_Soft;
/* Initialize the SPI_BaudRatePrescaler member */
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
/* Initialize the SPI_FirstBit member */
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
}
/**
* @brief Enables or disables the specified SPI peripheral.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param NewState: new state of the SPIx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected SPI peripheral */
SPIx->GCTL |= GCTL_SPIEN_Set;
}
else
{
/* Disable the selected SPI peripheral */
SPIx->GCTL &= GCTL_SPIEN_Reset;
}
}
/**
* @brief Enables or disables the specified SPIinterrupts.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to be
* enabled or disabled.
* This parameter can be one of the following values:
* @arg SPI_IT_TX: Tx buffer empty interrupt mask
* @arg SPI_IT_RX: Rx buffer interrupt mask
* @arg SPI_IT_UNDERRUN: under Error interrupt mask in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt mask
* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask
* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask
* @param NewState: new state of the specified SPI interrupt.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_CONFIG_IT(SPI_IT));
if (NewState != DISABLE)
{
/* Enable the selected SPI Global interrupt */
SPIx->GCTL |= SPI_INT_EN;
/* Enable the selected SPI interrupt */
SPIx->INTEN |= SPI_IT;
}
else
{
/* Disable the selected SPI interrupt */
SPIx->INTEN &= (uint16_t)~SPI_IT;
/* Disable the selected SPI Global interrupt */
SPIx->GCTL &= (uint16_t)~SPI_INT_EN;
}
}
/**
* @brief Enables or disables the SPIx DMA interface.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_DMAReq: specifies the SPI DMA transfer request
* to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg SPI_DMAReq_EN: DMA transfer request enable
* @param NewState: new state of the selected SPI DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
if (NewState != DISABLE)
{
/* Enable the selected SPI DMA requests */
SPIx->GCTL |= SPI_DMAReq;
}
else
{
/* Disable the selected SPI DMA requests */
SPIx->GCTL &= (uint32_t)~SPI_DMAReq;
}
}
/**
* @brief configure tn Fifo trigger level bit.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_FifoTriggerValue: specifies the Fifo trigger level
* This parameter can be any combination of the following values:
* SPI_TXTLF : SPI TX FIFO Trigger value set
* SPI_RXTLF : SPI RX FIFO Trigger value set
* @param NewState: new state of the selected SPI DMA transfer
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
assert_param(IS_SPI_FIFOTRIGGER(SPI_FifoTriggerValue));
if (NewState != DISABLE)
{
/* Enable the selected SPI DMA requests */
SPIx->GCTL |= SPI_FifoTriggerValue;
}
else
{
/* Disable the selected SPI DMA requests */
SPIx->GCTL &= (uint32_t)~SPI_FifoTriggerValue;
}
}
/**
* @brief Transmits a Data through the SPIx peripheral.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param Data : Data to be transmitted..
* @retval : None
*/
void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Write in the TXREG register the data to be sent */
SPIx->TXREG = Data;
}
/**
* @brief Returns the most recent received data by the SPIx peripheral.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @retval : The value of the received data.
*/
uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/* Return the data in the RXREG register */
return SPIx->RXREG;
}
/**
* @brief Slave chip csn single by selected
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_CSInternalSelected: specifies the SPI CS internal selected.
* This parameter can be one of the following values:
* @arg SPI_CS_BIT0: cs bit 0 selected
* @arg SPI_CS_BIT1: cs bit 1 selected
* @arg SPI_CS_BIT2: cs bit 2 selected
* @arg SPI_CS_BIT3: cs bit 3 selected
* @arg SPI_CS_BIT4: cs bit 4 selected
* @arg SPI_CS_BIT5: cs bit 5 selected
* @arg SPI_CS_BIT6: cs bit 6 selected
* @arg SPI_CS_BIT7: cs bit 7 selected
* @param NewState: new state of the selected SPI CS pin
* request.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected,FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CS(SPI_CSInternalSelected));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* selected cs pin according SCSR Value */
SPIx->SCSR &= SPI_CSInternalSelected;
}
else
{
/* release cs pin according SCSR Value*/
SPIx->SCSR |= ~SPI_CSInternalSelected;
}
}
/**
* @brief Configures the data size for the selected SPI.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_DataSize: specifies the SPI data size.
* This parameter can be one of the following values:
* @arg SPI_DataSize_32b: Set data frame format to 32bit
* @arg SPI_DataSize_16b: Set data frame format to 16bit
* @arg SPI_DataSize_8b: Set data frame format to 8bit
* @retval : None
*/
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DATASIZE(SPI_DataSize));
/* Clear data_sel bit */
SPIx->GCTL &= SPI_DataSize_Mask;
/* Set new data_sel bit value */
SPIx->GCTL |= SPI_DataSize;
}
/**
* @brief Selects the data transfer direction in bi-directional mode
* for the specified SPI.
* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
* @param SPI_Direction: specifies the data transfer direction in
* bi-directional mode.
* This parameter can be one of the following values:
* @arg SPI_Direction_Tx: Selects Tx transmission direction
* @arg SPI_Direction_Rx: Selects Rx receive direction
@arg SPI_Disable_Tx: Selects Rx receive direction
@arg SPI_Disable_Rx: Selects Rx receive direction
* @retval : None
*/
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_DIRECTION(SPI_Direction));
/* Set the Tx only mode */
if(SPI_Direction==SPI_Direction_Tx)
{
SPIx->GCTL |= SPI_Direction_Tx;
}
/* Set the Rx only mode */
if(SPI_Direction==SPI_Direction_Rx)
{
SPIx->GCTL |= SPI_Direction_Rx;
}
/* Disable the Tx only mode */
if(SPI_Direction==SPI_Disable_Tx)
{
SPIx->GCTL &= SPI_Disable_Tx;
}
/* Disable the Rx only mode */
if(SPI_Direction==SPI_Disable_Rx)
{
SPIx->GCTL &= SPI_Disable_Rx;
}
}
/**
* @brief Checks whether the specified SPI flag is set or not.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_FLAG: specifies the SPI flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag
* @arg SPI_FLAG_TXEPT: Tx buffer and tx shifter empty flag
* @retval : The new state of SPI_FLAG (SET or RESET).
*/
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
/* Check the status of the specified SPI flag */
if ((SPIx->CSTAT & SPI_FLAG) != (uint16_t)RESET)
{
/* SPI_FLAG is set */
bitstatus = SET;
}
else
{
/* SPI_FLAG is reset */
bitstatus = RESET;
}
/* Return the SPI_FLAG status */
return bitstatus;
}
/**
* @brief Checks whether the specified SPI interrupt has occurred or not.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TX: Tx buffer empty interrupt
* @arg SPI_IT_RX: Rx buffer interrupt
* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXFULL: Rx buffer full interrupt
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* @retval : The new state of SPI_IT (SET or RESET).
*/
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)
{
ITStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_GET_IT(SPI_IT));
/* Check the status of the specified SPI interrupt */
if ((SPIx->INTSTAT & SPI_IT) != (uint16_t)RESET)
{
/* SPI_IT is set */
bitstatus = SET;
}
else
{
/* SPI_IT is reset */
bitstatus = RESET;
}
/* Return the SPI_IT status */
return bitstatus;
}
/**
* @brief Clears the SPIx Error interrupt pending bit.
* @param SPIx: where x can be :
* 0, 1 in SPI mode
* @param SPI_IT: specifies the SPI interrupt pending bit to clear.
* @arg SPI_IT_TX: Tx buffer empty interrupt
* @arg SPI_IT_RX: Rx buffer interrupt
* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
* @arg SPI_IT_RXOVER: RX OVER Error interrupt
* @arg SPI_IT_RXMATCH: spectials rx data numbers interrupt
* @arg SPI_IT_RXFULL: Rx buffer full interrupt
* @arg SPI_IT_TXEPT: Tx buffer and tx shifter empty interrupt
* This function clears only ERR intetrrupt pending bit.
* @retval : None
*/
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_CLEAR_IT(SPI_IT));
/* Clear the selected SPI IT INTERRUPT */
SPIx->INTCLR |= (uint16_t)SPI_IT;
}
/**
* @brief SPI Hole a count Received bytes in next receive process.
* @param SPIx: where x can be 0, 1 in SPI mode
* @param Number: specifies the SPI receive Number.
* This parament can be 1-65535.
* This function can use only in SPI master single receive mode.
* @retval : None
*/
void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
/*set the received bytes in next receive process */
SPIx->RXDNR = Number;
}
/**
* @brief slave mode tx data transmit phase adjust set.
* @param SPIx: where x can be 0, 1 in SPI mode
* @param AdjustValue: specifies the SPI receive Number.
* This parament can be :
* SPI_SlaveAdjust_FAST: fast speed use
* SPI_SlaveAdjust_LOW: low speed use
* This function can use only in SPI master single receive mode.
* @retval : None
*/
void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue)
{
/* Check the parameters */
assert_param(IS_SPI_ALL_PERIPH(SPIx));
assert_param(IS_SPI_SlaveAdjust(AdjustValue));
/*set the AdjustValue according to txedge bit of CCTL register*/
SPIx->CCTL |= AdjustValue;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_syscfg.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides firmware functions to manage the following
* functionalities of the SYSCFG peripheral:
* + Remapping the memory mapped at 0x00000000
* + Remapping the DMA channels
* + Enabling I2C fast mode plus driving capability for I2C pins
* + Configuring the EXTI lines connection to the GPIO port
* + Configuring the CFGR2 features (Connecting some internal signal
* to the break input of TIM1)
*
* @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The SYSCFG registers can be accessed only when the SYSCFG
interface APB clock is enabled.
To enable SYSCFG APB clock use:
RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
* @endverbatim
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_syscfg.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup SYSCFG
* @brief SYSCFG driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Functions
* @{
*/
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
* @brief SYSCFG Initialization and Configuration functions
*
@verbatim
===============================================================================
##### SYSCFG Initialization and Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Deinitializes the SYSCFG registers to their default reset values.
* @param None
* @retval None
* @note MEM_MODE bits are not affected by APB reset.
* @note MEM_MODE bits took the value from the user option bytes.
* @note CFGR2 register is not affected by APB reset.
* @note CLABBB configuration bits are locked when set.
* @note To unlock the configuration, perform a system reset.
*/
void SYSCFG_DeInit(void)
{
/* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
SYSCFG->CFGR &= SYSCFG_CFGR_MEM_MODE;
/* Set EXTICRx registers to reset value */
SYSCFG->EXTICR[0] = 0;
SYSCFG->EXTICR[1] = 0;
SYSCFG->EXTICR[2] = 0;
SYSCFG->EXTICR[3] = 0;
}
/**
* @brief Configures the memory mapping at address 0x00000000.
* @param SYSCFG_MemoryRemap: selects the memory remapping.
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
{
uint32_t tmpctrl = 0;
/* Check the parameter */
assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
/* Get CFGR1 register value */
tmpctrl = SYSCFG->CFGR;
/* Clear MEM_MODE bits */
tmpctrl &= (uint32_t) (~SYSCFG_CFGR_MEM_MODE);
/* Set the new MEM_MODE bits value */
tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
/* Set CFGR1 register with the new memory remap configuration */
SYSCFG->CFGR = tmpctrl;
}
/**
* @brief Configure the DMA channels remapping.
* @param SYSCFG_DMARemap: selects the DMA channels remap.
* This parameter can be one of the following values:
* @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
* @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
* @arg SYSCFG_DMARemap_UART1Rx: Remap UART1 Rx DMA requests from channel3 to channel5
* @arg SYSCFG_DMARemap_UART1Tx: Remap UART1 Tx DMA requests from channel2 to channel4
* @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
* @param NewState: new state of the DMA channel remapping.
* This parameter can be: ENABLE or DISABLE.
* @note When enabled, DMA channel of the selected peripheral is remapped
* @note When disabled, Default DMA channel is mapped to the selected peripheral
* @note By default TIM17 DMA requests is mapped to channel 1,
* use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
* TIM17 DMA requests to channel 2 and use
* SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
* TIM17 DMA requests to channel 1 (default mapping)
* @retval None
*/
void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Remap the DMA channel */
SYSCFG->CFGR |= (uint32_t)SYSCFG_DMARemap;
}
else
{
/* use the default DMA channel mapping */
SYSCFG->CFGR &= (uint32_t)(~SYSCFG_DMARemap);
}
}
/**
* @brief Selects the GPIO pin used as EXTI Line.
* @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
* for EXTI lines where x can be (A, B, C, D, E or F).
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
* @note This parameter can be EXTI_PinSourcex where x can be:
* For MCU: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOD.
* @retval None
*/
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
{
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_UART.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the UART firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_uart.h"
#include "HAL_rcc.h"
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup UART
* @brief UART driver modules
* @{
*/
/** @defgroup UART_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup UART_Private_Defines
* @{
*/
/* UART UE Mask */
#define GCR_UE_Set ((uint16_t)0x0001) /* UART Enable Mask */
#define GCR_UE_Reset ((uint16_t)0xFFFE) /* UART Disable Mask */
#define CCR_CLEAR_Mask ((uint32_t)0xFFFFFF30) /* UART CCR Mask */
#define GCR_CLEAR_Mask ((uint32_t)0xFFFFFFE0) /* UART GCR Mask */
/**
* @}
*/
/** @defgroup UART_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup UART_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup UART_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup UART_Private_Functions
* @{
*/
/**
* @brief Deinitializes the UARTx peripheral registers to their
* default reset values.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @retval : None
*/
void UART_DeInit(UART_TypeDef* UARTx)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
switch (*(uint32_t*)&UARTx)
{
case UART1_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, DISABLE);
break;
default:
break;
}
}
/**
* @brief Initializes the UARTx peripheral according to the specified
* parameters in the UART_InitStruct .
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param UART_InitStruct: pointer to a UART_InitTypeDef structure
* that contains the configuration information for the
* specified UART peripheral.
* @retval : None
*/
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
{
uint32_t tmpreg = 0x00;
RCC_ClocksTypeDef RCC_ClocksStatus;
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate));
assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
/*---------------------------- UART CCR Configuration -----------------------*/
/* get UART CCR values */
tmpreg = UARTx->CCR;
/* Clear spb,psel,pen bits */
tmpreg &= CCR_CLEAR_Mask;
/* Configure the UART Word Length,the UART Stop Bits,Parity ------------*/
/* Set the char bits according to UART_WordLength value */
/* Set spb bit according to UART_StopBits value */
/* Set PEN bit according to UART_Parity value */
tmpreg |= (uint32_t)UART_InitStruct->UART_WordLength |(uint32_t)UART_InitStruct->UART_StopBits |UART_InitStruct->UART_Parity;
/* Write to UART CCR */
UARTx->CCR = tmpreg;
/*---------------------------- UART GCR Configuration -----------------------*/
/* get UART GCR values */
tmpreg = UARTx->GCR;
/* Clear TXEN and RXEN ,autoflowen, mode ,uarten bits */
tmpreg &= GCR_CLEAR_Mask;
/* Set autorlowen bit according to UART_HardwareFlowControl value */
/* Set rxen,txen bits according to UART_Mode value */
tmpreg |= UART_InitStruct->UART_HardwareFlowControl | UART_InitStruct->UART_Mode ;
/* Write to UART GCR */
UARTx->GCR = tmpreg;
/*---------------------------- UART BRR Configuration -----------------------*/
/* Configure the UART Baud Rate -------------------------------------------RCC_ClocksStatus.PCLK1_Frequency;*/
RCC_GetClocksFreq(&RCC_ClocksStatus);
/* Determine the UART_baud*/
tmpreg = ((RCC_ClocksStatus.PCLK1_Frequency)/(UART_InitStruct->UART_BaudRate)/16) ;
/* Write to UART BRR */
UARTx->BRR = tmpreg;
}
/**
* @brief Fills each UART_InitStruct member with its default value.
* @param UART_InitStruct: pointer to a UART_InitTypeDef structure
* which will be initialized.
* @retval : None
*/
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* UART_InitStruct members default value */
UART_InitStruct->UART_BaudRate = 9600;
UART_InitStruct->UART_WordLength = UART_WordLength_8b;
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_No ;
UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;
}
/**
* @brief Enables or disables the specified UART peripheral.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param NewState: new state of the UARTx peripheral.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the selected UART by setting the uarten bit in the GCR register */
UARTx->GCR |= GCR_UE_Set;
}
else
{
/* Disable the selected UART by clearing the uarten bit in the GCR register */
UARTx->GCR &= GCR_UE_Reset;
}
}
/**
* @brief Enables or disables the specified UART interrupts.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param UART_IT: specifies the UART interrupt sources to be
* enabled or disabled.
* This parameter can be one of the following values:
*
* @arg UART_IT_ERR: Error interrupt(Frame error,)
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_OVER_ERR: overrun Error interrupt
* @arg UART_TIMEOUT_ERR: timeout Error interrupt
* @arg UART_IT_RXIEN: Receive Data register interrupt
* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
* @param NewState: new state of the specified UARTx interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval : None
*/
void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_CONFIG_IT(UART_IT));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the UART_IT interrupt */
UARTx->IER |= UART_IT;
}
else
{
/* Disable the UART_IT interrupt */
UARTx->IER &= ~ UART_IT;
}
}
/**
* @brief Enables or disables the UART’s DMA interface.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3 .
* @param UART_DMAReq: specifies the DMA request.
* This parameter can be any combination of the following values:
* @arg UART_DMAReq_EN: UART DMA transmit request
*
* @param NewState: new state of the DMA Request sources.
* This parameter can be: ENABLE or DISABLE.
* @note The DMA mode is not available for UART5.
* @retval : None
*/
void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_UART_1234_PERIPH(UARTx));
assert_param(IS_UART_DMAREQ(UART_DMAReq));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
/* Enable the DMA transfer */
UARTx->GCR |= UART_DMAReq;
}
else
{
/* Disable the DMA transfer */
UARTx->GCR &= ~UART_DMAReq;
}
}
/**
* @brief Transmits single data through the UARTx peripheral.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param Data: the data to transmit.
* @retval : None
*/
void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_DATA(Data));
/* Transmit Data */
UARTx->TDR = (Data & (uint16_t)0x00FF);
}
/**
* @brief Returns the most recent received data by the UARTx peripheral.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @retval : The received data.
*/
uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
/* Receive Data */
return (uint16_t)(UARTx->RDR & (uint16_t)0x00FF);
}
/**
* @brief Checks whether the specified UART flag is set or not.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param UART_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag
* @arg UART_FLAG_TXFULL:Transmit data buffer full
* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag
* @arg UART_FLAG_OVER:OverRun Error flag
* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
* @retval : The new state of UART_FLAG (SET or RESET).
*/
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_FLAG(UART_FLAG));
if ((UARTx->CSR & UART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the UARTx's pending flags.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3, UART4 or UART5.
* @param UART_FLAG: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag
* @arg UART_FLAG_TXFULL:Transmit data buffer full
* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag
* @arg UART_FLAG_OVER:OverRun Error flag
* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
* @retval : None
*/
void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
}
/**
* @brief Checks whether the specified UART interrupt has occurred or not.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3.
* @param UART_IT: specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_ERR: Error interrupt(Frame error,)
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_OVER_ERR: overrun Error interrupt
* @arg UART_TIMEOUT_ERR: timeout Error interrupt
* @arg UART_IT_RXIEN: Receive Data register interrupt
* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
* @retval : The new state of UART_IT (SET or RESET).
*/
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
{
FlagStatus bitstatus = RESET;
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_FLAG(UART_FLAG));
assert_param(IS_UART_PERIPH_FLAG(UARTx, UART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */
if ((UARTx->ISR & UART_IT) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/**
* @brief Clears the UARTx’s interrupt pending bits.
* @param UARTx: Select the UART or the UART peripheral.
* This parameter can be one of the following values:
* UART1, UART2, UART3, UART4 or UART5.
* @param UART_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg UART_IT_ERR: Error interrupt(Frame error,)
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_OVER_ERR: overrun Error interrupt
* @arg UART_TIMEOUT_ERR: timeout Error interrupt
* @arg UART_IT_RXIEN: Receive Data register interrupt
* @arg UART_IT_TXIEN: Tansmit Data Register empty interrupt
* @retval : None
*/
void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
{
/* Check the parameters */
assert_param(IS_UART_ALL_PERIPH(UARTx));
assert_param(IS_UART_CLEAR_IT(UART_IT));
assert_param(IS_UART_PERIPH_IT(UARTx, UART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
/*clear UART_IT pendings bit*/
UARTx->ICR = UART_IT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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/**
******************************************************************************
* @file HAL_wwdg.c
* @author IC Applications Department
* @version V0.8
* @date 2019_08_02
* @brief This file provides all the WWDG firmware functions.
******************************************************************************
* @copy
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT,HOLOCENE SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 HOLOCENE</center></h2>
*/
/* Includes ------------------------------------------------------------------*/
#include "HAL_wwdg.h"
#include "HAL_rcc.h"
//WWDG_BASE 未定义
#ifdef 0
/** @addtogroup StdPeriph_Driver
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/** @defgroup WWDG_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Defines
* @{
*/
/* ----------- WWDG registers bit address in the alias region ----------- */
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
/* Alias word address of EWI bit */
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
#define EWI_BitNumber 0x09
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
/* --------------------- WWDG registers bit mask ------------------------ */
/* CR register bit mask */
#define CR_WDGA_Set ((uint32_t)0x00000080)
/* CFR register bit mask */
#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F)
/**
* @}
*/
/** @defgroup WWDG_Private_Macros
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Variables
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/**
* @brief Deinitializes the WWDG peripheral registers to their default
* reset values.
* @param None
* @retval : None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
}
/**
* @brief Sets the WWDG Prescaler.
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
* This parameter can be one of the following values:
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
* @retval : None
*/
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
/* Clear WDGTB[1:0] bits */
tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
tmpreg |= WWDG_Prescaler;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Sets the WWDG window value.
* @param WindowValue: specifies the window value to be compared to
* the downcounter.
* This parameter value must be lower than 0x80.
* @retval : None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
/* Clear W[6:0] bits */
tmpreg = WWDG->CFR & CFR_W_Mask;
/* Set W[6:0] bits according to WindowValue value */
tmpreg |= WindowValue & BIT_Mask;
/* Store the new value */
WWDG->CFR = tmpreg;
}
/**
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
* @param None
* @retval : None
*/
void WWDG_EnableIT(void)
{
WWDG->CFR |= (uint32_t)0x200;
}
/**
* @brief Sets the WWDG counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* @retval : None
*/
void WWDG_SetCounter(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
/* Write to T[6:0] bits to configure the counter value, no need to do
a read-modify-write; writing a 0 to WDGA bit does nothing */
WWDG->CR = Counter & BIT_Mask;
}
/**
* @brief Enables WWDG and load the counter value.
* @param Counter: specifies the watchdog counter value.
* This parameter must be a number between 0x40 and 0x7F.
* @retval : None
*/
void WWDG_Enable(uint8_t Counter)
{
/* Check the parameters */
assert_param(IS_WWDG_COUNTER(Counter));
WWDG->CR = CR_WDGA_Set | Counter;
}
/**
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
* @param None
* @retval : The new state of the Early Wakeup interrupt flag (SET or RESET)
*/
FlagStatus WWDG_GetFlagStatus(void)
{
return (FlagStatus)(WWDG->SR);
}
/**
* @brief Clears Early Wakeup interrupt flag.
* @param None
* @retval : None
*/
void WWDG_ClearFlag(void)
{
WWDG->SR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif // 0
/*-------------------------(C) COPYRIGHT 2016 HOLOCENE ----------------------*/

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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('Hal_lib/src/*.c')
src += [cwd + '/CMSIS_and_startup/sys.c']
src += [cwd + '/CMSIS_and_startup/startup_Tk499.s']
path = [
cwd + '/CMSIS_and_startup/CMSIS',
cwd + '/CMSIS_and_startup',
cwd + '/Hal_lib/inc',]
CPPDEFINES = []
group = DefineGroup('TKM32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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# TKM32F499
## 简介
本文档为 TKM32F499 液晶屏评估板的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
TKM32F499 液晶屏评估板是深圳市好钜润科技有限公司官方推出的开发板，搭载 TKM32F499 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 TKM32F499 的芯片性能。
开发板外观如下图所示：
![board](figures/board.jpg)
该开发板常用 **板载资源** 如下：
- MCU：TKM32F499，主频 240MHz ，8MB RAM，带FPU，DMA 单次 42 亿点
- 常用外设
- LED：3个，LD1（PD8），LD2（PB14），LD3（PB15）
- 按键：5 向按键 1 个，RESET
- 常用接口：TK80接口（向下兼容老式8080接口）
官方资料：[TKM32F499评估板参考资料](http://hjrkj.com/companyfile/1.html)
*更多相关信息资料见官网详情页：[TKM32F499芯片及评测](http://hjrkj.com/product/13.html)*
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------- | :----------: | :----------- |
| GPIO | 支持 | |
| UART | 支持 | UART1、UART2 |
| SPI | 暂不支持 | |
| I2C | 暂不支持 | |
| RTC | 暂不支持 | |
| PWM | 暂不支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，连接串口1到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 可以通过 bootloader 自带 usb下载，通过 u 盘方式下载：
>
> * 方法一：五向按键向上推（按下 PA1 按键，又名 APP 键） ，同时按一下复位（注意，松手时，先松复位，再松五向按键），然后点一下 KEIL 的下载按钮即可
> * 方法二：向上推， 同时按一下复位，然后先松开复位再松开向上按键， 就会进入程序下载模式， 电脑会弹出一个 TK499_V2 盘符的 U 盘，把 KEIL 工程目录下生成的 bin 程序拖进 U盘就行
>
> 本工程下自带官方的 bootloader ，通过把五向按键向左推（按下 PA13 按键，又名 BOOT 键） ， 同时再按一下复位，然后先松开复位再松开向上按键就进入了 Bootloader 下载模式。这时会弹出一个盘符为 TK499 的 U 盘，把本工程下的 Bootloader.bin 拖进去即可重新烧录 bootloader
>
> 注意：
>
> * bootloader 默认的波特率为460800，所以会在启动 rtthread 时存在乱码
> * 该芯片有个致命问题：复位引脚不能正常复位，断电重启了才可以。如有莫名其妙的问题请断电重启。出处https://www.amobbs.com/thread-5748003-1-1.html
#### 运行结果
下载程序成功之后，系统会自动运行，橘黄色 LD2 会周期性闪烁。
USB 虚拟 COM 端口默认连接串口 1，在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Oct 14 2021
2006 - 2021 Copyright by rt-thread team
msh >
```
* 注意：官方 bootloader 使用的是串口1，且波特率为460800，所以会在一开始有一段乱码
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口1 的功能，更多高级功能需要利用 ENV 工具对 BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## 联系人信息
维护人：[NU-LL](https://github.com/NU-LL)

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# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread-tkm32f4xx.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#include <rtdbg.h>
#include <stdio.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_gpio.h"
#define LED_PIN GET_PIN(D, 8)
#define LED0_PIN GET_PIN(B, 14)
#define LED1_PIN GET_PIN(B, 15)
int main(void)
{
/* set LED pin mode to output */
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
rt_pin_write(LED_PIN, PIN_LOW);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_pin_write(LED1_PIN, PIN_LOW);
while (1)
{
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}

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menu "Hardware Drivers Config"
config SOC_SERIES_TKM32F4
bool
default y
config SOC_TKM32F499
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_TKM32F4
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART
select BSP_USING_UART1
default y
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1 PA9/10(T/R)"
default y
config BSP_USING_UART2
bool "Enable UART2 PA2/3(T/R)"
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 175
default 22
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 175
default 23
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
board.c
""")
# add serial driver code
if GetDepend('RT_USING_SERIAL'):
src += ['drv_uart.c']
# add gpio driver code
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2017-2019, MindMotion AE Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#include <rtthread.h>
#include <rthw.h>
#include <board.h>
#include <drv_uart.h>
// extern uint32_t SystemCoreClock;
// extern void SystemInit(void);
#ifdef RT_USING_FINSH
#include <finsh.h>
static void reboot(uint8_t argc, char **argv)
{
rt_hw_cpu_reset();
}
MSH_CMD_EXPORT(reboot, Reboot System);
#endif /* RT_USING_FINSH */
static void bsp_clock_config(void)
{
RemapVtorTable();
SystemClk_HSEInit(RCC_PLLMul_20);//启动PLL时钟，12MHz*20=240MHz
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);//2：2，全局性函数，仅需设置一次
uint32_t sysclk = 0;
getSystemClock(&sysclk);
SysTick_Config(sysclk / RT_TICK_PER_SECOND);
SysTick->CTRL |= 0x00000004UL;
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void rt_hw_board_init()
{
bsp_clock_config();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
// volatile uint16_t i=0;
// rt_hw_uart_init();
// i = UINT16_MAX;
// while(i--); //wait for a while after uart initiated.
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

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/*
* Copyright (c) 2017-2019, MindMotion AE Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <hal_device.h>
#include "sys.h"
#define SRAM_SIZE (8 * 1024 * 1024)
// #define SRAM_BASE ((uint32_t)0x70000000)
#define SRAM_END (T_SDRAM_BASE + SRAM_SIZE)
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END SRAM_END
#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
extern void rt_hw_board_init(void);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include <rthw.h>
#include <drv_gpio.h>
#ifdef RT_USING_PIN
#define TKM32_PIN(index, rcc, gpio, gpio_index) { index, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, \
((rt_base_t)__TKM32_PORT(gpio)-(rt_base_t)GPIOA_BASE)/(0x0400UL), gpio_index}
#define TKM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
/* TKM32 GPIO driver */
struct pin_index
{
int index;
uint32_t rcc;
GPIO_TypeDef *gpio;
uint32_t pin;
uint8_t port_source;
uint8_t pin_source;
};
static const struct pin_index tkm32_pin_map[] =
{
TKM32_PIN_DEFAULT,
TKM32_PIN(0, AHB, A, 0),
TKM32_PIN(1, AHB, A, 1),
TKM32_PIN(2, AHB, A, 2),
TKM32_PIN(3, AHB, A, 3),
TKM32_PIN(4, AHB, A, 4),
TKM32_PIN(5, AHB, A, 5),
TKM32_PIN(6, AHB, A, 6),
TKM32_PIN(7, AHB, A, 7),
TKM32_PIN(8, AHB, A, 8),
TKM32_PIN(9, AHB, A, 9),
TKM32_PIN(10, AHB, A, 10),
TKM32_PIN(11, AHB, A, 11),
TKM32_PIN(12, AHB, A, 12),
TKM32_PIN(13, AHB, A, 13),
TKM32_PIN(14, AHB, A, 14),
TKM32_PIN(15, AHB, A, 15),
TKM32_PIN(16, AHB, B, 0),
TKM32_PIN(17, AHB, B, 1),
TKM32_PIN(18, AHB, B, 2),
TKM32_PIN(19, AHB, B, 3),
TKM32_PIN(20, AHB, B, 4),
TKM32_PIN(21, AHB, B, 5),
TKM32_PIN(22, AHB, B, 6),
TKM32_PIN(23, AHB, B, 7),
TKM32_PIN(24, AHB, B, 8),
TKM32_PIN(25, AHB, B, 9),
TKM32_PIN(26, AHB, B, 10),
TKM32_PIN(27, AHB, B, 11),
TKM32_PIN(28, AHB, B, 12),
TKM32_PIN(29, AHB, B, 13),
TKM32_PIN(30, AHB, B, 14),
TKM32_PIN(31, AHB, B, 15),
TKM32_PIN(32, AHB, C, 0),
TKM32_PIN(33, AHB, C, 1),
TKM32_PIN(34, AHB, C, 2),
TKM32_PIN(35, AHB, C, 3),
TKM32_PIN(36, AHB, C, 4),
TKM32_PIN(37, AHB, C, 5),
TKM32_PIN(38, AHB, C, 6),
TKM32_PIN(39, AHB, C, 7),
TKM32_PIN(40, AHB, C, 8),
TKM32_PIN(41, AHB, C, 9),
TKM32_PIN(42, AHB, C, 10),
TKM32_PIN(43, AHB, C, 11),
TKM32_PIN(44, AHB, C, 12),
TKM32_PIN(45, AHB, C, 13),
TKM32_PIN(46, AHB, C, 14),
TKM32_PIN(47, AHB, C, 15),
TKM32_PIN(48, AHB, D, 0),
TKM32_PIN(49, AHB, D, 1),
TKM32_PIN(50, AHB, D, 2),
TKM32_PIN(51, AHB, D, 3),
TKM32_PIN(52, AHB, D, 4),
TKM32_PIN(53, AHB, D, 5),
TKM32_PIN(54, AHB, D, 6),
TKM32_PIN(55, AHB, D, 7),
TKM32_PIN(56, AHB, D, 8),
TKM32_PIN(57, AHB, D, 9),
TKM32_PIN(58, AHB, D, 10),
TKM32_PIN(59, AHB, D, 11),
TKM32_PIN(60, AHB, D, 12),
TKM32_PIN(61, AHB, D, 13),
TKM32_PIN(62, AHB, D, 14),
TKM32_PIN(63, AHB, D, 15),
TKM32_PIN(64, AHB, E, 0),
TKM32_PIN(65, AHB, E, 1),
TKM32_PIN(66, AHB, E, 2),
TKM32_PIN(67, AHB, E, 3),
TKM32_PIN(68, AHB, E, 4),
TKM32_PIN(69, AHB, E, 5),
TKM32_PIN(70, AHB, E, 6),
TKM32_PIN(71, AHB, E, 7),
TKM32_PIN(72, AHB, E, 8),
TKM32_PIN(73, AHB, E, 9),
TKM32_PIN(74, AHB, E, 10),
TKM32_PIN(75, AHB, E, 11),
TKM32_PIN(76, AHB, E, 12),
TKM32_PIN(77, AHB, E, 13),
TKM32_PIN(78, AHB, E, 14),
TKM32_PIN(79, AHB, E, 15),
TKM32_PIN(80, AHB, E, 16),
TKM32_PIN(81, AHB, E, 17),
TKM32_PIN(82, AHB, E, 18),
TKM32_PIN(83, AHB, E, 19),
TKM32_PIN(84, AHB, E, 20),
TKM32_PIN(85, AHB, E, 21),
TKM32_PIN(86, AHB, E, 22),
TKM32_PIN(87, AHB, E, 23),
};
struct pin_irq_map
{
rt_uint16_t pinbit;
rt_uint32_t irqbit;
enum IRQn irqno;
};
const struct pin_irq_map tkm32_pin_irq_map[] =
{
{GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn },
{GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn },
{GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn },
{GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn },
{GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn },
{GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn },
{GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn },
{GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn },
{GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn },
{GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn },
{GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn},
{GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn},
{GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn},
{GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn},
{GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn},
{GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn},
};
struct rt_pin_irq_hdr tkm32_pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin+1 < ITEM_NUM(tkm32_pin_map))
{
index = &tkm32_pin_map[pin+1];
if (index->gpio == 0)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
void tkm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if (value == PIN_LOW)
{
GPIO_ResetBits(index->gpio, index->pin);
}
else
{
GPIO_SetBits(index->gpio, index->pin);
}
}
int tkm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
return PIN_LOW;
}
if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
{
value = PIN_LOW;
}
else
{
value = PIN_HIGH;
}
return value;
}
void tkm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStructure;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* GPIO Periph clock enable */
RCC_AHBPeriphClockCmd(index->rcc, ENABLE);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.GPIO_Pin = index->pin;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
}
else if (mode == PIN_MODE_OUTPUT_OD)
{
/* output setting: od. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
}
else
{
/* input setting:default. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
}
GPIO_Init( index->gpio, &GPIO_InitStructure);
GPIO_PinAFConfig(index->gpio, index->pin, GPIO_AF_GPIO);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for (i = 0; i < 32; i++)
{
if ((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if (mapindex < 0 || mapindex >= ITEM_NUM(tkm32_pin_irq_map))
{
return RT_NULL;
}
return &tkm32_pin_irq_map[mapindex];
};
rt_err_t tkm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (tkm32_pin_irq_hdr_tab[irqindex].pin == pin &&
tkm32_pin_irq_hdr_tab[irqindex].hdr == hdr &&
tkm32_pin_irq_hdr_tab[irqindex].mode == mode &&
tkm32_pin_irq_hdr_tab[irqindex].args == args
)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if (tkm32_pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
}
tkm32_pin_irq_hdr_tab[irqindex].pin = pin;
tkm32_pin_irq_hdr_tab[irqindex].hdr = hdr;
tkm32_pin_irq_hdr_tab[irqindex].mode = mode;
tkm32_pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t tkm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map))
{
return RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (tkm32_pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
tkm32_pin_irq_hdr_tab[irqindex].pin = -1;
tkm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
tkm32_pin_irq_hdr_tab[irqindex].mode = 0;
tkm32_pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t tkm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
index = get_pin(pin);
if (index == RT_NULL)
{
return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
if (irqindex < 0 || irqindex >= ITEM_NUM(tkm32_pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if (tkm32_pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return -RT_ENOSYS;
}
irqmap = &tkm32_pin_irq_map[irqindex];
/* GPIO Periph clock enable */
RCC_AHBPeriphClockCmd(index->rcc, ENABLE);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.GPIO_Pin = index->pin;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(index->gpio, &GPIO_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
// GPIO_EXTILineConfig(index->port_source, index->pin_source);
// EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
// EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
switch (tkm32_pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
Ex_NVIC_Config(index->port_source, index->pin_source, 2);
// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case PIN_IRQ_MODE_FALLING:
Ex_NVIC_Config(index->port_source, index->pin_source, 1);
// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
Ex_NVIC_Config(index->port_source, index->pin_source, 3);
// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
// EXTI_InitStructure.EXTI_LineCmd = ENABLE;
// EXTI_Init(&EXTI_InitStructure);
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if (irqmap == RT_NULL)
{
return -RT_ENOSYS;
}
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
EXTI_Init(&EXTI_InitStructure);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _tkm32_pin_ops =
{
tkm32_pin_mode,
tkm32_pin_write,
tkm32_pin_read,
tkm32_pin_attach_irq,
tkm32_pin_detach_irq,
tkm32_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)
{
int result;
result = rt_device_pin_register("pin", &_tkm32_pin_ops, RT_NULL);
return result;
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
{
EXTI_ClearITPendingBit(tkm32_pin_irq_map[irqno].irqbit);
if (tkm32_pin_irq_hdr_tab[irqno].hdr)
{
tkm32_pin_irq_hdr_tab[irqno].hdr(tkm32_pin_irq_hdr_tab[irqno].args);
}
}
void EXTI0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(0);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(1);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(2);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(3);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(4);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if (EXTI_GetITStatus(EXTI_Line5) != RESET)
{
pin_irq_hdr(5);
}
if (EXTI_GetITStatus(EXTI_Line6) != RESET)
{
pin_irq_hdr(6);
}
if (EXTI_GetITStatus(EXTI_Line7) != RESET)
{
pin_irq_hdr(7);
}
if (EXTI_GetITStatus(EXTI_Line8) != RESET)
{
pin_irq_hdr(8);
}
if (EXTI_GetITStatus(EXTI_Line9) != RESET)
{
pin_irq_hdr(9);
}
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if (EXTI_GetITStatus(EXTI_Line10) != RESET)
{
pin_irq_hdr(10);
}
if (EXTI_GetITStatus(EXTI_Line11) != RESET)
{
pin_irq_hdr(11);
}
if (EXTI_GetITStatus(EXTI_Line12) != RESET)
{
pin_irq_hdr(12);
}
if (EXTI_GetITStatus(EXTI_Line13) != RESET)
{
pin_irq_hdr(13);
}
if (EXTI_GetITStatus(EXTI_Line14) != RESET)
{
pin_irq_hdr(14);
}
if (EXTI_GetITStatus(EXTI_Line15) != RESET)
{
pin_irq_hdr(15);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_PIN */

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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#ifndef DRV_GPIO_H__
#define DRV_GPIO_H__
#define __TKM32_PORT(port) GPIO##port##_BASE
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__TKM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
int rt_hw_pin_init(void);
#endif

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bsp/tkm32F499/drivers/drv_log.h Normal file
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@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>

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bsp/tkm32F499/drivers/drv_uart.c Normal file
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include "drv_uart.h"
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
#define LOG_TAG "drv.uart"
#include <drv_log.h>
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
!defined(BSP_USING_UART4)
#error "Please define at least one BSP_USING_UARTx"
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
#endif
/* UART1 */
#define UART1_GPIO_TX GPIO_Pin_9
#define UART1_GPIO_RX GPIO_Pin_10
#define UART1_GPIO_AF GPIO_AF_UART_1
#define UART1_GPIO GPIOA
/* UART2 */
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_GPIO_AF GPIO_AF_UART_2345
#define UART2_GPIO GPIOA
static rt_err_t tkm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct tkm32_uart *uart;
UART_InitTypeDef UART_InitStructure;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct tkm32_uart *)serial->parent.user_data;
UART_InitStructure.UART_BaudRate = cfg->baud_rate;
if (cfg->data_bits == DATA_BITS_8)
UART_InitStructure.UART_WordLength = UART_WordLength_8b;
if (cfg->stop_bits == STOP_BITS_1)
UART_InitStructure.UART_StopBits = UART_StopBits_1;
else if (cfg->stop_bits == STOP_BITS_2)
UART_InitStructure.UART_StopBits = UART_StopBits_2;
UART_InitStructure.UART_Parity = UART_Parity_No;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
UART_Init(uart->uart, &UART_InitStructure);
/* Enable UART */
UART_Cmd(uart->uart, ENABLE);
return RT_EOK;
}
static rt_err_t tkm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct tkm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct tkm32_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
NVIC_DisableIRQ(uart->irq);
UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->irq);
/* enable interrupt */
UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
break;
}
return RT_EOK;
}
static int tkm32_uart_putc(struct rt_serial_device *serial, char c)
{
struct tkm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct tkm32_uart *)serial->parent.user_data;
while ((uart->uart->CSR & UART_IT_TXIEN) == 0);
uart->uart->TDR = (c & (uint16_t)0x00FF);
return 1;
}
static int tkm32_uart_getc(struct rt_serial_device *serial)
{
int ch;
struct tkm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct tkm32_uart *)serial->parent.user_data;
ch = -1;
if (uart->uart->CSR & UART_FLAG_RXAVL)
{
ch = uart->uart->RDR & 0xff;
}
return ch;
}
static const struct rt_uart_ops tkm32_uart_ops =
{
tkm32_uart_configure,
tkm32_uart_control,
tkm32_uart_putc,
tkm32_uart_getc,
};
#if defined(BSP_USING_UART1)
/* UART1 device driver structure */
static struct tkm32_uart uart1;
struct rt_serial_device serial1;
void UART1_IRQHandler(void)
{
struct tkm32_uart *uart;
uart = &uart1;
/* enter interrupt */
rt_interrupt_enter();
if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET)
{
UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN);
rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
}
if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET)
{
/* clear interrupt */
UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
/* UART2 device driver structure */
static struct tkm32_uart uart2;
struct rt_serial_device serial2;
void UART2_IRQHandler(void)
{
struct tkm32_uart *uart;
uart = &uart2;
/* enter interrupt */
rt_interrupt_enter();
if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET)
{
UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN);
rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
}
if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET)
{
/* clear interrupt */
UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* BSP_USING_UART2 */
#ifdef BSP_USING_UART1
static void UART1PINconfigStepA(void)
{
/* Enable UART clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE);
}
static void UART1PINconfigStepB(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Configure USART Rx/tx PIN */
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
GPIO_PinAFConfig(UART1_GPIO, UART1_GPIO_TX | UART1_GPIO_RX, UART1_GPIO_AF);
UART_ClearITPendingBit(UART1, 0xFF);
}
#endif
#ifdef BSP_USING_UART2
static void UART2PINconfigStepA(void)
{
/* Enable UART clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
}
static void UART2PINconfigStepB(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Configure USART Rx/tx PIN */
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
GPIO_PinAFConfig(UART2_GPIO, UART2_GPIO_TX | UART2_GPIO_RX, UART2_GPIO_AF);
UART_ClearITPendingBit(UART2, 0xFF);
}
#endif
int rt_hw_uart_init(void)
{
struct tkm32_uart *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART1
UART1PINconfigStepA();
uart = &uart1;
uart->uart = UART1;
uart->irq = UART1_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial1.ops = &tkm32_uart_ops;
serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX,
uart);
UART1PINconfigStepB();
#endif /* BSP_USING_UART1 */
#ifdef BSP_USING_UART2
UART2PINconfigStepA();
uart = &uart2;
uart->uart = UART2;
uart->irq = UART2_IRQn;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &tkm32_uart_ops;
serial2.config = config;
/* register UART2 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX,
uart);
UART2PINconfigStepB();
#endif /* BSP_USING_UART2 */
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
#endif /* RT_USING_SERIAL */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-02 spaceman first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
int rt_hw_uart_init(void);
/* uart driver */
struct tkm32_uart
{
UART_TypeDef *uart;
IRQn_Type irq;
};
#endif

34
bsp/tkm32F499/drivers/linker_scripts/link.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_IROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_IROM_end__ = 0x0001FFFF;
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_IRAM_end__ = 0x20004FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800;
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM_region = mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
do not initialize { section .noinit };
initialize by copy { readwrite };
if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
{
// Required in a multi-threaded application
initialize by copy with packing = none { section __DLIB_PERTHREAD };
}
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };

137
bsp/tkm32F499/drivers/linker_scripts/link.lds Normal file
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/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 20k /* 8K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

16
bsp/tkm32F499/drivers/linker_scripts/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x70020000 0x00200000 { ; load region size_region
ER_IROM1 0x70020000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x70220000 0x005DFFFF { ; RW data
.ANY (+RW +ZI)
}
}

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bsp/tkm32F499/project.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.7.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin -o .//@L.bin ./build/@L.axf</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>0</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"flash_download" (.//@L.bin TK499_V2)</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x70020000</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x70220000</StartAddress>
<Size>0x5dffff</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine></Undefine>
<IncludePath>applications;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m4;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\include;drivers;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\finsh;.;rt-thread\include;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;rt-thread\components\libc\compilers\common\nogcc;Libraries\CMSIS_and_startup\CMSIS;Libraries\CMSIS_and_startup;Libraries\Hal_lib\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Applications</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>applications\main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\libcpu\arm\common\backtrace.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>div0.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\libcpu\arm\cortex-m4\cpuport.c</FilePath>
</File>
<File>
<FileName>context_rvds.S</FileName>
<FileType>2</FileType>
<FilePath>rt-thread\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\serial\serial.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\waitqueue.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\workqueue.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\ringbuffer.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\pipe.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>completion.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\completion.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\drivers\src\dataqueue.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_uart.c</FilePath>
</File>
<File>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\board.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Filesystem</GroupName>
<Files>
<File>
<FileName>dfs_posix.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs_posix.c</FilePath>
</File>
<File>
<FileName>dfs_poll.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs_poll.c</FilePath>
</File>
<File>
<FileName>dfs_file.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs_file.c</FilePath>
</File>
<File>
<FileName>dfs.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs.c</FilePath>
</File>
<File>
<FileName>dfs_fs.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs_fs.c</FilePath>
</File>
<File>
<FileName>dfs_select.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\src\dfs_select.c</FilePath>
</File>
<File>
<FileName>devfs.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\dfs\filesystems\devfs\devfs.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>msh_file.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\finsh\msh_file.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>ipc.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\ipc.c</FilePath>
</File>
<File>
<FileName>irq.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\irq.c</FilePath>
</File>
<File>
<FileName>mem.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\mem.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\scheduler.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\device.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\components.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\mempool.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\idle.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\timer.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\object.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\clock.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\kservice.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\src\thread.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<Files>
<File>
<FileName>syscalls.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\armlibc\syscalls.c</FilePath>
</File>
<File>
<FileName>mem_std.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\armlibc\mem_std.c</FilePath>
</File>
<File>
<FileName>libc.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\armlibc\libc.c</FilePath>
</File>
<File>
<FileName>stdio.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\armlibc\stdio.c</FilePath>
</File>
<File>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\common\time.c</FilePath>
</File>
<File>
<FileName>stdlib.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\common\stdlib.c</FilePath>
</File>
<File>
<FileName>unistd.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\common\unistd.c</FilePath>
</File>
<File>
<FileName>delay.c</FileName>
<FileType>1</FileType>
<FilePath>rt-thread\components\libc\compilers\common\delay.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>TKM32_Lib</GroupName>
<Files>
<File>
<FileName>HAL_dma_bak.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_dma_bak.c</FilePath>
</File>
<File>
<FileName>HAL_exti.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_exti.c</FilePath>
</File>
<File>
<FileName>startup_Tk499.s</FileName>
<FileType>2</FileType>
<FilePath>Libraries\CMSIS_and_startup\startup_Tk499.s</FilePath>
</File>
<File>
<FileName>HAL_dma.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_dma.c</FilePath>
</File>
<File>
<FileName>HAL_can.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_can.c</FilePath>
</File>
<File>
<FileName>HAL_uart.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_uart.c</FilePath>
</File>
<File>
<FileName>HAL_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_rcc.c</FilePath>
</File>
<File>
<FileName>HAL_tim.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_tim.c</FilePath>
</File>
<File>
<FileName>HAL_misc.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_misc.c</FilePath>
</File>
<File>
<FileName>HAL_spi.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_spi.c</FilePath>
</File>
<File>
<FileName>HAL_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_wwdg.c</FilePath>
</File>
<File>
<FileName>HAL_pwr.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_pwr.c</FilePath>
</File>
<File>
<FileName>HAL_iwdg.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_iwdg.c</FilePath>
</File>
<File>
<FileName>HAL_syscfg.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_syscfg.c</FilePath>
</File>
<File>
<FileName>sys.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\CMSIS_and_startup\sys.c</FilePath>
</File>
<File>
<FileName>HAL_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_gpio.c</FilePath>
</File>
<File>
<FileName>HAL_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>Libraries\Hal_lib\src\HAL_i2c.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

189
bsp/tkm32F499/rtconfig.h Normal file
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@ -0,0 +1,189 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40004
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_POSIX
#define RT_LIBC_USING_TIME
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* Hardware Drivers Config */
#define SOC_SERIES_TKM32F4
#define SOC_TKM32F499
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_USING_UART2
/* Board extended module Drivers */
#endif

167
bsp/tkm32F499/rtconfig.py Normal file
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@ -0,0 +1,167 @@
import os
import sys
# toolchains options
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# device options
ARCH = 'arm'
CPU = 'cortex-m4'
CROSS_TOOL = 'keil'
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'D:/Keil/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
if PLATFORM == 'gcc':
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wall'
CFLAGS = DEVICE + ' -std=c99'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
# CC = 'armcc'
# CXX = 'armcc'
# AS = 'armasm'
# AR = 'armar'
# LINK = 'armlink'
# TARGET_EXT = 'axf'
# DEVICE = ' --cpu Cortex-M4.fp.sp'
# CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
# AFLAGS = DEVICE + ' --apcs=interwork '
# LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
# CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
# LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
# CFLAGS += ' -D__MICROLIB '
# AFLAGS += ' --pd "__MICROLIB SETA 1" '
# LFLAGS += ' --library_type=microlib '
# EXEC_PATH += '/ARM/ARMCC/bin/'
# if BUILD == 'debug':
# CFLAGS += ' -g -O0'
# AFLAGS += ' -g'
# else:
# CFLAGS += ' -O2'
# POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4.fp.sp --li'
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
CFLAGS += ' -I' + EXEC_PATH + '../Arm/Packs/ARM/CMSIS/5.7.0/Device/ARM/ARMCM4/Include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
# CFLAGS += ' -D__MICROLIB '
CFLAGS += ' -DARMCM4_FP '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
# LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
# CFLAGS += ' -std=c99'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm' # + ' -D' + PART_TYPE
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M3'
CFLAGS += ' -e'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu ' + CPU
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
#LFLAGS += ' --silent'
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''

406
bsp/tkm32F499/template.uvprojx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.7.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>1</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\keil\List\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin -o .//@L.bin ./build/@L.axf</UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>0</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"flash_download" (.//@L.bin TK499_V2)</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x70020000</StartAddress>
<Size>0x200000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x70220000</StartAddress>
<Size>0x5dffff</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>0</vShortEn>
<vShortWch>0</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>4</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>