[bsp] format drivers code
This commit is contained in:
Meco Man
Rbb666
parent
6a9c42a19d
commit
3782127116
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@ -1,5 +1,5 @@
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/*
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* COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
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* COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
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* All rights reserved.
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* Change Logs:
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* Date Author Notes
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@ -1,5 +1,5 @@
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/*
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* COPYRIGHT (C) 2012-2022, Shanghai Real-Thread Technology Co., Ltd
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* COPYRIGHT (C) 2012-2024, Shanghai Real-Thread Technology Co., Ltd
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* All rights reserved.
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* Change Logs:
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* Date Author Notes
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@ -50,11 +50,11 @@ static void avr32_set_sda(void *data, rt_int32_t state)
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struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
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if (state)
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{
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gpio_set_gpio_open_drain_pin(cfg->sda);
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gpio_set_gpio_open_drain_pin(cfg->sda);
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}
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else
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{
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gpio_clr_gpio_open_drain_pin(cfg->sda);
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gpio_clr_gpio_open_drain_pin(cfg->sda);
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}
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}
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@ -69,11 +69,11 @@ static void avr32_set_scl(void *data, rt_int32_t state)
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struct avr32_soft_i2c_config* cfg = (struct avr32_soft_i2c_config*)data;
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if (state)
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{
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gpio_set_gpio_open_drain_pin(cfg->scl);
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gpio_set_gpio_open_drain_pin(cfg->scl);
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}
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else
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{
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gpio_clr_gpio_open_drain_pin(cfg->scl);
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gpio_clr_gpio_open_drain_pin(cfg->scl);
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}
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}
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@ -126,10 +126,10 @@ static rt_err_t avr32_i2c_bus_unlock(const struct avr32_soft_i2c_config *cfg)
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{
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while (i++ < 9)
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{
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gpio_set_gpio_open_drain_pin(cfg->scl);
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rt_hw_us_delay(100);
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gpio_clr_gpio_open_drain_pin(cfg->scl);
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rt_hw_us_delay(100);
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gpio_set_gpio_open_drain_pin(cfg->scl);
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rt_hw_us_delay(100);
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gpio_clr_gpio_open_drain_pin(cfg->scl);
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rt_hw_us_delay(100);
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}
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}
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if (PIN_LOW == gpio_get_gpio_open_drain_pin_output_value(cfg->sda))
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@ -598,7 +598,7 @@ int rthw_sdctrl_init(void)
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#endif
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normalIrqFlgs |= NORMAL_IRQ_CC;
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/* register handler、irq enable bit and wait callback */
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/* register handler irq enable bit and wait callback */
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FSdCtrl_SetHandler(ft_sdctrl_p, FTSDCTRL_CMDIRQID, rthw_sdctrl_nomarl_callback, ft_sdctrl_p);
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FSdCtrl_NormalIrqSet(ft_sdctrl_p, normalIrqFlgs);
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FSdCtrl_CmdWaitRegister(ft_sdctrl_p, rthw_sdctrl_cmd_wait);
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@ -4,8 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-06-05 zengjianwei first version
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* Date Author Notes
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* 2023-06-05 zengjianwei first version
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*/
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#include <board.h>
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@ -19,7 +19,7 @@
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#define LOG_TAG "drv.sdio"
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#include "drv_log.h"
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#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步
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#define SDIO_DMA_USE_IPC 0//1:使用ipc做同步
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/* card status of R1 definitions */
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#define SD_R1_OUT_OF_RANGE BIT(31) /* command's argument was out of the allowed range */
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@ -15,100 +15,100 @@
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#include <rthw.h>
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/* UART registers */
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#define UART_DAT(base) HWREG8(base + 0x00)
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#define UART_IER(base) HWREG8(base + 0x01)
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#define UART_IIR(base) HWREG8(base + 0x02)
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#define UART_FCR(base) HWREG8(base + 0x02)
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#define UART_LCR(base) HWREG8(base + 0x03)
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#define UART_MCR(base) HWREG8(base + 0x04)
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#define UART_LSR(base) HWREG8(base + 0x05)
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#define UART_MSR(base) HWREG8(base + 0x06)
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#define UART_DAT(base) HWREG8(base + 0x00)
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#define UART_IER(base) HWREG8(base + 0x01)
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#define UART_IIR(base) HWREG8(base + 0x02)
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#define UART_FCR(base) HWREG8(base + 0x02)
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#define UART_LCR(base) HWREG8(base + 0x03)
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#define UART_MCR(base) HWREG8(base + 0x04)
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#define UART_LSR(base) HWREG8(base + 0x05)
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#define UART_MSR(base) HWREG8(base + 0x06)
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#define UART_LSB(base) HWREG8(base + 0x00)
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#define UART_MSB(base) HWREG8(base + 0x01)
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#define UART_LSB(base) HWREG8(base + 0x00)
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#define UART_MSB(base) HWREG8(base + 0x01)
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/* interrupt enable register */
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#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
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#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
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#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
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#define IER_IME 0x8 /* Modem状态中断使能 */
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#define IER_IRxE 0x1 /* 接收有效数据中断使能 */
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#define IER_ITxE 0x2 /* 传输保存寄存器为空中断使能 */
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#define IER_ILE 0x4 /* 接收器线路状态中断使能 */
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#define IER_IME 0x8 /* Modem状态中断使能 */
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/* interrupt identification register */
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#define IIR_IMASK 0xf /* mask */
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#define IIR_RXTOUT 0xc /* receive timeout */
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#define IIR_RLS 0x6 /* receive line status */
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#define IIR_RXRDY 0x4 /* receive ready */
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#define IIR_TXRDY 0x2 /* transmit ready */
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#define IIR_NOPEND 0x1 /* nothing */
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#define IIR_MLSC 0x0 /* modem status */
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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#define IIR_IMASK 0xf /* mask */
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#define IIR_RXTOUT 0xc /* receive timeout */
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#define IIR_RLS 0x6 /* receive line status */
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#define IIR_RXRDY 0x4 /* receive ready */
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#define IIR_TXRDY 0x2 /* transmit ready */
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#define IIR_NOPEND 0x1 /* nothing */
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#define IIR_MLSC 0x0 /* modem status */
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01 /* enable fifo */
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#define FIFO_RCV_RST 0x02 /* reset receive fifo */
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#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
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#define FIFO_DMA_MODE 0x08 /* enable dma mode */
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#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
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#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
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#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
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#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
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#define FIFO_ENABLE 0x01 /* enable fifo */
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#define FIFO_RCV_RST 0x02 /* reset receive fifo */
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#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
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#define FIFO_DMA_MODE 0x08 /* enable dma mode */
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#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
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#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
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#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
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#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
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// 线路控制寄存器
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/* character format control register */
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#define CFCR_DLAB 0x80 /* divisor latch */
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#define CFCR_SBREAK 0x40 /* send break */
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#define CFCR_PZERO 0x30 /* zero parity */
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#define CFCR_PONE 0x20 /* one parity */
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#define CFCR_PEVEN 0x10 /* even parity */
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#define CFCR_PODD 0x00 /* odd parity */
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#define CFCR_PENAB 0x08 /* parity enable */
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#define CFCR_STOPB 0x04 /* 2 stop bits */
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#define CFCR_8BITS 0x03 /* 8 data bits */
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#define CFCR_7BITS 0x02 /* 7 data bits */
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#define CFCR_6BITS 0x01 /* 6 data bits */
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#define CFCR_5BITS 0x00 /* 5 data bits */
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#define CFCR_DLAB 0x80 /* divisor latch */
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#define CFCR_SBREAK 0x40 /* send break */
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#define CFCR_PZERO 0x30 /* zero parity */
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#define CFCR_PONE 0x20 /* one parity */
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#define CFCR_PEVEN 0x10 /* even parity */
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#define CFCR_PODD 0x00 /* odd parity */
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#define CFCR_PENAB 0x08 /* parity enable */
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#define CFCR_STOPB 0x04 /* 2 stop bits */
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#define CFCR_8BITS 0x03 /* 8 data bits */
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#define CFCR_7BITS 0x02 /* 7 data bits */
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#define CFCR_6BITS 0x01 /* 6 data bits */
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#define CFCR_5BITS 0x00 /* 5 data bits */
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/* modem control register */
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#define MCR_LOOPBACK 0x10 /* loopback */
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#define MCR_IENABLE 0x08 /* output 2 = int enable */
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#define MCR_DRS 0x04 /* output 1 = xxx */
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#define MCR_RTS 0x02 /* enable RTS */
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#define MCR_DTR 0x01 /* enable DTR */
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#define MCR_LOOPBACK 0x10 /* loopback */
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#define MCR_IENABLE 0x08 /* output 2 = int enable */
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#define MCR_DRS 0x04 /* output 1 = xxx */
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#define MCR_RTS 0x02 /* enable RTS */
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#define MCR_DTR 0x01 /* enable DTR */
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/* line status register */
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#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
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#define LSR_TSRE 0x40 /* transmitter empty */
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#define LSR_TXRDY 0x20 /* transmitter ready */
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#define LSR_BI 0x10 /* break detected */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_RXRDY 0x01 /* receiver ready */
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#define LSR_RCV_MASK 0x1f
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#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
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#define LSR_TSRE 0x40 /* transmitter empty */
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#define LSR_TXRDY 0x20 /* transmitter ready */
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#define LSR_BI 0x10 /* break detected */
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#define LSR_FE 0x08 /* framing error */
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#define LSR_PE 0x04 /* parity error */
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#define LSR_OE 0x02 /* overrun error */
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#define LSR_RXRDY 0x01 /* receiver ready */
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#define LSR_RCV_MASK 0x1f
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/* UART interrupt enable register value */
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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#define UARTIER_IME (1 << 3)
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#define UARTIER_ILE (1 << 2)
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#define UARTIER_ITXE (1 << 1)
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#define UARTIER_IRXE (1 << 0)
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/* UART line control register value */
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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#define UARTLCR_DLAB (1 << 7)
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#define UARTLCR_BCB (1 << 6)
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#define UARTLCR_SPB (1 << 5)
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#define UARTLCR_EPS (1 << 4)
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#define UARTLCR_PE (1 << 3)
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#define UARTLCR_SB (1 << 2)
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/* UART line status register value */
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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#define UARTLSR_ERROR (1 << 7)
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#define UARTLSR_TE (1 << 6)
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#define UARTLSR_TFE (1 << 5)
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#define UARTLSR_BI (1 << 4)
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#define UARTLSR_FE (1 << 3)
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#define UARTLSR_PE (1 << 2)
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#define UARTLSR_OE (1 << 1)
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#define UARTLSR_DR (1 << 0)
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#endif
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@ -36,7 +36,7 @@ struct mm32_uart
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};
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static rt_err_t mm32_uart_configure(struct rt_serial_device *serial,
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struct serial_configure *cfg)
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struct serial_configure *cfg)
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{
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struct mm32_uart *uart;
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UART_InitTypeDef UART_InitStructure;
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@ -60,7 +60,7 @@ static rt_err_t mm32_uart_configure(struct rt_serial_device *serial,
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}
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static rt_err_t mm32_uart_control(struct rt_serial_device *serial,
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int cmd, void *arg)
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int cmd, void *arg)
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{
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struct mm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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@ -70,12 +70,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial,
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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NVIC_DisableIRQ(uart->irq);
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UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
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UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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NVIC_EnableIRQ(uart->irq);
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/* enable interrupt */
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/* enable interrupt */
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UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
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break;
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}
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@ -215,8 +215,8 @@ int rt_hw_uart_init(void)
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#ifdef BSP_USING_UART1
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UART1PINconfigStepA();
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uart = &uart1;
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uart->uart = UART1;
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uart->irq = UART1_IRQn;
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uart->uart = UART1;
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uart->irq = UART1_IRQn;
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config.baud_rate = BAUD_RATE_115200;
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serial1.ops = &mm32_uart_ops;
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serial1.config = config;
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@ -229,8 +229,8 @@ int rt_hw_uart_init(void)
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#ifdef BSP_USING_UART2
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UART2PINconfigStepA();
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uart = &uart2;
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uart->uart = UART2;
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uart->irq = UART2_IRQn;
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uart->uart = UART2;
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uart->irq = UART2_IRQn;
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config.baud_rate = BAUD_RATE_115200;
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serial2.ops = &mm32_uart_ops;
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serial2.config = config;
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@ -67,12 +67,12 @@ static rt_err_t mm32_uart_control(struct rt_serial_device *serial, int cmd, void
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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NVIC_DisableIRQ(uart->irq);
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UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
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UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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NVIC_EnableIRQ(uart->irq);
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/* enable interrupt */
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/* enable interrupt */
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UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
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break;
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}
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@ -167,7 +167,7 @@ static void UART1PINconfigStepA(void)
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/* Enable UART clock */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
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}
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@ -193,7 +193,7 @@ static void UART2PINconfigStepA(void)
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/* Enable UART clock */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
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GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
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}
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@ -219,8 +219,8 @@ int rt_hw_uart_init(void)
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#ifdef BSP_USING_UART1
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UART1PINconfigStepA();
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uart = &uart1;
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uart->uart = UART1;
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uart->irq = UART1_IRQn;
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uart->uart = UART1;
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uart->irq = UART1_IRQn;
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config.baud_rate = BAUD_RATE_115200;
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serial1.ops = &mm32_uart_ops;
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serial1.config = config;
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@ -234,8 +234,8 @@ int rt_hw_uart_init(void)
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#ifdef BSP_USING_UART2
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UART2PINconfigStepA();
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uart = &uart2;
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uart->uart = UART2;
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uart->irq = UART2_IRQn;
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uart->uart = UART2;
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uart->irq = UART2_IRQn;
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config.baud_rate = BAUD_RATE_115200;
|
||||
serial2.ops = &mm32_uart_ops;
|
||||
serial2.config = config;
|
||||
|
|
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|||
|
|
@ -293,9 +293,9 @@ static rt_size_t gt911_read_point(struct rt_touch_device *touch, void *buf, rt_s
|
|||
off_set = read_index * 8;
|
||||
read_id = read_buf[off_set] & 0x0f;
|
||||
pre_id[read_index] = read_id;
|
||||
input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */
|
||||
input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */
|
||||
input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */
|
||||
input_x = read_buf[off_set + 1] | (read_buf[off_set + 2] << 8); /* x */
|
||||
input_y = read_buf[off_set + 3] | (read_buf[off_set + 4] << 8); /* y */
|
||||
input_w = read_buf[off_set + 5] | (read_buf[off_set + 6] << 8); /* size */
|
||||
|
||||
gt911_touch_down(buf, read_id, input_x, input_y, input_w);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -194,7 +194,7 @@ void rt_hw_uart_init(void)
|
|||
config.parity = PARITY_NONE;
|
||||
config.stop_bits = STOP_BITS_1;
|
||||
config.invert = NRZ_NORMAL;
|
||||
config.bufsz = RT_SERIAL_RB_BUFSZ;
|
||||
config.bufsz = RT_SERIAL_RB_BUFSZ;
|
||||
|
||||
_sci2_serial.ops = &_sci_ops;
|
||||
_sci2_serial.config = config;
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ void uart1_rx_handler(mss_uart_instance_t *this_uart)
|
|||
}
|
||||
|
||||
static rt_err_t sf2_uart_configure(struct rt_serial_device *serial,
|
||||
struct serial_configure *cfg)
|
||||
struct serial_configure *cfg)
|
||||
{
|
||||
uint32_t baudRate;
|
||||
uint8_t datBits, parity, stopBits;
|
||||
|
|
@ -96,11 +96,11 @@ static rt_err_t sf2_uart_configure(struct rt_serial_device *serial,
|
|||
else
|
||||
MSS_UART_set_rx_handler(uart->uart, uart1_rx_handler, MSS_UART_FIFO_SINGLE_BYTE);
|
||||
|
||||
return RT_EOK;
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t sf2_uart_control(struct rt_serial_device *serial,
|
||||
int cmd, void *arg)
|
||||
int cmd, void *arg)
|
||||
{
|
||||
struct sf2_uart* uart;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue