From 364ef38e54136b1e7c9897bb13de7f88e54db830 Mon Sep 17 00:00:00 2001 From: Meco Man <920369182@qq.com> Date: Sun, 21 Mar 2021 23:32:39 +0800 Subject: [PATCH] =?UTF-8?q?[mb9bf506r]=E6=89=8B=E5=8A=A8-=E8=87=AA?= =?UTF-8?q?=E5=8A=A8=E6=A0=BC=E5=BC=8F=E6=95=B4=E7=90=86?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/mb9bf506r/applications/application.c | 42 +- bsp/mb9bf506r/applications/startup.c | 68 +- bsp/mb9bf506r/drivers/board.c | 38 +- bsp/mb9bf506r/drivers/board.h | 8 +- bsp/mb9bf506r/drivers/fm3_uart.c | 1341 +++++++++++----------- bsp/mb9bf506r/drivers/fm3_uart.h | 28 +- bsp/mb9bf506r/drivers/led.c | 40 +- bsp/mb9bf506r/drivers/led.h | 28 +- bsp/mb9bf506r/drivers/nand.c | 582 +++++----- bsp/mb9bf506r/drivers/nand.h | 12 +- 10 files changed, 1073 insertions(+), 1114 deletions(-) diff --git a/bsp/mb9bf506r/applications/application.c b/bsp/mb9bf506r/applications/application.c index ce1daa2327..fdc42a9100 100644 --- a/bsp/mb9bf506r/applications/application.c +++ b/bsp/mb9bf506r/applications/application.c @@ -1,11 +1,7 @@ /* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,35 +29,35 @@ void rt_init_thread_entry(void *parameter) { - /* LED Initialization */ - rt_hw_led_init(); + /* LED Initialization */ + rt_hw_led_init(); #ifdef RT_USING_COMPONENTS_INIT - /* initialization RT-Thread Components */ - rt_components_init(); + /* initialization RT-Thread Components */ + rt_components_init(); #endif - /* Filesystem Initialization */ + /* Filesystem Initialization */ #ifdef RT_USING_DFS - /* mount nand fat partition 1 as root directory */ - if (dfs_mount("nand", "/", "elm", 0, 0) == 0) - rt_kprintf("File System initialized!\n"); - else - rt_kprintf("File System init failed!\n"); + /* mount nand fat partition 1 as root directory */ + if (dfs_mount("nand", "/", "elm", 0, 0) == 0) + rt_kprintf("File System initialized!\n"); + else + rt_kprintf("File System init failed!\n"); #endif } int rt_application_init(void) { - rt_thread_t tid; + rt_thread_t tid; - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, RT_THREAD_PRIORITY_MAX/3, 20); - if (tid != RT_NULL) - rt_thread_startup(tid); + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, RT_THREAD_PRIORITY_MAX/3, 20); + if (tid != RT_NULL) + rt_thread_startup(tid); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/applications/startup.c b/bsp/mb9bf506r/applications/startup.c index 9076d572d6..ccb31d40b4 100644 --- a/bsp/mb9bf506r/applications/startup.c +++ b/bsp/mb9bf506r/applications/startup.c @@ -1,11 +1,7 @@ /* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -38,60 +34,60 @@ extern int __bss_end; */ void rtthread_startup(void) { - /* initialize board */ - rt_hw_board_init(); + /* initialize board */ + rt_hw_board_init(); - /* show version */ - rt_show_version(); + /* show version */ + rt_show_version(); #ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif #endif - /* init scheduler system */ - rt_system_scheduler_init(); + /* init scheduler system */ + rt_system_scheduler_init(); #ifdef RT_USING_DEVICE #if defined(RT_USING_DFS) && defined(RT_USING_DFS_UFFS) - rt_hw_nand_init(); + rt_hw_nand_init(); #endif #endif - /* initialize application */ - rt_application_init(); + /* initialize application */ + rt_application_init(); /* initialize timer */ rt_system_timer_init(); - /* initialize timer thread */ - rt_system_timer_thread_init(); + /* initialize timer thread */ + rt_system_timer_thread_init(); - /* initialize idle thread */ - rt_thread_idle_init(); + /* initialize idle thread */ + rt_thread_idle_init(); - /* start scheduler */ - rt_system_scheduler_start(); + /* start scheduler */ + rt_system_scheduler_start(); - /* never reach here */ - return ; + /* never reach here */ + return ; } int main(void) { - /* disable interrupt first */ - rt_hw_interrupt_disable(); + /* disable interrupt first */ + rt_hw_interrupt_disable(); - /* startup RT-Thread RTOS */ - rtthread_startup(); + /* startup RT-Thread RTOS */ + rtthread_startup(); - return 0; + return 0; } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.c b/bsp/mb9bf506r/drivers/board.c index 89d42c6329..d687bea929 100644 --- a/bsp/mb9bf506r/drivers/board.c +++ b/bsp/mb9bf506r/drivers/board.c @@ -1,11 +1,7 @@ /* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2012 RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -32,13 +28,13 @@ */ void SysTick_Handler(void) { - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - rt_tick_increase(); + rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } /** @@ -46,16 +42,16 @@ void SysTick_Handler(void) */ void rt_hw_board_init(void) { - /* init systick */ - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); - - /* initialize nand flash device */ - rt_hw_nand_init(); + /* init systick */ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); + + /* initialize nand flash device */ + rt_hw_nand_init(); } /*@}*/ diff --git a/bsp/mb9bf506r/drivers/board.h b/bsp/mb9bf506r/drivers/board.h index 960dac022b..d2f252990c 100644 --- a/bsp/mb9bf506r/drivers/board.h +++ b/bsp/mb9bf506r/drivers/board.h @@ -1,11 +1,7 @@ /* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/bsp/mb9bf506r/drivers/fm3_uart.c b/bsp/mb9bf506r/drivers/fm3_uart.c index 2c82afd288..ece042cca4 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.c +++ b/bsp/mb9bf506r/drivers/fm3_uart.c @@ -1,12 +1,7 @@ /* - * File : fm3_uart.c - * mb9bf506r uart driver - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,19 +17,19 @@ /* UART0 device driver structure */ struct uart03_device uart0 = { - FM3_MFS0_UART, - MFS0RX_IRQn, - MFS0TX_IRQn, + FM3_MFS0_UART, + MFS0RX_IRQn, + MFS0TX_IRQn, }; struct rt_serial_device serial0; void MFS0RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -42,19 +37,19 @@ void MFS0RX_IRQHandler(void) /* UART1 device driver structure */ struct uart03_device uart1 = { - FM3_MFS1_UART, - MFS1RX_IRQn, - MFS1TX_IRQn, + FM3_MFS1_UART, + MFS1RX_IRQn, + MFS1TX_IRQn, }; struct rt_serial_device serial1; void MFS1RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -62,19 +57,19 @@ void MFS1RX_IRQHandler(void) /* UART2 device driver structure */ struct uart03_device uart2 = { - FM3_MFS2_UART, - MFS2RX_IRQn, - MFS2TX_IRQn, + FM3_MFS2_UART, + MFS2RX_IRQn, + MFS2TX_IRQn, }; struct rt_serial_device serial2; void MFS2RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -82,19 +77,19 @@ void MFS2RX_IRQHandler(void) /* UART3 device driver structure */ struct uart03_device uart3 = { - FM3_MFS3_UART, - MFS3RX_IRQn, - MFS3TX_IRQn, + FM3_MFS3_UART, + MFS3RX_IRQn, + MFS3TX_IRQn, }; struct rt_serial_device serial3; void MFS3RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -102,20 +97,20 @@ void MFS3RX_IRQHandler(void) /* UART4 device driver structure */ struct uart47_device uart4 = { - FM3_MFS4_UART, - MFS4RX_IRQn, - MFS4TX_IRQn, - FIFO_SIZE, + FM3_MFS4_UART, + MFS4RX_IRQn, + MFS4TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial4; void MFS4RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -123,20 +118,20 @@ void MFS4RX_IRQHandler(void) /* UART5 device driver structure */ struct uart47_device uart5 = { - FM3_MFS5_UART, - MFS5RX_IRQn, - MFS5TX_IRQn, - FIFO_SIZE, + FM3_MFS5_UART, + MFS5RX_IRQn, + MFS5TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial5; void MFS5RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -144,20 +139,20 @@ void MFS5RX_IRQHandler(void) /* UART6 device driver structure */ struct uart47_device uart6 = { - FM3_MFS6_UART, - MFS6RX_IRQn, - MFS6TX_IRQn, - FIFO_SIZE, + FM3_MFS6_UART, + MFS6RX_IRQn, + MFS6TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial6; void MFS6RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial6, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -165,20 +160,20 @@ void MFS6RX_IRQHandler(void) /* UART7 device driver structure */ struct uart47_device uart7 = { - FM3_MFS7_UART, - MFS7RX_IRQn, - MFS7TX_IRQn, - FIFO_SIZE, + FM3_MFS7_UART, + MFS7RX_IRQn, + MFS7TX_IRQn, + FIFO_SIZE, }; struct rt_serial_device serial7; void MFS7RX_IRQHandler(void) { - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); - /* leave interrupt */ - rt_interrupt_leave(); + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&serial7, RT_SERIAL_EVENT_RX_IND); + /* leave interrupt */ + rt_interrupt_leave(); } #endif @@ -186,749 +181,749 @@ void MFS7RX_IRQHandler(void) void uart_pin_setup(void) { #if defined(RT_USING_UART0_0) - /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ - FM3_GPIO->PFR2_f.P1 = 1; - FM3_GPIO->PFR2_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 1; - FM3_GPIO->EPFR07_f.SIN0S1 = 0; - FM3_GPIO->EPFR07_f.SOT0B0 = 1; - FM3_GPIO->EPFR07_f.SOT0B1 = 0; + /* Set UART Ch0 Port, SIN0_0(P21), SOT0_0(P22) */ + FM3_GPIO->PFR2_f.P1 = 1; + FM3_GPIO->PFR2_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 1; + FM3_GPIO->EPFR07_f.SIN0S1 = 0; + FM3_GPIO->EPFR07_f.SOT0B0 = 1; + FM3_GPIO->EPFR07_f.SOT0B1 = 0; #elif defined(RT_USING_UART0_1) - /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ - FM3_GPIO->PFR1_f.P4 = 1; - FM3_GPIO->PFR1_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN0S0 = 0; - FM3_GPIO->EPFR07_f.SIN0S1 = 1; - FM3_GPIO->EPFR07_f.SOT0B0 = 0; - FM3_GPIO->EPFR07_f.SOT0B1 = 1; + /* Set UART Ch0 Port, SIN0_1(P14), SOT0_1(P15) */ + FM3_GPIO->PFR1_f.P4 = 1; + FM3_GPIO->PFR1_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN0S0 = 0; + FM3_GPIO->EPFR07_f.SIN0S1 = 1; + FM3_GPIO->EPFR07_f.SOT0B0 = 0; + FM3_GPIO->EPFR07_f.SOT0B1 = 1; #endif #if defined(RT_USING_UART1_0) - /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ - FM3_GPIO->PFR5_f.P6 = 1; - FM3_GPIO->PFR5_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 1; - FM3_GPIO->EPFR07_f.SIN1S1 = 0; - FM3_GPIO->EPFR07_f.SOT1B0 = 1; - FM3_GPIO->EPFR07_f.SOT1B1 = 0; + /* Set UART Ch1 Port, SIN1_0(P56), SOT1_0(P57) */ + FM3_GPIO->PFR5_f.P6 = 1; + FM3_GPIO->PFR5_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 1; + FM3_GPIO->EPFR07_f.SIN1S1 = 0; + FM3_GPIO->EPFR07_f.SOT1B0 = 1; + FM3_GPIO->EPFR07_f.SOT1B1 = 0; #elif defined(RT_USING_UART1_1) - /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ - FM3_GPIO->PFR1_f.P1 = 1; - FM3_GPIO->PFR1_f.P2 = 1; - FM3_GPIO->EPFR07_f.SIN1S0 = 0; - FM3_GPIO->EPFR07_f.SIN1S1 = 1; - FM3_GPIO->EPFR07_f.SOT1B0 = 0; - FM3_GPIO->EPFR07_f.SOT1B1 = 1; + /* Set UART Ch1 Port, SIN1_1(P11), SOT1_1(P12) */ + FM3_GPIO->PFR1_f.P1 = 1; + FM3_GPIO->PFR1_f.P2 = 1; + FM3_GPIO->EPFR07_f.SIN1S0 = 0; + FM3_GPIO->EPFR07_f.SIN1S1 = 1; + FM3_GPIO->EPFR07_f.SOT1B0 = 0; + FM3_GPIO->EPFR07_f.SOT1B1 = 1; #endif #if defined(RT_USING_UART2_0) - /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ - FM3_GPIO->PFR7_f.P2 = 1; - FM3_GPIO->PFR7_f.P3 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 0; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 0; + /* Set UART Ch2 Port, SIN2_0(P72), SOT2_0(P73) */ + FM3_GPIO->PFR7_f.P2 = 1; + FM3_GPIO->PFR7_f.P3 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 0; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 0; #elif defined(RT_USING_UART2_1) - /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ - FM3_GPIO->PFR2_f.P4 = 1; - FM3_GPIO->PFR2_f.P5 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 0; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 0; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_1(P24), SOT2_1(P25) */ + FM3_GPIO->PFR2_f.P4 = 1; + FM3_GPIO->PFR2_f.P5 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 0; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 0; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #elif defined(RT_USING_UART2_2) - /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ - FM3_GPIO->PFR1_f.P7 = 1; - FM3_GPIO->PFR1_f.P8 = 1; - FM3_GPIO->EPFR07_f.SIN2S0 = 1; - FM3_GPIO->EPFR07_f.SIN2S1 = 1; - FM3_GPIO->EPFR07_f.SOT2B0 = 1; - FM3_GPIO->EPFR07_f.SOT2B1 = 1; + /* Set UART Ch2 Port, SIN2_2(P17), SOT2_2(P18) */ + FM3_GPIO->PFR1_f.P7 = 1; + FM3_GPIO->PFR1_f.P8 = 1; + FM3_GPIO->EPFR07_f.SIN2S0 = 1; + FM3_GPIO->EPFR07_f.SIN2S1 = 1; + FM3_GPIO->EPFR07_f.SOT2B0 = 1; + FM3_GPIO->EPFR07_f.SOT2B1 = 1; #endif #if defined(RT_USING_UART3_0) - /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ - FM3_GPIO->PFR6_f.P6 = 1; - FM3_GPIO->PFR6_f.P7 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 0; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 0; + /* Set UART Ch3 Port, SIN3_0(P66), SOT3_0(P67) */ + FM3_GPIO->PFR6_f.P6 = 1; + FM3_GPIO->PFR6_f.P7 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 0; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 0; #elif defined(RT_USING_UART3_1) - /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ - FM3_GPIO->PFR5_f.P0 = 1; - FM3_GPIO->PFR5_f.P1 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 0; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 0; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_1(P50), SOT3_1(P51) */ + FM3_GPIO->PFR5_f.P0 = 1; + FM3_GPIO->PFR5_f.P1 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 0; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 0; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #elif defined(RT_USING_UART3_2) - /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ - FM3_GPIO->PFR4_f.P8 = 1; - FM3_GPIO->PFR4_f.P9 = 1; - FM3_GPIO->EPFR07_f.SIN3S0 = 1; - FM3_GPIO->EPFR07_f.SIN3S1 = 1; - FM3_GPIO->EPFR07_f.SOT3B0 = 1; - FM3_GPIO->EPFR07_f.SOT3B1 = 1; + /* Set UART Ch3 Port, SIN3_2(P48), SOT3_2(P49) */ + FM3_GPIO->PFR4_f.P8 = 1; + FM3_GPIO->PFR4_f.P9 = 1; + FM3_GPIO->EPFR07_f.SIN3S0 = 1; + FM3_GPIO->EPFR07_f.SIN3S1 = 1; + FM3_GPIO->EPFR07_f.SOT3B0 = 1; + FM3_GPIO->EPFR07_f.SOT3B1 = 1; #endif #if defined(RT_USING_UART4_0) - /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ - FM3_GPIO->PFR0_f.PA = 1; - FM3_GPIO->PFR0_f.PB = 1; - FM3_GPIO->PFR0_f.PD = 1; - FM3_GPIO->PFR0_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 0; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 0; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 0; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 0; + /* Set UART Ch4 Port, SIN4_0(P0A), SOT4_0(P0B), CTS4_0(P0E), RTS4_0(P0D) */ + FM3_GPIO->PFR0_f.PA = 1; + FM3_GPIO->PFR0_f.PB = 1; + FM3_GPIO->PFR0_f.PD = 1; + FM3_GPIO->PFR0_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 0; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 0; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 0; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 0; #elif defined(RT_USING_UART4_1) - /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ - FM3_GPIO->PFR1_f.PA = 1; - FM3_GPIO->PFR1_f.PB = 1; - FM3_GPIO->PFR1_f.PD = 1; - FM3_GPIO->PFR1_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 0; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 0; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 0; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 0; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_1(P1A), SOT4_1(P1B), CTS4_1(P1D), RTS4_1(P1E) */ + FM3_GPIO->PFR1_f.PA = 1; + FM3_GPIO->PFR1_f.PB = 1; + FM3_GPIO->PFR1_f.PD = 1; + FM3_GPIO->PFR1_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 0; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 0; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 0; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 0; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #elif defined(RT_USING_UART4_2) - /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ - FM3_GPIO->PFR0_f.P5 = 1; - FM3_GPIO->PFR0_f.P6 = 1; - FM3_GPIO->PFR0_f.P8 = 1; - FM3_GPIO->PFR0_f.P9 = 1; - FM3_GPIO->EPFR08_f.SIN4S0 = 1; - FM3_GPIO->EPFR08_f.SIN4S1 = 1; - FM3_GPIO->EPFR08_f.SOT4B0 = 1; - FM3_GPIO->EPFR08_f.SOT4B1 = 1; - FM3_GPIO->EPFR08_f.CTS4S0 = 1; - FM3_GPIO->EPFR08_f.CTS4S1 = 1; - FM3_GPIO->EPFR08_f.RTS4E0 = 1; - FM3_GPIO->EPFR08_f.RTS4E1 = 1; + /* Set UART Ch4 Port, SIN4_2(P05), SOT4_2(P06), CTS4_2(P08), RTS4_2(P09)*/ + FM3_GPIO->PFR0_f.P5 = 1; + FM3_GPIO->PFR0_f.P6 = 1; + FM3_GPIO->PFR0_f.P8 = 1; + FM3_GPIO->PFR0_f.P9 = 1; + FM3_GPIO->EPFR08_f.SIN4S0 = 1; + FM3_GPIO->EPFR08_f.SIN4S1 = 1; + FM3_GPIO->EPFR08_f.SOT4B0 = 1; + FM3_GPIO->EPFR08_f.SOT4B1 = 1; + FM3_GPIO->EPFR08_f.CTS4S0 = 1; + FM3_GPIO->EPFR08_f.CTS4S1 = 1; + FM3_GPIO->EPFR08_f.RTS4E0 = 1; + FM3_GPIO->EPFR08_f.RTS4E1 = 1; #endif #if defined(RT_USING_UART5_0) - /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ - FM3_GPIO->PFR6_f.P0 = 1; - FM3_GPIO->PFR6_f.P1 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 0; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 0; + /* Set UART Ch5 Port, SIN5_0(P60), SOT5_0(P61) */ + FM3_GPIO->PFR6_f.P0 = 1; + FM3_GPIO->PFR6_f.P1 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 0; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 0; #elif defined(RT_USING_UART5_1) - /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ - FM3_GPIO->PFR6_f.P3 = 1; - FM3_GPIO->PFR6_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 0; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 0; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_1(P63), SOT5_1(P64) */ + FM3_GPIO->PFR6_f.P3 = 1; + FM3_GPIO->PFR6_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 0; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 0; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #elif defined(RT_USING_UART5_2) - /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ - FM3_GPIO->PFR3_f.P6 = 1; - FM3_GPIO->PFR3_f.P7 = 1; - FM3_GPIO->EPFR08_f.SIN5S0 = 1; - FM3_GPIO->EPFR08_f.SIN5S1 = 1; - FM3_GPIO->EPFR08_f.SOT5B0 = 1; - FM3_GPIO->EPFR08_f.SOT5B1 = 1; + /* Set UART Ch5 Port, SIN5_2(P36), SOT5_2(P37) */ + FM3_GPIO->PFR3_f.P6 = 1; + FM3_GPIO->PFR3_f.P7 = 1; + FM3_GPIO->EPFR08_f.SIN5S0 = 1; + FM3_GPIO->EPFR08_f.SIN5S1 = 1; + FM3_GPIO->EPFR08_f.SOT5B0 = 1; + FM3_GPIO->EPFR08_f.SOT5B1 = 1; #endif #if defined(RT_USING_UART6_0) - /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ - FM3_GPIO->PFR5_f.P3 = 1; - FM3_GPIO->PFR5_f.P4 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 1; - FM3_GPIO->EPFR08_f.SIN6S1 = 0; - FM3_GPIO->EPFR08_f.SOT6B0 = 1; - FM3_GPIO->EPFR08_f.SOT6B1 = 0; + /* Set UART Ch6 Port, SIN6_0(P53), SOT6_0(P54) */ + FM3_GPIO->PFR5_f.P3 = 1; + FM3_GPIO->PFR5_f.P4 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 1; + FM3_GPIO->EPFR08_f.SIN6S1 = 0; + FM3_GPIO->EPFR08_f.SOT6B0 = 1; + FM3_GPIO->EPFR08_f.SOT6B1 = 0; #elif defined(RT_USING_UART6_1) - /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ - FM3_GPIO->PFR3_f.P2 = 1; - FM3_GPIO->PFR3_f.P3 = 1; - FM3_GPIO->EPFR08_f.SIN6S0 = 0; - FM3_GPIO->EPFR08_f.SIN6S1 = 1; - FM3_GPIO->EPFR08_f.SOT6B0 = 0; - FM3_GPIO->EPFR08_f.SOT6B1 = 1; + /* Set UART Ch6 Port, SIN6_1(P33), SOT6_1(P32) */ + FM3_GPIO->PFR3_f.P2 = 1; + FM3_GPIO->PFR3_f.P3 = 1; + FM3_GPIO->EPFR08_f.SIN6S0 = 0; + FM3_GPIO->EPFR08_f.SIN6S1 = 1; + FM3_GPIO->EPFR08_f.SOT6B0 = 0; + FM3_GPIO->EPFR08_f.SOT6B1 = 1; #endif #if defined(RT_USING_UART7_0) - /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ - FM3_GPIO->PFR5_f.P9 = 1; - FM3_GPIO->PFR5_f.PA = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 1; - FM3_GPIO->EPFR08_f.SIN7S1 = 0; - FM3_GPIO->EPFR08_f.SOT7B0 = 1; - FM3_GPIO->EPFR08_f.SOT7B1 = 0; + /* Set UART Ch7 Port, SIN7_0(P59), SOT7_0(P5A) */ + FM3_GPIO->PFR5_f.P9 = 1; + FM3_GPIO->PFR5_f.PA = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 1; + FM3_GPIO->EPFR08_f.SIN7S1 = 0; + FM3_GPIO->EPFR08_f.SOT7B0 = 1; + FM3_GPIO->EPFR08_f.SOT7B1 = 0; #elif defined(RT_USING_UART7_1) - /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ - FM3_GPIO->PFR4_f.PD = 1; - FM3_GPIO->PFR4_f.PE = 1; - FM3_GPIO->EPFR08_f.SIN7S0 = 0; - FM3_GPIO->EPFR08_f.SIN7S1 = 1; - FM3_GPIO->EPFR08_f.SOT7B0 = 0; - FM3_GPIO->EPFR08_f.SOT7B1 = 1; + /* Set UART Ch7 Port, SIN7_1(P4E), SOT7_1(P4D) */ + FM3_GPIO->PFR4_f.PD = 1; + FM3_GPIO->PFR4_f.PE = 1; + FM3_GPIO->EPFR08_f.SIN7S0 = 0; + FM3_GPIO->EPFR08_f.SIN7S1 = 1; + FM3_GPIO->EPFR08_f.SOT7B0 = 0; + FM3_GPIO->EPFR08_f.SOT7B1 = 1; #endif } static rt_err_t uart03_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart03_device *uart; + struct uart03_device *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; + uart = (struct uart03_device *)serial->parent.user_data; - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } - return RT_EOK; + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } - + static rt_err_t uart03_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart03_device *uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct uart03_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } + struct uart03_device *uart; - return (RT_EOK); + RT_ASSERT(serial != RT_NULL); + uart = (struct uart03_device *)serial->parent.user_data; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } - + static int uart03_putc(struct rt_serial_device *serial, char c) { - struct uart03_device *uart; + struct uart03_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* while send buffer is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to send buffer */ - uart->uart_regs->TDR = c; + RT_ASSERT(serial != RT_NULL); - return (1); + uart = (struct uart03_device *)serial->parent.user_data; + /* while send buffer is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to send buffer */ + uart->uart_regs->TDR = c; + + return (1); } static int uart03_getc(struct rt_serial_device *serial) -{ - struct uart03_device *uart; - int ch; - - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart03_device *)serial->parent.user_data; - /* receive buffer is full */ - if (uart->uart_regs->SSR & SSR_RDRF) - { - ch = uart->uart_regs->RDR & 0xff; - return (ch); - } - else - return (-1); +{ + struct uart03_device *uart; + int ch; + + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart03_device *)serial->parent.user_data; + /* receive buffer is full */ + if (uart->uart_regs->SSR & SSR_RDRF) + { + ch = uart->uart_regs->RDR & 0xff; + return (ch); + } + else + return (-1); } static struct rt_uart_ops uart03_ops = { - uart03_configure, - uart03_control, - uart03_putc, - uart03_getc, + uart03_configure, + uart03_control, + uart03_putc, + uart03_getc, }; static rt_err_t uart47_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; + uart = (struct uart47_device *)serial->parent.user_data; - uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; + uart->uart_regs->SMR = SMR_MD_UART | SMR_SOE; - /* set baudreate */ - uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; + /* set baudreate */ + uart->uart_regs->BGR = (40000000UL + (cfg->baud_rate/2))/cfg->baud_rate - 1; - /* set stop bits */ - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_2: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 0; - break; - case STOP_BITS_3: - uart->uart_regs->SMR_f.SBL = 0; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - case STOP_BITS_4: - uart->uart_regs->SMR_f.SBL = 1; - uart->uart_regs->ESCR_f.ESBL = 1; - break; - default: - return RT_ERROR; - } + /* set stop bits */ + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_2: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 0; + break; + case STOP_BITS_3: + uart->uart_regs->SMR_f.SBL = 0; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + case STOP_BITS_4: + uart->uart_regs->SMR_f.SBL = 1; + uart->uart_regs->ESCR_f.ESBL = 1; + break; + default: + return RT_ERROR; + } - /* set data bits */ - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_6: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_7: - uart->uart_regs->ESCR_f.L0 = 1; - uart->uart_regs->ESCR_f.L1 = 1; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_8: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 0; - break; - case DATA_BITS_9: - uart->uart_regs->ESCR_f.L0 = 0; - uart->uart_regs->ESCR_f.L1 = 0; - uart->uart_regs->ESCR_f.L2 = 1; - break; - default: - return RT_ERROR; - } + /* set data bits */ + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_6: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_7: + uart->uart_regs->ESCR_f.L0 = 1; + uart->uart_regs->ESCR_f.L1 = 1; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_8: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 0; + break; + case DATA_BITS_9: + uart->uart_regs->ESCR_f.L0 = 0; + uart->uart_regs->ESCR_f.L1 = 0; + uart->uart_regs->ESCR_f.L2 = 1; + break; + default: + return RT_ERROR; + } - /* set parity */ - switch (cfg->parity) - { - case PARITY_NONE: - uart->uart_regs->ESCR_f.PEN = 0; - break; - case PARITY_EVEN: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 0; - break; - case PARITY_ODD: - uart->uart_regs->ESCR_f.PEN = 1; - uart->uart_regs->ESCR_f.P = 1; - break; - default: - return RT_ERROR; - } + /* set parity */ + switch (cfg->parity) + { + case PARITY_NONE: + uart->uart_regs->ESCR_f.PEN = 0; + break; + case PARITY_EVEN: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 0; + break; + case PARITY_ODD: + uart->uart_regs->ESCR_f.PEN = 1; + uart->uart_regs->ESCR_f.P = 1; + break; + default: + return RT_ERROR; + } - /* set bit order */ - switch (cfg->bit_order) - { - case BIT_ORDER_LSB: - uart->uart_regs->SMR_f.BDS = 0; - break; - case BIT_ORDER_MSB: - uart->uart_regs->SMR_f.BDS = 1; - break; - default: - return RT_ERROR; - } + /* set bit order */ + switch (cfg->bit_order) + { + case BIT_ORDER_LSB: + uart->uart_regs->SMR_f.BDS = 0; + break; + case BIT_ORDER_MSB: + uart->uart_regs->SMR_f.BDS = 1; + break; + default: + return RT_ERROR; + } - /* set NRZ mode */ - switch (cfg->invert) - { - case NRZ_NORMAL: - uart->uart_regs->ESCR_f.INV = 0; - break; - case NRZ_INVERTED: - uart->uart_regs->ESCR_f.INV = 1; - break; - default: - return RT_ERROR; - } - - /* configure fifo */ - /* Disable the Data Lost detection */ - uart->uart_regs->FCR1_f.FLSTE = 0; - /* Enable the received FIFO idle detection */ - uart->uart_regs->FCR1_f.FRIE = 1; - /* Requests for the transmit FIFO data */ - uart->uart_regs->FCR1_f.FDRQ = 1; - /* Disable the transmit FIFO interrupt */ - uart->uart_regs->FCR1_f.FTIE = 0; - /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ - uart->uart_regs->FCR1_f.FSEL = 0; + /* set NRZ mode */ + switch (cfg->invert) + { + case NRZ_NORMAL: + uart->uart_regs->ESCR_f.INV = 0; + break; + case NRZ_INVERTED: + uart->uart_regs->ESCR_f.INV = 1; + break; + default: + return RT_ERROR; + } - /* Transfer data count */ - uart->uart_regs->FBYTE1 = 0; - /* Set the data count to generate a received interrupt */ - uart->uart_regs->FBYTE2 = uart->fifo_size; + /* configure fifo */ + /* Disable the Data Lost detection */ + uart->uart_regs->FCR1_f.FLSTE = 0; + /* Enable the received FIFO idle detection */ + uart->uart_regs->FCR1_f.FRIE = 1; + /* Requests for the transmit FIFO data */ + uart->uart_regs->FCR1_f.FDRQ = 1; + /* Disable the transmit FIFO interrupt */ + uart->uart_regs->FCR1_f.FTIE = 0; + /* Transmit FIFO:FIFO1; Received FIFO:FIFO2 */ + uart->uart_regs->FCR1_f.FSEL = 0; - /* FIFO pointer Not reloaded */ - uart->uart_regs->FCR0_f.FLD = 0; - /* FIFO pointer Not saved */ - uart->uart_regs->FCR0_f.FSET = 0; - /* FIFO2 is reset */ - uart->uart_regs->FCR0_f.FCL2 = 1; - /* FIFO1 is reset */ - uart->uart_regs->FCR0_f.FCL1 = 1; - /* Enables the FIFO2 operation */ - uart->uart_regs->FCR0_f.FE2 = 1; - /* Enables the FIFO1 operation */ - uart->uart_regs->FCR0_f.FE1 = 1; - - /* enable receive and send */ - uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + /* Transfer data count */ + uart->uart_regs->FBYTE1 = 0; + /* Set the data count to generate a received interrupt */ + uart->uart_regs->FBYTE2 = uart->fifo_size; - return RT_EOK; + /* FIFO pointer Not reloaded */ + uart->uart_regs->FCR0_f.FLD = 0; + /* FIFO pointer Not saved */ + uart->uart_regs->FCR0_f.FSET = 0; + /* FIFO2 is reset */ + uart->uart_regs->FCR0_f.FCL2 = 1; + /* FIFO1 is reset */ + uart->uart_regs->FCR0_f.FCL1 = 1; + /* Enables the FIFO2 operation */ + uart->uart_regs->FCR0_f.FE2 = 1; + /* Enables the FIFO1 operation */ + uart->uart_regs->FCR0_f.FE1 = 1; + + /* enable receive and send */ + uart->uart_regs->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + return RT_EOK; } static rt_err_t uart47_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct uart47_device *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - UART_DISABLE_IRQ(uart->rx_irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - UART_ENABLE_IRQ(uart->rx_irq); - break; - } + RT_ASSERT(serial != RT_NULL); + uart = (struct uart47_device *)serial->parent.user_data; - return (RT_EOK); + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + UART_DISABLE_IRQ(uart->rx_irq); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + UART_ENABLE_IRQ(uart->rx_irq); + break; + } + + return (RT_EOK); } static int uart47_putc(struct rt_serial_device *serial, char c) { - struct uart47_device *uart; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; + RT_ASSERT(serial != RT_NULL); - /* while send fifo is empty */ - while (!(uart->uart_regs->SSR & SSR_TDRE)); - /* write to fifo */ - uart->uart_regs->TDR = c; + uart = (struct uart47_device *)serial->parent.user_data; - return (1); + /* while send fifo is empty */ + while (!(uart->uart_regs->SSR & SSR_TDRE)); + /* write to fifo */ + uart->uart_regs->TDR = c; + + return (1); } static int uart47_getc(struct rt_serial_device *serial) -{ - int ch; - struct uart47_device *uart; +{ + int ch; + struct uart47_device *uart; - RT_ASSERT(serial != RT_NULL); - - uart = (struct uart47_device *)serial->parent.user_data; - - /* receive is disabled */ - if (!(uart->uart_regs->SCR & SCR_RXE)) - return (-1); + RT_ASSERT(serial != RT_NULL); + + uart = (struct uart47_device *)serial->parent.user_data; + + /* receive is disabled */ + if (!(uart->uart_regs->SCR & SCR_RXE)) + return (-1); /* receive fifo is not full */ - if ((uart->uart_regs->SSR & SSR_RDRF) == 0) - return (-1); - /* read char */ - ch = uart->uart_regs->RDR & 0xff; - - return (ch); + if ((uart->uart_regs->SSR & SSR_RDRF) == 0) + return (-1); + /* read char */ + ch = uart->uart_regs->RDR & 0xff; + + return (ch); } static struct rt_uart_ops uart47_ops = { - uart47_configure, - uart47_control, - uart47_putc, - uart47_getc, + uart47_configure, + uart47_control, + uart47_putc, + uart47_getc, }; void rt_hw_serial_init(void) { - struct serial_configure config; + struct serial_configure config; - uart_pin_setup(); + uart_pin_setup(); #if (defined(RT_USING_UART0_0) || defined(RT_USING_UART0_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial0.ops = &uart03_ops; - serial0.config = config; + serial0.ops = &uart03_ops; + serial0.config = config; - /* register UART0 device */ - rt_hw_serial_register(&serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart0); + /* register UART0 device */ + rt_hw_serial_register(&serial0, "uart0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart0); #endif #if (defined(RT_USING_UART1_0) || defined(RT_USING_UART1_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial1.ops = &uart03_ops; - serial1.config = config; + serial1.ops = &uart03_ops; + serial1.config = config; - /* register UART1 device */ - rt_hw_serial_register(&serial1, - "uart1", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart1); + /* register UART1 device */ + rt_hw_serial_register(&serial1, + "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart1); #endif #if (defined(RT_USING_UART2_0) || defined(RT_USING_UART2_1) || defined(RT_USING_UART2_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial2.ops = &uart03_ops; - serial2.config = config; + serial2.ops = &uart03_ops; + serial2.config = config; - /* register UART2 device */ - rt_hw_serial_register(&serial2, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); + /* register UART2 device */ + rt_hw_serial_register(&serial2, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); #endif #if (defined(RT_USING_UART3_0) || defined(RT_USING_UART3_1) || defined(RT_USING_UART3_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial3.ops = &uart03_ops; - serial3.config = config; + serial3.ops = &uart03_ops; + serial3.config = config; - /* register UART3 device */ - rt_hw_serial_register(&serial3, - "uart3", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart3); + /* register UART3 device */ + rt_hw_serial_register(&serial3, + "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart3); #endif #if (defined(RT_USING_UART4_0) || defined(RT_USING_UART4_1) || defined(RT_USING_UART4_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial4.ops = &uart47_ops; - serial4.config = config; + serial4.ops = &uart47_ops; + serial4.config = config; - /* register UART4 device */ - rt_hw_serial_register(&serial4, - "uart4", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart4); + /* register UART4 device */ + rt_hw_serial_register(&serial4, + "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart4); #endif #if (defined(RT_USING_UART5_0) || defined(RT_USING_UART5_1) || defined(RT_USING_UART5_2)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial5.ops = &uart47_ops; - serial5.config = config; + serial5.ops = &uart47_ops; + serial5.config = config; - /* register UART5 device */ - rt_hw_serial_register(&serial5, - "uart5", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart5); + /* register UART5 device */ + rt_hw_serial_register(&serial5, + "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart5); #endif #if (defined(RT_USING_UART6_0) || defined(RT_USING_UART6_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial6.ops = &uart47_ops; - serial6.config = config; + serial6.ops = &uart47_ops; + serial6.config = config; - /* register UART6 device */ - rt_hw_serial_register(&serial6, - "uart6", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart6); + /* register UART6 device */ + rt_hw_serial_register(&serial6, + "uart6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart6); #endif #if (defined(RT_USING_UART7_0) || defined(RT_USING_UART7_1)) - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - config.bufsz = RT_SERIAL_RB_BUFSZ; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + config.bufsz = RT_SERIAL_RB_BUFSZ; - serial7.ops = &uart47_ops; - serial7.config = config; + serial7.ops = &uart47_ops; + serial7.config = config; - /* register UART7 device */ - rt_hw_serial_register(&serial7, - "uart7", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart7); + /* register UART7 device */ + rt_hw_serial_register(&serial7, + "uart7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart7); #endif } diff --git a/bsp/mb9bf506r/drivers/fm3_uart.h b/bsp/mb9bf506r/drivers/fm3_uart.h index f8698dbe17..824592c850 100644 --- a/bsp/mb9bf506r/drivers/fm3_uart.h +++ b/bsp/mb9bf506r/drivers/fm3_uart.h @@ -1,11 +1,7 @@ /* - * File : fm3_uart.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -55,7 +51,7 @@ #define ESCR_DATABITS_7 0x03U #define ESCR_DATABITS_9 0x04U -#define FIFO_SIZE 16 +#define FIFO_SIZE 16 /* * Enable/DISABLE Interrupt Controller @@ -66,19 +62,19 @@ struct uart03_device { - FM3_MFS03_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; + FM3_MFS03_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; }; struct uart47_device { - FM3_MFS47_UART_TypeDef *uart_regs; - /* irq number */ - IRQn_Type rx_irq; - IRQn_Type tx_irq; - rt_uint8_t fifo_size; + FM3_MFS47_UART_TypeDef *uart_regs; + /* irq number */ + IRQn_Type rx_irq; + IRQn_Type tx_irq; + rt_uint8_t fifo_size; }; void rt_hw_serial_init(void); diff --git a/bsp/mb9bf506r/drivers/led.c b/bsp/mb9bf506r/drivers/led.c index a1ab6a0592..3f6a11fcfe 100644 --- a/bsp/mb9bf506r/drivers/led.c +++ b/bsp/mb9bf506r/drivers/led.c @@ -1,17 +1,13 @@ /* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #include #include @@ -20,8 +16,8 @@ void rt_hw_led_on(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -31,16 +27,16 @@ void rt_hw_led_on(rt_uint8_t num) USER_LED_PDOR &= ~USER_LED2; break; case 3: - USER_LED_PDOR &= ~USER_LED3; + USER_LED_PDOR &= ~USER_LED3; break; default: break; - } + } } void rt_hw_led_off(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); + RT_ASSERT(num < LEDS_MAX_NUMBER); switch (num) { @@ -51,17 +47,17 @@ void rt_hw_led_off(rt_uint8_t num) USER_LED_PDOR |= USER_LED2; break; case 3: - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void rt_hw_led_toggle(rt_uint8_t num) { - RT_ASSERT(num < LEDS_MAX_NUMBER); - + RT_ASSERT(num < LEDS_MAX_NUMBER); + switch (num) { case 1: @@ -80,11 +76,11 @@ void rt_hw_led_toggle(rt_uint8_t num) if (USER_LED_PDOR&USER_LED3) USER_LED_PDOR &= ~USER_LED3; else - USER_LED_PDOR |= USER_LED3; + USER_LED_PDOR |= USER_LED3; break; default: break; - } + } } void led_init(void) @@ -102,7 +98,7 @@ void led_init(void) void pwm_update(rt_uint16_t value) { - FM3_BT2_PWM->PDUT = value; + FM3_BT2_PWM->PDUT = value; } static void led1_thread_entry(void *parameter) @@ -130,11 +126,11 @@ void rt_hw_led_init(void) led_init(); led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) + if (led1_thread != RT_NULL) rt_thread_startup(led1_thread); - + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) + if (led2_thread != RT_NULL) rt_thread_startup(led2_thread); } diff --git a/bsp/mb9bf506r/drivers/led.h b/bsp/mb9bf506r/drivers/led.h index 5db0980520..bcbfaf9b62 100644 --- a/bsp/mb9bf506r/drivers/led.h +++ b/bsp/mb9bf506r/drivers/led.h @@ -1,38 +1,34 @@ /* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2011-03-03 lgnq */ - + #ifndef __LED_H__ #define __LED_H__ #include "mb9bf506r.h" -#define LEDS_MAX_NUMBER 4 +#define LEDS_MAX_NUMBER 4 /* LED */ #define USER_LED1 (1UL<<0x9) #define USER_LED2 (1UL<<0xa) #define USER_LED3 (1UL<<0xb) -#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) -#define USER_LED_PFR FM3_GPIO->PFR1 -#define USER_LED_PCR FM3_GPIO->PCR1 -#define USER_LED_PDOR FM3_GPIO->PDOR1 -#define USER_LED_DDR FM3_GPIO->DDR1 +#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) +#define USER_LED_PFR FM3_GPIO->PFR1 +#define USER_LED_PCR FM3_GPIO->PCR1 +#define USER_LED_PDOR FM3_GPIO->PDOR1 +#define USER_LED_DDR FM3_GPIO->DDR1 -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 void rt_hw_led_init(void); void rt_hw_led_on(rt_uint8_t num); diff --git a/bsp/mb9bf506r/drivers/nand.c b/bsp/mb9bf506r/drivers/nand.c index 22427a3d5f..fcd8cf42d4 100644 --- a/bsp/mb9bf506r/drivers/nand.c +++ b/bsp/mb9bf506r/drivers/nand.c @@ -1,11 +1,7 @@ /* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,17 +12,17 @@ #include "mb9bf506r.h" /* - * NandFlash driver for SamSung K9F5608 + * NandFlash driver for SamSung K9F5608 * 32M x 8bit */ -#define PAGE_SIZE 512 -#define PAGE_PER_BLOCK 32 -#define BLOCK_NUM 2048 +#define PAGE_SIZE 512 +#define PAGE_PER_BLOCK 32 +#define BLOCK_NUM 2048 /* device driver debug trace */ /* #define NAND_DEBUG */ #ifdef NAND_DEBUG -#define trace_log rt_kprintf +#define trace_log rt_kprintf #else #define trace_log(...) #endif @@ -38,14 +34,14 @@ */ struct rt_device_nand { - struct rt_device parent; /* which is inherited from rt_device */ + struct rt_device parent; /* which is inherited from rt_device */ - rt_uint16_t block_num; /* total block number in device */ - rt_uint16_t page_per_block; /* pages in one block */ - rt_uint16_t page_size; /* page size */ + rt_uint16_t block_num; /* total block number in device */ + rt_uint16_t page_per_block; /* pages in one block */ + rt_uint16_t page_size; /* page size */ - /* this buffer which used as to save data before erase block */ - rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; + /* this buffer which used as to save data before erase block */ + rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; }; static struct rt_device_nand _nand; @@ -60,8 +56,8 @@ static struct rt_device_nand _nand; #define NF_OE_H() {IO_NF_PDOR |= NF_EN;} #define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} -#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} -#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} +#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} +#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} static unsigned char NF_ReadStatus(void); static void Wait(unsigned int cnt); @@ -107,11 +103,11 @@ static unsigned char NF_ReadStatus(void) */ static void NF_Init(void) { - FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ - FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ - |1<<6 /* ALE, CLE, WEX, REX enable */ - |1<<0); /* D0-D7 enable */ + FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ + FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ + |1<<6 /* ALE, CLE, WEX, REX enable */ + |1<<0); /* D0-D7 enable */ FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ @@ -125,9 +121,9 @@ static void NF_Init(void) static void NF_UnInit(void) { - FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ - FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ + FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ + FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ |1<<6 /* disable ALE, CLE, WEX, REX enable */ |1<<0); /* disable D0-D7 enable */ FM3_EXBUS->MODE7 &= ~(1<<4); @@ -144,52 +140,52 @@ static void NF_UnInit(void) * Return: 0: Flash Operation OK * 1: Flash Operation NG */ -int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, +int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, unsigned char *oob) { unsigned int blockPage,i; NF_Init(); - blockPage=(block<<5)+page; /* 1 block=32 page */ + blockPage=(block<<5)+page; /* 1 block=32 page */ NF_OE_L(); NF_DATA_OUT(); - if (buffer != RT_NULL) - { - volatile unsigned char ch; + if (buffer != RT_NULL) + { + volatile unsigned char ch; - NF_CMD(NAND_CMD_READ0); /* send read data */ + NF_CMD(NAND_CMD_READ0); /* send read data */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); - Wait(500); + Wait(500); - for(i=0;i<512;i++) /* read 512 bytes data */ - buffer[i] = NF_RDDATA(); - for(i=0;i<16;i++) /* read 16 bytes oob */ - if (oob != RT_NULL) - oob[i] = NF_RDDATA(); - else - ch = NF_RDDATA(); - } - else - { - NF_CMD(NAND_CMD_READOOB); /* send read data */ + for(i=0;i<512;i++) /* read 512 bytes data */ + buffer[i] = NF_RDDATA(); + for(i=0;i<16;i++) /* read 16 bytes oob */ + if (oob != RT_NULL) + oob[i] = NF_RDDATA(); + else + ch = NF_RDDATA(); + } + else + { + NF_CMD(NAND_CMD_READOOB); /* send read data */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); - Wait(500); + Wait(500); - for (i=0; i<16; i++) /* read 16 bytes oob */ - oob[i] = NF_RDDATA(); - } + for (i=0; i<16; i++) /* read 16 bytes oob */ + oob[i] = NF_RDDATA(); + } NF_OE_H(); NF_UnInit(); @@ -206,7 +202,7 @@ int NF_EraseBlock(unsigned int block) { rt_uint32_t blockPage; - trace_log("Erase block %d: ", block); + trace_log("Erase block %d: ", block); NF_Init(); blockPage = (block << 5); @@ -219,19 +215,19 @@ int NF_EraseBlock(unsigned int block) if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - trace_log("Failed\n"); - rt_kprintf("erase block failed\n"); + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + trace_log("Failed\n"); + rt_kprintf("erase block failed\n"); - return FLASH_NG; + return FLASH_NG; } NF_OE_H(); NF_UnInit(); - trace_log("OK\n"); + trace_log("OK\n"); return FLASH_OK; } @@ -261,24 +257,24 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) NF_ADDR((blockPage>>8) & 0xff); NF_CLR_ALE(); - for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ - for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ + for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ + for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ - NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ + NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ if(NF_ReadStatus()) { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - - trace_log("write failed\n"); - return FLASH_NG; + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + + trace_log("write failed\n"); + return FLASH_NG; } /* verify the write data */ NF_DATA_OUT(); - NF_CMD(NAND_CMD_READ0); /* send read command */ + NF_CMD(NAND_CMD_READ0); /* send read command */ NF_ADDR(0); NF_ADDR(blockPage & 0xff); NF_ADDR((blockPage>>8) & 0xff); @@ -288,11 +284,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) Wait(500); for(i=0; i<512; i++) { - data=NF_RDDATA(); /* verify 1-512 byte */ + data=NF_RDDATA(); /* verify 1-512 byte */ if(data != buffer[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); NF_Reset(); NF_OE_H(); @@ -303,11 +299,11 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) for(i=0; i<16; i++) { - data=NF_RDDATA(); /* verify 16 byte dummy data */ + data=NF_RDDATA(); /* verify 16 byte dummy data */ if(data != se[i]) { - trace_log("block %d, page %d\n", block , page); - trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); + trace_log("block %d, page %d\n", block , page); + trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); NF_Reset(); NF_OE_H(); NF_UnInit(); @@ -327,7 +323,7 @@ int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) */ void NF_ReadID(unsigned char *id) { - unsigned char maker_code; + unsigned char maker_code; NF_Init(); NF_OE_L(); NF_DATA_OUT(); @@ -337,7 +333,7 @@ void NF_ReadID(unsigned char *id) Wait(10); NF_DATA_IN(); maker_code = NF_RDDATA(); - maker_code = maker_code; + maker_code = maker_code; *id = NF_RDDATA(); NF_OE_H(); NF_UnInit(); @@ -345,58 +341,58 @@ void NF_ReadID(unsigned char *id) static rt_err_t rt_nand_init (rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } static rt_err_t rt_nand_close(rt_device_t dev) { - /* empty implementation */ - return RT_EOK; + /* empty implementation */ + return RT_EOK; } /* nand device read */ -static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, +static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_ubase_t block; /* block of position */ - rt_ubase_t page, index; /* page in block of position */ - rt_uint8_t *page_ptr, oob[16]; - struct rt_device_nand *nand; + rt_ubase_t block; /* block of position */ + rt_ubase_t page, index; /* page in block of position */ + rt_uint8_t *page_ptr, oob[16]; + struct rt_device_nand *nand; - /* get nand device */ - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); + /* get nand device */ + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; - trace_log("nand read: position %d, block %d, page %d, size %d\n", - pos, block, page, size); + trace_log("nand read: position %d, block %d, page %d, size %d\n", + pos, block, page, size); - /* set page buffer pointer */ - page_ptr = (rt_uint8_t*) buffer; - for (index = 0; index < size; index ++) - { - NF_ReadPage(block, page + index, page_ptr, oob); - page_ptr += nand->page_size; - - if (page + index > nand->page_per_block) - { - block += 1; - page = 0; - } - } + /* set page buffer pointer */ + page_ptr = (rt_uint8_t*) buffer; + for (index = 0; index < size; index ++) + { + NF_ReadPage(block, page + index, page_ptr, oob); + page_ptr += nand->page_size; - /* return read size (count of block) */ - return size; + if (page + index > nand->page_per_block) + { + block += 1; + page = 0; + } + } + + /* return read size (count of block) */ + return size; } /* @@ -407,190 +403,190 @@ static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, * @param buffer the data buffer to be written * @param pages the number of pages to be written */ -static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, - rt_ubase_t block, rt_ubase_t page, - const rt_uint8_t *buffer, rt_ubase_t pages) +static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, + rt_ubase_t block, rt_ubase_t page, + const rt_uint8_t *buffer, rt_ubase_t pages) { - rt_ubase_t index; - rt_uint32_t page_status; - rt_uint8_t *page_ptr, oob[16]; + rt_ubase_t index; + rt_uint32_t page_status; + rt_uint8_t *page_ptr, oob[16]; - /* set page status */ - page_status = 0; + /* set page status */ + page_status = 0; - /* read each page in block */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - NF_ReadPage(block, index, page_ptr, oob); - if (!oob[0]) - page_status |= (1 << index); - page_ptr += nand->page_size; - } + /* read each page in block */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + NF_ReadPage(block, index, page_ptr, oob); + if (!oob[0]) + page_status |= (1 << index); + page_ptr += nand->page_size; + } - /* erase block */ - NF_EraseBlock(block); + /* erase block */ + NF_EraseBlock(block); - page_ptr = &(nand->block_buffer[page * nand->page_size]); - /* merge buffer to page buffer */ - for (index = 0; index < pages; index ++) - { - rt_memcpy(page_ptr, buffer, nand->page_size); + page_ptr = &(nand->block_buffer[page * nand->page_size]); + /* merge buffer to page buffer */ + for (index = 0; index < pages; index ++) + { + rt_memcpy(page_ptr, buffer, nand->page_size); - /* set page status */ - page_status |= (1 << (page + index)); + /* set page status */ + page_status |= (1 << (page + index)); - /* move to next page */ - page_ptr += nand->page_size; - buffer += nand->page_size; - } + /* move to next page */ + page_ptr += nand->page_size; + buffer += nand->page_size; + } - /* write to flash */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - if (page_status & (1 << index)) - NF_WritePage(block, index, page_ptr); + /* write to flash */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + if (page_status & (1 << index)) + NF_WritePage(block, index, page_ptr); - /* move to next page */ - page_ptr += nand->page_size; - } + /* move to next page */ + page_ptr += nand->page_size; + } - return 0; + return 0; } /* nand device write */ -static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, +static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_ubase_t block, page; - rt_uint8_t oob[16]; - struct rt_device_nand *nand; + rt_ubase_t block, page; + rt_uint8_t oob[16]; + struct rt_device_nand *nand; - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; - trace_log("nand write: position %d, block %d, page %d, size %d\n", - pos, block, page, size); + trace_log("nand write: position %d, block %d, page %d, size %d\n", + pos, block, page, size); - if (size == 1) - { - /* write one page */ + if (size == 1) + { + /* write one page */ - /* read oob to get page status */ - NF_ReadPage(block, page, RT_NULL, oob); - if (oob[0]) - NF_WritePage(block, page, buffer); - else - /* erase block and then write page */ - rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); - } - else if (size > 1) - { - rt_ubase_t index; - rt_ubase_t need_erase_block; - const rt_uint8_t *page_ptr; - rt_ubase_t chunk_pages, pages; + /* read oob to get page status */ + NF_ReadPage(block, page, RT_NULL, oob); + if (oob[0]) + NF_WritePage(block, page, buffer); + else + /* erase block and then write page */ + rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); + } + else if (size > 1) + { + rt_ubase_t index; + rt_ubase_t need_erase_block; + const rt_uint8_t *page_ptr; + rt_ubase_t chunk_pages, pages; - pages = size; - page_ptr = (const rt_uint8_t*) buffer; - do - { - need_erase_block = 0; - /* calculate pages in current chunk */ - if (pages > nand->page_per_block - page) - chunk_pages = nand->page_per_block - page; - else - chunk_pages = pages; + pages = size; + page_ptr = (const rt_uint8_t*) buffer; + do + { + need_erase_block = 0; + /* calculate pages in current chunk */ + if (pages > nand->page_per_block - page) + chunk_pages = nand->page_per_block - page; + else + chunk_pages = pages; - /* get page status in current block */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_ReadPage(block, index, RT_NULL, oob); - if (!oob[0]) - { - /* this page has data, need erase this block firstly */ - need_erase_block = 1; - break; - } - } + /* get page status in current block */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_ReadPage(block, index, RT_NULL, oob); + if (!oob[0]) + { + /* this page has data, need erase this block firstly */ + need_erase_block = 1; + break; + } + } - if (need_erase_block) - { - /* erase block and then write it */ - rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); - page_ptr += chunk_pages * nand->page_size; - } - else - { - /* write pages directly */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_WritePage(block, index, page_ptr); - page_ptr += nand->page_size; - } - } + if (need_erase_block) + { + /* erase block and then write it */ + rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); + page_ptr += chunk_pages * nand->page_size; + } + else + { + /* write pages directly */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_WritePage(block, index, page_ptr); + page_ptr += nand->page_size; + } + } - pages -= chunk_pages; - page = 0; block ++; /* move to next block */ - } - while (pages); - } + pages -= chunk_pages; + page = 0; block ++; /* move to next block */ + } + while (pages); + } - return size; + return size; } static rt_err_t rt_nand_control (rt_device_t dev, int cmd, void *args) { - struct rt_device_nand *nand; + struct rt_device_nand *nand; - nand = (struct rt_device_nand*) dev; + nand = (struct rt_device_nand*) dev; RT_ASSERT(dev != RT_NULL); switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - { - struct rt_device_blk_geometry *geometry; + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; - geometry->bytes_per_sector = nand->page_size; - geometry->block_size = nand->page_size * nand->page_per_block; - geometry->sector_count = nand->block_num * nand->page_per_block; - } - break; - } + geometry->bytes_per_sector = nand->page_size; + geometry->block_size = nand->page_size * nand->page_per_block; + geometry->sector_count = nand->block_num * nand->page_per_block; + } + break; + } - return RT_EOK; + return RT_EOK; } void rt_hw_nand_init(void) { - /* initialize nand flash structure */ - _nand.block_num = BLOCK_NUM; - _nand.page_per_block = PAGE_PER_BLOCK; - _nand.page_size = PAGE_SIZE; + /* initialize nand flash structure */ + _nand.block_num = BLOCK_NUM; + _nand.page_per_block = PAGE_PER_BLOCK; + _nand.page_size = PAGE_SIZE; - rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); + rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); - _nand.parent.type = RT_Device_Class_MTD; - _nand.parent.rx_indicate = RT_NULL; - _nand.parent.tx_complete = RT_NULL; - _nand.parent.init = rt_nand_init; - _nand.parent.open = rt_nand_open; - _nand.parent.close = rt_nand_close; - _nand.parent.read = rt_nand_read; - _nand.parent.write = rt_nand_write; - _nand.parent.control = rt_nand_control; + _nand.parent.type = RT_Device_Class_MTD; + _nand.parent.rx_indicate = RT_NULL; + _nand.parent.tx_complete = RT_NULL; + _nand.parent.init = rt_nand_init; + _nand.parent.open = rt_nand_open; + _nand.parent.close = rt_nand_close; + _nand.parent.read = rt_nand_read; + _nand.parent.write = rt_nand_write; + _nand.parent.control = rt_nand_control; - /* register a MTD device */ - rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); + /* register a MTD device */ + rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); } #ifdef NAND_DEBUG @@ -600,68 +596,68 @@ unsigned char nand_oob[16]; void dump_mem(unsigned char* buffer, int length) { - int i; + int i; - if (length > 64) length = 64; - for (i = 0; i < length; i ++) - { - rt_kprintf("%02x ", *buffer++); - if (((i+1) % 16) == 0) - rt_kprintf("\n"); - } - rt_kprintf("\n"); + if (length > 64) length = 64; + for (i = 0; i < length; i ++) + { + rt_kprintf("%02x ", *buffer++); + if (((i+1) % 16) == 0) + rt_kprintf("\n"); + } + rt_kprintf("\n"); } void nand_read(int block, int page) { - rt_kprintf("read block %d, page %d\n", block, page); + rt_kprintf("read block %d, page %d\n", block, page); - NF_ReadPage(block, page, nand_buffer, nand_oob); - rt_kprintf("page data:\n"); - dump_mem(nand_buffer, 512); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, nand_buffer, nand_oob); + rt_kprintf("page data:\n"); + dump_mem(nand_buffer, 512); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); void nand_write(int block, int page) { - int i; - for (i = 0; i < 512; i ++) - nand_buffer[i] = i; + int i; + for (i = 0; i < 512; i ++) + nand_buffer[i] = i; - NF_WritePage(block, page, nand_buffer); + NF_WritePage(block, page, nand_buffer); } FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); void nand_erase(int block) { - NF_EraseBlock(block); + NF_EraseBlock(block); } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); void nand_readoob(int block, int page) { - rt_kprintf("read oob on block %d, page %d\n", block, page); + rt_kprintf("read oob on block %d, page %d\n", block, page); - NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); + NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); } FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); void nand_erase_chip() { - int i; - unsigned char id; - - NF_ReadID(&id); - rt_kprintf("id: %02x\n", id); + int i; + unsigned char id; - for (i = 0; i < 2048; i ++) - { - NF_EraseBlock(i); - } + NF_ReadID(&id); + rt_kprintf("id: %02x\n", id); + + for (i = 0; i < 2048; i ++) + { + NF_EraseBlock(i); + } } FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); #endif diff --git a/bsp/mb9bf506r/drivers/nand.h b/bsp/mb9bf506r/drivers/nand.h index ffb4bae2c3..d00909ddce 100644 --- a/bsp/mb9bf506r/drivers/nand.h +++ b/bsp/mb9bf506r/drivers/nand.h @@ -1,11 +1,7 @@ /* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -33,7 +29,7 @@ #define NF_ALE_OFFSET 0x00003000 #define NF_ADDR_OFFSET 0x00002000 #define NF_CMD_OFFSET 0x00001000 -#define NF_DATA_OFFSET 0x00000000 +#define NF_DATA_OFFSET 0x00000000 /* NAND command */ #define NAND_CMD_READ0 0x00 @@ -47,7 +43,7 @@ #define NAND_CMD_READID1 0x91 #define NAND_CMD_ERASE2 0xd0 #define NAND_CMD_RESET 0xff - + #define FLASH_OK 0 #define FLASH_NG 1