libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

QEMU support, and code optimization for thead extension

This commit is contained in:
wormsX 2021-08-16 16:07:57 +08:00
parent f60514cd71
commit 360223a693
11 changed files with 58 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
bsp/thead-smart/README.md
View File

@ -3,7 +3,7 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im
## The main resources on board are as follows:
1. SMART-EVB for E906/E906F/E906FD
1. SMART-EVB for T-Head CPU E9xx Series
| res | description |
| -- | -- |
@ -25,15 +25,21 @@ SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide im
# Compile T-HEAD BSP
SMART-EVB BSP supports GCC compiler, the version information is:
1. SMART-EVB for E906/E906F/E906FD
1. SMART-EVB for E906/7/F/D/P
| IDE/Compiler| version|
| - | - |
| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) |
2. select cpu in rtconfig.py
3. scons -c; scons
# run smart-evb bsp
# Quick start with qemu
1. download qemu
wget https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource/1356021/1612269502091/csky-qemu-x86_64-Ubuntu-16.04-20210202-1445.tar.gz
2. qemu run
qemu-system-riscv32 -cpu e906fdp -M smartl -kernel rtthread-e9xx.elf -nographic
# Quick start with smart-evb
1. Connect JTAG
2. Connect the serial port
3. riscv64-unknown-elf-gdb rtthread-e906f.elf

2
bsp/thead-smart/drivers/board.c
View File

@ -23,7 +23,7 @@ extern int __bss_end__;
extern usart_handle_t console_handle;
extern void ioreuse_initial(void);
extern int rt_hw_usart_init(void);
/**
* This function will initial smart-evb board.

7
bsp/thead-smart/drivers/csi_config.h
View File

@ -13,12 +13,7 @@
#ifndef __CSI_CONFIG_H
#define __CSI_CONFIG_H
#define CONFIG_ARCH_RV32 1
#define CONFIG_CPU_E906FD 1
#define CONFIG_RV32_CORETIM 1
#define CONFIG_CHIP_SMARTL_RV32 1
#define CONFIG_BOARD_SMARTL_E906_EVB 1
#define CONFIG_BOARD_NAME_STR "smartl_e906_evb"
#define CONFIG_BOARD_NAME_STR "smart_e906_evb"
#define CONFIG_SUPPORT_TSPEND 1
#define CONFIG_ARCH_INTERRUPTSTACK 4096
#define CONFIG_NEWLIB_WRAP 1

3
bsp/thead-smart/drivers/system.c
View File

@ -65,7 +65,10 @@ void systemmap_config(void)
void SystemInit(void)
{
int i;
#if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1))
systemmap_config();
#endif
/* enable mstatus FS */
#if (__riscv_flen)
uint32_t mstatus = __get_MSTATUS();

3
bsp/thead-smart/gdbinit
View File

@ -6,6 +6,9 @@ set *(int *)0x40011008=0x0
set *(int *)0x4001101c=0x0
set disassemble-next-line on
show disassemble-next-line
hb Default_Handler
lo
c

14
bsp/thead-smart/rtconfig.h
View File

@ -38,20 +38,6 @@
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40003
#define ARCH_RISCV
#define ARCH_RISCV32
#if(__riscv_flen == 64)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_D
#elif(__riscv_flen == 32)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#else
#endif
#ifdef __riscv_zp64
#define ARCH_RISCV_DSP
#endif
/* RT-Thread Components */

6
bsp/thead-smart/rtconfig.py
View File

@ -67,11 +67,5 @@ if PLATFORM == 'gcc':
CXXFLAGS = CFLAGS
# M_CFLAGS = DEVICE + ' -EL -G0 -O2 -mno-abicalls -fno-common -fno-exceptions -fno-omit-frame-pointer -mlong-calls -fno-pic '
# M_CXXFLAGS = M_CFLAGS
# M_LFLAGS = DEVICE + ' -EL -r -Wl,--gc-sections,-z,max-page-size=0x4' +\
# ' -nostartfiles -static-libgcc'
# M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

24
bsp/thead-smart/theadconfig.h Normal file
View File

@ -0,0 +1,24 @@
#ifndef THEAD_CONFIG_H__
#define THAED_CONFIG_H__
#define ARCH_RISCV
#define ARCH_RISCV32
#if(__riscv_flen == 64)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_D
#elif(__riscv_flen == 32)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#else
#endif
#ifdef __riscv_zp64
#define ARCH_RISCV_DSP
#endif
#ifdef __riscv_xthead
#ifdef __riscv_xtheade
#define CONFIG_THEAD_EXT_SPUSHEN
#endif
#endif
#endif

26
libcpu/risc-v/t-head/e9xx/context_gcc.S
View File

@ -1,11 +1,13 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2021, Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting implementation
* 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.
*/
#include "cpuport.h"
@ -29,8 +31,6 @@ vPortYield:
ret
/*
* #ifdef RT_USING_SMP
* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
@ -56,12 +56,10 @@ rt_hw_context_switch_to:
li t1, 1
STORE t1, (t0)
/* enable mexstatus SPUSHEN and SPSWAPEN */
#if ((CONFIG_CPU_E906==1) || (CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
uint32_t mexstatus;
mexstatus = __get_MEXSTATUS();
mexstatus |= (0x2 << 16);
__set_MEXSTATUS(mexstatus);
/* enable mexstatus SPUSHEN */
#ifdef CONFIG_THEAD_EXT_SPUSHEN
li t0, 0x10000
csrs mexstatus, t0
#endif
csrw mscratch, sp
@ -140,7 +138,7 @@ PendSV_Handler:
lw t1, (t0)
beqz t1, .switch_to_thead
/* save from thread context */
/* restore from thread context t0,t1 */
lw t0, (-4)(sp)
lw t1, (-8)(sp)
@ -191,10 +189,6 @@ PendSV_Handler:
csrr x1, mepc
STORE x1, 0 * REGBYTES(sp)
csrr x1, mstatus
andi x1, x1, 8
beqz x1, .save_mpie
li x1, 0x80
.save_mpie:
STORE x1, 2 * REGBYTES(sp)
/* x3 don't need save */
STORE x4, 4 * REGBYTES(sp)
@ -256,11 +250,9 @@ PendSV_Handler:
csrw mepc, a1
LOAD x1, 1 * REGBYTES(sp)
/* force to machin mode(MPP=11) */
li a1, 0x1880
csrs mstatus, a1
/* force to machine mode(MPP=11) */
LOAD a1, 2 * REGBYTES(sp)
csrs mstatus, a1
csrw mstatus, a1
/* x3 don't need restore */
LOAD x4, 4 * REGBYTES(sp)
LOAD x5, 5 * REGBYTES(sp)

9
libcpu/risc-v/t-head/e9xx/cpuport.c
View File

@ -1,11 +1,13 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2021, Alibaba Group Holding Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/08/20 zx.chen The T-HEAD RISC-V CPU E906 porting code.
* 2021/08/13 zx.chen update T-HEAD E9xx-series(E906/7/F/D/P) CPU porting code.
*/
#include <rthw.h>
@ -143,8 +145,8 @@ rt_uint8_t *rt_hw_stack_init(void *tentry,
rt_base_t rt_hw_interrupt_disable(void)
{
__asm volatile("csrc mstatus, 8");
return 0;
__asm volatile("csrrci a0, mstatus, 8");
return;
}
/**
@ -154,9 +156,10 @@ rt_base_t rt_hw_interrupt_disable(void)
*
* @return none
*/
/* XXX:rename rt_hw_interrupt_restore? */
void rt_hw_interrupt_enable(rt_base_t level)
{
__asm volatile("csrs mstatus, 8");
__asm volatile("csrw mstatus, a0");
}
/** shutdown CPU */

1
libcpu/risc-v/t-head/e9xx/cpuport.h
View File

@ -12,6 +12,7 @@
#define CPUPORT_H__
#include <rtconfig.h>
#include <theadconfig.h>
/* bytes of register width */
#ifdef ARCH_RISCV_64