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fix formmating issue

This commit is contained in:
yandld 2024-08-26 11:40:35 +08:00 committed by Meco Man
parent 0179d7427a
commit 32635bb53a
3 changed files with 19 additions and 19 deletions
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6
bsp/nxp/mcx/mcxn/Libraries/drivers/drv_can.c
View File

@ -75,7 +75,7 @@ static void flexcan_callback(CAN_Type *base, flexcan_handle_t *handle, status_t
flexcan_mb_transfer_t rxXfer;
can = (struct imxrt_can *)userData;
switch (status)
{
case kStatus_FLEXCAN_RxIdle:
@ -107,7 +107,7 @@ static rt_err_t can_cfg(struct rt_can_device *can_dev, struct can_configure *cfg
config.baudRate = cfg->baud_rate;
config.enableIndividMask = true; /* one filter per MB */
config.disableSelfReception = true;
switch (cfg->mode)
{
case RT_CAN_MODE_NORMAL:
@ -328,7 +328,7 @@ static rt_ssize_t can_send(struct rt_can_device *can_dev, const void *buf, rt_ui
can = (struct imxrt_can *)can_dev->parent.user_data;
msg = (struct rt_can_msg *) buf;
RT_ASSERT(can != RT_NULL);
RT_ASSERT(msg != RT_NULL);

28
bsp/nxp/mcx/mcxn/Libraries/drivers/drv_wdt.c
View File

@ -31,15 +31,15 @@ static struct mcx_wdt wdt_dev;
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
uint32_t wdtFreq;
wwdt_config_t config;
/* The WDT divides the input frequency into it by 4 */
wdtFreq = WDT_CLK_FREQ / 4;
/* Enable FRO 1M clock for WWDT module. */
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
WWDT_GetDefaultConfig(&config);
config.timeoutValue = wdtFreq * 1;
@ -47,15 +47,15 @@ static rt_err_t wdt_init(rt_watchdog_t *wdt)
/* Configure WWDT to reset on timeout */
config.enableWatchdogReset = true;
/* Setup watchdog clock frequency(Hz). */
config.clockFreq_Hz = WDT_CLK_FREQ;
CLOCK_EnableClock(wdt_dev.clock_ip_name);
CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1U);
WWDT_Init(wdt_dev.wdt_base, &config);
return RT_EOK;
}
@ -66,15 +66,15 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
case RT_DEVICE_CTRL_WDT_START:
WWDT_Enable(wdt_dev.wdt_base);
return RT_EOK;
case RT_DEVICE_CTRL_WDT_STOP:
WWDT_Disable(wdt_dev.wdt_base);
return RT_EOK;
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
WWDT_Refresh(wdt_dev.wdt_base);
return RT_EOK;
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
if (arg != RT_NULL)
{
@ -84,7 +84,7 @@ static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
return RT_EOK;
}
return -RT_ERROR;
default:
return -RT_ERROR;
}
@ -101,15 +101,15 @@ int rt_hw_wdt_init(void)
wdt_dev.wdt_base = WWDT0;
wdt_dev.clock_src = kCLOCK_Clk1M;
wdt_dev.clock_ip_name = kCLOCK_Wwdt0;
wdt_dev.watchdog.ops = &wdt_ops;
if (rt_hw_watchdog_register(&wdt_dev.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
rt_kprintf("wdt register failed\n");
return -RT_ERROR;
}
return RT_EOK;
}

4
bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.c
View File

@ -125,12 +125,12 @@ void BOARD_InitBootPins(void)
PORT4->PCR[21] = PORT_PCR_MUX(FLEXIO_DATA13_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D13 */
PORT4->PCR[22] = PORT_PCR_MUX(FLEXIO_DATA14_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D14 */
PORT4->PCR[23] = PORT_PCR_MUX(FLEXIO_DATA15_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D15 */
#ifdef BSP_USING_CAN1
PORT4->PCR[15] = PORT_PCR_MUX(11) | PORT_PCR_IBE(1); /* CAN1_RXD */
PORT4->PCR[16] = PORT_PCR_MUX(11) | PORT_PCR_IBE(1); /* CAN1_TXD */
#endif
}