From 228a6be077a2e2f40e9cbc6f23ed232a8371e7d0 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Sat, 1 Jun 2013 02:16:10 +0800 Subject: [PATCH 1/5] cortex-r4: add __rt_ffs --- bsp/rm48x50/rtconfig.h | 1 + libcpu/arm/cortex-r4/cpu.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/bsp/rm48x50/rtconfig.h b/bsp/rm48x50/rtconfig.h index 86fc630c8c..d681ef736e 100644 --- a/bsp/rm48x50/rtconfig.h +++ b/bsp/rm48x50/rtconfig.h @@ -212,6 +212,7 @@ // #define RT_VFP_LAZY_STACKING +#define RT_USING_CPU_FFS // #endif diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index 569f7d0c29..3aa7cd35de 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -39,4 +39,17 @@ void rt_hw_cpu_shutdown() while (1); } +#ifdef RT_USING_CPU_FFS +int __rt_ffs(int value) +{ + if (value == 0) + return value; + + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); +} +#endif + /*@}*/ From e8bbbe67886f28db5600e6e5029cd24a48925e50 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Fri, 31 May 2013 22:43:53 +0800 Subject: [PATCH 2/5] cortex-r4: wrap asm functions with .asmfunc/.endasmfunc --- libcpu/arm/cortex-r4/context_ccs.asm | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/libcpu/arm/cortex-r4/context_ccs.asm b/libcpu/arm/cortex-r4/context_ccs.asm index dc4113f5e4..2b459f8238 100644 --- a/libcpu/arm/cortex-r4/context_ccs.asm +++ b/libcpu/arm/cortex-r4/context_ccs.asm @@ -28,18 +28,22 @@ ; * rt_base_t rt_hw_interrupt_disable(); ; */ .def rt_hw_interrupt_disable + .asmfunc rt_hw_interrupt_disable MRS r0, cpsr CPSID IF BX lr + .endasmfunc ;/* ; * void rt_hw_interrupt_enable(rt_base_t level); ; */ .def rt_hw_interrupt_enable + .asmfunc rt_hw_interrupt_enable MSR cpsr_c, r0 BX lr + .endasmfunc ;/* ; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); @@ -47,6 +51,7 @@ rt_hw_interrupt_enable ; * r1 --> to ; */ .def rt_hw_context_switch + .asmfunc rt_hw_context_switch STMDB sp!, {lr} ; push pc (lr should be pushed in place of PC) STMDB sp!, {r0-r12, lr} ; push lr & register file @@ -88,12 +93,14 @@ __no_vfp_frame2 MSR spsr_cxsf, r4 LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr + .endasmfunc ;/* ; * void rt_hw_context_switch_to(rt_uint32 to); ; * r0 --> to ; */ .def rt_hw_context_switch_to + .asmfunc rt_hw_context_switch_to LDR sp, [r0] ; get new task stack pointer @@ -112,12 +119,14 @@ __no_vfp_frame_to MSR spsr_cxsf, r4 LDMIA sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr + .endasmfunc ;/* ; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); ; */ .def rt_hw_context_switch_interrupt + .asmfunc rt_hw_context_switch_interrupt LDR r2, pintflag LDR r3, [r2] @@ -131,6 +140,7 @@ _reswitch LDR r2, ptothread ; set rt_interrupt_to_thread STR r1, [r2] BX lr + .endasmfunc .def IRQ_Handler IRQ_Handler From 9b949c28b7267ab46cb43abb427309770e64bf84 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Thu, 6 Jun 2013 15:14:34 +0800 Subject: [PATCH 3/5] rm48x50: add cache_{enable, disable} --- libcpu/arm/cortex-r4/cpu.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index 3aa7cd35de..d1b5c9df54 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -52,4 +52,43 @@ int __rt_ffs(int value) } #endif +#ifdef __TI_COMPILER_VERSION__ +void rt_hw_cpu_icache_enable() +{ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable"); + __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache"); + __asm(" ISB"); +} + +void rt_hw_cpu_icache_disable() +{ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache"); + __asm(" ISB"); +} + +void rt_hw_cpu_dcache_enable() +{ + __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" ORR R1, R1, #0x1 <<2"); + __asm(" DSB"); + __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache"); + __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache"); +} + +void rt_hw_cpu_dcache_disable() +{ + /* FIXME: Clean entire data cache. This routine depends on the data cache + * size. It can be omitted if it is known that the data cache has no dirty + * data. */ + __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"); + __asm(" BIC r1, r1, #0x1 <<2"); + __asm(" DSB"); + __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"); +} + +#endif /*@}*/ From 2df7fc310f29927d0184947c07deab0030bc880e Mon Sep 17 00:00:00 2001 From: Grissiom Date: Wed, 12 Jun 2013 23:48:29 +0800 Subject: [PATCH 4/5] RM48 does not have cache implemented --- bsp/rm48x50/application/startup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bsp/rm48x50/application/startup.c b/bsp/rm48x50/application/startup.c index 72d4ed795b..4b68910259 100644 --- a/bsp/rm48x50/application/startup.c +++ b/bsp/rm48x50/application/startup.c @@ -48,6 +48,11 @@ extern unsigned char * const system_data_end; */ void rtthread_startup(void) { + /*// RM48 does not have cache implemented + *rt_hw_cpu_icache_enable(); + *rt_hw_cpu_dcache_enable(); + */ + /* init hardware interrupt */ rt_hw_interrupt_init(); From 009239ceeddcdbd4ce5ad573784143df1f485ee8 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Wed, 12 Jun 2013 23:56:10 +0800 Subject: [PATCH 5/5] rm48x50: rt_interrupt_nest should be `volatile rt_uint8_t` --- libcpu/arm/cortex-r4/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 8d0a977db9..d001b509ee 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -22,7 +22,7 @@ /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; -extern rt_uint32_t rt_interrupt_nest; +extern volatile rt_uint8_t rt_interrupt_nest; /* exception and interrupt handler table */ rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;