[BSP][stm32f103-100ask-pro]add ext_sram driver to stm32f103-100ask-pro
This commit is contained in:
WKJay
Rbb666
parent
07d7b71345
commit
2fd9ff56dc
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@ -45,6 +45,7 @@ STM32F103 Pro开发板是百问网推出的一块基于ARM Cortex-M3内核的开
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| 电位器 | 支持 | ADC1/2/3 CH10 |
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| SPI FLASH | 支持 | W25Q64 |
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| EEPROM | 支持 | 软件i2c1 |
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| SRAM | 支持 | IS62WV51216BLL |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
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| UART | 支持 | UART1/2/3 |
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File diff suppressed because one or more lines are too long
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@ -19,6 +19,12 @@ CAN.CalculateBaudRate=749999
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CAN.CalculateTimeBit=1333
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CAN.CalculateTimeQuantum=444.44444444444446
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CAN.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate
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FSMC.AddressSetupTime1=0
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FSMC.BusTurnAroundDuration1=0
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FSMC.DataSetupTime1=3
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FSMC.ExtendedMode1=FSMC_EXTENDED_MODE_DISABLE
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FSMC.IPParameters=WriteOperation1,ExtendedMode1,AddressSetupTime1,BusTurnAroundDuration1,DataSetupTime1
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FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
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File.Version=6
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GPIO.groupedBy=Group By Peripherals
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KeepUserPlacement=false
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@ -26,79 +32,120 @@ Mcu.CPN=STM32F103ZET6
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Mcu.Family=STM32F1
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Mcu.IP0=ADC1
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Mcu.IP1=ADC2
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Mcu.IP10=SPI2
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Mcu.IP11=SYS
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Mcu.IP12=TIM2
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Mcu.IP13=TIM3
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Mcu.IP14=TIM4
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Mcu.IP15=USART1
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Mcu.IP16=USART2
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Mcu.IP17=USART3
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Mcu.IP10=SPI1
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Mcu.IP11=SPI2
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Mcu.IP12=SYS
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Mcu.IP13=TIM2
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Mcu.IP14=TIM3
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Mcu.IP15=TIM4
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Mcu.IP16=USART1
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Mcu.IP17=USART2
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Mcu.IP18=USART3
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Mcu.IP2=ADC3
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Mcu.IP3=CAN
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Mcu.IP4=I2C1
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Mcu.IP5=NVIC
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Mcu.IP6=RCC
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Mcu.IP7=RTC
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Mcu.IP8=SDIO
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Mcu.IP9=SPI1
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Mcu.IPNb=18
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Mcu.IP4=FSMC
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Mcu.IP5=I2C1
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Mcu.IP6=NVIC
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Mcu.IP7=RCC
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Mcu.IP8=RTC
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Mcu.IP9=SDIO
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Mcu.IPNb=19
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Mcu.Name=STM32F103Z(C-D-E)Tx
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Mcu.Package=LQFP144
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Mcu.Pin0=PC14-OSC32_IN
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Mcu.Pin1=PC15-OSC32_OUT
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Mcu.Pin10=PB0
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Mcu.Pin11=PB1
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Mcu.Pin12=PB10
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Mcu.Pin13=PB11
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Mcu.Pin14=PB13
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Mcu.Pin15=PB14
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Mcu.Pin16=PB15
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Mcu.Pin17=PC8
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Mcu.Pin18=PC9
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Mcu.Pin19=PA9
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Mcu.Pin2=OSC_IN
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Mcu.Pin20=PA10
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Mcu.Pin21=PA13
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Mcu.Pin22=PA14
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Mcu.Pin23=PC10
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Mcu.Pin24=PC11
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Mcu.Pin25=PC12
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Mcu.Pin26=PD2
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Mcu.Pin27=PB5
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Mcu.Pin28=PB6
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Mcu.Pin29=PB7
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Mcu.Pin3=OSC_OUT
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Mcu.Pin30=PB8
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Mcu.Pin31=PB9
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Mcu.Pin32=VP_RTC_VS_RTC_Activate
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Mcu.Pin33=VP_SYS_VS_Systick
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Mcu.Pin34=VP_TIM2_VS_ClockSourceINT
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Mcu.Pin35=VP_TIM3_VS_ClockSourceINT
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Mcu.Pin36=VP_TIM4_VS_ClockSourceINT
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Mcu.Pin4=PC0
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Mcu.Pin5=PA2
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Mcu.Pin6=PA3
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Mcu.Pin7=PA5
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Mcu.Pin8=PA6
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Mcu.Pin9=PA7
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Mcu.PinsNb=37
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Mcu.Pin10=PC0
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Mcu.Pin11=PA2
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Mcu.Pin12=PA3
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Mcu.Pin13=PA5
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Mcu.Pin14=PA6
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Mcu.Pin15=PA7
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Mcu.Pin16=PB0
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Mcu.Pin17=PB1
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Mcu.Pin18=PF12
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Mcu.Pin19=PF13
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Mcu.Pin2=PF0
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Mcu.Pin20=PF14
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Mcu.Pin21=PF15
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Mcu.Pin22=PG0
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Mcu.Pin23=PG1
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Mcu.Pin24=PE7
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Mcu.Pin25=PE8
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Mcu.Pin26=PE9
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Mcu.Pin27=PE10
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Mcu.Pin28=PE11
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Mcu.Pin29=PE12
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Mcu.Pin3=PF1
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Mcu.Pin30=PE13
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Mcu.Pin31=PE14
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Mcu.Pin32=PE15
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Mcu.Pin33=PB10
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Mcu.Pin34=PB11
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Mcu.Pin35=PB13
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Mcu.Pin36=PB14
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Mcu.Pin37=PB15
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Mcu.Pin38=PD8
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Mcu.Pin39=PD9
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Mcu.Pin4=PF2
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Mcu.Pin40=PD10
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Mcu.Pin41=PD11
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Mcu.Pin42=PD12
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Mcu.Pin43=PD13
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Mcu.Pin44=PD14
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Mcu.Pin45=PD15
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Mcu.Pin46=PG2
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Mcu.Pin47=PG3
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Mcu.Pin48=PG4
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Mcu.Pin49=PG5
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Mcu.Pin5=PF3
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Mcu.Pin50=PC8
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Mcu.Pin51=PC9
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Mcu.Pin52=PA9
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Mcu.Pin53=PA10
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Mcu.Pin54=PA13
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Mcu.Pin55=PA14
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Mcu.Pin56=PC10
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Mcu.Pin57=PC11
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Mcu.Pin58=PC12
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Mcu.Pin59=PD0
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Mcu.Pin6=PF4
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Mcu.Pin60=PD1
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Mcu.Pin61=PD2
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Mcu.Pin62=PD4
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Mcu.Pin63=PD5
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Mcu.Pin64=PG10
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Mcu.Pin65=PB5
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Mcu.Pin66=PB6
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Mcu.Pin67=PB7
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Mcu.Pin68=PB8
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Mcu.Pin69=PB9
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Mcu.Pin7=PF5
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Mcu.Pin70=PE0
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Mcu.Pin71=PE1
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Mcu.Pin72=VP_RTC_VS_RTC_Activate
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Mcu.Pin73=VP_SYS_VS_Systick
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Mcu.Pin74=VP_TIM2_VS_ClockSourceINT
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Mcu.Pin75=VP_TIM3_VS_ClockSourceINT
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Mcu.Pin76=VP_TIM4_VS_ClockSourceINT
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Mcu.Pin8=OSC_IN
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Mcu.Pin9=OSC_OUT
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Mcu.PinsNb=77
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Mcu.ThirdPartyNb=0
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Mcu.UserConstants=
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Mcu.UserName=STM32F103ZETx
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MxCube.Version=6.5.0
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MxDb.Version=DB.6.0.50
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.ForceEnableDMAVector=true
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
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NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
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NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
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NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
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NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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OSC_IN.Mode=HSE-External-Oscillator
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OSC_IN.Signal=RCC_OSC_IN
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OSC_OUT.Mode=HSE-External-Oscillator
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@ -163,8 +210,49 @@ PC8.Mode=SD_4_bits_Wide_bus
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PC8.Signal=SDIO_D0
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PC9.Mode=SD_4_bits_Wide_bus
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PC9.Signal=SDIO_D1
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PD0.Signal=FSMC_D2_DA2
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PD1.Signal=FSMC_D3_DA3
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PD10.Signal=FSMC_D15_DA15
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PD11.Signal=FSMC_A16_CLE
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PD12.Signal=FSMC_A17_ALE
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PD13.Signal=FSMC_A18
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PD14.Signal=FSMC_D0_DA0
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PD15.Signal=FSMC_D1_DA1
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PD2.Mode=SD_4_bits_Wide_bus
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PD2.Signal=SDIO_CMD
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PD4.Signal=FSMC_NOE
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PD5.Signal=FSMC_NWE
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PD8.Signal=FSMC_D13_DA13
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PD9.Signal=FSMC_D14_DA14
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PE0.Signal=FSMC_NBL0
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PE1.Signal=FSMC_NBL1
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PE10.Signal=FSMC_D7_DA7
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PE11.Signal=FSMC_D8_DA8
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PE12.Signal=FSMC_D9_DA9
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PE13.Signal=FSMC_D10_DA10
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PE14.Signal=FSMC_D11_DA11
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PE15.Signal=FSMC_D12_DA12
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PE7.Signal=FSMC_D4_DA4
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PE8.Signal=FSMC_D5_DA5
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PE9.Signal=FSMC_D6_DA6
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PF0.Signal=FSMC_A0
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PF1.Signal=FSMC_A1
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PF12.Signal=FSMC_A6
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PF13.Signal=FSMC_A7
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PF14.Signal=FSMC_A8
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PF15.Signal=FSMC_A9
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PF2.Signal=FSMC_A2
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PF3.Signal=FSMC_A3
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PF4.Signal=FSMC_A4
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PF5.Signal=FSMC_A5
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PG0.Signal=FSMC_A10
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PG1.Signal=FSMC_A11
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PG10.Mode=NorPsramChipSelect3_1
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PG10.Signal=FSMC_NE3
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PG2.Signal=FSMC_A12
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PG3.Signal=FSMC_A13
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PG4.Signal=FSMC_A14
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PG5.Signal=FSMC_A15
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PinOutPanel.RotationAngle=0
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ProjectManager.AskForMigrate=true
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ProjectManager.BackupPrevious=false
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@ -193,7 +281,7 @@ ProjectManager.StackSize=0x400
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ProjectManager.TargetToolchain=MDK-ARM V5
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ProjectManager.ToolChainLocation=
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ProjectManager.UnderRoot=false
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN_Init-CAN-false-HAL-true,5-MX_I2C1_Init-I2C1-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_SPI2_Init-SPI2-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USART2_UART_Init-USART2-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_CAN_Init-CAN-false-HAL-true,5-MX_I2C1_Init-I2C1-false-HAL-true,6-MX_SDIO_SD_Init-SDIO-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_SPI2_Init-SPI2-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_USART2_UART_Init-USART2-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true,12-MX_ADC2_Init-ADC2-false-HAL-true,13-MX_ADC3_Init-ADC3-false-HAL-true,14-MX_RTC_Init-RTC-false-HAL-true,15-MX_TIM2_Init-TIM2-false-HAL-true,16-MX_TIM3_Init-TIM3-false-HAL-true,17-MX_TIM4_Init-TIM4-false-HAL-true
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RCC.ADCFreqValue=12000000
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RCC.ADCPresc=RCC_ADCPCLK2_DIV6
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RCC.AHBFreq_Value=72000000
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@ -227,6 +315,84 @@ SH.ADCx_IN10.0=ADC1_IN10,IN10
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SH.ADCx_IN10.1=ADC2_IN10,IN10
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SH.ADCx_IN10.2=ADC3_IN10,IN10
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SH.ADCx_IN10.ConfNb=3
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SH.FSMC_A0.0=FSMC_A0,19b-a1
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SH.FSMC_A0.ConfNb=1
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SH.FSMC_A1.0=FSMC_A1,19b-a1
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SH.FSMC_A1.ConfNb=1
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SH.FSMC_A10.0=FSMC_A10,19b-a1
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SH.FSMC_A10.ConfNb=1
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SH.FSMC_A11.0=FSMC_A11,19b-a1
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SH.FSMC_A11.ConfNb=1
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SH.FSMC_A12.0=FSMC_A12,19b-a1
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SH.FSMC_A12.ConfNb=1
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SH.FSMC_A13.0=FSMC_A13,19b-a1
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SH.FSMC_A13.ConfNb=1
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SH.FSMC_A14.0=FSMC_A14,19b-a1
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SH.FSMC_A14.ConfNb=1
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SH.FSMC_A15.0=FSMC_A15,19b-a1
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SH.FSMC_A15.ConfNb=1
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SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1
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SH.FSMC_A16_CLE.ConfNb=1
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SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1
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SH.FSMC_A17_ALE.ConfNb=1
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SH.FSMC_A18.0=FSMC_A18,19b-a1
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SH.FSMC_A18.ConfNb=1
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SH.FSMC_A2.0=FSMC_A2,19b-a1
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SH.FSMC_A2.ConfNb=1
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SH.FSMC_A3.0=FSMC_A3,19b-a1
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SH.FSMC_A3.ConfNb=1
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SH.FSMC_A4.0=FSMC_A4,19b-a1
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SH.FSMC_A4.ConfNb=1
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SH.FSMC_A5.0=FSMC_A5,19b-a1
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SH.FSMC_A5.ConfNb=1
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SH.FSMC_A6.0=FSMC_A6,19b-a1
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SH.FSMC_A6.ConfNb=1
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SH.FSMC_A7.0=FSMC_A7,19b-a1
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SH.FSMC_A7.ConfNb=1
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SH.FSMC_A8.0=FSMC_A8,19b-a1
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SH.FSMC_A8.ConfNb=1
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SH.FSMC_A9.0=FSMC_A9,19b-a1
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SH.FSMC_A9.ConfNb=1
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SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1
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SH.FSMC_D0_DA0.ConfNb=1
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SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1
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SH.FSMC_D10_DA10.ConfNb=1
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SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1
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SH.FSMC_D11_DA11.ConfNb=1
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SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1
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SH.FSMC_D12_DA12.ConfNb=1
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SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1
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SH.FSMC_D13_DA13.ConfNb=1
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SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1
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SH.FSMC_D14_DA14.ConfNb=1
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SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1
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SH.FSMC_D15_DA15.ConfNb=1
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SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1
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SH.FSMC_D1_DA1.ConfNb=1
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SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1
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SH.FSMC_D2_DA2.ConfNb=1
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SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1
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SH.FSMC_D3_DA3.ConfNb=1
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SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1
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SH.FSMC_D4_DA4.ConfNb=1
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SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1
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SH.FSMC_D5_DA5.ConfNb=1
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SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1
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SH.FSMC_D6_DA6.ConfNb=1
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SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1
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SH.FSMC_D7_DA7.ConfNb=1
|
||||
SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1
|
||||
SH.FSMC_D8_DA8.ConfNb=1
|
||||
SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1
|
||||
SH.FSMC_D9_DA9.ConfNb=1
|
||||
SH.FSMC_NBL0.0=FSMC_NBL0,2ByteEnable1
|
||||
SH.FSMC_NBL0.ConfNb=1
|
||||
SH.FSMC_NBL1.0=FSMC_NBL1,2ByteEnable1
|
||||
SH.FSMC_NBL1.ConfNb=1
|
||||
SH.FSMC_NOE.0=FSMC_NOE,Sram1
|
||||
SH.FSMC_NOE.ConfNb=1
|
||||
SH.FSMC_NWE.0=FSMC_NWE,Sram1
|
||||
SH.FSMC_NWE.ConfNb=1
|
||||
SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2
|
||||
SH.S_TIM3_CH2.ConfNb=1
|
||||
SH.S_TIM3_CH3.0=TIM3_CH3,PWM Generation3 CH3
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@
|
|||
/*#define HAL_SDRAM_MODULE_ENABLED */
|
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
/*#define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/*#define HAL_USART_MODULE_ENABLED */
|
||||
|
|
|
|||
|
|
@ -870,6 +870,190 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
|
|||
|
||||
}
|
||||
|
||||
static uint32_t FSMC_Initialized = 0;
|
||||
|
||||
static void HAL_FSMC_MspInit(void){
|
||||
/* USER CODE BEGIN FSMC_MspInit 0 */
|
||||
|
||||
/* USER CODE END FSMC_MspInit 0 */
|
||||
GPIO_InitTypeDef GPIO_InitStruct ={0};
|
||||
if (FSMC_Initialized) {
|
||||
return;
|
||||
}
|
||||
FSMC_Initialized = 1;
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_FSMC_CLK_ENABLE();
|
||||
|
||||
/** FSMC GPIO Configuration
|
||||
PF0 ------> FSMC_A0
|
||||
PF1 ------> FSMC_A1
|
||||
PF2 ------> FSMC_A2
|
||||
PF3 ------> FSMC_A3
|
||||
PF4 ------> FSMC_A4
|
||||
PF5 ------> FSMC_A5
|
||||
PF12 ------> FSMC_A6
|
||||
PF13 ------> FSMC_A7
|
||||
PF14 ------> FSMC_A8
|
||||
PF15 ------> FSMC_A9
|
||||
PG0 ------> FSMC_A10
|
||||
PG1 ------> FSMC_A11
|
||||
PE7 ------> FSMC_D4
|
||||
PE8 ------> FSMC_D5
|
||||
PE9 ------> FSMC_D6
|
||||
PE10 ------> FSMC_D7
|
||||
PE11 ------> FSMC_D8
|
||||
PE12 ------> FSMC_D9
|
||||
PE13 ------> FSMC_D10
|
||||
PE14 ------> FSMC_D11
|
||||
PE15 ------> FSMC_D12
|
||||
PD8 ------> FSMC_D13
|
||||
PD9 ------> FSMC_D14
|
||||
PD10 ------> FSMC_D15
|
||||
PD11 ------> FSMC_A16
|
||||
PD12 ------> FSMC_A17
|
||||
PD13 ------> FSMC_A18
|
||||
PD14 ------> FSMC_D0
|
||||
PD15 ------> FSMC_D1
|
||||
PG2 ------> FSMC_A12
|
||||
PG3 ------> FSMC_A13
|
||||
PG4 ------> FSMC_A14
|
||||
PG5 ------> FSMC_A15
|
||||
PD0 ------> FSMC_D2
|
||||
PD1 ------> FSMC_D3
|
||||
PD4 ------> FSMC_NOE
|
||||
PD5 ------> FSMC_NWE
|
||||
PG10 ------> FSMC_NE3
|
||||
PE0 ------> FSMC_NBL0
|
||||
PE1 ------> FSMC_NBL1
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
|
||||
|GPIO_PIN_14|GPIO_PIN_15;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|
||||
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|
||||
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|
||||
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
|
||||
|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN FSMC_MspInit 1 */
|
||||
|
||||
/* USER CODE END FSMC_MspInit 1 */
|
||||
}
|
||||
|
||||
void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
|
||||
/* USER CODE BEGIN SRAM_MspInit 0 */
|
||||
|
||||
/* USER CODE END SRAM_MspInit 0 */
|
||||
HAL_FSMC_MspInit();
|
||||
/* USER CODE BEGIN SRAM_MspInit 1 */
|
||||
|
||||
/* USER CODE END SRAM_MspInit 1 */
|
||||
}
|
||||
|
||||
static uint32_t FSMC_DeInitialized = 0;
|
||||
|
||||
static void HAL_FSMC_MspDeInit(void){
|
||||
/* USER CODE BEGIN FSMC_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END FSMC_MspDeInit 0 */
|
||||
if (FSMC_DeInitialized) {
|
||||
return;
|
||||
}
|
||||
FSMC_DeInitialized = 1;
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_FSMC_CLK_DISABLE();
|
||||
|
||||
/** FSMC GPIO Configuration
|
||||
PF0 ------> FSMC_A0
|
||||
PF1 ------> FSMC_A1
|
||||
PF2 ------> FSMC_A2
|
||||
PF3 ------> FSMC_A3
|
||||
PF4 ------> FSMC_A4
|
||||
PF5 ------> FSMC_A5
|
||||
PF12 ------> FSMC_A6
|
||||
PF13 ------> FSMC_A7
|
||||
PF14 ------> FSMC_A8
|
||||
PF15 ------> FSMC_A9
|
||||
PG0 ------> FSMC_A10
|
||||
PG1 ------> FSMC_A11
|
||||
PE7 ------> FSMC_D4
|
||||
PE8 ------> FSMC_D5
|
||||
PE9 ------> FSMC_D6
|
||||
PE10 ------> FSMC_D7
|
||||
PE11 ------> FSMC_D8
|
||||
PE12 ------> FSMC_D9
|
||||
PE13 ------> FSMC_D10
|
||||
PE14 ------> FSMC_D11
|
||||
PE15 ------> FSMC_D12
|
||||
PD8 ------> FSMC_D13
|
||||
PD9 ------> FSMC_D14
|
||||
PD10 ------> FSMC_D15
|
||||
PD11 ------> FSMC_A16
|
||||
PD12 ------> FSMC_A17
|
||||
PD13 ------> FSMC_A18
|
||||
PD14 ------> FSMC_D0
|
||||
PD15 ------> FSMC_D1
|
||||
PG2 ------> FSMC_A12
|
||||
PG3 ------> FSMC_A13
|
||||
PG4 ------> FSMC_A14
|
||||
PG5 ------> FSMC_A15
|
||||
PD0 ------> FSMC_D2
|
||||
PD1 ------> FSMC_D3
|
||||
PD4 ------> FSMC_NOE
|
||||
PD5 ------> FSMC_NWE
|
||||
PG10 ------> FSMC_NE3
|
||||
PE0 ------> FSMC_NBL0
|
||||
PE1 ------> FSMC_NBL1
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13
|
||||
|GPIO_PIN_14|GPIO_PIN_15);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|
||||
|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
|
||||
|GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11
|
||||
|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15
|
||||
|GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
|
||||
|
||||
/* USER CODE BEGIN FSMC_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END FSMC_MspDeInit 1 */
|
||||
}
|
||||
|
||||
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){
|
||||
/* USER CODE BEGIN SRAM_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SRAM_MspDeInit 0 */
|
||||
HAL_FSMC_MspDeInit();
|
||||
/* USER CODE BEGIN SRAM_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SRAM_MspDeInit 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
|
|
|||
|
|
@ -37,6 +37,12 @@ menu "Onboard Peripheral Drivers"
|
|||
select BSP_USING_I2C1
|
||||
default n
|
||||
|
||||
config BSP_USING_EXT_SRAM
|
||||
bool "Enable external sram"
|
||||
default n
|
||||
help
|
||||
Chip name is IS62WV51216BLL, 1Mbytes static RAMs organized as 512K words by 16bits.
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
|
|
|||
|
|
@ -12,6 +12,9 @@ board.c
|
|||
CubeMX_Config/Src/stm32f1xx_hal_msp.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_EXT_SRAM']):
|
||||
src += Glob('ports/drv_sram.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/spi_flash_init.c')
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,169 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-01-05 linyiyang first version
|
||||
* 2024-05-28 WKjay add this file to stm32f103-100ask-pro
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef BSP_USING_EXT_SRAM
|
||||
#include <sram_port.h>
|
||||
|
||||
#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.ext_sram"
|
||||
#include <drv_log.h>
|
||||
|
||||
static SRAM_HandleTypeDef hsram1;
|
||||
#ifdef RT_USING_MEMHEAP_AS_HEAP
|
||||
static struct rt_memheap system_heap;
|
||||
#endif
|
||||
|
||||
static int external_sram_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
|
||||
FSMC_NORSRAM_TimingTypeDef Timing = {0};
|
||||
|
||||
/** Perform the SRAM1 memory initialization sequence
|
||||
*/
|
||||
hsram1.Instance = FSMC_NORSRAM_DEVICE;
|
||||
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
|
||||
|
||||
/* hsram1.Init */
|
||||
hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
|
||||
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
|
||||
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
|
||||
#if EXTERNAL_SRAM_DATA_WIDTH == 8
|
||||
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
|
||||
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
|
||||
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
|
||||
#else
|
||||
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
|
||||
#endif
|
||||
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
|
||||
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
|
||||
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
|
||||
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
|
||||
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
|
||||
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
|
||||
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
|
||||
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
|
||||
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
|
||||
|
||||
/* Timing */
|
||||
Timing.AddressSetupTime = 0;
|
||||
Timing.AddressHoldTime = 15;
|
||||
Timing.DataSetupTime = 3;
|
||||
Timing.BusTurnAroundDuration = 0;
|
||||
Timing.CLKDivision = 16;
|
||||
Timing.DataLatency = 17;
|
||||
Timing.AccessMode = FSMC_ACCESS_MODE_A;
|
||||
/* ExtTiming */
|
||||
|
||||
/* Initialize the SRAM controller */
|
||||
if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
|
||||
{
|
||||
LOG_E("External SRAM init failed!");
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("External sram init success, mapped at 0x%X, size is %d bytes, data width is %d", EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE, EXTERNAL_SRAM_DATA_WIDTH);
|
||||
#ifdef RT_USING_MEMHEAP_AS_HEAP
|
||||
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
|
||||
rt_memheap_init(&system_heap, "ext_sram", (void *)EXTERNAL_SRAM_BANK_ADDR, EXTERNAL_SRAM_SIZE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disconnect NADV
|
||||
*/
|
||||
|
||||
__HAL_AFIO_FSMCNADV_DISCONNECTED();
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(external_sram_init);
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#ifdef FINSH_USING_MSH
|
||||
int external_sram_test(void)
|
||||
{
|
||||
int i = 0;
|
||||
uint32_t start_time = 0, time_cast = 0;
|
||||
#if EXTERNAL_SRAM_DATA_WIDTH == 8
|
||||
char data_width = 1;
|
||||
uint8_t data = 0;
|
||||
uint8_t *ptr = (uint8_t *)EXTERNAL_SRAM_BANK_ADDR;
|
||||
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
|
||||
char data_width = 2;
|
||||
uint16_t data = 0;
|
||||
uint16_t *ptr = (uint16_t *)EXTERNAL_SRAM_BANK_ADDR;
|
||||
#else
|
||||
char data_width = 4;
|
||||
uint32_t data = 0;
|
||||
uint32_t *ptr = (uint32_t *)EXTERNAL_SRAM_BANK_ADDR;
|
||||
#endif
|
||||
|
||||
/* write data */
|
||||
LOG_D("Writing the %ld bytes data, waiting....", EXTERNAL_SRAM_SIZE);
|
||||
start_time = rt_tick_get();
|
||||
for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
|
||||
{
|
||||
#if EXTERNAL_SRAM_DATA_WIDTH == 8
|
||||
((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
|
||||
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
|
||||
((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
|
||||
#else
|
||||
((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
|
||||
#endif
|
||||
}
|
||||
time_cast = rt_tick_get() - start_time;
|
||||
LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
|
||||
time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
|
||||
|
||||
/* read data */
|
||||
LOG_D("start Reading and verifying data, waiting....");
|
||||
for (i = 0; i < EXTERNAL_SRAM_SIZE / data_width; i++)
|
||||
{
|
||||
#if EXTERNAL_SRAM_DATA_WIDTH == 8
|
||||
data = ((__IO uint8_t *)ptr)[i];
|
||||
if (data != 0x55)
|
||||
{
|
||||
LOG_E("External SRAM test failed!");
|
||||
break;
|
||||
}
|
||||
#elif EXTERNAL_SRAM_DATA_WIDTH == 16
|
||||
data = ((__IO uint16_t *)ptr)[i];
|
||||
if (data != 0x5555)
|
||||
{
|
||||
LOG_E("External SRAM test failed!");
|
||||
break;
|
||||
}
|
||||
#else
|
||||
data = ((__IO uint32_t *)ptr)[i];
|
||||
if (data != 0x55555555)
|
||||
{
|
||||
LOG_E("External SRAM test failed!");
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if (i >= EXTERNAL_SRAM_SIZE / data_width)
|
||||
{
|
||||
LOG_D("External SRAM test success!");
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
MSH_CMD_EXPORT(external_sram_test, sram test);
|
||||
#endif /* FINSH_USING_MSH */
|
||||
#endif /* DRV_DEBUG */
|
||||
#endif /* BSP_USING_EXT_SRAM */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-01-05 linyiyang first version
|
||||
* 2024-05-28 WKjay add this file to stm32f103-100ask-pro
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
/* stm32f1 Bank1:0x68000000 */
|
||||
#define EXTERNAL_SRAM_BANK_ADDR ((uint32_t)0x68000000)
|
||||
/* data width: 8, 16, 32 */
|
||||
#define EXTERNAL_SRAM_DATA_WIDTH 16
|
||||
/* sram size */
|
||||
#define EXTERNAL_SRAM_SIZE ((uint32_t)0x100000)
|
||||
|
||||
#endif
|
||||
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Reference in New Issue