[Renesas]Add HMI-Board bsp
|
@ -183,6 +183,7 @@ jobs:
|
||||||
- "xplorer4330/M4"
|
- "xplorer4330/M4"
|
||||||
- "renesas/ra6m3-ek"
|
- "renesas/ra6m3-ek"
|
||||||
- "renesas/ra6m4-cpk"
|
- "renesas/ra6m4-cpk"
|
||||||
|
- "renesas/ra6m3-hmi-board"
|
||||||
- RTT_BSP: "gd32_n32_apm32"
|
- RTT_BSP: "gd32_n32_apm32"
|
||||||
RTT_TOOL_CHAIN: "sourcery-arm"
|
RTT_TOOL_CHAIN: "sourcery-arm"
|
||||||
SUB_RTT_BSP:
|
SUB_RTT_BSP:
|
||||||
|
|
|
@ -0,0 +1,756 @@
|
||||||
|
#
|
||||||
|
# Automatically generated file; DO NOT EDIT.
|
||||||
|
# RT-Thread Configuration
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# RT-Thread Kernel
|
||||||
|
#
|
||||||
|
CONFIG_RT_NAME_MAX=8
|
||||||
|
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
|
||||||
|
# CONFIG_RT_USING_SMART is not set
|
||||||
|
# CONFIG_RT_USING_SMP is not set
|
||||||
|
CONFIG_RT_ALIGN_SIZE=8
|
||||||
|
# CONFIG_RT_THREAD_PRIORITY_8 is not set
|
||||||
|
CONFIG_RT_THREAD_PRIORITY_32=y
|
||||||
|
# CONFIG_RT_THREAD_PRIORITY_256 is not set
|
||||||
|
CONFIG_RT_THREAD_PRIORITY_MAX=32
|
||||||
|
CONFIG_RT_TICK_PER_SECOND=1000
|
||||||
|
CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||||
|
CONFIG_RT_USING_HOOK=y
|
||||||
|
CONFIG_RT_HOOK_USING_FUNC_PTR=y
|
||||||
|
CONFIG_RT_USING_IDLE_HOOK=y
|
||||||
|
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
|
||||||
|
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||||
|
CONFIG_RT_USING_TIMER_SOFT=y
|
||||||
|
CONFIG_RT_TIMER_THREAD_PRIO=4
|
||||||
|
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
|
||||||
|
|
||||||
|
#
|
||||||
|
# kservice optimization
|
||||||
|
#
|
||||||
|
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
|
||||||
|
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
|
||||||
|
# CONFIG_RT_USING_TINY_FFS is not set
|
||||||
|
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
|
||||||
|
CONFIG_RT_DEBUG=y
|
||||||
|
CONFIG_RT_DEBUG_COLOR=y
|
||||||
|
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
|
||||||
|
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Inter-Thread communication
|
||||||
|
#
|
||||||
|
CONFIG_RT_USING_SEMAPHORE=y
|
||||||
|
CONFIG_RT_USING_MUTEX=y
|
||||||
|
CONFIG_RT_USING_EVENT=y
|
||||||
|
CONFIG_RT_USING_MAILBOX=y
|
||||||
|
CONFIG_RT_USING_MESSAGEQUEUE=y
|
||||||
|
# CONFIG_RT_USING_SIGNALS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Memory Management
|
||||||
|
#
|
||||||
|
CONFIG_RT_PAGE_MAX_ORDER=11
|
||||||
|
# CONFIG_RT_USING_MEMPOOL is not set
|
||||||
|
CONFIG_RT_USING_SMALL_MEM=y
|
||||||
|
# CONFIG_RT_USING_SLAB is not set
|
||||||
|
# CONFIG_RT_USING_MEMHEAP is not set
|
||||||
|
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
|
||||||
|
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
|
||||||
|
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
|
||||||
|
# CONFIG_RT_USING_USERHEAP is not set
|
||||||
|
# CONFIG_RT_USING_NOHEAP is not set
|
||||||
|
# CONFIG_RT_USING_MEMTRACE is not set
|
||||||
|
# CONFIG_RT_USING_HEAP_ISR is not set
|
||||||
|
CONFIG_RT_USING_HEAP=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Kernel Device Object
|
||||||
|
#
|
||||||
|
CONFIG_RT_USING_DEVICE=y
|
||||||
|
# CONFIG_RT_USING_DEVICE_OPS is not set
|
||||||
|
# CONFIG_RT_USING_DM is not set
|
||||||
|
# CONFIG_RT_USING_INTERRUPT_INFO is not set
|
||||||
|
CONFIG_RT_USING_CONSOLE=y
|
||||||
|
CONFIG_RT_CONSOLEBUF_SIZE=128
|
||||||
|
CONFIG_RT_CONSOLE_DEVICE_NAME="uart9"
|
||||||
|
CONFIG_RT_VER_NUM=0x50001
|
||||||
|
# CONFIG_RT_USING_STDC_ATOMIC is not set
|
||||||
|
# CONFIG_RT_USING_CACHE is not set
|
||||||
|
CONFIG_RT_USING_HW_ATOMIC=y
|
||||||
|
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
|
||||||
|
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
|
||||||
|
CONFIG_RT_USING_CPU_FFS=y
|
||||||
|
CONFIG_ARCH_ARM=y
|
||||||
|
CONFIG_ARCH_ARM_CORTEX_M=y
|
||||||
|
CONFIG_ARCH_ARM_CORTEX_M4=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# RT-Thread Components
|
||||||
|
#
|
||||||
|
CONFIG_RT_USING_COMPONENTS_INIT=y
|
||||||
|
CONFIG_RT_USING_USER_MAIN=y
|
||||||
|
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
|
||||||
|
CONFIG_RT_MAIN_THREAD_PRIORITY=10
|
||||||
|
# CONFIG_RT_USING_LEGACY is not set
|
||||||
|
CONFIG_RT_USING_MSH=y
|
||||||
|
CONFIG_RT_USING_FINSH=y
|
||||||
|
CONFIG_FINSH_USING_MSH=y
|
||||||
|
CONFIG_FINSH_THREAD_NAME="tshell"
|
||||||
|
CONFIG_FINSH_THREAD_PRIORITY=20
|
||||||
|
CONFIG_FINSH_THREAD_STACK_SIZE=4096
|
||||||
|
CONFIG_FINSH_USING_HISTORY=y
|
||||||
|
CONFIG_FINSH_HISTORY_LINES=5
|
||||||
|
CONFIG_FINSH_USING_SYMTAB=y
|
||||||
|
CONFIG_FINSH_CMD_SIZE=80
|
||||||
|
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
|
||||||
|
CONFIG_FINSH_USING_DESCRIPTION=y
|
||||||
|
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
|
||||||
|
# CONFIG_FINSH_USING_AUTH is not set
|
||||||
|
CONFIG_FINSH_ARG_MAX=10
|
||||||
|
|
||||||
|
#
|
||||||
|
# DFS: device virtual file system
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_DFS is not set
|
||||||
|
# CONFIG_RT_USING_FAL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Device Drivers
|
||||||
|
#
|
||||||
|
CONFIG_RT_USING_DEVICE_IPC=y
|
||||||
|
CONFIG_RT_UNAMED_PIPE_NUMBER=64
|
||||||
|
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
|
||||||
|
CONFIG_RT_USING_SERIAL=y
|
||||||
|
# CONFIG_RT_USING_SERIAL_V1 is not set
|
||||||
|
CONFIG_RT_USING_SERIAL_V2=y
|
||||||
|
CONFIG_RT_SERIAL_USING_DMA=y
|
||||||
|
# CONFIG_RT_USING_CAN is not set
|
||||||
|
# CONFIG_RT_USING_HWTIMER is not set
|
||||||
|
# CONFIG_RT_USING_CPUTIME is not set
|
||||||
|
# CONFIG_RT_USING_I2C is not set
|
||||||
|
# CONFIG_RT_USING_PHY is not set
|
||||||
|
CONFIG_RT_USING_PIN=y
|
||||||
|
# CONFIG_RT_USING_ADC is not set
|
||||||
|
# CONFIG_RT_USING_DAC is not set
|
||||||
|
# CONFIG_RT_USING_NULL is not set
|
||||||
|
# CONFIG_RT_USING_ZERO is not set
|
||||||
|
# CONFIG_RT_USING_RANDOM is not set
|
||||||
|
# CONFIG_RT_USING_PWM is not set
|
||||||
|
# CONFIG_RT_USING_MTD_NOR is not set
|
||||||
|
# CONFIG_RT_USING_MTD_NAND is not set
|
||||||
|
# CONFIG_RT_USING_PM is not set
|
||||||
|
# CONFIG_RT_USING_FDT is not set
|
||||||
|
# CONFIG_RT_USING_RTC is not set
|
||||||
|
# CONFIG_RT_USING_SDIO is not set
|
||||||
|
# CONFIG_RT_USING_SPI is not set
|
||||||
|
# CONFIG_RT_USING_WDT is not set
|
||||||
|
# CONFIG_RT_USING_AUDIO is not set
|
||||||
|
# CONFIG_RT_USING_SENSOR is not set
|
||||||
|
# CONFIG_RT_USING_TOUCH is not set
|
||||||
|
# CONFIG_RT_USING_LCD is not set
|
||||||
|
# CONFIG_RT_USING_HWCRYPTO is not set
|
||||||
|
# CONFIG_RT_USING_PULSE_ENCODER is not set
|
||||||
|
# CONFIG_RT_USING_INPUT_CAPTURE is not set
|
||||||
|
# CONFIG_RT_USING_DEV_BUS is not set
|
||||||
|
# CONFIG_RT_USING_WIFI is not set
|
||||||
|
# CONFIG_RT_USING_VIRTIO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Using USB
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_USB is not set
|
||||||
|
# CONFIG_RT_USING_USB_HOST is not set
|
||||||
|
# CONFIG_RT_USING_USB_DEVICE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# C/C++ and POSIX layer
|
||||||
|
#
|
||||||
|
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
|
||||||
|
|
||||||
|
#
|
||||||
|
# POSIX (Portable Operating System Interface) layer
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_POSIX_FS is not set
|
||||||
|
# CONFIG_RT_USING_POSIX_DELAY is not set
|
||||||
|
# CONFIG_RT_USING_POSIX_CLOCK is not set
|
||||||
|
# CONFIG_RT_USING_POSIX_TIMER is not set
|
||||||
|
# CONFIG_RT_USING_PTHREADS is not set
|
||||||
|
# CONFIG_RT_USING_MODULE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Interprocess Communication (IPC)
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_POSIX_PIPE is not set
|
||||||
|
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
|
||||||
|
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Socket is in the 'Network' category
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_CPLUSPLUS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Network
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_SAL is not set
|
||||||
|
# CONFIG_RT_USING_NETDEV is not set
|
||||||
|
# CONFIG_RT_USING_LWIP is not set
|
||||||
|
# CONFIG_RT_USING_AT is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Utilities
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_RYM is not set
|
||||||
|
# CONFIG_RT_USING_ULOG is not set
|
||||||
|
# CONFIG_RT_USING_UTEST is not set
|
||||||
|
# CONFIG_RT_USING_VAR_EXPORT is not set
|
||||||
|
# CONFIG_RT_USING_ADT is not set
|
||||||
|
# CONFIG_RT_USING_RT_LINK is not set
|
||||||
|
# CONFIG_RT_USING_VBUS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# RT-Thread Utestcases
|
||||||
|
#
|
||||||
|
# CONFIG_RT_USING_UTESTCASES is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# RT-Thread online packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# IoT - internet of things
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_LWIP is not set
|
||||||
|
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
|
||||||
|
# CONFIG_PKG_USING_PAHOMQTT is not set
|
||||||
|
# CONFIG_PKG_USING_UMQTT is not set
|
||||||
|
# CONFIG_PKG_USING_WEBCLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_WEBNET is not set
|
||||||
|
# CONFIG_PKG_USING_MONGOOSE is not set
|
||||||
|
# CONFIG_PKG_USING_MYMQTT is not set
|
||||||
|
# CONFIG_PKG_USING_KAWAII_MQTT is not set
|
||||||
|
# CONFIG_PKG_USING_BC28_MQTT is not set
|
||||||
|
# CONFIG_PKG_USING_WEBTERMINAL is not set
|
||||||
|
# CONFIG_PKG_USING_LIBMODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_FREEMODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_NANOPB is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Wi-Fi
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Marvell WiFi
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_WLANMARVELL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Wiced WiFi
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_WLAN_WICED is not set
|
||||||
|
# CONFIG_PKG_USING_RW007 is not set
|
||||||
|
# CONFIG_PKG_USING_COAP is not set
|
||||||
|
# CONFIG_PKG_USING_NOPOLL is not set
|
||||||
|
# CONFIG_PKG_USING_NETUTILS is not set
|
||||||
|
# CONFIG_PKG_USING_CMUX is not set
|
||||||
|
# CONFIG_PKG_USING_PPP_DEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_AT_DEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
|
||||||
|
# CONFIG_PKG_USING_WIZNET is not set
|
||||||
|
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# IoT Cloud
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ONENET is not set
|
||||||
|
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
|
||||||
|
# CONFIG_PKG_USING_ALI_IOTKIT is not set
|
||||||
|
# CONFIG_PKG_USING_AZURE is not set
|
||||||
|
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
|
||||||
|
# CONFIG_PKG_USING_JIOT-C-SDK is not set
|
||||||
|
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_JOYLINK is not set
|
||||||
|
# CONFIG_PKG_USING_EZ_IOT_OS is not set
|
||||||
|
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_NIMBLE is not set
|
||||||
|
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
|
||||||
|
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
|
||||||
|
# CONFIG_PKG_USING_IPMSG is not set
|
||||||
|
# CONFIG_PKG_USING_LSSDP is not set
|
||||||
|
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
|
||||||
|
# CONFIG_PKG_USING_LIBRWS is not set
|
||||||
|
# CONFIG_PKG_USING_TCPSERVER is not set
|
||||||
|
# CONFIG_PKG_USING_PROTOBUF_C is not set
|
||||||
|
# CONFIG_PKG_USING_DLT645 is not set
|
||||||
|
# CONFIG_PKG_USING_QXWZ is not set
|
||||||
|
# CONFIG_PKG_USING_SMTP_CLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_ABUP_FOTA is not set
|
||||||
|
# CONFIG_PKG_USING_LIBCURL2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_CAPNP is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_TELNET is not set
|
||||||
|
# CONFIG_PKG_USING_NMEALIB is not set
|
||||||
|
# CONFIG_PKG_USING_PDULIB is not set
|
||||||
|
# CONFIG_PKG_USING_BTSTACK is not set
|
||||||
|
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
|
||||||
|
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
|
||||||
|
# CONFIG_PKG_USING_MAVLINK is not set
|
||||||
|
# CONFIG_PKG_USING_BSAL is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_FTP is not set
|
||||||
|
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
|
||||||
|
# CONFIG_PKG_USING_RT_LINK_HW is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
|
||||||
|
# CONFIG_PKG_USING_HM is not set
|
||||||
|
# CONFIG_PKG_USING_SMALL_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_NET_SERVER is not set
|
||||||
|
# CONFIG_PKG_USING_ZFTP is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# security packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_MBEDTLS is not set
|
||||||
|
# CONFIG_PKG_USING_LIBSODIUM is not set
|
||||||
|
# CONFIG_PKG_USING_LIBHYDROGEN is not set
|
||||||
|
# CONFIG_PKG_USING_TINYCRYPT is not set
|
||||||
|
# CONFIG_PKG_USING_TFM is not set
|
||||||
|
# CONFIG_PKG_USING_YD_CRYPTO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# language packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# JSON: JavaScript Object Notation, a lightweight data-interchange format
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CJSON is not set
|
||||||
|
# CONFIG_PKG_USING_LJSON is not set
|
||||||
|
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
|
||||||
|
# CONFIG_PKG_USING_RAPIDJSON is not set
|
||||||
|
# CONFIG_PKG_USING_JSMN is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_JSMN is not set
|
||||||
|
# CONFIG_PKG_USING_PARSON is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# XML: Extensible Markup Language
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_SIMPLE_XML is not set
|
||||||
|
# CONFIG_PKG_USING_EZXML is not set
|
||||||
|
# CONFIG_PKG_USING_LUATOS_SOC is not set
|
||||||
|
# CONFIG_PKG_USING_LUA is not set
|
||||||
|
# CONFIG_PKG_USING_JERRYSCRIPT is not set
|
||||||
|
# CONFIG_PKG_USING_MICROPYTHON is not set
|
||||||
|
# CONFIG_PKG_USING_PIKASCRIPT is not set
|
||||||
|
# CONFIG_PKG_USING_RTT_RUST is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# multimedia packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# LVGL: powerful and easy-to-use embedded GUI library
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_LVGL is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
|
||||||
|
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# u8g2: a monochrome graphic library
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
|
||||||
|
# CONFIG_PKG_USING_U8G2 is not set
|
||||||
|
# CONFIG_PKG_USING_OPENMV is not set
|
||||||
|
# CONFIG_PKG_USING_MUPDF is not set
|
||||||
|
# CONFIG_PKG_USING_STEMWIN is not set
|
||||||
|
# CONFIG_PKG_USING_WAVPLAYER is not set
|
||||||
|
# CONFIG_PKG_USING_TJPGD is not set
|
||||||
|
# CONFIG_PKG_USING_PDFGEN is not set
|
||||||
|
# CONFIG_PKG_USING_HELIX is not set
|
||||||
|
# CONFIG_PKG_USING_AZUREGUIX is not set
|
||||||
|
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_NUEMWIN is not set
|
||||||
|
# CONFIG_PKG_USING_MP3PLAYER is not set
|
||||||
|
# CONFIG_PKG_USING_TINYJPEG is not set
|
||||||
|
# CONFIG_PKG_USING_UGUI is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# PainterEngine: A cross-platform graphics application framework written in C language
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_PAINTERENGINE is not set
|
||||||
|
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
|
||||||
|
# CONFIG_PKG_USING_MCURSES is not set
|
||||||
|
# CONFIG_PKG_USING_TERMBOX is not set
|
||||||
|
# CONFIG_PKG_USING_VT100 is not set
|
||||||
|
# CONFIG_PKG_USING_QRCODE is not set
|
||||||
|
# CONFIG_PKG_USING_GUIENGINE is not set
|
||||||
|
# CONFIG_PKG_USING_PERSIMMON is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# tools packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMBACKTRACE is not set
|
||||||
|
# CONFIG_PKG_USING_EASYFLASH is not set
|
||||||
|
# CONFIG_PKG_USING_EASYLOGGER is not set
|
||||||
|
# CONFIG_PKG_USING_SYSTEMVIEW is not set
|
||||||
|
# CONFIG_PKG_USING_SEGGER_RTT is not set
|
||||||
|
# CONFIG_PKG_USING_RDB is not set
|
||||||
|
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
|
||||||
|
# CONFIG_PKG_USING_ULOG_FILE is not set
|
||||||
|
# CONFIG_PKG_USING_LOGMGR is not set
|
||||||
|
# CONFIG_PKG_USING_ADBD is not set
|
||||||
|
# CONFIG_PKG_USING_COREMARK is not set
|
||||||
|
# CONFIG_PKG_USING_DHRYSTONE is not set
|
||||||
|
# CONFIG_PKG_USING_MEMORYPERF is not set
|
||||||
|
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
|
||||||
|
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
|
||||||
|
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
|
||||||
|
# CONFIG_PKG_USING_BS8116A is not set
|
||||||
|
# CONFIG_PKG_USING_GPS_RMC is not set
|
||||||
|
# CONFIG_PKG_USING_URLENCODE is not set
|
||||||
|
# CONFIG_PKG_USING_UMCN is not set
|
||||||
|
# CONFIG_PKG_USING_LWRB2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_CPU_USAGE is not set
|
||||||
|
# CONFIG_PKG_USING_GBK2UTF8 is not set
|
||||||
|
# CONFIG_PKG_USING_VCONSOLE is not set
|
||||||
|
# CONFIG_PKG_USING_KDB is not set
|
||||||
|
# CONFIG_PKG_USING_WAMR is not set
|
||||||
|
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
|
||||||
|
# CONFIG_PKG_USING_LWLOG is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_TRACE is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
|
||||||
|
# CONFIG_PKG_USING_ANV_BENCH is not set
|
||||||
|
# CONFIG_PKG_USING_DEVMEM is not set
|
||||||
|
# CONFIG_PKG_USING_REGEX is not set
|
||||||
|
# CONFIG_PKG_USING_MEM_SANDBOX is not set
|
||||||
|
# CONFIG_PKG_USING_SOLAR_TERMS is not set
|
||||||
|
# CONFIG_PKG_USING_GAN_ZHI is not set
|
||||||
|
# CONFIG_PKG_USING_FDT is not set
|
||||||
|
# CONFIG_PKG_USING_CBOX is not set
|
||||||
|
# CONFIG_PKG_USING_SNOWFLAKE is not set
|
||||||
|
# CONFIG_PKG_USING_HASH_MATCH is not set
|
||||||
|
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
|
||||||
|
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
|
||||||
|
# CONFIG_PKG_USING_VOFA_PLUS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# system packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# enhanced kernel services
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
|
||||||
|
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
|
||||||
|
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# acceleration: Assembly language or algorithmic acceleration packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
|
||||||
|
# CONFIG_PKG_USING_QFPLIB_M3 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMSIS_5 is not set
|
||||||
|
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
|
||||||
|
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Micrium: Micrium software products porting for RT-Thread
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
|
||||||
|
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
|
||||||
|
# CONFIG_PKG_USING_UC_CRC is not set
|
||||||
|
# CONFIG_PKG_USING_UC_CLK is not set
|
||||||
|
# CONFIG_PKG_USING_UC_COMMON is not set
|
||||||
|
# CONFIG_PKG_USING_UC_MODBUS is not set
|
||||||
|
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
|
||||||
|
# CONFIG_PKG_USING_CAIRO is not set
|
||||||
|
# CONFIG_PKG_USING_PIXMAN is not set
|
||||||
|
# CONFIG_PKG_USING_PARTITION is not set
|
||||||
|
# CONFIG_PKG_USING_PERF_COUNTER is not set
|
||||||
|
# CONFIG_PKG_USING_FLASHDB is not set
|
||||||
|
# CONFIG_PKG_USING_SQLITE is not set
|
||||||
|
# CONFIG_PKG_USING_RTI is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_YAFFS is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLEFS is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_JFFS2 is not set
|
||||||
|
# CONFIG_PKG_USING_DFS_UFFS is not set
|
||||||
|
# CONFIG_PKG_USING_LWEXT4 is not set
|
||||||
|
# CONFIG_PKG_USING_THREAD_POOL is not set
|
||||||
|
# CONFIG_PKG_USING_ROBOTS is not set
|
||||||
|
# CONFIG_PKG_USING_EV is not set
|
||||||
|
# CONFIG_PKG_USING_SYSWATCH is not set
|
||||||
|
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
|
||||||
|
# CONFIG_PKG_USING_PLCCORE is not set
|
||||||
|
# CONFIG_PKG_USING_RAMDISK is not set
|
||||||
|
# CONFIG_PKG_USING_MININI is not set
|
||||||
|
# CONFIG_PKG_USING_QBOOT is not set
|
||||||
|
# CONFIG_PKG_USING_PPOOL is not set
|
||||||
|
# CONFIG_PKG_USING_OPENAMP is not set
|
||||||
|
# CONFIG_PKG_USING_LPM is not set
|
||||||
|
# CONFIG_PKG_USING_TLSF is not set
|
||||||
|
# CONFIG_PKG_USING_EVENT_RECORDER is not set
|
||||||
|
# CONFIG_PKG_USING_ARM_2D is not set
|
||||||
|
# CONFIG_PKG_USING_MCUBOOT is not set
|
||||||
|
# CONFIG_PKG_USING_TINYUSB is not set
|
||||||
|
# CONFIG_PKG_USING_CHERRYUSB is not set
|
||||||
|
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
|
||||||
|
# CONFIG_PKG_USING_TFDB is not set
|
||||||
|
# CONFIG_PKG_USING_QPC is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# peripheral libraries and drivers
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||||
|
# CONFIG_PKG_USING_SHT2X is not set
|
||||||
|
# CONFIG_PKG_USING_SHT3X is not set
|
||||||
|
# CONFIG_PKG_USING_ADT74XX is not set
|
||||||
|
# CONFIG_PKG_USING_AS7341 is not set
|
||||||
|
# CONFIG_PKG_USING_STM32_SDIO is not set
|
||||||
|
# CONFIG_PKG_USING_ESP_IDF is not set
|
||||||
|
# CONFIG_PKG_USING_ICM20608 is not set
|
||||||
|
# CONFIG_PKG_USING_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_PCF8574 is not set
|
||||||
|
# CONFIG_PKG_USING_SX12XX is not set
|
||||||
|
# CONFIG_PKG_USING_SIGNAL_LED is not set
|
||||||
|
# CONFIG_PKG_USING_LEDBLINK is not set
|
||||||
|
# CONFIG_PKG_USING_LITTLED is not set
|
||||||
|
# CONFIG_PKG_USING_LKDGUI is not set
|
||||||
|
# CONFIG_PKG_USING_NRF5X_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_NRFX is not set
|
||||||
|
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Kendryte SDK
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_K210_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_INFRARED is not set
|
||||||
|
# CONFIG_PKG_USING_ILI9341 is not set
|
||||||
|
# CONFIG_PKG_USING_MULTI_INFRARED is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_LED is not set
|
||||||
|
# CONFIG_PKG_USING_AT24CXX is not set
|
||||||
|
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_AD7746 is not set
|
||||||
|
# CONFIG_PKG_USING_PCA9685 is not set
|
||||||
|
# CONFIG_PKG_USING_I2C_TOOLS is not set
|
||||||
|
# CONFIG_PKG_USING_NRF24L01 is not set
|
||||||
|
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_MAX17048 is not set
|
||||||
|
# CONFIG_PKG_USING_RPLIDAR is not set
|
||||||
|
# CONFIG_PKG_USING_AS608 is not set
|
||||||
|
# CONFIG_PKG_USING_RC522 is not set
|
||||||
|
# CONFIG_PKG_USING_WS2812B is not set
|
||||||
|
# CONFIG_PKG_USING_EMBARC_BSP is not set
|
||||||
|
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
|
||||||
|
# CONFIG_PKG_USING_MULTI_RTIMER is not set
|
||||||
|
# CONFIG_PKG_USING_MAX7219 is not set
|
||||||
|
# CONFIG_PKG_USING_BEEP is not set
|
||||||
|
# CONFIG_PKG_USING_EASYBLINK is not set
|
||||||
|
# CONFIG_PKG_USING_PMS_SERIES is not set
|
||||||
|
# CONFIG_PKG_USING_CAN_YMODEM is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
|
||||||
|
# CONFIG_PKG_USING_QLED is not set
|
||||||
|
# CONFIG_PKG_USING_PAJ7620 is not set
|
||||||
|
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
|
||||||
|
# CONFIG_PKG_USING_LD3320 is not set
|
||||||
|
# CONFIG_PKG_USING_WK2124 is not set
|
||||||
|
# CONFIG_PKG_USING_LY68L6400 is not set
|
||||||
|
# CONFIG_PKG_USING_DM9051 is not set
|
||||||
|
# CONFIG_PKG_USING_SSD1306 is not set
|
||||||
|
# CONFIG_PKG_USING_QKEY is not set
|
||||||
|
# CONFIG_PKG_USING_RS485 is not set
|
||||||
|
# CONFIG_PKG_USING_RS232 is not set
|
||||||
|
# CONFIG_PKG_USING_NES is not set
|
||||||
|
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
|
||||||
|
# CONFIG_PKG_USING_VDEVICE is not set
|
||||||
|
# CONFIG_PKG_USING_SGM706 is not set
|
||||||
|
# CONFIG_PKG_USING_STM32WB55_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_RDA58XX is not set
|
||||||
|
# CONFIG_PKG_USING_LIBNFC is not set
|
||||||
|
# CONFIG_PKG_USING_MFOC is not set
|
||||||
|
# CONFIG_PKG_USING_TMC51XX is not set
|
||||||
|
# CONFIG_PKG_USING_TCA9534 is not set
|
||||||
|
# CONFIG_PKG_USING_KOBUKI is not set
|
||||||
|
# CONFIG_PKG_USING_ROSSERIAL is not set
|
||||||
|
# CONFIG_PKG_USING_MICRO_ROS is not set
|
||||||
|
# CONFIG_PKG_USING_MCP23008 is not set
|
||||||
|
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
|
||||||
|
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
|
||||||
|
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
|
||||||
|
# CONFIG_PKG_USING_BL_MCU_SDK is not set
|
||||||
|
# CONFIG_PKG_USING_SOFT_SERIAL is not set
|
||||||
|
# CONFIG_PKG_USING_MB85RS16 is not set
|
||||||
|
# CONFIG_PKG_USING_CW2015 is not set
|
||||||
|
# CONFIG_PKG_USING_RFM300 is not set
|
||||||
|
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
|
||||||
|
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# AI packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_LIBANN is not set
|
||||||
|
# CONFIG_PKG_USING_NNOM is not set
|
||||||
|
# CONFIG_PKG_USING_ONNX_BACKEND is not set
|
||||||
|
# CONFIG_PKG_USING_ONNX_PARSER is not set
|
||||||
|
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
|
||||||
|
# CONFIG_PKG_USING_ELAPACK is not set
|
||||||
|
# CONFIG_PKG_USING_ULAPACK is not set
|
||||||
|
# CONFIG_PKG_USING_QUEST is not set
|
||||||
|
# CONFIG_PKG_USING_NAXOS is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# miscellaneous packages
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# project laboratory
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# samples: kernel and components samples
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
|
||||||
|
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# entertainment: terminal games and other interesting software packages
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_CMATRIX is not set
|
||||||
|
# CONFIG_PKG_USING_SL is not set
|
||||||
|
# CONFIG_PKG_USING_CAL is not set
|
||||||
|
# CONFIG_PKG_USING_ACLOCK is not set
|
||||||
|
# CONFIG_PKG_USING_THREES is not set
|
||||||
|
# CONFIG_PKG_USING_2048 is not set
|
||||||
|
# CONFIG_PKG_USING_SNAKE is not set
|
||||||
|
# CONFIG_PKG_USING_TETRIS is not set
|
||||||
|
# CONFIG_PKG_USING_DONUT is not set
|
||||||
|
# CONFIG_PKG_USING_COWSAY is not set
|
||||||
|
# CONFIG_PKG_USING_LIBCSV is not set
|
||||||
|
# CONFIG_PKG_USING_OPTPARSE is not set
|
||||||
|
# CONFIG_PKG_USING_FASTLZ is not set
|
||||||
|
# CONFIG_PKG_USING_MINILZO is not set
|
||||||
|
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||||
|
# CONFIG_PKG_USING_LZMA is not set
|
||||||
|
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||||
|
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||||
|
# CONFIG_PKG_USING_ZLIB is not set
|
||||||
|
# CONFIG_PKG_USING_MINIZIP is not set
|
||||||
|
# CONFIG_PKG_USING_HEATSHRINK is not set
|
||||||
|
# CONFIG_PKG_USING_DSTR is not set
|
||||||
|
# CONFIG_PKG_USING_TINYFRAME is not set
|
||||||
|
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
|
||||||
|
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||||
|
# CONFIG_PKG_USING_UPACKER is not set
|
||||||
|
# CONFIG_PKG_USING_UPARAM is not set
|
||||||
|
# CONFIG_PKG_USING_HELLO is not set
|
||||||
|
# CONFIG_PKG_USING_VI is not set
|
||||||
|
# CONFIG_PKG_USING_KI is not set
|
||||||
|
# CONFIG_PKG_USING_ARMv7M_DWT is not set
|
||||||
|
# CONFIG_PKG_USING_UKAL is not set
|
||||||
|
# CONFIG_PKG_USING_CRCLIB is not set
|
||||||
|
# CONFIG_PKG_USING_LWGPS is not set
|
||||||
|
# CONFIG_PKG_USING_STATE_MACHINE is not set
|
||||||
|
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
|
||||||
|
# CONFIG_PKG_USING_CONTROLLER is not set
|
||||||
|
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
|
||||||
|
# CONFIG_PKG_USING_MFBD is not set
|
||||||
|
# CONFIG_PKG_USING_SLCAN2RTT is not set
|
||||||
|
# CONFIG_PKG_USING_SOEM is not set
|
||||||
|
# CONFIG_PKG_USING_QPARAM is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Arduino libraries
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_RTDUINO is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Sensor libraries
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Display libraries
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Timing libraries
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Project libraries
|
||||||
|
#
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
|
||||||
|
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
|
||||||
|
CONFIG_SOC_FAMILY_RENESAS=y
|
||||||
|
CONFIG_SOC_SERIES_R7FA6M3=y
|
||||||
|
# CONFIG_SOC_SERIES_R7FA6M4 is not set
|
||||||
|
# CONFIG_SOC_SERIES_R7FA2L1 is not set
|
||||||
|
# CONFIG_SOC_SERIES_R7FA6M5 is not set
|
||||||
|
# CONFIG_SOC_SERIES_R7FA4M2 is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Hardware Drivers Config
|
||||||
|
#
|
||||||
|
CONFIG_SOC_R7FA6M4AF=y
|
||||||
|
|
||||||
|
#
|
||||||
|
# Onboard Peripheral Drivers
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# On-chip Peripheral Drivers
|
||||||
|
#
|
||||||
|
CONFIG_BSP_USING_GPIO=y
|
||||||
|
# CONFIG_BSP_USING_ONCHIP_FLASH is not set
|
||||||
|
# CONFIG_BSP_USING_WDT is not set
|
||||||
|
# CONFIG_BSP_USING_ONCHIP_RTC is not set
|
||||||
|
CONFIG_BSP_USING_UART=y
|
||||||
|
# CONFIG_BSP_USING_UART4 is not set
|
||||||
|
CONFIG_BSP_USING_UART9=y
|
||||||
|
# CONFIG_BSP_UART9_RX_USING_DMA is not set
|
||||||
|
# CONFIG_BSP_UART9_TX_USING_DMA is not set
|
||||||
|
CONFIG_BSP_UART9_RX_BUFSIZE=256
|
||||||
|
CONFIG_BSP_UART9_TX_BUFSIZE=0
|
||||||
|
# CONFIG_BSP_USING_SPI is not set
|
||||||
|
# CONFIG_BSP_USING_FS is not set
|
||||||
|
# CONFIG_BSP_USING_SDHI is not set
|
||||||
|
# CONFIG_BSP_USING_PWM is not set
|
||||||
|
# CONFIG_BSP_USING_LCD is not set
|
||||||
|
# CONFIG_BSP_USING_SPI_LCD is not set
|
||||||
|
# CONFIG_BSP_USING_G2D is not set
|
||||||
|
# CONFIG_BSP_USING_JPEG is not set
|
||||||
|
# CONFIG_BSP_USING_LVGL is not set
|
||||||
|
|
||||||
|
#
|
||||||
|
# Board extended module Drivers
|
||||||
|
#
|
|
@ -0,0 +1,220 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||||
|
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094">
|
||||||
|
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||||
|
<externalSettings/>
|
||||||
|
<extensions>
|
||||||
|
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||||
|
</extensions>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<configuration artifactExtension="elf" artifactName="rtthread" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
|
||||||
|
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094." name="/" resourcePath="">
|
||||||
|
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1201710416" name="ARM Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.244767666" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1055848773" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.501941135" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.dwarf2" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1696308067" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" useByScannerDiscovery="false" value="GNU Tools for ARM Embedded Processors" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.1558403188" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.749415257" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m4" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.2114153533" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1600865811" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" useByScannerDiscovery="false" value="arm-none-eabi-" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1109963929" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1040883831" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1678200391" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1171840296" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.342604837" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.898269225" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2016398076" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1606171496" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id.540792084" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id" useByScannerDiscovery="false" value="1287942917" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.430121817" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.none" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.966735324" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.hard" valueType="enumerated"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1381561249" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" useByScannerDiscovery="true" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.target.other.2041717463" name="Other target flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.target.other" useByScannerDiscovery="true" value="" valueType="string"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.1463655269" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.fpv4spd16" valueType="enumerated"/>
|
||||||
|
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1798638225" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform"/>
|
||||||
|
<builder buildPath="${workspace_loc:/${ProjName}/Debug" cleanBuildTarget="clean2" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1736709688" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder"/>
|
||||||
|
<tool commandLinePattern="${COMMAND} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.1810966071" name="GNU ARM Cross Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1072524326" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.161242639" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" useByScannerDiscovery="true"/>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1521934876" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true"/>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags.1325367962" name="Assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags" useByScannerDiscovery="false" valueType="stringList">
|
||||||
|
<listOptionValue builtIn="false" value="-mimplicit-it=thumb"/>
|
||||||
|
</option>
|
||||||
|
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other.647856572" name="Other assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.other" useByScannerDiscovery="false" value=" -c -mcpu=cortex-m4 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections -x assembler-with-cpp -Wa,-mimplicit-it=thumb -gdwarf-2" valueType="string"/>
|
||||||
|
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1843333483" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input"/>
|
||||||
|
</tool>
|
||||||
|
<tool commandLinePattern="${COMMAND} ${FLAGS} -c ${OUTPUT_FLAG} ${OUTPUT_PREFIX}${OUTPUT} ${INPUTS}" id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559" name="GNU ARM Cross C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.634882052" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//.}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//board/ports}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//board}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//libraries/HAL_Drivers/config}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//libraries/HAL_Drivers}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra/arm/CMSIS_5/CMSIS/Core/Include}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra/fsp/inc/api}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra/fsp/inc/instances}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra/fsp/inc}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra_cfg/fsp_cfg/bsp}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra_cfg/fsp_cfg}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//ra_gen}""/>
|
||||||
|
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}""/>
|
||||||
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||||||
|
<entry excluding="//board/lvgl|//libraries/HAL_Drivers/drv_adc.c|//libraries/HAL_Drivers/drv_can.c|//libraries/HAL_Drivers/drv_dac.c|//libraries/HAL_Drivers/drv_flash.c|//libraries/HAL_Drivers/drv_i2c.c|//libraries/HAL_Drivers/drv_lcd.c|//libraries/HAL_Drivers/drv_pwm.c|//libraries/HAL_Drivers/drv_rtc.c|//libraries/HAL_Drivers/drv_sci_spi.c|//libraries/HAL_Drivers/drv_sdhi.c|//libraries/HAL_Drivers/drv_soft_i2c.c|//libraries/HAL_Drivers/drv_spi.c|//libraries/HAL_Drivers/drv_wdt.c|//ra/board|//rt-thread/components/dfs|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/can|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/fdt|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/i2c|//rt-thread/components/drivers/misc/adc.c|//rt-thread/components/drivers/misc/dac.c|//rt-thread/components/drivers/misc/pulse_encoder.c|//rt-thread/components/drivers/misc/rt_dev_bus.c|//rt-thread/components/drivers/misc/rt_drv_pwm.c|//rt-thread/components/drivers/misc/rt_inputcapture.c|//rt-thread/components/drivers/misc/rt_null.c|//rt-thread/components/drivers/misc/rt_random.c|//rt-thread/components/drivers/misc/rt_zero.c|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/sensors|//rt-thread/components/drivers/serial/serial.c|//rt-thread/components/drivers/spi|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/tty|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/finsh/msh_file.c|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/net|//rt-thread/components/utilities/resource|//rt-thread/components/utilities/rt-link|//rt-thread/components/utilities/ulog|//rt-thread/components/utilities/utest|//rt-thread/components/utilities/var_export|//rt-thread/components/utilities/ymodem|//rt-thread/components/utilities/zmodem|//rt-thread/components/vbus|//rt-thread/components/vmm|//rt-thread/libcpu/arm/AT91SAM7S|//rt-thread/libcpu/arm/AT91SAM7X|//rt-thread/libcpu/arm/am335x|//rt-thread/libcpu/arm/arm926|//rt-thread/libcpu/arm/armv6|//rt-thread/libcpu/arm/common/divsi3.S|//rt-thread/libcpu/arm/cortex-a|//rt-thread/libcpu/arm/cortex-m0|//rt-thread/libcpu/arm/cortex-m23|//rt-thread/libcpu/arm/cortex-m3|//rt-thread/libcpu/arm/cortex-m33|//rt-thread/libcpu/arm/cortex-m4/context_iar.S|//rt-thread/libcpu/arm/cortex-m4/context_rvds.S|//rt-thread/libcpu/arm/cortex-m7|//rt-thread/libcpu/arm/cortex-r4|//rt-thread/libcpu/arm/dm36x|//rt-thread/libcpu/arm/lpc214x|//rt-thread/libcpu/arm/lpc24xx|//rt-thread/libcpu/arm/realview-a8-vmm|//rt-thread/libcpu/arm/s3c24x0|//rt-thread/libcpu/arm/s3c44b0|//rt-thread/libcpu/arm/sep4020|//rt-thread/libcpu/arm/zynqmp-r5|//rt-thread/src/cpu.c|//rt-thread/src/driver.c|//rt-thread/src/memheap.c|//rt-thread/src/mempool.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//rt-thread/tools" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||||
|
</cconfiguration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<project id="qemu-vexpress-a9.ilg.gnuarmeclipse.managedbuild.cross.target.elf.860020518" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf"/>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="scannerConfiguration">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||||
|
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||||
|
<configuration configurationName="Debug">
|
||||||
|
<resource resourceType="PROJECT" workspacePath="/ra6m3-temp"/>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings">
|
||||||
|
<doc-comment-owner id="org.eclipse.cdt.ui.doxygen">
|
||||||
|
<path value=""/>
|
||||||
|
</doc-comment-owner>
|
||||||
|
</storageModule>
|
||||||
|
</cproject>
|
|
@ -0,0 +1,5 @@
|
||||||
|
/RTE
|
||||||
|
/Listings
|
||||||
|
/Objects
|
||||||
|
ra_cfg.txt
|
||||||
|
|
|
@ -0,0 +1,9 @@
|
||||||
|
# files format check exclude path, please follow the instructions below to modify;
|
||||||
|
# If you need to exclude an entire folder, add the folder path in dir_path;
|
||||||
|
# If you need to exclude a file, add the path to the file in file_path.
|
||||||
|
|
||||||
|
dir_path:
|
||||||
|
- ra
|
||||||
|
- ra_gen
|
||||||
|
- ra_cfg
|
||||||
|
- RTE
|
|
@ -0,0 +1,28 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>ra6m3-temp</name>
|
||||||
|
<comment />
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>org.rt-thread.studio.rttnature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
<linkedResources />
|
||||||
|
</projectDescription>
|
|
@ -0,0 +1,14 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<project>
|
||||||
|
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
|
||||||
|
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1208902908258079360" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||||
|
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||||
|
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||||
|
</provider>
|
||||||
|
</extension>
|
||||||
|
</configuration>
|
||||||
|
</project>
|
|
@ -0,0 +1,3 @@
|
||||||
|
content-types/enabled=true
|
||||||
|
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
|
||||||
|
eclipse.preferences.version=1
|
|
@ -0,0 +1,19 @@
|
||||||
|
#RT-Thread Studio Project Configuration
|
||||||
|
#Tue Jan 10 14:37:39 CST 2023
|
||||||
|
cfg_version=v3.0
|
||||||
|
board_name=ra6m3-ek
|
||||||
|
example_name=
|
||||||
|
hardware_adapter=J-Link
|
||||||
|
board_base_nano_proj=false
|
||||||
|
project_type=rt-thread
|
||||||
|
chip_name=R7FA6M3AH\n
|
||||||
|
selected_rtt_version=latest
|
||||||
|
bsp_version=
|
||||||
|
os_branch=master
|
||||||
|
project_base_rtt_bsp=true
|
||||||
|
output_project_path=E\:softwareRT-ThreadStudioworkspace\ra6m3-temp
|
||||||
|
is_base_example_project=false
|
||||||
|
is_use_scons_build=true
|
||||||
|
project_name=ra6m3-temp
|
||||||
|
os_version=latest
|
||||||
|
bsp_path=
|
|
@ -0,0 +1,90 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="J-Link"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.binFileStartAddress" value=""/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="false"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseEndAddress" value=""/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseMode" value="0"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseStartAddress" value=""/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDeviceName" value="R7FA6M3AH "/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="true"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.forceQuitGdbServer" value="false"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="R7FA6M3AH"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="100000"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLinkGDBServerCL.exe"/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun"/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerRunAfterStopDebug" value="true"/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.jlinkExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLink.exe"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||||
|
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.runAfterDownload" value="true"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||||
|
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||||
|
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||||
|
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="ra6m3-temp"/>
|
||||||
|
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||||
|
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||||
|
<listEntry value="/ra6m3-temp"/>
|
||||||
|
</listAttribute>
|
||||||
|
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||||
|
<listEntry value="4"/>
|
||||||
|
</listAttribute>
|
||||||
|
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||||
|
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||||
|
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||||
|
</launchConfiguration>
|
|
@ -0,0 +1,19 @@
|
||||||
|
#Tue Apr 18 17:25:03 CST 2023
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#fsp\#\#\#\#3.5.0/all=3427620923,ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h|143358381,ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h|2743353138,ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h
|
||||||
|
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.552817864=false
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1728953905,ra/fsp/inc/fsp_features.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2208590403,ra/fsp/inc/instances/r_ioport.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|3297195641,ra/fsp/inc/fsp_version.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2425160085,ra/fsp/inc/api/bsp_api.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|546480625,ra/fsp/inc/fsp_common_api.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#R7FA6M3AH3CFB\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1441545198,ra/arm/CMSIS_5/LICENSE.txt|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/all=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m3\#\#device\#\#\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#3.5.0/libraries=
|
||||||
|
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
|
|
@ -0,0 +1,9 @@
|
||||||
|
<?xml version="1.0" encoding="utf-8"?>
|
||||||
|
|
||||||
|
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||||
|
|
||||||
|
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||||
|
<events>
|
||||||
|
</events>
|
||||||
|
|
||||||
|
</component_viewer>
|
|
@ -0,0 +1,40 @@
|
||||||
|
[BREAKPOINTS]
|
||||||
|
ForceImpTypeAny = 0
|
||||||
|
ShowInfoWin = 1
|
||||||
|
EnableFlashBP = 2
|
||||||
|
BPDuringExecution = 0
|
||||||
|
[CFI]
|
||||||
|
CFISize = 0x00
|
||||||
|
CFIAddr = 0x00
|
||||||
|
[CPU]
|
||||||
|
MonModeVTableAddr = 0xFFFFFFFF
|
||||||
|
MonModeDebug = 0
|
||||||
|
MaxNumAPs = 0
|
||||||
|
LowPowerHandlingMode = 0
|
||||||
|
OverrideMemMap = 0
|
||||||
|
AllowSimulation = 1
|
||||||
|
ScriptFile=""
|
||||||
|
[FLASH]
|
||||||
|
EraseType = 0x00
|
||||||
|
CacheExcludeSize = 0x00
|
||||||
|
CacheExcludeAddr = 0x00
|
||||||
|
MinNumBytesFlashDL = 0
|
||||||
|
SkipProgOnCRCMatch = 1
|
||||||
|
VerifyDownload = 1
|
||||||
|
AllowCaching = 1
|
||||||
|
EnableFlashDL = 2
|
||||||
|
Override = 0
|
||||||
|
Device="ARM7"
|
||||||
|
[GENERAL]
|
||||||
|
WorkRAMSize = 0xA0000
|
||||||
|
WorkRAMAddr = 0x1FFE0000
|
||||||
|
RAMUsageLimit = 0x00
|
||||||
|
[SWO]
|
||||||
|
SWOLogFile=""
|
||||||
|
[MEM]
|
||||||
|
RdOverrideOrMask = 0x00
|
||||||
|
RdOverrideAndMask = 0xFFFFFFFF
|
||||||
|
RdOverrideAddr = 0xFFFFFFFF
|
||||||
|
WrOverrideOrMask = 0x00
|
||||||
|
WrOverrideAndMask = 0xFFFFFFFF
|
||||||
|
WrOverrideAddr = 0xFFFFFFFF
|
|
@ -0,0 +1,29 @@
|
||||||
|
mainmenu "RT-Thread Configuration"
|
||||||
|
|
||||||
|
config BSP_DIR
|
||||||
|
string
|
||||||
|
option env="BSP_ROOT"
|
||||||
|
default "."
|
||||||
|
|
||||||
|
config RTT_DIR
|
||||||
|
string
|
||||||
|
option env="RTT_ROOT"
|
||||||
|
default "../../.."
|
||||||
|
|
||||||
|
# you can change the RTT_ROOT default "../.." to your rtthread_root,
|
||||||
|
# example : default "F:/git_repositories/rt-thread"
|
||||||
|
|
||||||
|
config PKGS_DIR
|
||||||
|
string
|
||||||
|
option env="PKGS_ROOT"
|
||||||
|
default "packages"
|
||||||
|
|
||||||
|
config ENV_DIR
|
||||||
|
string
|
||||||
|
option env="ENV_ROOT"
|
||||||
|
default "/"
|
||||||
|
|
||||||
|
source "$RTT_DIR/Kconfig"
|
||||||
|
source "$PKGS_DIR/Kconfig"
|
||||||
|
source "../libraries/Kconfig"
|
||||||
|
source "$BSP_DIR/board/Kconfig"
|
|
@ -0,0 +1,36 @@
|
||||||
|
<?xml version="1.0" encoding="utf-8"?>
|
||||||
|
<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
|
||||||
|
<v1:pinMappingsRef version="2.03" file="" />
|
||||||
|
<v1:deviceSetting id="renesas.ra6m3_fc" pattern="R7FA6M3****FC">
|
||||||
|
<v1:packageSetting id="renesas.176lqfp" />
|
||||||
|
</v1:deviceSetting>
|
||||||
|
<v1:configSetting configurationId="debug0.mode" altId="debug0.mode.jtag" />
|
||||||
|
<v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
|
||||||
|
<v1:configSetting configurationId="p300" altId="p300.debug0.tck">
|
||||||
|
<v1:connectionSetting altId="debug0.tck.p300" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="debug0.tck" altId="debug0.tck.p300">
|
||||||
|
<v1:connectionSetting altId="p300.debug0.tck" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
|
||||||
|
<v1:configSetting configurationId="p108" altId="p108.debug0.tms">
|
||||||
|
<v1:connectionSetting altId="debug0.tms.p108" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="debug0.tms" altId="debug0.tms.p108">
|
||||||
|
<v1:connectionSetting altId="p108.debug0.tms" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="p109.gpio_mode" altId="p109.gpio_mode.gpio_mode_peripheral" />
|
||||||
|
<v1:configSetting configurationId="p109" altId="p109.debug0.tdo">
|
||||||
|
<v1:connectionSetting altId="debug0.tdo.p109" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="debug0.tdo" altId="debug0.tdo.p109">
|
||||||
|
<v1:connectionSetting altId="p109.debug0.tdo" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="p110.gpio_mode" altId="p110.gpio_mode.gpio_mode_peripheral" />
|
||||||
|
<v1:configSetting configurationId="p110" altId="p110.debug0.tdi">
|
||||||
|
<v1:connectionSetting altId="debug0.tdi.p110" />
|
||||||
|
</v1:configSetting>
|
||||||
|
<v1:configSetting configurationId="debug0.tdi" altId="debug0.tdi.p110">
|
||||||
|
<v1:connectionSetting altId="p110.debug0.tdi" />
|
||||||
|
</v1:configSetting>
|
||||||
|
</v1:pinSettings>
|
|
@ -0,0 +1,145 @@
|
||||||
|
# 瑞萨 RA6M3-HMI-Board 开发板 BSP 说明
|
||||||
|
|
||||||
|
## 简介
|
||||||
|
|
||||||
|
本文档为 RA6M3-HMI-Board 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。
|
||||||
|
|
||||||
|
主要内容如下:
|
||||||
|
|
||||||
|
- 开发板介绍
|
||||||
|
- BSP 快速上手指南
|
||||||
|
|
||||||
|
## 开发板介绍
|
||||||
|
|
||||||
|
基于瑞萨 RA6M3 MCU 开发的 EK-RA6M3 MCU 评估板,通过灵活配置软件包和 IDE,可帮助用户对 RA6M3 MCU 群组的特性轻松进行评估,并对嵌入系统应用程序进行开发。
|
||||||
|
|
||||||
|
开发板正面外观如下图:
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
该开发板常用 **板载资源** 如下:
|
||||||
|
|
||||||
|
- MCU:R7FA6M3AH,120MHz,Arm Cortex®-M4 内核,2MB 代码闪存, 640KB SRAM
|
||||||
|
- 调试接口:板载 J-Link 接口
|
||||||
|
- 扩展接口:两个 PMOD 连接器
|
||||||
|
|
||||||
|
**更多详细资料及工具**
|
||||||
|
|
||||||
|
## 外设支持
|
||||||
|
|
||||||
|
本 BSP 目前对外设的支持情况如下:
|
||||||
|
|
||||||
|
| **片上外设** | **支持情况** | **备注** |
|
||||||
|
| :----------------- | :----------------- | :------------- |
|
||||||
|
| UART | 支持 | UART9 为默认日志输出端口 |
|
||||||
|
| GPIO | 支持 | |
|
||||||
|
| LCD | 支持 | |
|
||||||
|
|
||||||
|
* 注意:仓库刚拉下来是最小系统,若需添加/使能其他外设需参考:[外设驱动使用教程 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列BSP外设驱动使用教程)
|
||||||
|
|
||||||
|
## 使用说明
|
||||||
|
|
||||||
|
使用说明分为如下两个章节:
|
||||||
|
|
||||||
|
- 快速上手
|
||||||
|
|
||||||
|
本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
|
||||||
|
- 进阶使用
|
||||||
|
|
||||||
|
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
|
||||||
|
|
||||||
|
### 快速上手
|
||||||
|
|
||||||
|
本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
|
||||||
|
|
||||||
|
**硬件连接**
|
||||||
|
|
||||||
|
使用 USB 数据线连接开发板到 PC,使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART7:P401(TXD)、P402(RXD)。
|
||||||
|
|
||||||
|
**编译下载**
|
||||||
|
|
||||||
|
- 编译:双击 project.uvprojx 文件,打开 MDK5 工程,编译程序。
|
||||||
|
|
||||||
|
- 下载:点击 MDK 的 Debug 按钮进行下载调试
|
||||||
|
|
||||||
|
**查看运行结果**
|
||||||
|
|
||||||
|
下载程序成功之后,系统会自动运行并打印系统信息。
|
||||||
|
|
||||||
|
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
|
||||||
|
|
||||||
|
```bash
|
||||||
|
\ | /
|
||||||
|
- RT - Thread Operating System
|
||||||
|
/ | \ 5.0.0 build Jan 4 2023 10:14:56
|
||||||
|
2006 - 2022 Copyright by RT-Thread team
|
||||||
|
Hello RT-Thread!
|
||||||
|
msh >
|
||||||
|
msh >help
|
||||||
|
help - RT-Thread shell help.
|
||||||
|
ps - List threads in the system.
|
||||||
|
free - Show the memory usage in the system.
|
||||||
|
clear - clear the terminal screen
|
||||||
|
version - show RT-Thread version information
|
||||||
|
list - list objects
|
||||||
|
|
||||||
|
msh >
|
||||||
|
```
|
||||||
|
|
||||||
|
**应用入口函数**
|
||||||
|
|
||||||
|
应用层的入口函数在 **bsp\ra6m3-ek\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
|
||||||
|
|
||||||
|
```c
|
||||||
|
void hal_entry(void)
|
||||||
|
{
|
||||||
|
rt_kprintf("\nHello RT-Thread!\n");
|
||||||
|
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
rt_pin_write(LED3_PIN, PIN_HIGH);
|
||||||
|
rt_thread_mdelay(500);
|
||||||
|
rt_pin_write(LED3_PIN, PIN_LOW);
|
||||||
|
rt_thread_mdelay(500);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
```
|
||||||
|
|
||||||
|
### 进阶使用
|
||||||
|
|
||||||
|
**资料及文档**
|
||||||
|
|
||||||
|
- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra6m4-evaluation-board)
|
||||||
|
- [开发板用户手册](https://www2.renesas.cn/cn/zh/document/mah/1527156?language=zh&r=1527191)
|
||||||
|
- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
|
||||||
|
- [RA6 MCU 快速设计指南](https://www2.renesas.cn/cn/zh/document/apn/ra6-quick-design-guide)
|
||||||
|
|
||||||
|
**FSP 配置**
|
||||||
|
|
||||||
|
需要修改瑞萨的 BSP 外设配置或添加新的外设端口,需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
|
||||||
|
|
||||||
|
1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp),请使用 FSP 3.5.0 版本
|
||||||
|
2. 下载安装完成后,需要添加 EK-RA6M3 开发板的官方板级支持包
|
||||||
|
> 打开[ EK-RA6M3 开发板详情页](https://www.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m3-evaluation-kit-ra6m3-mcu-group#document),在 **“下载”** 列表中找到 **” EK-RA6M3板级支持包“** ,点击链接即可下载
|
||||||
|
3. 如何将 **”EK-RA6M3板级支持包“**添加到 FSP 中,请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
|
||||||
|
4. 请查看文档:[使用 FSP 配置外设驱动](../docs/RA系列使用FSP配置外设驱动.md),在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
|
||||||
|
|
||||||
|
**ENV 配置**
|
||||||
|
|
||||||
|
- 如何使用 ENV 工具:[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
|
||||||
|
|
||||||
|
此 BSP 默认只开启了 UART7 的功能,如果需使用更多高级功能例如组件、软件包等,需要利用 ENV 工具进行配置。
|
||||||
|
|
||||||
|
步骤如下:
|
||||||
|
1. 在 bsp 下打开 env 工具。
|
||||||
|
2. 输入`menuconfig`命令配置工程,配置好之后保存退出。
|
||||||
|
3. 输入`pkgs --update`命令更新软件包。
|
||||||
|
4. 输入`scons --target=mdk5` 命令重新生成工程。
|
||||||
|
|
||||||
|
## 联系人信息
|
||||||
|
|
||||||
|
在使用过程中若您有任何的想法和建议,建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
|
||||||
|
|
||||||
|
## 贡献代码
|
||||||
|
|
||||||
|
如果您对 EK-RA6M3 感兴趣,并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码,您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
|
|
@ -0,0 +1,27 @@
|
||||||
|
# for module compiling
|
||||||
|
import os
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
Import('rtconfig')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
src = []
|
||||||
|
CPPPATH = []
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM in ['iccarm']:
|
||||||
|
print("\nThe current project does not support IAR build\n")
|
||||||
|
Return('group')
|
||||||
|
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||||
|
if GetOption('target') != 'mdk5':
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
src = Glob('./src/*.c')
|
||||||
|
|
||||||
|
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
for d in list:
|
||||||
|
path = os.path.join(cwd, d)
|
||||||
|
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||||
|
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||||
|
|
||||||
|
Return('group')
|
|
@ -0,0 +1,54 @@
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
import rtconfig
|
||||||
|
|
||||||
|
if os.getenv('RTT_ROOT'):
|
||||||
|
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||||
|
else:
|
||||||
|
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||||
|
|
||||||
|
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||||
|
try:
|
||||||
|
from building import *
|
||||||
|
except:
|
||||||
|
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||||
|
print(RTT_ROOT)
|
||||||
|
exit(-1)
|
||||||
|
|
||||||
|
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||||
|
|
||||||
|
DefaultEnvironment(tools=[])
|
||||||
|
env = Environment(tools = ['mingw'],
|
||||||
|
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||||
|
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||||
|
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||||
|
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||||
|
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM in ['iccarm']:
|
||||||
|
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||||
|
env.Replace(ARFLAGS = [''])
|
||||||
|
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
|
||||||
|
|
||||||
|
Export('RTT_ROOT')
|
||||||
|
Export('rtconfig')
|
||||||
|
|
||||||
|
SDK_ROOT = os.path.abspath('./')
|
||||||
|
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||||
|
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||||
|
else:
|
||||||
|
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||||
|
|
||||||
|
SDK_LIB = libraries_path_prefix
|
||||||
|
Export('SDK_LIB')
|
||||||
|
|
||||||
|
rtconfig.BSP_LIBRARY_TYPE = None
|
||||||
|
|
||||||
|
# prepare building environment
|
||||||
|
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||||
|
|
||||||
|
# include drivers
|
||||||
|
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
|
||||||
|
|
||||||
|
# make a building
|
||||||
|
DoBuilding(TARGET, objs)
|
|
@ -0,0 +1,196 @@
|
||||||
|
menu "Hardware Drivers Config"
|
||||||
|
|
||||||
|
config SOC_R7FA6M4AF
|
||||||
|
bool
|
||||||
|
select SOC_SERIES_R7FA6M3
|
||||||
|
select RT_USING_COMPONENTS_INIT
|
||||||
|
select RT_USING_USER_MAIN
|
||||||
|
default y
|
||||||
|
|
||||||
|
menu "Onboard Peripheral Drivers"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
menu "On-chip Peripheral Drivers"
|
||||||
|
|
||||||
|
source "../libraries/HAL_Drivers/Kconfig"
|
||||||
|
|
||||||
|
menuconfig BSP_USING_UART
|
||||||
|
bool "Enable UART"
|
||||||
|
default y
|
||||||
|
select RT_USING_SERIAL
|
||||||
|
select RT_USING_SERIAL_V2
|
||||||
|
if BSP_USING_UART
|
||||||
|
menuconfig BSP_USING_UART4
|
||||||
|
bool "Enable UART4"
|
||||||
|
default n
|
||||||
|
if BSP_USING_UART4
|
||||||
|
config BSP_UART4_RX_USING_DMA
|
||||||
|
bool "Enable UART4 RX DMA"
|
||||||
|
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART4_TX_USING_DMA
|
||||||
|
bool "Enable UART4 TX DMA"
|
||||||
|
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART4_RX_BUFSIZE
|
||||||
|
int "Set UART4 RX buffer size"
|
||||||
|
range 64 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
|
config BSP_UART4_TX_BUFSIZE
|
||||||
|
int "Set UART4 TX buffer size"
|
||||||
|
range 0 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 0
|
||||||
|
endif
|
||||||
|
menuconfig BSP_USING_UART9
|
||||||
|
bool "Enable UART9"
|
||||||
|
default n
|
||||||
|
if BSP_USING_UART9
|
||||||
|
config BSP_UART9_RX_USING_DMA
|
||||||
|
bool "Enable UART9 RX DMA"
|
||||||
|
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART9_TX_USING_DMA
|
||||||
|
bool "Enable UART9 TX DMA"
|
||||||
|
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_UART9_RX_BUFSIZE
|
||||||
|
int "Set UART9 RX buffer size"
|
||||||
|
range 64 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 256
|
||||||
|
|
||||||
|
config BSP_UART9_TX_BUFSIZE
|
||||||
|
int "Set UART9 TX buffer size"
|
||||||
|
range 0 65535
|
||||||
|
depends on RT_USING_SERIAL_V2
|
||||||
|
default 0
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_SPI
|
||||||
|
bool "Enable SPI BUS"
|
||||||
|
default n
|
||||||
|
select RT_USING_SPI
|
||||||
|
if BSP_USING_SPI
|
||||||
|
config BSP_USING_SPI0
|
||||||
|
bool "Enable SPI0 BUS"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_SPI1
|
||||||
|
bool "Enable SPI1 BUS"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_SCI_SPI0
|
||||||
|
bool "Enable SCI SPI0 BUS"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_SCI_SPI6
|
||||||
|
bool "Enable SCI SPI6 BUS"
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_FS
|
||||||
|
bool "Enable filesystem"
|
||||||
|
default n
|
||||||
|
if BSP_USING_FS
|
||||||
|
config BSP_USING_SDCARD_FS
|
||||||
|
bool "Enable SDCARD filesystem"
|
||||||
|
select BSP_USING_SDHI
|
||||||
|
select RT_USING_DFS_ELMFAT
|
||||||
|
default n
|
||||||
|
config BSP_USING_SPICARD_FS
|
||||||
|
bool "Enable SPI FLASH filesystem"
|
||||||
|
select BSP_USING_SPI
|
||||||
|
select BSP_USING_SCI_SPI6
|
||||||
|
select RT_USING_SPI_MSD
|
||||||
|
select RT_USING_DFS_ELMFAT
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_SDHI
|
||||||
|
bool "Enable SDHI"
|
||||||
|
default n
|
||||||
|
select RT_USING_SDIO
|
||||||
|
select RT_USING_DFS
|
||||||
|
select RT_LIBC_USING_FILEIO
|
||||||
|
select RT_USING_POSIX_DEVIO
|
||||||
|
if BSP_USING_SDHI
|
||||||
|
config SDHI_USING_1_BIT
|
||||||
|
bool "Use 1-bit Mode(4-bit when disable)"
|
||||||
|
default y
|
||||||
|
endif
|
||||||
|
|
||||||
|
menuconfig BSP_USING_PWM
|
||||||
|
bool "Enable PWM"
|
||||||
|
default n
|
||||||
|
select RT_USING_PWM
|
||||||
|
if BSP_USING_PWM
|
||||||
|
config BSP_USING_PWM12
|
||||||
|
bool "Enable GPT12 (16-Bits) output PWM"
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
config BSP_USING_LCD
|
||||||
|
bool "Enable LCD"
|
||||||
|
select BSP_USING_GPIO
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_SPI_LCD
|
||||||
|
bool "Enable SPI LCD"
|
||||||
|
select BSP_USING_GPIO
|
||||||
|
select BSP_USING_SPI
|
||||||
|
select BSP_USING_SPI0
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_G2D
|
||||||
|
bool "Enable G2D"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_JPEG
|
||||||
|
bool "Enable JPEG"
|
||||||
|
default n
|
||||||
|
|
||||||
|
config BSP_USING_ETH
|
||||||
|
bool "Enable Ethernet"
|
||||||
|
select RT_USING_SAL
|
||||||
|
select RT_USING_LWIP
|
||||||
|
select RT_USING_NETDEV
|
||||||
|
default n
|
||||||
|
|
||||||
|
menuconfig BSP_USING_LVGL
|
||||||
|
bool "Enable LVGL for LCD"
|
||||||
|
select PKG_USING_LVGL
|
||||||
|
default n
|
||||||
|
if BSP_USING_LVGL
|
||||||
|
config BSP_USING_LCD_ILI9431
|
||||||
|
bool "Enable LVGL for LCD_ILI9431"
|
||||||
|
select PKG_USING_ILI9341
|
||||||
|
select BSP_USING_SPI_LCD
|
||||||
|
default n
|
||||||
|
config BSP_USING_LCD_RGB
|
||||||
|
bool "Enable LVGL for LCD_RGB565"
|
||||||
|
select BSP_USING_LCD
|
||||||
|
default n
|
||||||
|
endif
|
||||||
|
|
||||||
|
if BSP_USING_LVGL
|
||||||
|
config BSP_USING_LVGL_DEMO
|
||||||
|
bool "Enable LVGL demo"
|
||||||
|
select PKG_USING_LV_MUSIC_DEMO
|
||||||
|
default y
|
||||||
|
endif
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
|
||||||
|
menu "Board extended module Drivers"
|
||||||
|
|
||||||
|
endmenu
|
||||||
|
endmenu
|
|
@ -0,0 +1,16 @@
|
||||||
|
import os
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
objs = []
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
src = Glob('*.c')
|
||||||
|
|
||||||
|
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
for item in list:
|
||||||
|
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||||
|
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||||
|
|
||||||
|
Return('objs')
|
|
@ -0,0 +1,38 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-10-10 Sherman first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __BOARD_H__
|
||||||
|
#define __BOARD_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define RA_SRAM_SIZE 640 /* The SRAM size of the chip needs to be modified */
|
||||||
|
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
|
||||||
|
|
||||||
|
#ifdef __ARMCC_VERSION
|
||||||
|
extern int Image$$RAM_END$$ZI$$Base;
|
||||||
|
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
|
||||||
|
#elif __ICCARM__
|
||||||
|
#pragma section="CSTACK"
|
||||||
|
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||||
|
#else
|
||||||
|
extern int __RAM_segment_used_end__;
|
||||||
|
#define HEAP_BEGIN (&__RAM_segment_used_end__)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define HEAP_END RA_SRAM_END
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,16 @@
|
||||||
|
from building import *
|
||||||
|
import os
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
group = []
|
||||||
|
src = Glob('*.c')
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
for d in list:
|
||||||
|
path = os.path.join(cwd, d)
|
||||||
|
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||||
|
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||||
|
|
||||||
|
group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH)
|
||||||
|
Return('group')
|
|
@ -0,0 +1,17 @@
|
||||||
|
from building import *
|
||||||
|
import os
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
group = []
|
||||||
|
src = Glob('*.c')
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
for d in list:
|
||||||
|
path = os.path.join(cwd, d)
|
||||||
|
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||||
|
group = group + SConscript(os.path.join(d, 'SConscript'))
|
||||||
|
|
||||||
|
group = group + DefineGroup('LVGL-demo', src, depend = ['BSP_USING_LVGL', 'BSP_USING_LVGL_DEMO'], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
Return('group')
|
|
@ -0,0 +1,17 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-10-17 Meco Man First version
|
||||||
|
* 2022-05-10 Meco Man improve rt-thread initialization process
|
||||||
|
*/
|
||||||
|
|
||||||
|
void lv_user_gui_init(void)
|
||||||
|
{
|
||||||
|
/* display demo; you may replace with your LVGL application at here */
|
||||||
|
extern void lv_demo_music(void);
|
||||||
|
lv_demo_music();
|
||||||
|
}
|
|
@ -0,0 +1,48 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2023-02-22 Rbb666 First version
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef LV_CONF_H
|
||||||
|
#define LV_CONF_H
|
||||||
|
|
||||||
|
#include <rtconfig.h>
|
||||||
|
|
||||||
|
/* Enable additional color format support */
|
||||||
|
#define DLG_LVGL_CF 1
|
||||||
|
|
||||||
|
/* Enable sub byte color formats to be swapped. If disabled, which is recommended for
|
||||||
|
* performance, bitmaps need to be in correct order */
|
||||||
|
#define DLG_LVGL_CF_SUB_BYTE_SWAP 0
|
||||||
|
|
||||||
|
#define LV_USE_PERF_MONITOR 1
|
||||||
|
#define LV_COLOR_DEPTH 16
|
||||||
|
|
||||||
|
#ifdef PKG_USING_ILI9341
|
||||||
|
#define LV_HOR_RES_MAX 240
|
||||||
|
#define LV_VER_RES_MAX 320
|
||||||
|
#define LV_COLOR_16_SWAP 1
|
||||||
|
#define LV_DPI_DEF 99
|
||||||
|
#else
|
||||||
|
#define LV_HOR_RES_MAX 480
|
||||||
|
#define LV_VER_RES_MAX 272
|
||||||
|
#define LV_DPI_DEF 89
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DLG_LVGL_USE_GPU_RA6M3 0
|
||||||
|
|
||||||
|
#ifdef PKG_USING_LV_MUSIC_DEMO
|
||||||
|
/* music player demo */
|
||||||
|
#define LV_USE_DEMO_RTT_MUSIC 1
|
||||||
|
#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
|
||||||
|
#define LV_FONT_MONTSERRAT_12 1
|
||||||
|
#define LV_FONT_MONTSERRAT_16 1
|
||||||
|
#define LV_COLOR_SCREEN_TRANSP 0
|
||||||
|
#endif /* PKG_USING_LV_MUSIC_DEMO */
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,141 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-11-24 Rbb666 The first version
|
||||||
|
*/
|
||||||
|
#include <lvgl.h>
|
||||||
|
#include "hal_data.h"
|
||||||
|
|
||||||
|
#if DLG_LVGL_USE_GPU_RA6M3
|
||||||
|
#include "lv_port_gpu.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef PKG_USING_ILI9341
|
||||||
|
#include "lcd_ili9341.h"
|
||||||
|
#else
|
||||||
|
#include "lcd_port.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define COLOR_BUFFER (LV_HOR_RES_MAX * LV_VER_RES_MAX / 4)
|
||||||
|
|
||||||
|
/*A static or global variable to store the buffers*/
|
||||||
|
static lv_disp_draw_buf_t disp_buf;
|
||||||
|
|
||||||
|
/*Descriptor of a display driver*/
|
||||||
|
static lv_disp_drv_t disp_drv;
|
||||||
|
static struct rt_device_graphic_info info;
|
||||||
|
|
||||||
|
/*Static or global buffer(s). The second buffer is optional*/
|
||||||
|
// 0x1FFE0000 0x20040000
|
||||||
|
__attribute__((section(".ARM.__at_0x1FFE0000"))) lv_color_t buf_1[COLOR_BUFFER];
|
||||||
|
|
||||||
|
#if !DLG_LVGL_USE_GPU_RA6M3
|
||||||
|
static void color_to16_maybe(lv_color16_t *dst, lv_color_t *src)
|
||||||
|
{
|
||||||
|
#if (LV_COLOR_DEPTH == 16)
|
||||||
|
dst->full = src->full;
|
||||||
|
#else
|
||||||
|
dst->ch.blue = src->ch.blue;
|
||||||
|
dst->ch.green = src->ch.green;
|
||||||
|
dst->ch.red = src->ch.red;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void disp_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
|
||||||
|
{
|
||||||
|
#ifdef PKG_USING_ILI9341
|
||||||
|
lcd_fill_array_spi(area->x1, area->y1, area->x2, area->y2, color_p);
|
||||||
|
#elif DLG_LVGL_USE_GPU_RA6M3
|
||||||
|
lv_port_gpu_flush();
|
||||||
|
#else
|
||||||
|
int x1, x2, y1, y2;
|
||||||
|
|
||||||
|
x1 = area->x1;
|
||||||
|
x2 = area->x2;
|
||||||
|
y1 = area->y1;
|
||||||
|
y2 = area->y2;
|
||||||
|
|
||||||
|
/*Return if the area is out the screen*/
|
||||||
|
if (x2 < 0)
|
||||||
|
return;
|
||||||
|
if (y2 < 0)
|
||||||
|
return;
|
||||||
|
if (x1 > info.width - 1)
|
||||||
|
return;
|
||||||
|
if (y1 > info.height - 1)
|
||||||
|
return;
|
||||||
|
|
||||||
|
/*Truncate the area to the screen*/
|
||||||
|
int32_t act_x1 = x1 < 0 ? 0 : x1;
|
||||||
|
int32_t act_y1 = y1 < 0 ? 0 : y1;
|
||||||
|
int32_t act_x2 = x2 > info.width - 1 ? info.width - 1 : x2;
|
||||||
|
int32_t act_y2 = y2 > info.height - 1 ? info.height - 1 : y2;
|
||||||
|
|
||||||
|
uint32_t x;
|
||||||
|
uint32_t y;
|
||||||
|
long int location = 0;
|
||||||
|
|
||||||
|
/* color_p is a buffer pointer; the buffer is provided by LVGL */
|
||||||
|
lv_color16_t *fbp16 = (lv_color16_t *)info.framebuffer;
|
||||||
|
|
||||||
|
for (y = act_y1; y <= act_y2; y++)
|
||||||
|
{
|
||||||
|
for (x = act_x1; x <= act_x2; x++)
|
||||||
|
{
|
||||||
|
location = (x) + (y) * info.width;
|
||||||
|
color_to16_maybe(&fbp16[location], color_p);
|
||||||
|
color_p++;
|
||||||
|
}
|
||||||
|
|
||||||
|
color_p += x2 - act_x2;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
lv_disp_flush_ready(disp_drv);
|
||||||
|
}
|
||||||
|
|
||||||
|
void lv_port_disp_init(void)
|
||||||
|
{
|
||||||
|
#ifdef PKG_USING_ILI9341
|
||||||
|
spi_lcd_init(20);
|
||||||
|
#else
|
||||||
|
static rt_device_t device;
|
||||||
|
/* LCD Device Init */
|
||||||
|
device = rt_device_find("lcd");
|
||||||
|
RT_ASSERT(device != RT_NULL);
|
||||||
|
|
||||||
|
if (rt_device_open(device, RT_DEVICE_OFLAG_RDWR) == RT_EOK)
|
||||||
|
{
|
||||||
|
rt_device_control(device, RTGRAPHIC_CTRL_GET_INFO, &info);
|
||||||
|
}
|
||||||
|
|
||||||
|
RT_ASSERT(info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
|
||||||
|
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
|
||||||
|
#endif
|
||||||
|
/*Initialize `disp_buf` with the buffer(s). With only one buffer use NULL instead buf_2 */
|
||||||
|
lv_disp_draw_buf_init(&disp_buf, buf_1, NULL, COLOR_BUFFER);
|
||||||
|
|
||||||
|
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
|
||||||
|
|
||||||
|
/*Set the resolution of the display*/
|
||||||
|
disp_drv.hor_res = LV_HOR_RES_MAX;
|
||||||
|
disp_drv.ver_res = LV_VER_RES_MAX;
|
||||||
|
|
||||||
|
/*Set a display buffer*/
|
||||||
|
disp_drv.draw_buf = &disp_buf;
|
||||||
|
|
||||||
|
/*Used to copy the buffer's content to the display*/
|
||||||
|
disp_drv.flush_cb = disp_flush;
|
||||||
|
|
||||||
|
#if DLG_LVGL_USE_GPU_RA6M3
|
||||||
|
/* Initialize GPU module */
|
||||||
|
lv_port_gpu_init();
|
||||||
|
#endif /* LV_PORT_DISP_GPU_EN */
|
||||||
|
|
||||||
|
/*Finally register the driver*/
|
||||||
|
lv_disp_drv_register(&disp_drv);
|
||||||
|
}
|
|
@ -0,0 +1,15 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2021-10-18 Meco Man The first version
|
||||||
|
*/
|
||||||
|
#include <lvgl.h>
|
||||||
|
#include <rtdevice.h>
|
||||||
|
|
||||||
|
void lv_port_indev_init(void)
|
||||||
|
{
|
||||||
|
}
|
|
@ -0,0 +1,16 @@
|
||||||
|
import os
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
src = []
|
||||||
|
objs = []
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
CPPPATH = [cwd]
|
||||||
|
|
||||||
|
objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
|
||||||
|
list = os.listdir(cwd)
|
||||||
|
for item in list:
|
||||||
|
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||||
|
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||||
|
|
||||||
|
Return('objs')
|
|
@ -0,0 +1,82 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2022-01-19 Sherman first version
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Number of IRQ channels on the device */
|
||||||
|
#define RA_IRQ_MAX 16
|
||||||
|
|
||||||
|
/* PIN to IRQx table */
|
||||||
|
#define PIN2IRQX_TABLE \
|
||||||
|
{ \
|
||||||
|
switch (pin) \
|
||||||
|
{ \
|
||||||
|
case BSP_IO_PORT_04_PIN_00: \
|
||||||
|
case BSP_IO_PORT_02_PIN_06: \
|
||||||
|
case BSP_IO_PORT_01_PIN_05: \
|
||||||
|
return 0; \
|
||||||
|
case BSP_IO_PORT_02_PIN_05: \
|
||||||
|
case BSP_IO_PORT_01_PIN_01: \
|
||||||
|
case BSP_IO_PORT_01_PIN_04: \
|
||||||
|
return 1; \
|
||||||
|
case BSP_IO_PORT_02_PIN_03: \
|
||||||
|
case BSP_IO_PORT_01_PIN_00: \
|
||||||
|
case BSP_IO_PORT_02_PIN_13: \
|
||||||
|
return 2; \
|
||||||
|
case BSP_IO_PORT_02_PIN_02: \
|
||||||
|
case BSP_IO_PORT_01_PIN_10: \
|
||||||
|
case BSP_IO_PORT_02_PIN_12: \
|
||||||
|
return 3; \
|
||||||
|
case BSP_IO_PORT_04_PIN_02: \
|
||||||
|
case BSP_IO_PORT_01_PIN_11: \
|
||||||
|
case BSP_IO_PORT_04_PIN_11: \
|
||||||
|
return 4; \
|
||||||
|
case BSP_IO_PORT_04_PIN_01: \
|
||||||
|
case BSP_IO_PORT_03_PIN_02: \
|
||||||
|
case BSP_IO_PORT_04_PIN_10: \
|
||||||
|
return 5; \
|
||||||
|
case BSP_IO_PORT_03_PIN_01: \
|
||||||
|
case BSP_IO_PORT_00_PIN_00: \
|
||||||
|
case BSP_IO_PORT_04_PIN_09: \
|
||||||
|
return 6; \
|
||||||
|
case BSP_IO_PORT_00_PIN_01: \
|
||||||
|
case BSP_IO_PORT_04_PIN_08: \
|
||||||
|
return 7; \
|
||||||
|
case BSP_IO_PORT_00_PIN_02: \
|
||||||
|
case BSP_IO_PORT_03_PIN_05: \
|
||||||
|
case BSP_IO_PORT_04_PIN_15: \
|
||||||
|
return 8; \
|
||||||
|
case BSP_IO_PORT_00_PIN_04: \
|
||||||
|
case BSP_IO_PORT_03_PIN_04: \
|
||||||
|
case BSP_IO_PORT_04_PIN_14: \
|
||||||
|
return 9; \
|
||||||
|
case BSP_IO_PORT_00_PIN_05: \
|
||||||
|
case BSP_IO_PORT_07_PIN_09: \
|
||||||
|
return 10; \
|
||||||
|
case BSP_IO_PORT_05_PIN_01: \
|
||||||
|
case BSP_IO_PORT_00_PIN_06: \
|
||||||
|
case BSP_IO_PORT_07_PIN_08: \
|
||||||
|
return 11; \
|
||||||
|
case BSP_IO_PORT_05_PIN_02: \
|
||||||
|
case BSP_IO_PORT_00_PIN_08: \
|
||||||
|
return 12; \
|
||||||
|
case BSP_IO_PORT_00_PIN_15: \
|
||||||
|
case BSP_IO_PORT_00_PIN_09: \
|
||||||
|
return 13; \
|
||||||
|
case BSP_IO_PORT_04_PIN_03: \
|
||||||
|
case BSP_IO_PORT_05_PIN_12: \
|
||||||
|
case BSP_IO_PORT_05_PIN_05: \
|
||||||
|
return 14; \
|
||||||
|
case BSP_IO_PORT_04_PIN_04: \
|
||||||
|
case BSP_IO_PORT_05_PIN_11: \
|
||||||
|
case BSP_IO_PORT_05_PIN_06: \
|
||||||
|
return 15; \
|
||||||
|
default : \
|
||||||
|
return -1; \
|
||||||
|
} \
|
||||||
|
}
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Change Logs:
|
||||||
|
* Date Author Notes
|
||||||
|
* 2018-07-28 liu2guang the first version for STM32F469NI-Discovery.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DRV_LCD_H_
|
||||||
|
#define __DRV_LCD_H_
|
||||||
|
|
||||||
|
#include <rtthread.h>
|
||||||
|
#include <rtdevice.h>
|
||||||
|
#include <board.h>
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
ROTATION_ZERO = 0,
|
||||||
|
ROTATION_090 = 90,
|
||||||
|
ROTATION_180 = 180,
|
||||||
|
ROTATION_270 = 270,
|
||||||
|
} bsp_rotation;
|
||||||
|
|
||||||
|
#define LCD_WIDTH DISPLAY_HSIZE_INPUT0
|
||||||
|
#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0
|
||||||
|
#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1
|
||||||
|
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
|
||||||
|
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)
|
||||||
|
|
||||||
|
#define LCD_BL_PIN BSP_IO_PORT_06_PIN_03
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,159 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
|
||||||
|
<vendor>Renesas</vendor>
|
||||||
|
<name>Project Content</name>
|
||||||
|
<description>Project content managed by the Renesas Smart Configurator</description>
|
||||||
|
<url/>
|
||||||
|
<releases>
|
||||||
|
<release version="1.0.0"/>
|
||||||
|
</releases>
|
||||||
|
<generators>
|
||||||
|
<generator id="Renesas RA Smart Configurator">
|
||||||
|
<project_files>
|
||||||
|
<file category="include" name="src/"/>
|
||||||
|
<file category="source" name="src/hal_entry.c"/>
|
||||||
|
</project_files>
|
||||||
|
</generator>
|
||||||
|
</generators>
|
||||||
|
<components generator="Renesas RA Smart Configurator">
|
||||||
|
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
|
||||||
|
<files>
|
||||||
|
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
|
||||||
|
<file category="include" name="ra/fsp/inc/"/>
|
||||||
|
<file category="include" name="ra/fsp/inc/api/"/>
|
||||||
|
<file category="include" name="ra/fsp/inc/instances/"/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
|
||||||
|
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
|
||||||
|
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
|
||||||
|
<file category="header" name="ra/board/ra6m3/board.h" path=""/>
|
||||||
|
<file category="header" name="ra/board/ra6m3/board_ethernet_phy.h" path=""/>
|
||||||
|
<file category="source" name="ra/board/ra6m3/board_init.c"/>
|
||||||
|
<file category="header" name="ra/board/ra6m3/board_init.h" path=""/>
|
||||||
|
<file category="source" name="ra/board/ra6m3/board_leds.c"/>
|
||||||
|
<file category="header" name="ra/board/ra6m3/board_leds.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/instances/r_glcdc.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
|
||||||
|
<file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_elc.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h" path=""/>
|
||||||
|
<file category="header" name="ra/fsp/src/bsp/mcu/ra6m3/bsp_mcu_info.h" path=""/>
|
||||||
|
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
|
||||||
|
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
|
||||||
|
<file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
|
||||||
|
<file category="other" name="ra/SConscript"/>
|
||||||
|
</files>
|
||||||
|
</component>
|
||||||
|
<component Cclass="Flex Software" Cgroup="Build Configuration">
|
||||||
|
<files>
|
||||||
|
<file category="include" name="ra_cfg/fsp_cfg/"/>
|
||||||
|
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
|
||||||
|
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
|
||||||
|
<file category="other" name="ra_cfg/SConscript"/>
|
||||||
|
</files>
|
||||||
|
</component>
|
||||||
|
<component Cclass="Flex Software" Cgroup="Generated Data">
|
||||||
|
<files>
|
||||||
|
<file category="include" name="ra_gen/"/>
|
||||||
|
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
|
||||||
|
<file category="source" name="ra_gen/common_data.c"/>
|
||||||
|
<file category="header" name="ra_gen/common_data.h" path=""/>
|
||||||
|
<file category="source" name="ra_gen/hal_data.c"/>
|
||||||
|
<file category="header" name="ra_gen/hal_data.h" path=""/>
|
||||||
|
<file category="source" name="ra_gen/main.c"/>
|
||||||
|
<file category="source" name="ra_gen/pin_data.c"/>
|
||||||
|
<file category="other" name="ra_gen/SConscript"/>
|
||||||
|
<file category="source" name="ra_gen/vector_data.c"/>
|
||||||
|
<file category="header" name="ra_gen/vector_data.h" path=""/>
|
||||||
|
</files>
|
||||||
|
</component>
|
||||||
|
<component Cclass="Flex Software" Cgroup="Linker Script">
|
||||||
|
<files>
|
||||||
|
<file category="linkerScript" name="script/fsp.scat"/>
|
||||||
|
<file category="other" name="script/ac6/fsp_keep.via"/>
|
||||||
|
</files>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
</package>
|
|
@ -0,0 +1,238 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<raConfiguration version="7">
|
||||||
|
<generalSettings>
|
||||||
|
<option key="#Board#" value="board.custom"/>
|
||||||
|
<option key="CPU" value="RA6M3"/>
|
||||||
|
<option key="#TargetName#" value="R7FA6M3AH3CFB"/>
|
||||||
|
<option key="#TargetARCHITECTURE#" value="cortex-m4"/>
|
||||||
|
<option key="#DeviceCommand#" value="R7FA6M3AH"/>
|
||||||
|
<option key="#RTOS#" value="_none"/>
|
||||||
|
<option key="#pinconfiguration#" value="R7FA6M3AH3CFB.pincfg"/>
|
||||||
|
<option key="#FSPVersion#" value="3.5.0"/>
|
||||||
|
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
|
||||||
|
</generalSettings>
|
||||||
|
<raBspConfiguration>
|
||||||
|
<config id="config.bsp.ra6m3.R7FA6M3AH3CFB">
|
||||||
|
<property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
|
||||||
|
<property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
|
||||||
|
<property id="config.bsp.rom_size_bytes_hidden" value="2097152"/>
|
||||||
|
<property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
|
||||||
|
<property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
|
||||||
|
<property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
|
||||||
|
<property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
|
||||||
|
</config>
|
||||||
|
<config id="config.bsp.ra6m3">
|
||||||
|
<property id="config.bsp.series" value="config.bsp.series.value"/>
|
||||||
|
</config>
|
||||||
|
<config id="config.bsp.ra6m3.fsp">
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
|
||||||
|
<property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
|
||||||
|
<property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.280"/>
|
||||||
|
<property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc0_start" value="0xFFFFFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc0_end" value="0xFFFFFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc1_start" value="0xFFFFFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_pc1_end" value="0xFFFFFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg0_start" value="0x00FFFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg0_end" value="0x00FFFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
|
||||||
|
<property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
|
||||||
|
<property id="config.bsp.fsp.hoco_fll" value="config.bsp.fsp.hoco_fll.disabled"/>
|
||||||
|
<property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="60000000"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="20000000"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="1"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="30000000"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.spi.max_bitrate" value="30000000"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="1"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
|
||||||
|
<property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
|
||||||
|
<property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
|
||||||
|
<property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
|
||||||
|
<property id="config.bsp.common.id1" value=""/>
|
||||||
|
<property id="config.bsp.common.id2" value=""/>
|
||||||
|
<property id="config.bsp.common.id3" value=""/>
|
||||||
|
<property id="config.bsp.common.id4" value=""/>
|
||||||
|
<property id="config.bsp.common.id_fixed" value=""/>
|
||||||
|
</config>
|
||||||
|
<config id="config.bsp.ra">
|
||||||
|
<property id="config.bsp.common.main" value="0x400"/>
|
||||||
|
<property id="config.bsp.common.heap" value="0"/>
|
||||||
|
<property id="config.bsp.common.vcc" value="3300"/>
|
||||||
|
<property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
|
||||||
|
<property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
|
||||||
|
<property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
|
||||||
|
<property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
|
||||||
|
<property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.enabled"/>
|
||||||
|
<property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
|
||||||
|
<property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
|
||||||
|
<property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
|
||||||
|
<property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
|
||||||
|
<property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.enabled"/>
|
||||||
|
<property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
|
||||||
|
<property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
|
||||||
|
</config>
|
||||||
|
</raBspConfiguration>
|
||||||
|
<raClockConfiguration>
|
||||||
|
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
|
||||||
|
<node id="board.clock.usbmclk.freq" option="board.clock.usbmclk.freq"/>
|
||||||
|
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
|
||||||
|
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
|
||||||
|
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
|
||||||
|
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
|
||||||
|
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
|
||||||
|
<node id="board.clock.pll.div" option="board.clock.pll.div.2"/>
|
||||||
|
<node id="board.clock.pll.mul" option="board.clock.pll.mul.200"/>
|
||||||
|
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
|
||||||
|
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
|
||||||
|
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
|
||||||
|
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
|
||||||
|
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
|
||||||
|
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
|
||||||
|
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
|
||||||
|
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
|
||||||
|
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
|
||||||
|
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
|
||||||
|
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
|
||||||
|
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
|
||||||
|
<node id="board.clock.sdclkout.div" option="board.clock.sdclkout.div.1"/>
|
||||||
|
<node id="board.clock.sdclkout.display" option="board.clock.sdclkout.display.value"/>
|
||||||
|
<node id="board.clock.bclk.div" option="board.clock.bclk.div.2"/>
|
||||||
|
<node id="board.clock.bclk.display" option="board.clock.bclk.display.value"/>
|
||||||
|
<node id="board.clock.bclkout.div" option="board.clock.bclkout.div.2"/>
|
||||||
|
<node id="board.clock.bclkout.display" option="board.clock.bclkout.display.value"/>
|
||||||
|
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
|
||||||
|
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
|
||||||
|
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
|
||||||
|
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
|
||||||
|
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
|
||||||
|
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
|
||||||
|
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
|
||||||
|
</raClockConfiguration>
|
||||||
|
<raComponentSelection>
|
||||||
|
<component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>Board Support Package Common Files</description>
|
||||||
|
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>I/O Port</description>
|
||||||
|
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.8.0+renesas.0.fsp.3.5.0">
|
||||||
|
<description>Arm CMSIS Version 5 - Core (M)</description>
|
||||||
|
<originalPack>Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="device" variant="R7FA6M3AH3CFB" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>Board support package for R7FA6M3AH3CFB</description>
|
||||||
|
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="device" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>Board support package for RA6M3</description>
|
||||||
|
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="BSP" condition="" group="ra6m3" subgroup="fsp" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>Board support package for RA6M3 - FSP Data</description>
|
||||||
|
<originalPack>Renesas.RA_mcu_ra6m3.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="BSP" condition="" group="Board" subgroup="custom" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>Custom Board Support Files</description>
|
||||||
|
<originalPack>Renesas.RA_board_custom.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
<component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.5.0">
|
||||||
|
<description>SCI UART</description>
|
||||||
|
<originalPack>Renesas.RA.3.5.0.pack</originalPack>
|
||||||
|
</component>
|
||||||
|
</raComponentSelection>
|
||||||
|
<raElcConfiguration/>
|
||||||
|
<raIcuConfiguration/>
|
||||||
|
<raModuleConfiguration>
|
||||||
|
<module id="module.driver.ioport_on_ioport.0">
|
||||||
|
<property id="module.driver.ioport.name" value="g_ioport"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioportb" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioportc" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioportd" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.elc_trigger_ioporte" value="_disabled"/>
|
||||||
|
<property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
|
||||||
|
</module>
|
||||||
|
<module id="module.driver.uart_on_sci_uart.552817864">
|
||||||
|
<property id="module.driver.uart.name" value="g_uart9"/>
|
||||||
|
<property id="module.driver.uart.channel" value="9"/>
|
||||||
|
<property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
|
||||||
|
<property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
|
||||||
|
<property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
|
||||||
|
<property id="module.driver.uart.baud" value="115200"/>
|
||||||
|
<property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
|
||||||
|
<property id="module.driver.uart.baudrate_max_err" value="5"/>
|
||||||
|
<property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
|
||||||
|
<property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
|
||||||
|
<property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
|
||||||
|
<property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
|
||||||
|
<property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
|
||||||
|
<property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
|
||||||
|
<property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
|
||||||
|
<property id="module.driver.uart.callback" value="user_uart9_callback"/>
|
||||||
|
<property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority12"/>
|
||||||
|
<property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority12"/>
|
||||||
|
<property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority12"/>
|
||||||
|
<property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority12"/>
|
||||||
|
</module>
|
||||||
|
<context id="_hal.0">
|
||||||
|
<stack module="module.driver.ioport_on_ioport.0"/>
|
||||||
|
<stack module="module.driver.uart_on_sci_uart.552817864"/>
|
||||||
|
</context>
|
||||||
|
<config id="config.driver.ioport">
|
||||||
|
<property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
|
||||||
|
</config>
|
||||||
|
<config id="config.driver.sci_uart">
|
||||||
|
<property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
|
||||||
|
<property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
|
||||||
|
<property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
|
||||||
|
<property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
|
||||||
|
</config>
|
||||||
|
</raModuleConfiguration>
|
||||||
|
<raPinConfiguration>
|
||||||
|
<pincfg active="true" name="R7FA6M3AH3CFB.pincfg" selected="true" symbol="g_bsp_pin_cfg">
|
||||||
|
<configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
|
||||||
|
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
|
||||||
|
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
|
||||||
|
<configSetting altId="p108.debug0.swdio" configurationId="p108"/>
|
||||||
|
<configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
|
||||||
|
<configSetting altId="p109.sci9.txd" configurationId="p109"/>
|
||||||
|
<configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
|
||||||
|
<configSetting altId="p110.sci9.rxd" configurationId="p110"/>
|
||||||
|
<configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
|
||||||
|
<configSetting altId="p300.debug0.swclk" configurationId="p300"/>
|
||||||
|
<configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
|
||||||
|
<configSetting altId="sci9.mode.asynchronous.free" configurationId="sci9.mode"/>
|
||||||
|
<configSetting altId="sci9.rxd.p110" configurationId="sci9.rxd"/>
|
||||||
|
<configSetting altId="sci9.txd.p109" configurationId="sci9.txd"/>
|
||||||
|
</pincfg>
|
||||||
|
</raPinConfiguration>
|
||||||
|
</raConfiguration>
|
|
@ -0,0 +1,105 @@
|
||||||
|
# RA6M3-HMI-Board-lvgl 使用文档
|
||||||
|
|
||||||
|
## ENV 配置
|
||||||
|
|
||||||
|
首先在BSP目录下打开env工具,输入 `menuconfig` 进入配置界面
|
||||||
|
|
||||||
|
![](picture/lvgl/00.png)
|
||||||
|
|
||||||
|
## RGB 屏使用配置
|
||||||
|
|
||||||
|
在 `Hardware Drivers Config → On-chip Peripheral Drivers → Enable LVGL for LCD` 中使能 `Enable LVGL for LCD_RGB565` 选项
|
||||||
|
|
||||||
|
![](picture/lvgl/12.png)
|
||||||
|
|
||||||
|
接下来退出菜单界面,输入 `pkgs --update` 命令手动联网获取 lvgl 的软件包到 `packages` 文件夹下
|
||||||
|
|
||||||
|
![](picture/lvgl/02.png)
|
||||||
|
|
||||||
|
接着在env 终端中输入 `scons --target=mdk5` 生成 mdk 工程
|
||||||
|
|
||||||
|
![](picture/lvgl/03.png)
|
||||||
|
|
||||||
|
### fsp 中配置 GLCDC 外设
|
||||||
|
|
||||||
|
点击 mdk 中的 `Tools->RA Smart Configurator` 进入 rasc 配置软件
|
||||||
|
|
||||||
|
![](picture/lvgl/04.png)
|
||||||
|
|
||||||
|
点击 New Stack,选择 `Graphics->Graphics LCD`,使能 LCD 外设
|
||||||
|
|
||||||
|
![](picture/lvgl/05.png)
|
||||||
|
|
||||||
|
在 `Interrupt->Callback Function` 中,设置中断回调函数,输入 :`_ra_port_display_callback`
|
||||||
|
|
||||||
|
![](picture/lvgl/06.png)
|
||||||
|
|
||||||
|
在 `Input->Graphics Layer 1->Framebuffer` 中,将 `Number of framebuffers` 属性设置为1,其他选项默认
|
||||||
|
|
||||||
|
![](picture/lvgl/07.png)
|
||||||
|
|
||||||
|
接着我们配置 LCD 的引脚属性,进入 Pins 界面按照下图进行配置:
|
||||||
|
|
||||||
|
![](picture/lvgl/08.png)
|
||||||
|
|
||||||
|
接着向下拉,按照下图配置 LCD_TCONx 引脚:
|
||||||
|
|
||||||
|
![](picture/lvgl/09.png)
|
||||||
|
|
||||||
|
完成以上配置后,点击 `Generate Project Content` 生成配置相关代码
|
||||||
|
|
||||||
|
![](picture/lvgl/10.png)
|
||||||
|
|
||||||
|
### 编译烧录
|
||||||
|
|
||||||
|
退出 rasc 后,在 mdk 中进行编译,仿真下载即可
|
||||||
|
|
||||||
|
![](picture/lvgl/11.png)
|
||||||
|
|
||||||
|
## SPI(ILI9431) 屏使用配置
|
||||||
|
|
||||||
|
### 硬件连接
|
||||||
|
|
||||||
|
硬件按照如下引脚进行连接:
|
||||||
|
|
||||||
|
![](picture/lvgl/tft-pin.png)
|
||||||
|
|
||||||
|
在 `Hardware Drivers Config → On-chip Peripheral Drivers → Enable LVGL for LCD` 中使能 `Enable LVGL for LCD_ILI9431` 选项
|
||||||
|
|
||||||
|
![](picture/lvgl/01.png)
|
||||||
|
|
||||||
|
接下来退出菜单界面,输入 `pkgs --update` 命令手动联网获取 lvgl 的软件包到 `packages` 文件夹下
|
||||||
|
|
||||||
|
![](picture/lvgl/02.png)
|
||||||
|
|
||||||
|
接着在env 终端中输入 `scons --target=mdk5` 生成 mdk 工程
|
||||||
|
|
||||||
|
![](picture/lvgl/03.png)
|
||||||
|
|
||||||
|
### fsp 中配置 SPI 外设
|
||||||
|
|
||||||
|
点击 mdk 中的 `Tools->RA Smart Configurator` 进入 rasc 配置软件
|
||||||
|
|
||||||
|
![](picture/lvgl/04.png)
|
||||||
|
|
||||||
|
点击 New Stack,选择 `Connectivity->SPI(r_spi)`,使能 SPI 外设
|
||||||
|
|
||||||
|
![](picture/lvgl/13.png)
|
||||||
|
|
||||||
|
在 `Callback` 中,设置中断回调函数,(默认使用SPI0)输入 :`spi0_callback`
|
||||||
|
|
||||||
|
![](picture/lvgl/14.png)
|
||||||
|
|
||||||
|
接着我们配置 SPI 的引脚属性(默认使用SPI0),进入 Pins 界面按照下图进行配置:
|
||||||
|
|
||||||
|
![](picture/lvgl/15.png)
|
||||||
|
|
||||||
|
完成以上配置后,点击 `Generate Project Content` 生成配置相关代码
|
||||||
|
|
||||||
|
![](picture/lvgl/16.png)
|
||||||
|
|
||||||
|
### 编译烧录
|
||||||
|
|
||||||
|
退出 rasc 后,在 mdk 中进行编译,仿真下载即可
|
||||||
|
|
||||||
|
![](picture/lvgl/11.png)
|
After Width: | Height: | Size: 3.9 KiB |
After Width: | Height: | Size: 17 KiB |
After Width: | Height: | Size: 21 KiB |
After Width: | Height: | Size: 3.5 KiB |
After Width: | Height: | Size: 12 KiB |
After Width: | Height: | Size: 28 KiB |
After Width: | Height: | Size: 14 KiB |
After Width: | Height: | Size: 12 KiB |
After Width: | Height: | Size: 54 KiB |
After Width: | Height: | Size: 23 KiB |
After Width: | Height: | Size: 6.0 KiB |
After Width: | Height: | Size: 4.1 KiB |
After Width: | Height: | Size: 18 KiB |
After Width: | Height: | Size: 11 KiB |
After Width: | Height: | Size: 12 KiB |
After Width: | Height: | Size: 18 KiB |
After Width: | Height: | Size: 4.7 KiB |
After Width: | Height: | Size: 5.2 KiB |
|
@ -0,0 +1,762 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj; *.o</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
<nMigrate>0</nMigrate>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>Target 1</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>12000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>0</RunSim>
|
||||||
|
<RunTarget>1</RunTarget>
|
||||||
|
<RunAbUc>1</RunAbUc>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\Listings\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>255</CpuCode>
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<tRtrace>1</tRtrace>
|
||||||
|
<sRSysVw>1</sRSysVw>
|
||||||
|
<tRSysVw>1</tRSysVw>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<bEvRecOn>1</bEvRecOn>
|
||||||
|
<bSchkAxf>0</bSchkAxf>
|
||||||
|
<bTchkAxf>0</bTchkAxf>
|
||||||
|
<nTsel>3</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<TargetDriverDllRegistry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>CMSIS_AGDI</Key>
|
||||||
|
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC2000 -FN3 -FF0RA6M3_2M.FLM -FS00 -FL0200000 -FP0($$Device:R7FA6M3AH$Flash\RA6M3_2M.FLM) -FF1RA6M3_DATA_C2M.FLM -FS140100000 -FL110000 -FP1($$Device:R7FA6M3AH$Flash\RA6M3_DATA_C2M.FLM) -FF2RA6M3_CONF.FLM -FS2100A100 -FL280 -FP2($$Device:R7FA6M3AH$Flash\RA6M3_CONF.FLM)</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>UL2CM3</Key>
|
||||||
|
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M3_2M -FS00 -FL0200000 -FF1RA6M3_DATA_C2M -FS140100000 -FL110000 -FF2RA6M3_CONF -FS2100A100 -FL280 -FP0($$Device:R7FA6M3AH$Flash\RA6M3_2M.FLM) -FP1($$Device:R7FA6M3AH$Flash\RA6M3_DATA_C2M.FLM) -FP2($$Device:R7FA6M3AH$Flash\RA6M3_CONF.FLM))</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>JL2CM3</Key>
|
||||||
|
<Name>-U831004110 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(5BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD0 -FC800 -FN0</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
</TargetDriverDllRegistry>
|
||||||
|
<Breakpoint/>
|
||||||
|
<Tracepoint>
|
||||||
|
<THDelay>0</THDelay>
|
||||||
|
</Tracepoint>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>1</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
<bLintAuto>0</bLintAuto>
|
||||||
|
<bAutoGenD>0</bAutoGenD>
|
||||||
|
<LntExFlags>0</LntExFlags>
|
||||||
|
<pMisraName></pMisraName>
|
||||||
|
<pszMrule></pszMrule>
|
||||||
|
<pSingCmds></pSingCmds>
|
||||||
|
<pMultCmds></pMultCmds>
|
||||||
|
<pMisraNamep></pMisraNamep>
|
||||||
|
<pszMrulep></pszMrulep>
|
||||||
|
<pSingCmdsp></pSingCmdsp>
|
||||||
|
<pMultCmdsp></pMultCmdsp>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>Compiler</GroupName>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>1</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>syscall_mem.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>2</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\components\libc\compilers\armlibc\syscalls.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>syscalls.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>3</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\components\libc\compilers\common\cctype.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>cctype.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>4</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\components\libc\compilers\common\cstdio.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>cstdio.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
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<RteFlg>0</RteFlg>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>31</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\clock.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>clock.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>32</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\components.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>components.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>33</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\device.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>device.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>34</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>idle.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>35</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>ipc.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>36</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\irq.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>irq.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>37</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\kservice.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>kservice.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>38</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\mem.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>mem.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>39</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\object.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>object.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>40</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\scheduler_up.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>scheduler_up.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>41</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>thread.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>6</GroupNumber>
|
||||||
|
<FileNumber>42</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>..\..\..\src\timer.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>timer.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>7</GroupNumber>
|
||||||
|
<FileNumber>43</FileNumber>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>.\src\hal_entry.c</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>hal_entry.c</FilenameWithoutPath>
|
||||||
|
<RteFlg>0</RteFlg>
|
||||||
|
<bShared>0</bShared>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>::Flex Software</GroupName>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<RteFlg>1</RteFlg>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
|
@ -0,0 +1,669 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>2.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>Target 1</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
|
||||||
|
<uAC6>1</uAC6>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>R7FA6M3AH</Device>
|
||||||
|
<Vendor>Renesas</Vendor>
|
||||||
|
<PackID>Renesas.RA_DFP.4.2.0</PackID>
|
||||||
|
<PackURL>https://www2.renesas.eu/Keil_MDK_Packs/</PackURL>
|
||||||
|
<Cpu>IRAM(0x1FFE0000,0x020000) IRAM2(0x20000000,0x080000) IROM(0x00000000,0x200000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile></StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M3_2M -FS00 -FL0200000 -FF1RA6M3_DATA_C2M -FS140100000 -FL110000 -FF2RA6M3_CONF -FS2100A100 -FL280 -FP0($$Device:R7FA6M3AH$Flash\RA6M3_2M.FLM) -FP1($$Device:R7FA6M3AH$Flash\RA6M3_DATA_C2M.FLM) -FP2($$Device:R7FA6M3AH$Flash\RA6M3_CONF.FLM))</FlashDriverDll>
|
||||||
|
<DeviceId>0</DeviceId>
|
||||||
|
<RegisterFile></RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc></SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>$$Device:R7FA6M3AH$SVD\R7FA6M3AH.svd</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath></RegisterFilePath>
|
||||||
|
<DBRegisterFilePath></DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||||
|
<OutputName>rtthread</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>1</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>0</BrowseInformation>
|
||||||
|
<ListingPath>.\Listings\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopB1X>0</nStopB1X>
|
||||||
|
<nStopB2X>0</nStopB2X>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out"""</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopA1X>2</nStopA1X>
|
||||||
|
<nStopA2X>0</nStopA2X>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
<ComprImg>1</ComprImg>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments> -MPU</SimDllArguments>
|
||||||
|
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||||
|
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4096</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<bUseTDR>1</bUseTDR>
|
||||||
|
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
<pFcarmOut></pFcarmOut>
|
||||||
|
<pFcarmGrp></pFcarmGrp>
|
||||||
|
<pFcArmRoot></pFcArmRoot>
|
||||||
|
<FcArmLst>0</FcArmLst>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
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<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
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<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
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|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>2</RvdsVP>
|
||||||
|
<RvdsMve>0</RvdsMve>
|
||||||
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<RvdsCdeCp>0</RvdsCdeCp>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
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||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
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<StupSel>8</StupSel>
|
||||||
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<useUlib>1</useUlib>
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||||||
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<EndSel>0</EndSel>
|
||||||
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<uLtcg>0</uLtcg>
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||||||
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<nSecure>0</nSecure>
|
||||||
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<RoSelD>3</RoSelD>
|
||||||
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<RwSelD>4</RwSelD>
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||||||
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<CodeSel>0</CodeSel>
|
||||||
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<OptFeed>0</OptFeed>
|
||||||
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<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
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<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>0</Im1Chk>
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||||||
|
<Im2Chk>1</Im2Chk>
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||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
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||||||
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<StartAddress>0x0</StartAddress>
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||||||
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<Size>0x0</Size>
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||||||
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</Ocm1>
|
||||||
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<Ocm2>
|
||||||
|
<Type>0</Type>
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||||||
|
<StartAddress>0x0</StartAddress>
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||||||
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<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
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<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
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||||||
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<Size>0x0</Size>
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||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
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<Size>0x0</Size>
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||||||
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</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x1ffe0000</StartAddress>
|
||||||
|
<Size>0x20000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x200000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
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<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>1</Type>
|
||||||
|
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|
||||||
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<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x200000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x1ffe0000</StartAddress>
|
||||||
|
<Size>0x20000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x80000</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>6</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>1</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
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|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<uC99>0</uC99>
|
||||||
|
<uGnu>0</uGnu>
|
||||||
|
<useXO>0</useXO>
|
||||||
|
<v6Lang>3</v6Lang>
|
||||||
|
<v6LangP>3</v6LangP>
|
||||||
|
<vShortEn>0</vShortEn>
|
||||||
|
<vShortWch>0</vShortWch>
|
||||||
|
<v6Lto>0</v6Lto>
|
||||||
|
<v6WtE>0</v6WtE>
|
||||||
|
<v6Rtti>0</v6Rtti>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>-Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal</MiscControls>
|
||||||
|
<Define>RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath>..\..\..\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\extension;.;..\libraries\HAL_Drivers\config;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\ipc;..\libraries\HAL_Drivers;board\ports\ili9341;board;board\ports;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include</IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
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|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
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|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
<ClangAsOpt>4</ClangAsOpt>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
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|
||||||
|
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|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>0</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange></TextAddressRange>
|
||||||
|
<DataAddressRange></DataAddressRange>
|
||||||
|
<pXoBase></pXoBase>
|
||||||
|
<ScatterFile>.\script\fsp.scat</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc></Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings>6319,6314</DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Compiler</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>syscall_mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\armlibc\syscall_mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>syscalls.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cctype.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\cctype.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\cstdio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstdlib.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\cstdlib.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cstring.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\cstring.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ctime.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\ctime.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cwchar.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\libc\compilers\common\cwchar.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>CPU</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>atomic_arm.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\common\atomic_arm.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>backtrace.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>div0.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>showmem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>context_rvds.S</FileName>
|
||||||
|
<FileType>2</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\cortex-m4\context_rvds.S</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cpuport.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\libcpu\arm\cortex-m4\cpuport.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>DeviceDrivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>completion.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\completion.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>dataqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\dataqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>pipe.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\pipe.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ringblk_buf.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\ringblk_buf.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ringbuffer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\ringbuffer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>waitqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\waitqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>workqueue.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\ipc\workqueue.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>pin.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>serial_v2.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\drivers\serial\serial_v2.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Drivers</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_common.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\HAL_Drivers\drv_common.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_gpio.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\HAL_Drivers\drv_gpio.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>drv_usart_v2.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\libraries\HAL_Drivers\drv_usart_v2.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Finsh</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>shell.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>msh.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>msh_parse.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\finsh\msh_parse.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>cmd.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>Kernel</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>clock.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\clock.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>components.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\components.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>device.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\device.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>idle.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\idle.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>ipc.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\ipc.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>irq.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\irq.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>kservice.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\kservice.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>mem.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\mem.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>object.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\object.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>scheduler_up.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\scheduler_up.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>thread.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\thread.c</FilePath>
|
||||||
|
</File>
|
||||||
|
<File>
|
||||||
|
<FileName>timer.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>..\..\..\src\timer.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>:Renesas RA Smart Configurator:Common Sources</GroupName>
|
||||||
|
<Files>
|
||||||
|
<File>
|
||||||
|
<FileName>hal_entry.c</FileName>
|
||||||
|
<FileType>1</FileType>
|
||||||
|
<FilePath>.\src\hal_entry.c</FilePath>
|
||||||
|
</File>
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
<Group>
|
||||||
|
<GroupName>::Flex Software</GroupName>
|
||||||
|
</Group>
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
<RTE>
|
||||||
|
<gpdscs>
|
||||||
|
<gpdsc name="buildinfo.gpdsc">
|
||||||
|
<targetInfos>
|
||||||
|
<targetInfo name="Target 1"/>
|
||||||
|
</targetInfos>
|
||||||
|
</gpdsc>
|
||||||
|
</gpdscs>
|
||||||
|
<apis/>
|
||||||
|
<components>
|
||||||
|
<component Cclass="Flex Software" Cgroup="RA Configuration" Cvendor="Renesas" Cversion="1.0.0" condition="RA Device" generator="Renesas RA Smart Configurator">
|
||||||
|
<package name="RA_DFP" schemaVersion="1.7.2" url="https://www2.renesas.eu/Keil_MDK_Packs/" vendor="Renesas" version="4.2.0"/>
|
||||||
|
<targetInfos>
|
||||||
|
<targetInfo name="Target 1"/>
|
||||||
|
</targetInfos>
|
||||||
|
</component>
|
||||||
|
</components>
|
||||||
|
<files/>
|
||||||
|
</RTE>
|
||||||
|
|
||||||
|
<LayerInfo>
|
||||||
|
<Layers>
|
||||||
|
<Layer>
|
||||||
|
<LayName>project</LayName>
|
||||||
|
<LayPrjMark>1</LayPrjMark>
|
||||||
|
</Layer>
|
||||||
|
</Layers>
|
||||||
|
</LayerInfo>
|
||||||
|
|
||||||
|
</Project>
|
|
@ -0,0 +1,25 @@
|
||||||
|
Import('RTT_ROOT')
|
||||||
|
Import('rtconfig')
|
||||||
|
from building import *
|
||||||
|
|
||||||
|
cwd = GetCurrentDir()
|
||||||
|
src = []
|
||||||
|
group = []
|
||||||
|
CPPPATH = []
|
||||||
|
|
||||||
|
if rtconfig.PLATFORM in ['iccarm']:
|
||||||
|
print("\nThe current project does not support IAR build\n")
|
||||||
|
Return('group')
|
||||||
|
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||||
|
if GetOption('target') != 'mdk5':
|
||||||
|
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
|
||||||
|
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
|
||||||
|
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
|
||||||
|
src += Glob(cwd + '/fsp/src/r_*/*.c')
|
||||||
|
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
|
||||||
|
cwd + '/fsp/inc',
|
||||||
|
cwd + '/fsp/inc/api',
|
||||||
|
cwd + '/fsp/inc/instances',]
|
||||||
|
|
||||||
|
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
|
||||||
|
Return('group')
|
|
@ -0,0 +1,411 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file cachel1_armv7.h
|
||||||
|
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 19. April 2021
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_CACHEL1_ARMV7_H
|
||||||
|
#define ARM_CACHEL1_ARMV7_H
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||||
|
\brief Functions that configure Instruction and Data cache.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Cache Size ID Register Macros */
|
||||||
|
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||||
|
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||||
|
|
||||||
|
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||||
|
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||||
|
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable I-Cache
|
||||||
|
\details Turns on I-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||||
|
{
|
||||||
|
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||||
|
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable I-Cache
|
||||||
|
\details Turns off I-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||||
|
{
|
||||||
|
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||||
|
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Invalidate I-Cache
|
||||||
|
\details Invalidates I-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||||
|
{
|
||||||
|
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
SCB->ICIALLU = 0UL;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief I-Cache Invalidate by address
|
||||||
|
\details Invalidates I-Cache for the given address.
|
||||||
|
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||||
|
\param[in] addr address
|
||||||
|
\param[in] isize size of memory block (in number of bytes)
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||||
|
{
|
||||||
|
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||||
|
if ( isize > 0 ) {
|
||||||
|
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||||
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
do {
|
||||||
|
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
|
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||||
|
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||||
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable D-Cache
|
||||||
|
\details Turns on D-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t ccsidr;
|
||||||
|
uint32_t sets;
|
||||||
|
uint32_t ways;
|
||||||
|
|
||||||
|
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
ccsidr = SCB->CCSIDR;
|
||||||
|
|
||||||
|
/* invalidate D-Cache */
|
||||||
|
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||||
|
do {
|
||||||
|
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||||
|
do {
|
||||||
|
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||||
|
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__schedule_barrier();
|
||||||
|
#endif
|
||||||
|
} while (ways-- != 0U);
|
||||||
|
} while(sets-- != 0U);
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable D-Cache
|
||||||
|
\details Turns off D-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t ccsidr;
|
||||||
|
uint32_t sets;
|
||||||
|
uint32_t ways;
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
ccsidr = SCB->CCSIDR;
|
||||||
|
|
||||||
|
/* clean & invalidate D-Cache */
|
||||||
|
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||||
|
do {
|
||||||
|
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||||
|
do {
|
||||||
|
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||||
|
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__schedule_barrier();
|
||||||
|
#endif
|
||||||
|
} while (ways-- != 0U);
|
||||||
|
} while(sets-- != 0U);
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Invalidate D-Cache
|
||||||
|
\details Invalidates D-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t ccsidr;
|
||||||
|
uint32_t sets;
|
||||||
|
uint32_t ways;
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
ccsidr = SCB->CCSIDR;
|
||||||
|
|
||||||
|
/* invalidate D-Cache */
|
||||||
|
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||||
|
do {
|
||||||
|
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||||
|
do {
|
||||||
|
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||||
|
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__schedule_barrier();
|
||||||
|
#endif
|
||||||
|
} while (ways-- != 0U);
|
||||||
|
} while(sets-- != 0U);
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clean D-Cache
|
||||||
|
\details Cleans D-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t ccsidr;
|
||||||
|
uint32_t sets;
|
||||||
|
uint32_t ways;
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
ccsidr = SCB->CCSIDR;
|
||||||
|
|
||||||
|
/* clean D-Cache */
|
||||||
|
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||||
|
do {
|
||||||
|
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||||
|
do {
|
||||||
|
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||||
|
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__schedule_barrier();
|
||||||
|
#endif
|
||||||
|
} while (ways-- != 0U);
|
||||||
|
} while(sets-- != 0U);
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clean & Invalidate D-Cache
|
||||||
|
\details Cleans and Invalidates D-Cache
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
uint32_t ccsidr;
|
||||||
|
uint32_t sets;
|
||||||
|
uint32_t ways;
|
||||||
|
|
||||||
|
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
ccsidr = SCB->CCSIDR;
|
||||||
|
|
||||||
|
/* clean & invalidate D-Cache */
|
||||||
|
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||||
|
do {
|
||||||
|
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||||
|
do {
|
||||||
|
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||||
|
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
__schedule_barrier();
|
||||||
|
#endif
|
||||||
|
} while (ways-- != 0U);
|
||||||
|
} while(sets-- != 0U);
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief D-Cache Invalidate by address
|
||||||
|
\details Invalidates D-Cache for the given address.
|
||||||
|
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||||
|
\param[in] addr address
|
||||||
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
if ( dsize > 0 ) {
|
||||||
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
do {
|
||||||
|
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief D-Cache Clean by address
|
||||||
|
\details Cleans D-Cache for the given address
|
||||||
|
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||||
|
\param[in] addr address
|
||||||
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
if ( dsize > 0 ) {
|
||||||
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
do {
|
||||||
|
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief D-Cache Clean and Invalidate by address
|
||||||
|
\details Cleans and invalidates D_Cache for the given address
|
||||||
|
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||||
|
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||||
|
\param[in] addr address (aligned to 32-byte boundary)
|
||||||
|
\param[in] dsize size of memory block (in number of bytes)
|
||||||
|
*/
|
||||||
|
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||||
|
{
|
||||||
|
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||||
|
if ( dsize > 0 ) {
|
||||||
|
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||||
|
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
|
||||||
|
do {
|
||||||
|
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||||
|
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||||
|
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||||
|
} while ( op_size > 0 );
|
||||||
|
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_CacheFunctions */
|
||||||
|
|
||||||
|
#endif /* ARM_CACHEL1_ARMV7_H */
|
|
@ -0,0 +1,888 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_armcc.h
|
||||||
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
|
* @version V5.3.2
|
||||||
|
* @date 27. May 2021
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ARMCC_H
|
||||||
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
/* CMSIS compiler control DSP macros */
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __ARM_FEATURE_DSP 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#define __COMPILER_BARRIER() __memory_changed()
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ######################### Startup and Lowlevel Init ######################## */
|
||||||
|
|
||||||
|
#ifndef __PROGRAM_START
|
||||||
|
#define __PROGRAM_START __main
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INITIAL_SP
|
||||||
|
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STACK_LIMIT
|
||||||
|
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE
|
||||||
|
#define __VECTOR_TABLE __Vectors
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||||
|
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief No Operation
|
||||||
|
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Interrupt
|
||||||
|
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Wait For Event
|
||||||
|
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Send Event
|
||||||
|
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Instruction Synchronization Barrier
|
||||||
|
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or memory,
|
||||||
|
after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() __isb(0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Synchronization Barrier
|
||||||
|
\details Acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() __dsb(0xF)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Data Memory Barrier
|
||||||
|
\details Ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() __dmb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (32 bit)
|
||||||
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse byte order (16 bit)
|
||||||
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
\param [in] op1 Value to rotate
|
||||||
|
\param [in] op2 Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Breakpoint
|
||||||
|
\details Causes the processor to enter Debug state.
|
||||||
|
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||||
|
\param [in] value is ignored by the processor.
|
||||||
|
If required, a debugger can use it to store additional information about the breakpoint.
|
||||||
|
*/
|
||||||
|
#define __BKPT(value) __breakpoint(value)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reverse bit order of value
|
||||||
|
\details Reverses the bit order of the given value.
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
#define __RBIT __rbit
|
||||||
|
#else
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
|
{
|
||||||
|
result <<= 1U;
|
||||||
|
result |= value & 1U;
|
||||||
|
s--;
|
||||||
|
}
|
||||||
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Count leading zeros
|
||||||
|
\details Counts the number of leading zeros of a data value.
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
#else
|
||||||
|
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (8 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (16 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STR Exclusive (32 bit)
|
||||||
|
\details Executes a exclusive STR instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
#else
|
||||||
|
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Remove the exclusive lock
|
||||||
|
\details Removes the exclusive lock which is created by LDREX.
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Rotate Right with Extend (32 bit)
|
||||||
|
\details Moves each bit of a bitstring right by one bit.
|
||||||
|
The carry input is shifted in at the left end of the bitstring.
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
|
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
rrx r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief LDRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (8 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (16 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief STRT Unprivileged (32 bit)
|
||||||
|
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
*/
|
||||||
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Control Register
|
||||||
|
\details Returns the content of the Control Register.
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Control Register
|
||||||
|
\details Writes the given value to the Control Register.
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get IPSR Register
|
||||||
|
\details Returns the content of the IPSR Register.
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get APSR Register
|
||||||
|
\details Returns the content of the APSR Register.
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get xPSR Register
|
||||||
|
\details Returns the content of the xPSR Register.
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Process Stack Pointer
|
||||||
|
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Process Stack Pointer
|
||||||
|
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Main Stack Pointer
|
||||||
|
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Main Stack Pointer
|
||||||
|
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Priority Mask
|
||||||
|
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Priority Mask
|
||||||
|
\details Assigns the given value to the Priority Mask Register.
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable FIQ
|
||||||
|
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable FIQ
|
||||||
|
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Base Priority
|
||||||
|
\details Returns the current value of the Base Priority register.
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority
|
||||||
|
\details Assigns the given value to the Base Priority register.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Base Priority with condition
|
||||||
|
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||||
|
or the new value increases the BASEPRI priority level.
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||||
|
__regBasePriMax = (basePri & 0xFFU);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Fault Mask
|
||||||
|
\details Returns the current value of the Fault Mask register.
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Fault Mask
|
||||||
|
\details Assigns the given value to the Fault Mask register.
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get FPSCR
|
||||||
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0U);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set FPSCR
|
||||||
|
\details Assigns the given value to the Floating Point Status/Control register.
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
|
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||||
|
|
||||||
|
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ARMCC_H */
|
|
@ -0,0 +1,283 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.1.0
|
||||||
|
* @date 09. October 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6.6 LTM (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||||
|
#include "cmsis_armclang_ltm.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler above 6.10.1 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
#ifndef __COMPILER_BARRIER
|
||||||
|
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||||
|
#define __COMPILER_BARRIER() (void)0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
|
@ -0,0 +1,39 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 23. July 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
|
@ -0,0 +1,952 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm0.h
|
||||||
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
|
* @version V5.0.8
|
||||||
|
* @date 21. August 2019
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_GENERIC
|
||||||
|
#define __CORE_CM0_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M0
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM0 definitions */
|
||||||
|
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_FP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM0_H_DEPENDANT
|
||||||
|
#define __CORE_CM0_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM0_REV
|
||||||
|
#define __CM0_REV 0x0000U
|
||||||
|
#warning "__CM0_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M0 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RESERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M0 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||||
|
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||||
|
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||||
|
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
|
@ -0,0 +1,979 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm1.h
|
||||||
|
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 12. November 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_GENERIC
|
||||||
|
#define __CORE_CM1_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M1
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM1 definitions */
|
||||||
|
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_FP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_DEPENDANT
|
||||||
|
#define __CORE_CM1_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM1_REV
|
||||||
|
#define __CM1_REV 0x0100U
|
||||||
|
#warning "__CM1_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M1 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2U];
|
||||||
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||||
|
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M1 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__COMPILER_BARRIER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
|
@ -0,0 +1,275 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.1.2
|
||||||
|
* @date 25. May 2020
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||||
|
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||||
|
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||||
|
(((MPU_RASR_ENABLE_Msk))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rasr Value for RASR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rasr Value for RASR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,352 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv8.h
|
||||||
|
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||||
|
* @version V5.1.3
|
||||||
|
* @date 03. February 2021
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
|
/** \brief Attribute for device memory (outer only) */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
|
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
|
/** \brief Memory Attribute
|
||||||
|
* \param O Outer memory attributes
|
||||||
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||||
|
|
||||||
|
/** \brief Normal memory non-shareable */
|
||||||
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
|
/** \brief Normal memory outer shareable */
|
||||||
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
|
/** \brief Normal memory inner shareable */
|
||||||
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
|
/** \brief Memory access permissions
|
||||||
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||||
|
|
||||||
|
/** \brief Region Base Address Register value
|
||||||
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
|
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||||
|
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
|
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
|
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
#if defined(MPU_RLAR_PXN_Pos)
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register with PXN value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||||
|
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||||
|
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Enable the Non-secure MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the Non-secure MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
|
{
|
||||||
|
__DMB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
|
const uint32_t mask = 0xFFU << pos;
|
||||||
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
|
return; // invalid index
|
||||||
|
}
|
||||||
|
|
||||||
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RLAR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Configure the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RBAR = rbar;
|
||||||
|
mpu->RLAR = rlar;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Configure the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
|
} else {
|
||||||
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
|
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
|
cnt -= c;
|
||||||
|
rnrOffset = 0U;
|
||||||
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
|
@ -0,0 +1,337 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file pmu_armv8.h
|
||||||
|
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 15. April 2020
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_PMU_ARMV8_H
|
||||||
|
#define ARM_PMU_ARMV8_H
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief PMU Events
|
||||||
|
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||||
|
* */
|
||||||
|
|
||||||
|
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||||
|
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||||
|
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||||
|
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||||
|
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||||
|
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||||
|
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||||
|
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||||
|
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||||
|
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||||
|
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||||
|
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||||
|
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||||
|
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||||
|
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||||
|
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||||
|
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||||
|
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||||
|
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||||
|
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||||
|
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||||
|
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||||
|
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||||
|
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||||
|
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||||
|
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||||
|
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||||
|
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||||
|
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||||
|
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||||
|
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||||
|
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||||
|
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||||
|
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||||
|
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||||
|
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||||
|
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||||
|
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||||
|
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||||
|
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||||
|
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||||
|
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||||
|
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||||
|
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||||
|
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||||
|
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||||
|
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||||
|
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||||
|
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||||
|
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||||
|
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||||
|
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||||
|
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||||
|
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||||
|
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||||
|
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||||
|
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||||
|
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||||
|
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||||
|
|
||||||
|
/** \brief PMU Functions */
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||||
|
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable the PMU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable the PMU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set event to count for PMU eventer counter
|
||||||
|
\param [in] num Event counter (0-30) to configure
|
||||||
|
\param [in] type Event to count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||||
|
{
|
||||||
|
PMU->EVTYPER[num] = type;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reset cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Reset all event counters
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||||
|
{
|
||||||
|
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable counters
|
||||||
|
\param [in] mask Counters to enable
|
||||||
|
\note Enables one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->CNTENSET = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable counters
|
||||||
|
\param [in] mask Counters to enable
|
||||||
|
\note Disables one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->CNTENCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read cycle counter
|
||||||
|
\return Cycle count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||||
|
{
|
||||||
|
return PMU->CCNTR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read event counter
|
||||||
|
\param [in] num Event counter (0-30) to read
|
||||||
|
\return Event count
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||||
|
{
|
||||||
|
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Read counter overflow status
|
||||||
|
\return Counter overflow status bits for the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||||
|
{
|
||||||
|
return PMU->OVSSET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear counter overflow status
|
||||||
|
\param [in] mask Counter overflow status bits to clear
|
||||||
|
\note Clears overflow status bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->OVSCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable counter overflow interrupt request
|
||||||
|
\param [in] mask Counter overflow interrupt request bits to set
|
||||||
|
\note Sets overflow interrupt request bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->INTENSET = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable counter overflow interrupt request
|
||||||
|
\param [in] mask Counter overflow interrupt request bits to clear
|
||||||
|
\note Clears overflow interrupt request bits for one or more of the following:
|
||||||
|
- event counters (0-30)
|
||||||
|
- cycle counter
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->INTENCLR = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Software increment event counter
|
||||||
|
\param [in] mask Counters to increment
|
||||||
|
\note Software increment bits for one or more event counters (0-30)
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||||
|
{
|
||||||
|
PMU->SWINC = mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,70 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file tz_context.h
|
||||||
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef TZ_CONTEXT_H
|
||||||
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifndef TZ_MODULEID_T
|
||||||
|
#define TZ_MODULEID_T
|
||||||
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
|
/// Initialize secure context memory system
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
|
/// \return value 0 no memory available or internal error
|
||||||
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
#endif // TZ_CONTEXT_H
|
|
@ -0,0 +1,201 @@
|
||||||
|
Apache License
|
||||||
|
Version 2.0, January 2004
|
||||||
|
http://www.apache.org/licenses/
|
||||||
|
|
||||||
|
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||||
|
|
||||||
|
1. Definitions.
|
||||||
|
|
||||||
|
"License" shall mean the terms and conditions for use, reproduction,
|
||||||
|
and distribution as defined by Sections 1 through 9 of this document.
|
||||||
|
|
||||||
|
"Licensor" shall mean the copyright owner or entity authorized by
|
||||||
|
the copyright owner that is granting the License.
|
||||||
|
|
||||||
|
"Legal Entity" shall mean the union of the acting entity and all
|
||||||
|
other entities that control, are controlled by, or are under common
|
||||||
|
control with that entity. For the purposes of this definition,
|
||||||
|
"control" means (i) the power, direct or indirect, to cause the
|
||||||
|
direction or management of such entity, whether by contract or
|
||||||
|
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||||
|
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||||
|
|
||||||
|
"You" (or "Your") shall mean an individual or Legal Entity
|
||||||
|
exercising permissions granted by this License.
|
||||||
|
|
||||||
|
"Source" form shall mean the preferred form for making modifications,
|
||||||
|
including but not limited to software source code, documentation
|
||||||
|
source, and configuration files.
|
||||||
|
|
||||||
|
"Object" form shall mean any form resulting from mechanical
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||||||
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transformation or translation of a Source form, including but
|
||||||
|
not limited to compiled object code, generated documentation,
|
||||||
|
and conversions to other media types.
|
||||||
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|
"Work" shall mean the work of authorship, whether in Source or
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||||||
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Object form, made available under the License, as indicated by a
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||||||
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copyright notice that is included in or attached to the work
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(an example is provided in the Appendix below).
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"Derivative Works" shall mean any work, whether in Source or Object
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||||||
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|
||||||
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editorial revisions, annotations, elaborations, or other modifications
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"Contribution" shall mean any work of authorship, including
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||||||
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|
||||||
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"Contributor" shall mean Licensor and any individual or Legal Entity
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||||||
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||||||
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2. Grant of Copyright License. Subject to the terms and conditions of
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||||||
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this License, each Contributor hereby grants to You a perpetual,
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||||||
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worldwide, non-exclusive, no-charge, royalty-free, irrevocable
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3. Grant of Patent License. Subject to the terms and conditions of
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4. Redistribution. You may reproduce and distribute copies of the
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(a) You must give any other recipients of the Work or
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(c) You must retain, in the Source form of any Derivative Works
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(d) If the Work includes a "NOTICE" text file as part of its
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5. Submission of Contributions. Unless You explicitly state otherwise,
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|
incurred by, or claims asserted against, such Contributor by reason
|
||||||
|
of your accepting any such warranty or additional liability.
|
||||||
|
|
||||||
|
END OF TERMS AND CONDITIONS
|
||||||
|
|
||||||
|
APPENDIX: How to apply the Apache License to your work.
|
||||||
|
|
||||||
|
To apply the Apache License to your work, attach the following
|
||||||
|
boilerplate notice, with the fields enclosed by brackets "{}"
|
||||||
|
replaced with your own identifying information. (Don't include
|
||||||
|
the brackets!) The text should be enclosed in the appropriate
|
||||||
|
comment syntax for the file format. We also recommend that a
|
||||||
|
file or class name and description of purpose be included on the
|
||||||
|
same "printed page" as the copyright notice for easier
|
||||||
|
identification within third-party archives.
|
||||||
|
|
||||||
|
Copyright {yyyy} {name of copyright owner}
|
||||||
|
|
||||||
|
Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
you may not use this file except in compliance with the License.
|
||||||
|
You may obtain a copy of the License at
|
||||||
|
|
||||||
|
http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
|
||||||
|
Unless required by applicable law or agreed to in writing, software
|
||||||
|
distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
See the License for the specific language governing permissions and
|
||||||
|
limitations under the License.
|
|
@ -0,0 +1,66 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||||
|
*
|
||||||
|
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||||
|
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||||
|
*
|
||||||
|
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||||
|
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||||
|
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||||
|
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||||
|
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||||
|
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||||
|
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||||
|
* included in this file may be subject to different terms.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* File Name : board.h
|
||||||
|
* Description : Includes and API function available for this board.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup BSP_Boards
|
||||||
|
* @defgroup BOARD_RA6M2_CPK for the RA6M4_CPK Board
|
||||||
|
* @brief BSP for the RA6M4_CPK Board
|
||||||
|
*
|
||||||
|
* The RA6M4_CPK is a development kit for the Renesas RA6M2 microcontroller.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef BOARD_H
|
||||||
|
#define BOARD_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes <System Includes> , "Project Includes"
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* BSP Board Specific Includes. */
|
||||||
|
#include "../ra6m3/board_ethernet_phy.h"
|
||||||
|
#include "../ra6m3/board_init.h"
|
||||||
|
#include "../ra6m3/board_leds.h"
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#define BOARD_RA6M3
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global functions (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** @} (end defgroup BOARD_RA6M4_CPK) */
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,60 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup BOARD_RA6M4_CPK
|
||||||
|
* @defgroup BOARD_RA6M4_CPK_ETHERNET_PHY Board Ethernet Phy
|
||||||
|
* @brief Ethernet Phy information for this board.
|
||||||
|
*
|
||||||
|
* This is code specific to the RA6M4_CPK board.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef BSP_ETHERNET_PHY_H
|
||||||
|
#define BSP_ETHERNET_PHY_H
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#define BOARD_PHY_TYPE (0)
|
||||||
|
#define BOARD_PHY_REF_CLK (1)
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} (end defgroup BOARD_RA6M4_CPK_ETHERNET_PHY) */
|
|
@ -0,0 +1,66 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||||
|
*
|
||||||
|
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||||
|
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||||
|
*
|
||||||
|
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||||
|
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||||
|
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||||
|
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||||
|
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||||
|
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||||
|
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||||
|
* included in this file may be subject to different terms.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* File Name : bsp_init.c
|
||||||
|
* Description : This module calls any initialization code specific to this BSP.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup BOARD_RA6M4_CPK_INIT
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes <System Includes> , "Project Includes"
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
#if defined(BOARD_RA6M3)
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Private global variables and functions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @brief Performs any initialization specific to this BSP.
|
||||||
|
*
|
||||||
|
* @param[in] p_args Pointer to arguments of the user's choice.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
void bsp_init (void * p_args)
|
||||||
|
{
|
||||||
|
FSP_PARAMETER_NOT_USED(p_args);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} (end addtogroup BOARD_RA6M4_CPK_INIT) */
|
|
@ -0,0 +1,63 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||||
|
*
|
||||||
|
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||||
|
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||||
|
*
|
||||||
|
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||||
|
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||||
|
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||||
|
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||||
|
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||||
|
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||||
|
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||||
|
* included in this file may be subject to different terms.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* File Name : board_init.h
|
||||||
|
* Description : This module calls any initialization code specific to this BSP.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup BOARD_RA6M4_CPK
|
||||||
|
* @defgroup BOARD_RA6M4_CPK Board Specific Code
|
||||||
|
* @brief Board specific code for the RA6M4_CPK Board
|
||||||
|
*
|
||||||
|
* This is code specific to the RA6M4_CPK board.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef BOARD_INIT_H
|
||||||
|
#define BOARD_INIT_H
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global functions (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
void bsp_init(void * p_args);
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} (end defgroup BOARD_RA6M4_CPK_INIT) */
|
|
@ -0,0 +1,74 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||||
|
*
|
||||||
|
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||||
|
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||||
|
*
|
||||||
|
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||||
|
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||||
|
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||||
|
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||||
|
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||||
|
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||||
|
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||||
|
* included in this file may be subject to different terms.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* File Name : board_leds.c
|
||||||
|
* Description : This module has information about the LEDs on this board.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup BSP_RA6M4_CPK_LEDS
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
#if defined(BOARD_RA6M4_CPK)
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Private global variables and functions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Array of LED IOPORT pins. */
|
||||||
|
static const uint16_t g_bsp_prv_leds[] =
|
||||||
|
{
|
||||||
|
(uint16_t) BSP_IO_PORT_01_PIN_06, ///< USER LED
|
||||||
|
};
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Structure with LED information for this board. */
|
||||||
|
|
||||||
|
const bsp_leds_t g_bsp_leds =
|
||||||
|
{
|
||||||
|
.led_count = (uint16_t) ((sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0]))),
|
||||||
|
.p_leds = &g_bsp_prv_leds[0]
|
||||||
|
};
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @} (end addtogroup BSP_RA6M4_CPK_LEDS) */
|
|
@ -0,0 +1,75 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This file is part of Renesas RA Flexible Software Package (FSP)
|
||||||
|
*
|
||||||
|
* The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
|
||||||
|
* and/or its licensors ("Renesas") and subject to statutory and contractual protections.
|
||||||
|
*
|
||||||
|
* This file is subject to a Renesas FSP license agreement. Unless otherwise agreed in an FSP license agreement with
|
||||||
|
* Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
|
||||||
|
* or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
|
||||||
|
* MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
|
||||||
|
* "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||||
|
* PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
|
||||||
|
* CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
|
||||||
|
* included in this file may be subject to different terms.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* File Name : board_leds.h
|
||||||
|
* Description : This module has information about the LEDs on this board.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup BOARD_RA6M4_CPK
|
||||||
|
* @defgroup BSP_RA6M4_CPK_LEDS Board LEDs
|
||||||
|
* @brief LED information for this board.
|
||||||
|
*
|
||||||
|
* This is code specific to the RA6M4_CPK board.
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef BOARD_LEDS_H
|
||||||
|
#define BOARD_LEDS_H
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Information on how many LEDs and what pins they are on. */
|
||||||
|
typedef struct st_bsp_leds
|
||||||
|
{
|
||||||
|
uint16_t led_count; ///< The number of LEDs on this board
|
||||||
|
uint16_t const * p_leds; ///< Pointer to an array of IOPORT pins for controlling LEDs
|
||||||
|
} bsp_leds_t;
|
||||||
|
|
||||||
|
/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins
|
||||||
|
* found in the bsp_leds_t structure. */
|
||||||
|
typedef enum e_bsp_led
|
||||||
|
{
|
||||||
|
BSP_LED_LED3 = 0, ///< TB LED - Red
|
||||||
|
} bsp_led_t;
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
#endif /* BOARD_LEDS_H */
|
||||||
|
|
||||||
|
/** @} (end defgroup BSP_RA6M4_CPK_LEDS) */
|
|
@ -0,0 +1,107 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef BSP_API_H
|
||||||
|
#define BSP_API_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes <System Includes> , "Project Includes"
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* FSP Common Includes. */
|
||||||
|
#include "fsp_common_api.h"
|
||||||
|
|
||||||
|
/* Gets MCU configuration information. */
|
||||||
|
#include "bsp_cfg.h"
|
||||||
|
|
||||||
|
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||||
|
|
||||||
|
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
|
||||||
|
* We are not modifying these files so we will ignore these warnings temporarily. */
|
||||||
|
#pragma GCC diagnostic ignored "-Wconversion"
|
||||||
|
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Vector information for this project. This is generated by the tooling. */
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_arm_exceptions.h"
|
||||||
|
#include "vector_data.h"
|
||||||
|
|
||||||
|
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
|
||||||
|
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
|
||||||
|
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
|
||||||
|
|
||||||
|
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
|
||||||
|
|
||||||
|
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
|
||||||
|
#pragma GCC diagnostic pop
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* BSP Common Includes. */
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_common.h"
|
||||||
|
|
||||||
|
/* BSP MCU Specific Includes. */
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_irq.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_io.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_clocks.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_security.h"
|
||||||
|
|
||||||
|
/* Factory MCU information. */
|
||||||
|
#include "../../inc/fsp_features.h"
|
||||||
|
|
||||||
|
/* BSP Common Includes (Other than bsp_common.h) */
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_delay.h"
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
|
||||||
|
|
||||||
|
/* BSP TFU Includes. */
|
||||||
|
#if BSP_FEATURE_TFU_SUPPORTED
|
||||||
|
#include "../../src/bsp/mcu/all/bsp_tfu.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Exported global functions (to be accessed by other files)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup BSP_MCU
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
|
||||||
|
|
||||||
|
/** @} (end addtogroup BSP_MCU) */
|
||||||
|
|
||||||
|
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,384 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup RENESAS_INTERFACES
|
||||||
|
* @defgroup IOPORT_API I/O Port Interface
|
||||||
|
* @brief Interface for accessing I/O ports and configuring I/O functionality.
|
||||||
|
*
|
||||||
|
* @section IOPORT_API_SUMMARY Summary
|
||||||
|
* The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level.
|
||||||
|
* Port and pin direction can be changed.
|
||||||
|
*
|
||||||
|
* IOPORT Interface description: @ref IOPORT
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef R_IOPORT_API_H
|
||||||
|
#define R_IOPORT_API_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Common error codes and definitions. */
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Private definition to set enumeration values. */
|
||||||
|
#define IOPORT_PRV_PFS_PSEL_OFFSET (24)
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** IO port type used with ports */
|
||||||
|
typedef uint16_t ioport_size_t; ///< IO port size on this device
|
||||||
|
|
||||||
|
/** Superset of all peripheral functions. */
|
||||||
|
typedef enum e_ioport_peripheral
|
||||||
|
{
|
||||||
|
/** Pin will functions as an IO pin */
|
||||||
|
IOPORT_PERIPHERAL_IO = 0x00,
|
||||||
|
|
||||||
|
/** Pin will function as a DEBUG pin */
|
||||||
|
IOPORT_PERIPHERAL_DEBUG = (0x00UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an AGT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a GPT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a GPT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_GPT1 = (0x03UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SCI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_SCI0_2_4_6_8 = (0x04UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SCI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_SCI1_3_5_7_9 = (0x05UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a SPI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_SPI = (0x06UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a IIC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_IIC = (0x07UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a KEY peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_KEY = (0x08UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a clock/comparator/RTC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CLKOUT_COMP_RTC = (0x09UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CAC/ADC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CAC_AD = (0x0AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a BUS peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_BUS = (0x0BUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CTSU peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CTSU = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CMPHS peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_ACMPHS = (0x0CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a segment LCD peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_LCDC = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SCI peripheral DEn pin */
|
||||||
|
IOPORT_PERIPHERAL_DE_SCI1_3_5_7_9 = (0x0DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a DALI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_DALI = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SCI DEn peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_DE_SCI0_2_4_6_8 = (0x0EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CAN peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CAN = (0x10UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a QSPI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_QSPI = (0x11UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SSI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_SSI = (0x12UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a USB full speed peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_USB_FS = (0x13UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a USB high speed peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_USB_HS = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a GPT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_GPT2 = (0x14UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an SD/MMC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_SDHI_MMC = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a GPT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_GPT3 = (0x15UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an Ethernet MMI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_ETHER_MII = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a GPT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_GPT4 = (0x16UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as an Ethernet RMMI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_ETHER_RMII = (0x17UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a PDC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_PDC = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a graphics LCD peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_LCD_GRAPHICS = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CAC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CAC = (0x19UL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a debug trace peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_TRACE = (0x1AUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a OSPI peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_OSPI = (0x1CUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a CEC peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_CEC = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a PGAOUT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_PGAOUT0 = (0x1DUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
|
||||||
|
/** Pin will function as a PGAOUT peripheral pin */
|
||||||
|
IOPORT_PERIPHERAL_PGAOUT1 = (0x1EUL << IOPORT_PRV_PFS_PSEL_OFFSET),
|
||||||
|
} ioport_peripheral_t;
|
||||||
|
|
||||||
|
/* DEPRECATED Superset of Ethernet channels. */
|
||||||
|
typedef enum e_ioport_eth_ch
|
||||||
|
{
|
||||||
|
IOPORT_ETHERNET_CHANNEL_0 = 0x10, ///< Used to select Ethernet channel 0
|
||||||
|
IOPORT_ETHERNET_CHANNEL_1 = 0x20, ///< Used to select Ethernet channel 1
|
||||||
|
IOPORT_ETHERNET_CHANNEL_END ///< Marks end of enum - used by parameter checking
|
||||||
|
} ioport_ethernet_channel_t;
|
||||||
|
|
||||||
|
/* DEPRECATED Superset of Ethernet PHY modes. */
|
||||||
|
typedef enum e_ioport_eth_mode
|
||||||
|
{
|
||||||
|
IOPORT_ETHERNET_MODE_RMII = 0x00, ///< Ethernet PHY mode set to MII
|
||||||
|
IOPORT_ETHERNET_MODE_MII = 0x10, ///< Ethernet PHY mode set to RMII
|
||||||
|
IOPORT_ETHERNET_MODE_END ///< Marks end of enum - used by parameter checking
|
||||||
|
} ioport_ethernet_mode_t;
|
||||||
|
|
||||||
|
/** Options to configure pin functions */
|
||||||
|
typedef enum e_ioport_cfg_options
|
||||||
|
{
|
||||||
|
IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000000, ///< Sets the pin direction to input (default)
|
||||||
|
IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000004, ///< Sets the pin direction to output
|
||||||
|
IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000, ///< Sets the pin level to low
|
||||||
|
IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001, ///< Sets the pin level to high
|
||||||
|
IOPORT_CFG_PULLUP_ENABLE = 0x00000010, ///< Enables the pin's internal pull-up
|
||||||
|
IOPORT_CFG_PIM_TTL = 0x00000020, ///< Enables the pin's input mode
|
||||||
|
IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< Enables the pin's NMOS open-drain output
|
||||||
|
IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< Enables the pin's PMOS open-drain ouput
|
||||||
|
IOPORT_CFG_DRIVE_MID = 0x00000400, ///< Sets pin drive output to medium
|
||||||
|
IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< Sets pin drive output to high along with supporting high speed
|
||||||
|
IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< Sets pin to drive output needed for IIC on a 20mA port
|
||||||
|
IOPORT_CFG_DRIVE_HIGH = 0x00000C00, ///< Sets pin drive output to high
|
||||||
|
IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< Sets pin event trigger to rising edge
|
||||||
|
IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< Sets pin event trigger to falling edge
|
||||||
|
IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< Sets pin event trigger to both edges
|
||||||
|
IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< Sets pin as an IRQ pin
|
||||||
|
IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< Enables pin to operate as an analog pin
|
||||||
|
IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< Enables pin to operate as a peripheral pin
|
||||||
|
} ioport_cfg_options_t;
|
||||||
|
|
||||||
|
/* PFS writing enable/disable. */
|
||||||
|
typedef enum e_ioport_pwpr
|
||||||
|
{
|
||||||
|
IOPORT_PFS_WRITE_DISABLE = 0, ///< Disable PFS write access
|
||||||
|
IOPORT_PFS_WRITE_ENABLE = 1 ///< Enable PFS write access
|
||||||
|
} ioport_pwpr_t;
|
||||||
|
|
||||||
|
/** Pin identifier and pin PFS pin configuration value */
|
||||||
|
typedef struct st_ioport_pin_cfg
|
||||||
|
{
|
||||||
|
uint32_t pin_cfg; ///< Pin PFS configuration - Use ioport_cfg_options_t parameters to configure
|
||||||
|
bsp_io_port_pin_t pin; ///< Pin identifier
|
||||||
|
} ioport_pin_cfg_t;
|
||||||
|
|
||||||
|
/** Multiple pin configuration data for loading into PFS registers by R_IOPORT_Init() */
|
||||||
|
typedef struct st_ioport_cfg
|
||||||
|
{
|
||||||
|
uint16_t number_of_pins; ///< Number of pins for which there is configuration data
|
||||||
|
ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data
|
||||||
|
} ioport_cfg_t;
|
||||||
|
|
||||||
|
/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls.
|
||||||
|
* @par Implemented as
|
||||||
|
* - ioport_instance_ctrl_t
|
||||||
|
*/
|
||||||
|
typedef void ioport_ctrl_t;
|
||||||
|
|
||||||
|
/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */
|
||||||
|
typedef struct st_ioport_api
|
||||||
|
{
|
||||||
|
/** Initialize internal driver data and initial pin configurations. Called during startup. Do
|
||||||
|
* not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of
|
||||||
|
* multiple pins.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_Open()
|
||||||
|
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||||
|
|
||||||
|
/** Close the API.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_Close()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to control structure.
|
||||||
|
**/
|
||||||
|
fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl);
|
||||||
|
|
||||||
|
/** Configure multiple pins.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinsCfg()
|
||||||
|
* @param[in] p_cfg Pointer to pin configuration data array.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||||
|
|
||||||
|
/** Configure settings for an individual pin.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinCfg()
|
||||||
|
* @param[in] pin Pin to be read.
|
||||||
|
* @param[in] cfg Configuration options for the pin.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||||
|
|
||||||
|
/** Read the event input data of the specified pin and return the level.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinEventInputRead()
|
||||||
|
* @param[in] pin Pin to be read.
|
||||||
|
* @param[in] p_pin_event Pointer to return the event data.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||||
|
|
||||||
|
/** Write pin event data.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinEventOutputWrite()
|
||||||
|
* @param[in] pin Pin event data is to be written to.
|
||||||
|
* @param[in] pin_value Level to be written to pin output event.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||||
|
|
||||||
|
/* DEPRECATED Configure the PHY mode of the Ethernet channels.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_EthernetModeCfg()
|
||||||
|
* @param[in] channel Channel configuration will be set for.
|
||||||
|
* @param[in] mode PHY mode to set the channel to.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinEthernetModeCfg)(ioport_ctrl_t * const p_ctrl, ioport_ethernet_channel_t channel,
|
||||||
|
ioport_ethernet_mode_t mode);
|
||||||
|
|
||||||
|
/** Read level of a pin.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinRead()
|
||||||
|
* @param[in] pin Pin to be read.
|
||||||
|
* @param[in] p_pin_value Pointer to return the pin level.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||||
|
|
||||||
|
/** Write specified level to a pin.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PinWrite()
|
||||||
|
* @param[in] pin Pin to be written to.
|
||||||
|
* @param[in] level State to be written to the pin.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||||
|
|
||||||
|
/** Set the direction of one or more pins on a port.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PortDirectionSet()
|
||||||
|
* @param[in] port Port being configured.
|
||||||
|
* @param[in] direction_values Value controlling direction of pins on port (1 - output, 0 - input).
|
||||||
|
* @param[in] mask Mask controlling which pins on the port are to be configured.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values,
|
||||||
|
ioport_size_t mask);
|
||||||
|
|
||||||
|
/** Read captured event data for a port.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PortEventInputRead()
|
||||||
|
* @param[in] port Port to be read.
|
||||||
|
* @param[in] p_event_data Pointer to return the event data.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data);
|
||||||
|
|
||||||
|
/** Write event output data for a port.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PortEventOutputWrite()
|
||||||
|
* @param[in] port Port event data will be written to.
|
||||||
|
* @param[in] event_data Data to be written as event data to specified port.
|
||||||
|
* @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data.
|
||||||
|
* being written to port.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data,
|
||||||
|
ioport_size_t mask_value);
|
||||||
|
|
||||||
|
/** Read states of pins on the specified port.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PortRead()
|
||||||
|
* @param[in] port Port to be read.
|
||||||
|
* @param[in] p_port_value Pointer to return the port value.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||||
|
|
||||||
|
/** Write to multiple pins on a port.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_IOPORT_PortWrite()
|
||||||
|
* @param[in] port Port to be written to.
|
||||||
|
* @param[in] value Value to be written to the port.
|
||||||
|
* @param[in] mask Mask controlling which pins on the port are written to.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||||
|
} ioport_api_t;
|
||||||
|
|
||||||
|
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||||
|
typedef struct st_ioport_instance
|
||||||
|
{
|
||||||
|
ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||||
|
ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||||
|
ioport_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||||
|
} ioport_instance_t;
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @} (end defgroup IOPORT_API)
|
||||||
|
**********************************************************************************************************************/
|
|
@ -0,0 +1,371 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup RENESAS_INTERFACES
|
||||||
|
* @defgroup TRANSFER_API Transfer Interface
|
||||||
|
*
|
||||||
|
* @brief Interface for data transfer functions.
|
||||||
|
*
|
||||||
|
* @section TRANSFER_API_SUMMARY Summary
|
||||||
|
* The transfer interface supports background data transfer (no CPU intervention).
|
||||||
|
*
|
||||||
|
* Implemented by:
|
||||||
|
* - @ref DTC
|
||||||
|
* - @ref DMAC
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef R_TRANSFER_API_H
|
||||||
|
#define R_TRANSFER_API_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Common error codes and definitions. */
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#define TRANSFER_SETTINGS_MODE_BITS (30U)
|
||||||
|
#define TRANSFER_SETTINGS_SIZE_BITS (28U)
|
||||||
|
#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U)
|
||||||
|
#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U)
|
||||||
|
#define TRANSFER_SETTINGS_IRQ_BITS (21U)
|
||||||
|
#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U)
|
||||||
|
#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U)
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls.
|
||||||
|
* @par Implemented as
|
||||||
|
* - dtc_instance_ctrl_t
|
||||||
|
* - dmac_instance_ctrl_t
|
||||||
|
*/
|
||||||
|
typedef void transfer_ctrl_t;
|
||||||
|
|
||||||
|
/** Transfer mode describes what will happen when a transfer request occurs. */
|
||||||
|
typedef enum e_transfer_mode
|
||||||
|
{
|
||||||
|
/** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to
|
||||||
|
* the destination pointer. The transfer length is decremented and the source and address pointers are
|
||||||
|
* updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests
|
||||||
|
* will not cause any further transfers. */
|
||||||
|
TRANSFER_MODE_NORMAL = 0,
|
||||||
|
|
||||||
|
/** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the
|
||||||
|
* repeat area and the transfer length will be reset to their initial values. If DMAC is used, the
|
||||||
|
* transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats
|
||||||
|
* transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is
|
||||||
|
* used, the transfer repeats continuously (no limit to the number of repeat transfers). */
|
||||||
|
TRANSFER_MODE_REPEAT = 1,
|
||||||
|
|
||||||
|
/** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t.
|
||||||
|
* After each individual transfer, the source and destination pointers are updated according to
|
||||||
|
* @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is
|
||||||
|
* decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any
|
||||||
|
* further transfers. */
|
||||||
|
TRANSFER_MODE_BLOCK = 2,
|
||||||
|
|
||||||
|
/** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets
|
||||||
|
* within a block (to split blocks into arrays of their first data, second data, etc.) */
|
||||||
|
TRANSFER_MODE_REPEAT_BLOCK = 3
|
||||||
|
} transfer_mode_t;
|
||||||
|
|
||||||
|
/** Transfer size specifies the size of each individual transfer.
|
||||||
|
* Total transfer length = transfer_size_t * transfer_length_t
|
||||||
|
*/
|
||||||
|
typedef enum e_transfer_size
|
||||||
|
{
|
||||||
|
TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value
|
||||||
|
TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value
|
||||||
|
TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value
|
||||||
|
} transfer_size_t;
|
||||||
|
|
||||||
|
/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */
|
||||||
|
typedef enum e_transfer_addr_mode
|
||||||
|
{
|
||||||
|
/** Address pointer remains fixed after each transfer. */
|
||||||
|
TRANSFER_ADDR_MODE_FIXED = 0,
|
||||||
|
|
||||||
|
/** Offset is added to the address pointer after each transfer. */
|
||||||
|
TRANSFER_ADDR_MODE_OFFSET = 1,
|
||||||
|
|
||||||
|
/** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */
|
||||||
|
TRANSFER_ADDR_MODE_INCREMENTED = 2,
|
||||||
|
|
||||||
|
/** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */
|
||||||
|
TRANSFER_ADDR_MODE_DECREMENTED = 3
|
||||||
|
} transfer_addr_mode_t;
|
||||||
|
|
||||||
|
/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its
|
||||||
|
* original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK,
|
||||||
|
* the selected pointer returns to its original value after each transfer. */
|
||||||
|
typedef enum e_transfer_repeat_area
|
||||||
|
{
|
||||||
|
/** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
|
||||||
|
TRANSFER_REPEAT_AREA_DESTINATION = 0,
|
||||||
|
|
||||||
|
/** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */
|
||||||
|
TRANSFER_REPEAT_AREA_SOURCE = 1
|
||||||
|
} transfer_repeat_area_t;
|
||||||
|
|
||||||
|
/** Chain transfer mode options.
|
||||||
|
* @note Only applies for DTC. */
|
||||||
|
typedef enum e_transfer_chain_mode
|
||||||
|
{
|
||||||
|
/** Chain mode not used. */
|
||||||
|
TRANSFER_CHAIN_MODE_DISABLED = 0,
|
||||||
|
|
||||||
|
/** Switch to next transfer after a single transfer from this @ref transfer_info_t. */
|
||||||
|
TRANSFER_CHAIN_MODE_EACH = 2,
|
||||||
|
|
||||||
|
/** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */
|
||||||
|
TRANSFER_CHAIN_MODE_END = 3
|
||||||
|
} transfer_chain_mode_t;
|
||||||
|
|
||||||
|
/** Interrupt options. */
|
||||||
|
typedef enum e_transfer_irq
|
||||||
|
{
|
||||||
|
/** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer,
|
||||||
|
* the interrupt will occur only after subsequent chained transfer(s) are complete.
|
||||||
|
* @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will
|
||||||
|
* prevent activation source interrupts until the transfer is complete. */
|
||||||
|
TRANSFER_IRQ_END = 0,
|
||||||
|
|
||||||
|
/** Interrupt occurs after each transfer.
|
||||||
|
* @note Not available in all HAL drivers. See HAL driver for details. */
|
||||||
|
TRANSFER_IRQ_EACH = 1
|
||||||
|
} transfer_irq_t;
|
||||||
|
|
||||||
|
/** Driver specific information. */
|
||||||
|
typedef struct st_transfer_properties
|
||||||
|
{
|
||||||
|
uint32_t block_count_max; ///< Maximum number of blocks
|
||||||
|
uint32_t block_count_remaining; ///< Number of blocks remaining
|
||||||
|
uint32_t transfer_length_max; ///< Maximum number of transfers
|
||||||
|
uint32_t transfer_length_remaining; ///< Number of transfers remaining
|
||||||
|
} transfer_properties_t;
|
||||||
|
|
||||||
|
/** This structure specifies the properties of the transfer.
|
||||||
|
* @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC.
|
||||||
|
* The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.
|
||||||
|
* @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must
|
||||||
|
* have a unique transfer_info_t.
|
||||||
|
* @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this
|
||||||
|
* structure must remain in scope until the transfer it is used for is closed.
|
||||||
|
* @note When using DTC, consider placing instances of this structure in a protected section of memory. */
|
||||||
|
typedef struct st_transfer_info
|
||||||
|
{
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t : 16;
|
||||||
|
uint32_t : 2;
|
||||||
|
|
||||||
|
/** Select what happens to destination pointer after each transfer. */
|
||||||
|
transfer_addr_mode_t dest_addr_mode : 2;
|
||||||
|
|
||||||
|
/** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */
|
||||||
|
transfer_repeat_area_t repeat_area : 1;
|
||||||
|
|
||||||
|
/** Select if interrupts should occur after each individual transfer or after the completion of all planned
|
||||||
|
* transfers. */
|
||||||
|
transfer_irq_t irq : 1;
|
||||||
|
|
||||||
|
/** Select when the chain transfer ends. */
|
||||||
|
transfer_chain_mode_t chain_mode : 2;
|
||||||
|
|
||||||
|
uint32_t : 2;
|
||||||
|
|
||||||
|
/** Select what happens to source pointer after each transfer. */
|
||||||
|
transfer_addr_mode_t src_addr_mode : 2;
|
||||||
|
|
||||||
|
/** Select number of bytes to transfer at once. @see transfer_info_t::length. */
|
||||||
|
transfer_size_t size : 2;
|
||||||
|
|
||||||
|
/** Select mode from @ref transfer_mode_t. */
|
||||||
|
transfer_mode_t mode : 2;
|
||||||
|
};
|
||||||
|
uint32_t transfer_settings_word;
|
||||||
|
};
|
||||||
|
|
||||||
|
void const * volatile p_src; ///< Source pointer
|
||||||
|
void * volatile p_dest; ///< Destination pointer
|
||||||
|
|
||||||
|
/** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or
|
||||||
|
* @ref TRANSFER_MODE_REPEAT (DMAC only) or
|
||||||
|
* @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */
|
||||||
|
volatile uint16_t num_blocks;
|
||||||
|
|
||||||
|
/** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT,
|
||||||
|
* and @ref TRANSFER_MODE_REPEAT_BLOCK
|
||||||
|
* see HAL driver for details. */
|
||||||
|
volatile uint16_t length;
|
||||||
|
} transfer_info_t;
|
||||||
|
|
||||||
|
/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be
|
||||||
|
* initialized. */
|
||||||
|
typedef struct st_transfer_cfg
|
||||||
|
{
|
||||||
|
/** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to
|
||||||
|
* an array of chained transfers that will be completed in order. */
|
||||||
|
transfer_info_t * p_info;
|
||||||
|
|
||||||
|
void const * p_extend; ///< Extension parameter for hardware specific settings.
|
||||||
|
} transfer_cfg_t;
|
||||||
|
|
||||||
|
/** Select whether to start single or repeated transfer with software start. */
|
||||||
|
typedef enum e_transfer_start_mode
|
||||||
|
{
|
||||||
|
TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer.
|
||||||
|
TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete.
|
||||||
|
} transfer_start_mode_t;
|
||||||
|
|
||||||
|
/** Transfer functions implemented at the HAL layer will follow this API. */
|
||||||
|
typedef struct st_transfer_api
|
||||||
|
{
|
||||||
|
/** Initial configuration.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Open()
|
||||||
|
* - @ref R_DMAC_Open()
|
||||||
|
*
|
||||||
|
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||||
|
* @param[in] p_cfg Pointer to configuration structure. All elements of this structure
|
||||||
|
* must be set by user.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg);
|
||||||
|
|
||||||
|
/** Reconfigure the transfer.
|
||||||
|
* Enable the transfer if p_info is valid.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Reconfigure()
|
||||||
|
* - @ref R_DMAC_Reconfigure()
|
||||||
|
*
|
||||||
|
* @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here.
|
||||||
|
* @param[in] p_info Pointer to a new transfer info structure.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info);
|
||||||
|
|
||||||
|
/** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same.
|
||||||
|
* Enable the transfer if p_src, p_dest, and length are valid.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Reset()
|
||||||
|
* - @ref R_DMAC_Reset()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
* @param[in] p_src Pointer to source. Set to NULL if source pointer should not change.
|
||||||
|
* @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change.
|
||||||
|
* @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only,
|
||||||
|
* resets number of repeats (initially stored in transfer_info_t::num_blocks) in
|
||||||
|
* repeat mode. Not used in repeat mode for DTC.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest,
|
||||||
|
uint16_t const num_transfers);
|
||||||
|
|
||||||
|
/** Enable transfer. Transfers occur after the activation source event (or when
|
||||||
|
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as activation source).
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Enable()
|
||||||
|
* - @ref R_DMAC_Enable()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl);
|
||||||
|
|
||||||
|
/** Disable transfer. Transfers do not occur after the activation source event (or when
|
||||||
|
* @ref transfer_api_t::softwareStart is called if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source).
|
||||||
|
* @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a
|
||||||
|
* transfer.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Disable()
|
||||||
|
* - @ref R_DMAC_Disable()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl);
|
||||||
|
|
||||||
|
/** Start transfer in software.
|
||||||
|
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||||
|
* @note Not supported for DTC.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DMAC_SoftwareStart()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
* @param[in] mode Select mode from @ref transfer_start_mode_t.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode);
|
||||||
|
|
||||||
|
/** Stop transfer in software. The transfer will stop after completion of the current transfer.
|
||||||
|
* @note Not supported for DTC.
|
||||||
|
* @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT.
|
||||||
|
* @warning Only works if ELC_EVENT_ELC_NONE is chosen as the DMAC activation source.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DMAC_SoftwareStop()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl);
|
||||||
|
|
||||||
|
/** Provides information about this transfer.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_InfoGet()
|
||||||
|
* - @ref R_DMAC_InfoGet()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
* @param[out] p_properties Driver specific information.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties);
|
||||||
|
|
||||||
|
/** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_DTC_Close()
|
||||||
|
* - @ref R_DMAC_Close()
|
||||||
|
* @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl);
|
||||||
|
} transfer_api_t;
|
||||||
|
|
||||||
|
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||||
|
typedef struct st_transfer_instance
|
||||||
|
{
|
||||||
|
transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||||
|
transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||||
|
transfer_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||||
|
} transfer_instance_t;
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @} (end defgroup TRANSFER_API)
|
||||||
|
**********************************************************************************************************************/
|
|
@ -0,0 +1,293 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup RENESAS_INTERFACES
|
||||||
|
* @defgroup UART_API UART Interface
|
||||||
|
* @brief Interface for UART communications.
|
||||||
|
*
|
||||||
|
* @section UART_INTERFACE_SUMMARY Summary
|
||||||
|
* The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features:
|
||||||
|
* - Full-duplex UART communication
|
||||||
|
* - Interrupt driven transmit/receive processing
|
||||||
|
* - Callback function with returned event code
|
||||||
|
* - Runtime baud-rate change
|
||||||
|
* - Hardware resource locking during a transaction
|
||||||
|
* - CTS/RTS hardware flow control support (with an associated IOPORT pin)
|
||||||
|
*
|
||||||
|
* Implemented by:
|
||||||
|
* - @ref SCI_UART
|
||||||
|
* - @ref SCI_B_UART
|
||||||
|
*
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef R_UART_API_H
|
||||||
|
#define R_UART_API_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Includes board and MCU related header files. */
|
||||||
|
#include "bsp_api.h"
|
||||||
|
#include "r_transfer_api.h"
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** UART Event codes */
|
||||||
|
typedef enum e_sf_event
|
||||||
|
{
|
||||||
|
UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event
|
||||||
|
UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event
|
||||||
|
UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received
|
||||||
|
UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event
|
||||||
|
UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event
|
||||||
|
UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event
|
||||||
|
UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event
|
||||||
|
UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data
|
||||||
|
} uart_event_t;
|
||||||
|
|
||||||
|
/** UART Data bit length definition */
|
||||||
|
typedef enum e_uart_data_bits
|
||||||
|
{
|
||||||
|
UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit
|
||||||
|
UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit
|
||||||
|
UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit
|
||||||
|
} uart_data_bits_t;
|
||||||
|
|
||||||
|
/** UART Parity definition */
|
||||||
|
typedef enum e_uart_parity
|
||||||
|
{
|
||||||
|
UART_PARITY_OFF = 0U, ///< No parity
|
||||||
|
UART_PARITY_EVEN = 2U, ///< Even parity
|
||||||
|
UART_PARITY_ODD = 3U, ///< Odd parity
|
||||||
|
} uart_parity_t;
|
||||||
|
|
||||||
|
/** UART Stop bits definition */
|
||||||
|
typedef enum e_uart_stop_bits
|
||||||
|
{
|
||||||
|
UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit
|
||||||
|
UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit
|
||||||
|
} uart_stop_bits_t;
|
||||||
|
|
||||||
|
/** UART transaction definition */
|
||||||
|
typedef enum e_uart_dir
|
||||||
|
{
|
||||||
|
UART_DIR_RX_TX = 3U, ///< Both RX and TX
|
||||||
|
UART_DIR_RX = 1U, ///< Only RX
|
||||||
|
UART_DIR_TX = 2U, ///< Only TX
|
||||||
|
} uart_dir_t;
|
||||||
|
|
||||||
|
/** UART driver specific information */
|
||||||
|
typedef struct st_uart_info
|
||||||
|
{
|
||||||
|
/** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */
|
||||||
|
uint32_t write_bytes_max;
|
||||||
|
|
||||||
|
/** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */
|
||||||
|
uint32_t read_bytes_max;
|
||||||
|
} uart_info_t;
|
||||||
|
|
||||||
|
/** UART Callback parameter definition */
|
||||||
|
typedef struct st_uart_callback_arg
|
||||||
|
{
|
||||||
|
uint32_t channel; ///< Device channel number
|
||||||
|
uart_event_t event; ///< Event code
|
||||||
|
|
||||||
|
/** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY,
|
||||||
|
* UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */
|
||||||
|
uint32_t data;
|
||||||
|
void const * p_context; ///< Context provided to user during callback
|
||||||
|
} uart_callback_args_t;
|
||||||
|
|
||||||
|
/** UART Configuration */
|
||||||
|
typedef struct st_uart_cfg
|
||||||
|
{
|
||||||
|
/* UART generic configuration */
|
||||||
|
uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware.
|
||||||
|
uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9)
|
||||||
|
uart_parity_t parity; ///< Parity type (none or odd or even)
|
||||||
|
uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2)
|
||||||
|
uint8_t rxi_ipl; ///< Receive interrupt priority
|
||||||
|
IRQn_Type rxi_irq; ///< Receive interrupt IRQ number
|
||||||
|
uint8_t txi_ipl; ///< Transmit interrupt priority
|
||||||
|
IRQn_Type txi_irq; ///< Transmit interrupt IRQ number
|
||||||
|
uint8_t tei_ipl; ///< Transmit end interrupt priority
|
||||||
|
IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number
|
||||||
|
uint8_t eri_ipl; ///< Error interrupt priority
|
||||||
|
IRQn_Type eri_irq; ///< Error interrupt IRQ number
|
||||||
|
|
||||||
|
/** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused.
|
||||||
|
* If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */
|
||||||
|
transfer_instance_t const * p_transfer_rx;
|
||||||
|
|
||||||
|
/** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused.
|
||||||
|
* If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */
|
||||||
|
transfer_instance_t const * p_transfer_tx;
|
||||||
|
|
||||||
|
/* Configuration for UART Event processing */
|
||||||
|
void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function
|
||||||
|
void const * p_context; ///< User defined context passed into callback function
|
||||||
|
|
||||||
|
/* Pointer to UART peripheral specific configuration */
|
||||||
|
void const * p_extend; ///< UART hardware dependent configuration
|
||||||
|
} uart_cfg_t;
|
||||||
|
|
||||||
|
/** UART control block. Allocate an instance specific control block to pass into the UART API calls.
|
||||||
|
* @par Implemented as
|
||||||
|
* - sci_uart_instance_ctrl_t
|
||||||
|
*/
|
||||||
|
typedef void uart_ctrl_t;
|
||||||
|
|
||||||
|
/** Shared Interface definition for UART */
|
||||||
|
typedef struct st_uart_api
|
||||||
|
{
|
||||||
|
/** Open UART device.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_Open()
|
||||||
|
* - @ref R_SCI_B_UART_Open()
|
||||||
|
*
|
||||||
|
* @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here.
|
||||||
|
* @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by
|
||||||
|
* user.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg);
|
||||||
|
|
||||||
|
/** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the
|
||||||
|
* callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in
|
||||||
|
* the callback function with event UART_EVENT_RX_CHAR.
|
||||||
|
* The maximum transfer size is reported by infoGet().
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_Read()
|
||||||
|
* - @ref R_SCI_B_UART_Read()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block for the channel.
|
||||||
|
* @param[in] p_dest Destination address to read data from.
|
||||||
|
* @param[in] bytes Read data length.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes);
|
||||||
|
|
||||||
|
/** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer
|
||||||
|
* contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire),
|
||||||
|
* the callback called with event UART_EVENT_TX_COMPLETE.
|
||||||
|
* The maximum transfer size is reported by infoGet().
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_Write()
|
||||||
|
* - @ref R_SCI_B_UART_Write()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in] p_src Source address to write data to.
|
||||||
|
* @param[in] bytes Write data length.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes);
|
||||||
|
|
||||||
|
/** Change baud rate.
|
||||||
|
* @warning Calling this API aborts any in-progress transmission and disables reception until the new baud
|
||||||
|
* settings have been applied.
|
||||||
|
*
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_BaudSet()
|
||||||
|
* - @ref R_SCI_B_UART_BaudSet()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info);
|
||||||
|
|
||||||
|
/** Get the driver specific information.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_InfoGet()
|
||||||
|
* - @ref R_SCI_B_UART_InfoGet()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in] baudrate Baud rate in bps.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Abort ongoing transfer.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_Abort()
|
||||||
|
* - @ref R_SCI_B_UART_Abort()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in] communication_to_abort Type of abort request.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Specify callback function and optional context pointer and working memory pointer.
|
||||||
|
* @par Implemented as
|
||||||
|
* - R_SCI_Uart_CallbackSet()
|
||||||
|
* - R_SCI_B_Uart_CallbackSet()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in] p_callback Callback function
|
||||||
|
* @param[in] p_context Pointer to send to callback function
|
||||||
|
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
|
||||||
|
* Callback arguments allocated here are only valid during the callback.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* callbackSet)(uart_ctrl_t * const p_api_ctrl, void (* p_callback)(uart_callback_args_t *),
|
||||||
|
void const * const p_context, uart_callback_args_t * const p_callback_memory);
|
||||||
|
|
||||||
|
/** Close UART device.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_Close()
|
||||||
|
* - @ref R_SCI_B_UART_Close()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* close)(uart_ctrl_t * const p_ctrl);
|
||||||
|
|
||||||
|
/** Stop ongoing read and return the number of bytes remaining in the read.
|
||||||
|
* @par Implemented as
|
||||||
|
* - @ref R_SCI_UART_ReadStop()
|
||||||
|
* - @ref R_SCI_B_UART_ReadStop()
|
||||||
|
*
|
||||||
|
* @param[in] p_ctrl Pointer to the UART control block.
|
||||||
|
* @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read.
|
||||||
|
*/
|
||||||
|
fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes);
|
||||||
|
} uart_api_t;
|
||||||
|
|
||||||
|
/** This structure encompasses everything that is needed to use an instance of this interface. */
|
||||||
|
typedef struct st_uart_instance
|
||||||
|
{
|
||||||
|
uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
|
||||||
|
uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
|
||||||
|
uart_api_t const * p_api; ///< Pointer to the API structure for this instance
|
||||||
|
} uart_instance_t;
|
||||||
|
|
||||||
|
/** @} (end defgroup UART_API) */
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,364 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef FSP_COMMON_API_H
|
||||||
|
#define FSP_COMMON_API_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#include <assert.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* Includes FSP version macros. */
|
||||||
|
#include "fsp_version.h"
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @ingroup RENESAS_COMMON
|
||||||
|
* @defgroup RENESAS_ERROR_CODES Common Error Codes
|
||||||
|
* All FSP modules share these common error codes.
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing
|
||||||
|
* about using this implementation is that it does not take any extra RAM or ROM. */
|
||||||
|
|
||||||
|
#define FSP_PARAMETER_NOT_USED(p) (void) ((p))
|
||||||
|
|
||||||
|
/** Determine if a C++ compiler is being used.
|
||||||
|
* If so, ensure that standard C is used to process the API information. */
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
#define FSP_CPP_HEADER extern "C" {
|
||||||
|
#define FSP_CPP_FOOTER }
|
||||||
|
#else
|
||||||
|
#define FSP_CPP_HEADER
|
||||||
|
#define FSP_CPP_FOOTER
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** FSP Header and Footer definitions */
|
||||||
|
#define FSP_HEADER FSP_CPP_HEADER
|
||||||
|
#define FSP_FOOTER FSP_CPP_FOOTER
|
||||||
|
|
||||||
|
/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically
|
||||||
|
* defined on the Secure side. */
|
||||||
|
#define FSP_SECURE_ARGUMENT (NULL)
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Common error codes */
|
||||||
|
typedef enum e_fsp_err
|
||||||
|
{
|
||||||
|
FSP_SUCCESS = 0,
|
||||||
|
|
||||||
|
FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed
|
||||||
|
FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location
|
||||||
|
FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter
|
||||||
|
FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist
|
||||||
|
FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode
|
||||||
|
FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API
|
||||||
|
FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open
|
||||||
|
FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy
|
||||||
|
FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h
|
||||||
|
FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked
|
||||||
|
FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP
|
||||||
|
FSP_ERR_OVERFLOW = 12, ///< Hardware overflow
|
||||||
|
FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow
|
||||||
|
FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration
|
||||||
|
FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result
|
||||||
|
FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason
|
||||||
|
FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met
|
||||||
|
FSP_ERR_ABORTED = 18, ///< An operation was aborted
|
||||||
|
FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled
|
||||||
|
FSP_ERR_TIMEOUT = 20, ///< Timeout error
|
||||||
|
FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied
|
||||||
|
FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied
|
||||||
|
FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation
|
||||||
|
FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed
|
||||||
|
FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed
|
||||||
|
FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made
|
||||||
|
FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition
|
||||||
|
FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU
|
||||||
|
FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state
|
||||||
|
FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed
|
||||||
|
FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed
|
||||||
|
FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete
|
||||||
|
FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found
|
||||||
|
FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback
|
||||||
|
FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer
|
||||||
|
FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed
|
||||||
|
|
||||||
|
/* Start of RTOS only error codes */
|
||||||
|
FSP_ERR_INTERNAL = 100, ///< Internal error
|
||||||
|
FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted
|
||||||
|
|
||||||
|
/* Start of UART specific */
|
||||||
|
FSP_ERR_FRAMING = 200, ///< Framing error occurs
|
||||||
|
FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects
|
||||||
|
FSP_ERR_PARITY = 202, ///< Parity error occurs
|
||||||
|
FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow
|
||||||
|
FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue
|
||||||
|
FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer
|
||||||
|
FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer
|
||||||
|
|
||||||
|
/* Start of SPI specific */
|
||||||
|
FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted.
|
||||||
|
FSP_ERR_MODE_FAULT = 301, ///< Mode fault error.
|
||||||
|
FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow.
|
||||||
|
FSP_ERR_SPI_PARITY = 303, ///< Parity error.
|
||||||
|
FSP_ERR_OVERRUN = 304, ///< Overrun error.
|
||||||
|
|
||||||
|
/* Start of CGC Specific */
|
||||||
|
FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock.
|
||||||
|
FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first.
|
||||||
|
FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off
|
||||||
|
FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off
|
||||||
|
FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled
|
||||||
|
FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set
|
||||||
|
FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active
|
||||||
|
FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit
|
||||||
|
FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled
|
||||||
|
FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out
|
||||||
|
FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode
|
||||||
|
|
||||||
|
/* Start of FLASH Specific */
|
||||||
|
FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode.
|
||||||
|
FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state
|
||||||
|
FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz
|
||||||
|
FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory
|
||||||
|
FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed
|
||||||
|
|
||||||
|
/* Start of CAC Specific */
|
||||||
|
FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate
|
||||||
|
|
||||||
|
/* Start of GLCD Specific */
|
||||||
|
FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock
|
||||||
|
FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter
|
||||||
|
FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter
|
||||||
|
FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found
|
||||||
|
FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter
|
||||||
|
FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer
|
||||||
|
FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update
|
||||||
|
FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry
|
||||||
|
FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting
|
||||||
|
FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter
|
||||||
|
|
||||||
|
/* Start of JPEG Specific */
|
||||||
|
FSP_ERR_JPEG_ERR = 1100, ///< JPEG error
|
||||||
|
FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected.
|
||||||
|
FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected.
|
||||||
|
FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected.
|
||||||
|
FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected.
|
||||||
|
FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected.
|
||||||
|
FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4.
|
||||||
|
FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS.
|
||||||
|
FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected.
|
||||||
|
FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected.
|
||||||
|
FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default)
|
||||||
|
FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected.
|
||||||
|
FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected.
|
||||||
|
FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected.
|
||||||
|
FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected.
|
||||||
|
FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough
|
||||||
|
FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU
|
||||||
|
|
||||||
|
/* Start of touch panel framework specific */
|
||||||
|
FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed
|
||||||
|
|
||||||
|
/* Start of IP specific */
|
||||||
|
FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device
|
||||||
|
FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device
|
||||||
|
FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device
|
||||||
|
|
||||||
|
/* Start of USB specific */
|
||||||
|
FSP_ERR_USB_FAILED = 1500,
|
||||||
|
FSP_ERR_USB_BUSY = 1501,
|
||||||
|
FSP_ERR_USB_SIZE_SHORT = 1502,
|
||||||
|
FSP_ERR_USB_SIZE_OVER = 1503,
|
||||||
|
FSP_ERR_USB_NOT_OPEN = 1504,
|
||||||
|
FSP_ERR_USB_NOT_SUSPEND = 1505,
|
||||||
|
FSP_ERR_USB_PARAMETER = 1506,
|
||||||
|
|
||||||
|
/* Start of Message framework specific */
|
||||||
|
FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool
|
||||||
|
FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool
|
||||||
|
FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid
|
||||||
|
FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid
|
||||||
|
FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many
|
||||||
|
FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found
|
||||||
|
FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue
|
||||||
|
FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue
|
||||||
|
FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal
|
||||||
|
FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released
|
||||||
|
|
||||||
|
/* Start of 2DG Driver specific */
|
||||||
|
FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization
|
||||||
|
FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization
|
||||||
|
FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering
|
||||||
|
FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering
|
||||||
|
|
||||||
|
/* Start of ETHER Driver specific */
|
||||||
|
FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer.
|
||||||
|
FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation
|
||||||
|
FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled
|
||||||
|
FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty
|
||||||
|
FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable
|
||||||
|
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication
|
||||||
|
FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active.
|
||||||
|
|
||||||
|
/* Start of ETHER_PHY Driver specific */
|
||||||
|
FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up.
|
||||||
|
FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation
|
||||||
|
|
||||||
|
/* Start of BYTEQ library specific */
|
||||||
|
FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data
|
||||||
|
FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue
|
||||||
|
|
||||||
|
/* Start of CTSU Driver specific */
|
||||||
|
FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning.
|
||||||
|
FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data.
|
||||||
|
FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning.
|
||||||
|
FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet.
|
||||||
|
FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed.
|
||||||
|
FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed.
|
||||||
|
|
||||||
|
/* Start of SDMMC specific */
|
||||||
|
FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize.
|
||||||
|
FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed.
|
||||||
|
FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing.
|
||||||
|
FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed.
|
||||||
|
FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected.
|
||||||
|
FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress.
|
||||||
|
FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error.
|
||||||
|
|
||||||
|
/* Start of FX_IO specific */
|
||||||
|
FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed.
|
||||||
|
FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed.
|
||||||
|
|
||||||
|
/* Start of CAN specific */
|
||||||
|
FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available.
|
||||||
|
FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed.
|
||||||
|
FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed.
|
||||||
|
FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress.
|
||||||
|
FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox.
|
||||||
|
FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox.
|
||||||
|
FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun.
|
||||||
|
FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full.
|
||||||
|
|
||||||
|
/* Start of SF_WIFI Specific */
|
||||||
|
FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed.
|
||||||
|
FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed.
|
||||||
|
FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed
|
||||||
|
FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode
|
||||||
|
FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed.
|
||||||
|
FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed.
|
||||||
|
FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point
|
||||||
|
|
||||||
|
/* Start of SF_CELLULAR Specific */
|
||||||
|
FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed.
|
||||||
|
FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed.
|
||||||
|
FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed
|
||||||
|
FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate
|
||||||
|
FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed
|
||||||
|
FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed.
|
||||||
|
FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state.
|
||||||
|
FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed
|
||||||
|
|
||||||
|
/* Start of SF_BLE specific */
|
||||||
|
FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed
|
||||||
|
FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed
|
||||||
|
FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed
|
||||||
|
FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled
|
||||||
|
FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled
|
||||||
|
|
||||||
|
/* Start of SF_BLE_ABS specific */
|
||||||
|
FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed.
|
||||||
|
FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found.
|
||||||
|
|
||||||
|
/* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */
|
||||||
|
FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function
|
||||||
|
FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy
|
||||||
|
FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty
|
||||||
|
FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index
|
||||||
|
FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry
|
||||||
|
FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed
|
||||||
|
FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened
|
||||||
|
FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized
|
||||||
|
FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred
|
||||||
|
FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter
|
||||||
|
FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented
|
||||||
|
FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified
|
||||||
|
FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred
|
||||||
|
FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid
|
||||||
|
FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state
|
||||||
|
FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened
|
||||||
|
FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid.
|
||||||
|
FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed
|
||||||
|
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher
|
||||||
|
FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed
|
||||||
|
FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal.
|
||||||
|
FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred.
|
||||||
|
|
||||||
|
/* Start of SF_CRYPTO specific */
|
||||||
|
FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened
|
||||||
|
FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error
|
||||||
|
FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key
|
||||||
|
FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold
|
||||||
|
FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode.
|
||||||
|
FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long.
|
||||||
|
FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error.
|
||||||
|
|
||||||
|
/** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module.
|
||||||
|
* Refer to sf_cryoto_err.h for Crypto error codes.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Start of Sensor specific */
|
||||||
|
FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid.
|
||||||
|
FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing.
|
||||||
|
FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished.
|
||||||
|
|
||||||
|
/* Start of COMMS specific */
|
||||||
|
FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open.
|
||||||
|
} fsp_err_t;
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Function prototypes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,294 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef FSP_FEATURES_H
|
||||||
|
#define FSP_FEATURES_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes <System Includes> , "Project Includes"
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* C99 includes. */
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stddef.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
#include <assert.h>
|
||||||
|
|
||||||
|
/* Different compiler support. */
|
||||||
|
#include "fsp_common_api.h"
|
||||||
|
#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h"
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup BSP_MCU
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Available modules. */
|
||||||
|
typedef enum e_fsp_ip
|
||||||
|
{
|
||||||
|
FSP_IP_CFLASH = 0, ///< Code Flash
|
||||||
|
FSP_IP_DFLASH = 1, ///< Data Flash
|
||||||
|
FSP_IP_RAM = 2, ///< RAM
|
||||||
|
FSP_IP_LVD = 3, ///< Low Voltage Detection
|
||||||
|
FSP_IP_CGC = 3, ///< Clock Generation Circuit
|
||||||
|
FSP_IP_LPM = 3, ///< Low Power Modes
|
||||||
|
FSP_IP_FCU = 4, ///< Flash Control Unit
|
||||||
|
FSP_IP_ICU = 6, ///< Interrupt Control Unit
|
||||||
|
FSP_IP_DMAC = 7, ///< DMA Controller
|
||||||
|
FSP_IP_DTC = 8, ///< Data Transfer Controller
|
||||||
|
FSP_IP_IOPORT = 9, ///< I/O Ports
|
||||||
|
FSP_IP_PFS = 10, ///< Pin Function Select
|
||||||
|
FSP_IP_ELC = 11, ///< Event Link Controller
|
||||||
|
FSP_IP_MPU = 13, ///< Memory Protection Unit
|
||||||
|
FSP_IP_MSTP = 14, ///< Module Stop
|
||||||
|
FSP_IP_MMF = 15, ///< Memory Mirror Function
|
||||||
|
FSP_IP_KEY = 16, ///< Key Interrupt Function
|
||||||
|
FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit
|
||||||
|
FSP_IP_DOC = 18, ///< Data Operation Circuit
|
||||||
|
FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator
|
||||||
|
FSP_IP_SCI = 20, ///< Serial Communications Interface
|
||||||
|
FSP_IP_IIC = 21, ///< I2C Bus Interface
|
||||||
|
FSP_IP_SPI = 22, ///< Serial Peripheral Interface
|
||||||
|
FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit
|
||||||
|
FSP_IP_SCE = 24, ///< Secure Cryptographic Engine
|
||||||
|
FSP_IP_SLCDC = 25, ///< Segment LCD Controller
|
||||||
|
FSP_IP_AES = 26, ///< Advanced Encryption Standard
|
||||||
|
FSP_IP_TRNG = 27, ///< True Random Number Generator
|
||||||
|
FSP_IP_FCACHE = 30, ///< Flash Cache
|
||||||
|
FSP_IP_SRAM = 31, ///< SRAM
|
||||||
|
FSP_IP_ADC = 32, ///< A/D Converter
|
||||||
|
FSP_IP_DAC = 33, ///< 12-Bit D/A Converter
|
||||||
|
FSP_IP_TSN = 34, ///< Temperature Sensor
|
||||||
|
FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit
|
||||||
|
FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator
|
||||||
|
FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator
|
||||||
|
FSP_IP_OPAMP = 38, ///< Operational Amplifier
|
||||||
|
FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter
|
||||||
|
FSP_IP_RTC = 40, ///< Real Time Clock
|
||||||
|
FSP_IP_WDT = 41, ///< Watch Dog Timer
|
||||||
|
FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer
|
||||||
|
FSP_IP_GPT = 43, ///< General PWM Timer
|
||||||
|
FSP_IP_POEG = 44, ///< Port Output Enable for GPT
|
||||||
|
FSP_IP_OPS = 45, ///< Output Phase Switch
|
||||||
|
FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer
|
||||||
|
FSP_IP_CAN = 48, ///< Controller Area Network
|
||||||
|
FSP_IP_IRDA = 49, ///< Infrared Data Association
|
||||||
|
FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface
|
||||||
|
FSP_IP_USBFS = 51, ///< USB Full Speed
|
||||||
|
FSP_IP_SDHI = 52, ///< SD/MMC Host Interface
|
||||||
|
FSP_IP_SRC = 53, ///< Sampling Rate Converter
|
||||||
|
FSP_IP_SSI = 54, ///< Serial Sound Interface
|
||||||
|
FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface
|
||||||
|
FSP_IP_ETHER = 64, ///< Ethernet MAC Controller
|
||||||
|
FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller
|
||||||
|
FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller
|
||||||
|
FSP_IP_PDC = 66, ///< Parallel Data Capture Unit
|
||||||
|
FSP_IP_GLCDC = 67, ///< Graphics LCD Controller
|
||||||
|
FSP_IP_DRW = 68, ///< 2D Drawing Engine
|
||||||
|
FSP_IP_JPEG = 69, ///< JPEG
|
||||||
|
FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter
|
||||||
|
FSP_IP_USBHS = 71, ///< USB High Speed
|
||||||
|
FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface
|
||||||
|
FSP_IP_CEC = 73, ///< HDMI CEC
|
||||||
|
FSP_IP_TFU = 74, ///< Trigonometric Function Unit
|
||||||
|
FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator
|
||||||
|
FSP_IP_CANFD = 76, ///< CAN-FD
|
||||||
|
} fsp_ip_t;
|
||||||
|
|
||||||
|
/** Signals that can be mapped to an interrupt. */
|
||||||
|
typedef enum e_fsp_signal
|
||||||
|
{
|
||||||
|
FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH
|
||||||
|
FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH
|
||||||
|
FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END
|
||||||
|
FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B
|
||||||
|
FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A
|
||||||
|
FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B
|
||||||
|
FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ
|
||||||
|
FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ
|
||||||
|
FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A
|
||||||
|
FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B
|
||||||
|
FSP_SIGNAL_AGT_INT, ///< AGT INT
|
||||||
|
FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR
|
||||||
|
FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END
|
||||||
|
FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW
|
||||||
|
FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR
|
||||||
|
FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX
|
||||||
|
FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX
|
||||||
|
FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX
|
||||||
|
FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX
|
||||||
|
FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP
|
||||||
|
FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST
|
||||||
|
FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1
|
||||||
|
FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2
|
||||||
|
FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD
|
||||||
|
FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT
|
||||||
|
FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT
|
||||||
|
FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT
|
||||||
|
FSP_SIGNAL_CTSU_END = 0, ///< CTSU END
|
||||||
|
FSP_SIGNAL_CTSU_READ, ///< CTSU READ
|
||||||
|
FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE
|
||||||
|
FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI
|
||||||
|
FSP_SIGNAL_DALI_CLI, ///< DALI CLI
|
||||||
|
FSP_SIGNAL_DALI_SDI, ///< DALI SDI
|
||||||
|
FSP_SIGNAL_DALI_BPI, ///< DALI BPI
|
||||||
|
FSP_SIGNAL_DALI_FEI, ///< DALI FEI
|
||||||
|
FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI
|
||||||
|
FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT
|
||||||
|
FSP_SIGNAL_DOC_INT = 0, ///< DOC INT
|
||||||
|
FSP_SIGNAL_DRW_INT = 0, ///< DRW INT
|
||||||
|
FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE
|
||||||
|
FSP_SIGNAL_DTC_END, ///< DTC END
|
||||||
|
FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT
|
||||||
|
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0
|
||||||
|
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1
|
||||||
|
FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS
|
||||||
|
FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT
|
||||||
|
FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL
|
||||||
|
FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE
|
||||||
|
FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR
|
||||||
|
FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI
|
||||||
|
FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT
|
||||||
|
FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1
|
||||||
|
FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2
|
||||||
|
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A
|
||||||
|
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B
|
||||||
|
FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C
|
||||||
|
FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D
|
||||||
|
FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E
|
||||||
|
FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F
|
||||||
|
FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW
|
||||||
|
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW
|
||||||
|
FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A
|
||||||
|
FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B
|
||||||
|
FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE
|
||||||
|
FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0
|
||||||
|
FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1
|
||||||
|
FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2
|
||||||
|
FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3
|
||||||
|
FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4
|
||||||
|
FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5
|
||||||
|
FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6
|
||||||
|
FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7
|
||||||
|
FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8
|
||||||
|
FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9
|
||||||
|
FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10
|
||||||
|
FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11
|
||||||
|
FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12
|
||||||
|
FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13
|
||||||
|
FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14
|
||||||
|
FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15
|
||||||
|
FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL
|
||||||
|
FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI
|
||||||
|
FSP_SIGNAL_IIC_RXI, ///< IIC RXI
|
||||||
|
FSP_SIGNAL_IIC_TEI, ///< IIC TEI
|
||||||
|
FSP_SIGNAL_IIC_TXI, ///< IIC TXI
|
||||||
|
FSP_SIGNAL_IIC_WUI, ///< IIC WUI
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D
|
||||||
|
FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E
|
||||||
|
FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW
|
||||||
|
FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI
|
||||||
|
FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI
|
||||||
|
FSP_SIGNAL_KEY_INT = 0, ///< KEY INT
|
||||||
|
FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END
|
||||||
|
FSP_SIGNAL_PDC_INT, ///< PDC INT
|
||||||
|
FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY
|
||||||
|
FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT
|
||||||
|
FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT
|
||||||
|
FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM
|
||||||
|
FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD
|
||||||
|
FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY
|
||||||
|
FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY
|
||||||
|
FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY
|
||||||
|
FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG
|
||||||
|
FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY
|
||||||
|
FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0
|
||||||
|
FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1
|
||||||
|
FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK
|
||||||
|
FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY
|
||||||
|
FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0
|
||||||
|
FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1
|
||||||
|
FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4
|
||||||
|
FSP_SIGNAL_SCI_AM = 0, ///< SCI AM
|
||||||
|
FSP_SIGNAL_SCI_ERI, ///< SCI ERI
|
||||||
|
FSP_SIGNAL_SCI_RXI, ///< SCI RXI
|
||||||
|
FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI
|
||||||
|
FSP_SIGNAL_SCI_TEI, ///< SCI TEI
|
||||||
|
FSP_SIGNAL_SCI_TXI, ///< SCI TXI
|
||||||
|
FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI
|
||||||
|
FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND
|
||||||
|
FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND
|
||||||
|
FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS
|
||||||
|
FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD
|
||||||
|
FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ
|
||||||
|
FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO
|
||||||
|
FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI
|
||||||
|
FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE
|
||||||
|
FSP_SIGNAL_SPI_RXI, ///< SPI RXI
|
||||||
|
FSP_SIGNAL_SPI_TEI, ///< SPI TEI
|
||||||
|
FSP_SIGNAL_SPI_TXI, ///< SPI TXI
|
||||||
|
FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END
|
||||||
|
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY
|
||||||
|
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL
|
||||||
|
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW
|
||||||
|
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW
|
||||||
|
FSP_SIGNAL_SSI_INT = 0, ///< SSI INT
|
||||||
|
FSP_SIGNAL_SSI_RXI, ///< SSI RXI
|
||||||
|
FSP_SIGNAL_SSI_TXI, ///< SSI TXI
|
||||||
|
FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI
|
||||||
|
FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ
|
||||||
|
FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0
|
||||||
|
FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1
|
||||||
|
FSP_SIGNAL_USB_INT, ///< USB INT
|
||||||
|
FSP_SIGNAL_USB_RESUME, ///< USB RESUME
|
||||||
|
FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME
|
||||||
|
FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW
|
||||||
|
} fsp_signal_t;
|
||||||
|
|
||||||
|
typedef void (* fsp_vector_t)(void);
|
||||||
|
|
||||||
|
/** @} (end addtogroup BSP_MCU) */
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,80 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef FSP_VERSION_H
|
||||||
|
#define FSP_VERSION_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Includes board and MCU related header files. */
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup RENESAS_COMMON
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** FSP pack major version. */
|
||||||
|
#define FSP_VERSION_MAJOR (3U)
|
||||||
|
|
||||||
|
/** FSP pack minor version. */
|
||||||
|
#define FSP_VERSION_MINOR (5U)
|
||||||
|
|
||||||
|
/** FSP pack patch version. */
|
||||||
|
#define FSP_VERSION_PATCH (0U)
|
||||||
|
|
||||||
|
/** FSP pack version build number (currently unused). */
|
||||||
|
#define FSP_VERSION_BUILD (0U)
|
||||||
|
|
||||||
|
/** Public FSP version name. */
|
||||||
|
#define FSP_VERSION_STRING ("3.5.0")
|
||||||
|
|
||||||
|
/** Unique FSP version ID. */
|
||||||
|
#define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 3.5.0")
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** FSP Pack version structure */
|
||||||
|
typedef union st_fsp_pack_version
|
||||||
|
{
|
||||||
|
/** Version id */
|
||||||
|
uint32_t version_id;
|
||||||
|
|
||||||
|
/** Code version parameters, little endian order. */
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint8_t build; ///< Build version of FSP Pack
|
||||||
|
uint8_t patch; ///< Patch version of FSP Pack
|
||||||
|
uint8_t minor; ///< Minor version of FSP Pack
|
||||||
|
uint8_t major; ///< Major version of FSP Pack
|
||||||
|
};
|
||||||
|
} fsp_pack_version_t;
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,244 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup GLCDC
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef R_GLCDC_H
|
||||||
|
#define R_GLCDC_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#include "bsp_api.h"
|
||||||
|
#include "r_display_api.h"
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** Display control block. DO NOT INITIALIZE. */
|
||||||
|
typedef struct st_glcdc_instance_ctrl
|
||||||
|
{
|
||||||
|
display_state_t state; // Status of GLCDC module
|
||||||
|
|
||||||
|
/* Parameters to Event processing for display devices */
|
||||||
|
void (* p_callback)(display_callback_args_t * p_args); // Pointer to callback function
|
||||||
|
void const * p_context; // Pointer to the higher level device context
|
||||||
|
const display_cfg_t * p_cfg; // Pointer to initial configurations
|
||||||
|
} glcdc_instance_ctrl_t;
|
||||||
|
|
||||||
|
/** Clock source select */
|
||||||
|
typedef enum e_glcdc_clk_src
|
||||||
|
{
|
||||||
|
GLCDC_CLK_SRC_INTERNAL, ///< Internal
|
||||||
|
GLCDC_CLK_SRC_EXTERNAL, ///< External
|
||||||
|
} glcdc_clk_src_t;
|
||||||
|
|
||||||
|
/** Clock frequency division ratio */
|
||||||
|
typedef enum e_glcdc_panel_clk_div
|
||||||
|
{
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_1 = 1, ///< Division Ratio 1/1
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_2 = 2, ///< Division Ratio 1/2
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_3 = 3, ///< Division Ratio 1/3
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_4 = 4, ///< Division Ratio 1/4
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_5 = 5, ///< Division Ratio 1/5
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_6 = 6, ///< Division Ratio 1/6
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_7 = 7, ///< Division Ratio 1/7
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_8 = 8, ///< Division Ratio 1/8
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_9 = 9, ///< Division Ratio 1/9
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_12 = 12, ///< Division Ratio 1/12
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_16 = 16, ///< Division Ratio 1/16
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_24 = 24, ///< Division Ratio 1/24
|
||||||
|
GLCDC_PANEL_CLK_DIVISOR_32 = 32, ///< Division Ratio 1/32
|
||||||
|
} glcdc_panel_clk_div_t;
|
||||||
|
|
||||||
|
/** LCD TCON output pin select */
|
||||||
|
typedef enum e_glcdc_tcon_pin
|
||||||
|
{
|
||||||
|
GLCDC_TCON_PIN_NONE = -1, ///< No output
|
||||||
|
GLCDC_TCON_PIN_0, ///< LCD_TCON0
|
||||||
|
GLCDC_TCON_PIN_1, ///< LCD_TCON1
|
||||||
|
GLCDC_TCON_PIN_2, ///< LCD_TCON2
|
||||||
|
GLCDC_TCON_PIN_3, ///< LCD_TCON3
|
||||||
|
} glcdc_tcon_pin_t;
|
||||||
|
|
||||||
|
/** Bus Arbitration setting */
|
||||||
|
typedef enum e_glcdc_bus_arbitraion
|
||||||
|
{
|
||||||
|
GLCDC_BUS_ARBITRATION_ROUNDROBIN, ///< Round robin
|
||||||
|
GLCDC_BUS_ARBITRATION_FIX_PRIORITY ///< Fixed
|
||||||
|
} glcdc_bus_arbitration_t;
|
||||||
|
|
||||||
|
/** Correction circuit sequence control */
|
||||||
|
typedef enum e_glcdc_correction_proc_order
|
||||||
|
{
|
||||||
|
GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA, ///< Brightness -> contrast -> gamma correction
|
||||||
|
GLCDC_CORRECTION_PROC_ORDER_GAMMA2BRIGHTNESS_CONTRAST ///< Gamma correction -> brightness -> contrast
|
||||||
|
} glcdc_correction_proc_order_t;
|
||||||
|
|
||||||
|
/** Timing signals for driving the LCD panel */
|
||||||
|
typedef enum e_glcdc_tcon_signal_select
|
||||||
|
{
|
||||||
|
GLCDC_TCON_SIGNAL_SELECT_STVA_VS = 0, ///< STVA/VS
|
||||||
|
GLCDC_TCON_SIGNAL_SELECT_STVB_VE = 1, ///< STVB/VE
|
||||||
|
GLCDC_TCON_SIGNAL_SELECT_STHA_HS = 2, ///< STH/SP/HS
|
||||||
|
GLCDC_TCON_SIGNAL_SELECT_STHB_HE = 3, ///< STB/LP/HE
|
||||||
|
GLCDC_TCON_SIGNAL_SELECT_DE = 7 ///< DE
|
||||||
|
} glcdc_tcon_signal_select_t;
|
||||||
|
|
||||||
|
/** Clock phase adjustment for serial RGB output */
|
||||||
|
typedef enum e_glcdc_clut_plane
|
||||||
|
{
|
||||||
|
GLCDC_CLUT_PLANE_0 = 0, ///< GLCDC CLUT plane 0
|
||||||
|
GLCDC_CLUT_PLANE_1 = 1, ///< GLCDC CLUT plane 1
|
||||||
|
} glcdc_clut_plane_t;
|
||||||
|
|
||||||
|
/** Dithering mode */
|
||||||
|
typedef enum e_glcdc_dithering_mode
|
||||||
|
{
|
||||||
|
GLCDC_DITHERING_MODE_TRUNCATE = 0, ///< No dithering (truncate)
|
||||||
|
GLCDC_DITHERING_MODE_ROUND_OFF = 1, ///< Dithering with round off
|
||||||
|
GLCDC_DITHERING_MODE_2X2PATTERN = 2, ///< Dithering with 2x2 pattern
|
||||||
|
GLCDC_DITHERING_MODE_SETTING_MAX
|
||||||
|
} glcdc_dithering_mode_t;
|
||||||
|
|
||||||
|
/** Dithering mode */
|
||||||
|
typedef enum e_glcdc_dithering_pattern
|
||||||
|
{
|
||||||
|
GLCDC_DITHERING_PATTERN_00 = 0, ///< 2x2 pattern '00'
|
||||||
|
GLCDC_DITHERING_PATTERN_01 = 1, ///< 2x2 pattern '01'
|
||||||
|
GLCDC_DITHERING_PATTERN_10 = 2, ///< 2x2 pattern '10'
|
||||||
|
GLCDC_DITHERING_PATTERN_11 = 3, ///< 2x2 pattern '11'
|
||||||
|
} glcdc_dithering_pattern_t;
|
||||||
|
|
||||||
|
/** Output interface format */
|
||||||
|
typedef enum e_glcdc_input_interface_format
|
||||||
|
{
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_RGB565 = 0, ///< Input interface format RGB565
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_RGB888 = 1, ///< Input interface format RGB888
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555 = 2, ///< Input interface format ARGB1555
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444 = 3, ///< Input interface format ARGB4444
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888 = 4, ///< Input interface format ARGB8888
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_CLUT8 = 5, ///< Input interface format CLUT8
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_CLUT4 = 6, ///< Input interface format CLUT4
|
||||||
|
GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 = 7, ///< Input interface format CLUT1
|
||||||
|
} glcdc_input_interface_format_t;
|
||||||
|
|
||||||
|
/** Output interface format */
|
||||||
|
typedef enum e_glcdc_output_interface_format
|
||||||
|
{
|
||||||
|
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888 = 0, ///< Output interface format RGB888
|
||||||
|
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666 = 1, ///< Output interface format RGB666
|
||||||
|
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565 = 2, ///< Output interface format RGB565
|
||||||
|
GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB = 3, ///< Output interface format Serial RGB
|
||||||
|
} glcdc_output_interface_format_t;
|
||||||
|
|
||||||
|
/** Dithering output format */
|
||||||
|
typedef enum e_glcdc_dithering_output_format
|
||||||
|
{
|
||||||
|
GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 = 0, ///< Dithering output format RGB888
|
||||||
|
GLCDC_DITHERING_OUTPUT_FORMAT_RGB666 = 1, ///< Dithering output format RGB666
|
||||||
|
GLCDC_DITHERING_OUTPUT_FORMAT_RGB565 = 2, ///< Dithering output format RGB565
|
||||||
|
} glcdc_dithering_output_format_t;
|
||||||
|
|
||||||
|
/** GLCDC hardware specific configuration */
|
||||||
|
typedef struct st_glcdc_extended_cfg
|
||||||
|
{
|
||||||
|
glcdc_tcon_pin_t tcon_hsync; ///< GLCDC TCON output pin select
|
||||||
|
glcdc_tcon_pin_t tcon_vsync; ///< GLCDC TCON output pin select
|
||||||
|
glcdc_tcon_pin_t tcon_de; ///< GLCDC TCON output pin select
|
||||||
|
glcdc_correction_proc_order_t correction_proc_order; ///< Correction control route select
|
||||||
|
glcdc_clk_src_t clksrc; ///< Clock Source selection
|
||||||
|
glcdc_panel_clk_div_t clock_div_ratio; ///< Clock divide ratio for dot clock
|
||||||
|
glcdc_dithering_mode_t dithering_mode; ///< Dithering mode
|
||||||
|
glcdc_dithering_pattern_t dithering_pattern_A; ///< Dithering pattern A
|
||||||
|
glcdc_dithering_pattern_t dithering_pattern_B; ///< Dithering pattern B
|
||||||
|
glcdc_dithering_pattern_t dithering_pattern_C; ///< Dithering pattern C
|
||||||
|
glcdc_dithering_pattern_t dithering_pattern_D; ///< Dithering pattern D
|
||||||
|
} glcdc_extended_cfg_t;
|
||||||
|
|
||||||
|
/* GLCDC hardware specific control block */
|
||||||
|
typedef struct st_glcdc_ctrl
|
||||||
|
{
|
||||||
|
display_coordinate_t back_porch; ///< Zero coordinate for graphics plane(Back porch end)
|
||||||
|
uint16_t hsize; ///< Horizontal pixel size in a line
|
||||||
|
uint16_t vsize; ///< Vertical pixel size in a frame
|
||||||
|
void * p_context; ///< Pointer to the function level device context
|
||||||
|
// (e.g. display_ctrl_t type data)
|
||||||
|
} glcdc_ctrl_t;
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* @cond INC_HEADER_DEFS_SEC */
|
||||||
|
/* Filled in Interface API structure for this Instance. */
|
||||||
|
extern const display_api_t g_display_on_glcdc;
|
||||||
|
|
||||||
|
/* @endcond */
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Public APIs
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
fsp_err_t R_GLCDC_Open(display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg);
|
||||||
|
fsp_err_t R_GLCDC_Close(display_ctrl_t * const p_api_ctrl);
|
||||||
|
fsp_err_t R_GLCDC_Start(display_ctrl_t * const p_api_ctrl);
|
||||||
|
fsp_err_t R_GLCDC_Stop(display_ctrl_t * const p_api_ctrl);
|
||||||
|
fsp_err_t R_GLCDC_LayerChange(display_ctrl_t const * const p_api_ctrl,
|
||||||
|
display_runtime_cfg_t const * const p_cfg,
|
||||||
|
display_frame_layer_t layer);
|
||||||
|
fsp_err_t R_GLCDC_BufferChange(display_ctrl_t const * const p_api_ctrl,
|
||||||
|
uint8_t * const framebuffer,
|
||||||
|
display_frame_layer_t layer);
|
||||||
|
|
||||||
|
#if GLCDC_CFG_COLOR_CORRECTION_ENABLE
|
||||||
|
fsp_err_t R_GLCDC_ColorCorrection(display_ctrl_t const * const p_api_ctrl,
|
||||||
|
display_correction_t const * const p_correction);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
fsp_err_t R_GLCDC_ClutUpdate(display_ctrl_t const * const p_api_ctrl,
|
||||||
|
display_clut_cfg_t const * const p_clut_cfg,
|
||||||
|
display_frame_layer_t layer);
|
||||||
|
fsp_err_t R_GLCDC_ClutEdit(display_ctrl_t const * const p_api_ctrl,
|
||||||
|
display_frame_layer_t layer,
|
||||||
|
uint8_t index,
|
||||||
|
uint32_t color);
|
||||||
|
fsp_err_t R_GLCDC_StatusGet(display_ctrl_t const * const p_api_ctrl, display_status_t * const status);
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @} (end defgroup GLCDC)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,359 @@
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
|
||||||
|
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
|
||||||
|
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
|
||||||
|
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
|
||||||
|
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
|
||||||
|
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
|
||||||
|
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
|
||||||
|
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
|
||||||
|
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
|
||||||
|
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
|
||||||
|
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
|
||||||
|
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
|
||||||
|
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
|
||||||
|
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
|
||||||
|
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @addtogroup IOPORT
|
||||||
|
* @{
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef R_IOPORT_H
|
||||||
|
#define R_IOPORT_H
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Includes
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
#include "bsp_api.h"
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
|
||||||
|
FSP_HEADER
|
||||||
|
|
||||||
|
#include "r_ioport_api.h"
|
||||||
|
#include "r_ioport_cfg.h"
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Macro definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Typedef definitions
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */
|
||||||
|
typedef struct st_ioport_instance_ctrl
|
||||||
|
{
|
||||||
|
uint32_t open;
|
||||||
|
void const * p_context;
|
||||||
|
} ioport_instance_ctrl_t;
|
||||||
|
|
||||||
|
/* This typedef is here temporarily. See SWFLEX-144 for details. */
|
||||||
|
/** Superset list of all possible IO port pins. */
|
||||||
|
typedef enum e_ioport_port_pin_t
|
||||||
|
{
|
||||||
|
IOPORT_PORT_00_PIN_00 = 0x0000, ///< IO port 0 pin 0
|
||||||
|
IOPORT_PORT_00_PIN_01 = 0x0001, ///< IO port 0 pin 1
|
||||||
|
IOPORT_PORT_00_PIN_02 = 0x0002, ///< IO port 0 pin 2
|
||||||
|
IOPORT_PORT_00_PIN_03 = 0x0003, ///< IO port 0 pin 3
|
||||||
|
IOPORT_PORT_00_PIN_04 = 0x0004, ///< IO port 0 pin 4
|
||||||
|
IOPORT_PORT_00_PIN_05 = 0x0005, ///< IO port 0 pin 5
|
||||||
|
IOPORT_PORT_00_PIN_06 = 0x0006, ///< IO port 0 pin 6
|
||||||
|
IOPORT_PORT_00_PIN_07 = 0x0007, ///< IO port 0 pin 7
|
||||||
|
IOPORT_PORT_00_PIN_08 = 0x0008, ///< IO port 0 pin 8
|
||||||
|
IOPORT_PORT_00_PIN_09 = 0x0009, ///< IO port 0 pin 9
|
||||||
|
IOPORT_PORT_00_PIN_10 = 0x000A, ///< IO port 0 pin 10
|
||||||
|
IOPORT_PORT_00_PIN_11 = 0x000B, ///< IO port 0 pin 11
|
||||||
|
IOPORT_PORT_00_PIN_12 = 0x000C, ///< IO port 0 pin 12
|
||||||
|
IOPORT_PORT_00_PIN_13 = 0x000D, ///< IO port 0 pin 13
|
||||||
|
IOPORT_PORT_00_PIN_14 = 0x000E, ///< IO port 0 pin 14
|
||||||
|
IOPORT_PORT_00_PIN_15 = 0x000F, ///< IO port 0 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_01_PIN_00 = 0x0100, ///< IO port 1 pin 0
|
||||||
|
IOPORT_PORT_01_PIN_01 = 0x0101, ///< IO port 1 pin 1
|
||||||
|
IOPORT_PORT_01_PIN_02 = 0x0102, ///< IO port 1 pin 2
|
||||||
|
IOPORT_PORT_01_PIN_03 = 0x0103, ///< IO port 1 pin 3
|
||||||
|
IOPORT_PORT_01_PIN_04 = 0x0104, ///< IO port 1 pin 4
|
||||||
|
IOPORT_PORT_01_PIN_05 = 0x0105, ///< IO port 1 pin 5
|
||||||
|
IOPORT_PORT_01_PIN_06 = 0x0106, ///< IO port 1 pin 6
|
||||||
|
IOPORT_PORT_01_PIN_07 = 0x0107, ///< IO port 1 pin 7
|
||||||
|
IOPORT_PORT_01_PIN_08 = 0x0108, ///< IO port 1 pin 8
|
||||||
|
IOPORT_PORT_01_PIN_09 = 0x0109, ///< IO port 1 pin 9
|
||||||
|
IOPORT_PORT_01_PIN_10 = 0x010A, ///< IO port 1 pin 10
|
||||||
|
IOPORT_PORT_01_PIN_11 = 0x010B, ///< IO port 1 pin 11
|
||||||
|
IOPORT_PORT_01_PIN_12 = 0x010C, ///< IO port 1 pin 12
|
||||||
|
IOPORT_PORT_01_PIN_13 = 0x010D, ///< IO port 1 pin 13
|
||||||
|
IOPORT_PORT_01_PIN_14 = 0x010E, ///< IO port 1 pin 14
|
||||||
|
IOPORT_PORT_01_PIN_15 = 0x010F, ///< IO port 1 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_02_PIN_00 = 0x0200, ///< IO port 2 pin 0
|
||||||
|
IOPORT_PORT_02_PIN_01 = 0x0201, ///< IO port 2 pin 1
|
||||||
|
IOPORT_PORT_02_PIN_02 = 0x0202, ///< IO port 2 pin 2
|
||||||
|
IOPORT_PORT_02_PIN_03 = 0x0203, ///< IO port 2 pin 3
|
||||||
|
IOPORT_PORT_02_PIN_04 = 0x0204, ///< IO port 2 pin 4
|
||||||
|
IOPORT_PORT_02_PIN_05 = 0x0205, ///< IO port 2 pin 5
|
||||||
|
IOPORT_PORT_02_PIN_06 = 0x0206, ///< IO port 2 pin 6
|
||||||
|
IOPORT_PORT_02_PIN_07 = 0x0207, ///< IO port 2 pin 7
|
||||||
|
IOPORT_PORT_02_PIN_08 = 0x0208, ///< IO port 2 pin 8
|
||||||
|
IOPORT_PORT_02_PIN_09 = 0x0209, ///< IO port 2 pin 9
|
||||||
|
IOPORT_PORT_02_PIN_10 = 0x020A, ///< IO port 2 pin 10
|
||||||
|
IOPORT_PORT_02_PIN_11 = 0x020B, ///< IO port 2 pin 11
|
||||||
|
IOPORT_PORT_02_PIN_12 = 0x020C, ///< IO port 2 pin 12
|
||||||
|
IOPORT_PORT_02_PIN_13 = 0x020D, ///< IO port 2 pin 13
|
||||||
|
IOPORT_PORT_02_PIN_14 = 0x020E, ///< IO port 2 pin 14
|
||||||
|
IOPORT_PORT_02_PIN_15 = 0x020F, ///< IO port 2 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_03_PIN_00 = 0x0300, ///< IO port 3 pin 0
|
||||||
|
IOPORT_PORT_03_PIN_01 = 0x0301, ///< IO port 3 pin 1
|
||||||
|
IOPORT_PORT_03_PIN_02 = 0x0302, ///< IO port 3 pin 2
|
||||||
|
IOPORT_PORT_03_PIN_03 = 0x0303, ///< IO port 3 pin 3
|
||||||
|
IOPORT_PORT_03_PIN_04 = 0x0304, ///< IO port 3 pin 4
|
||||||
|
IOPORT_PORT_03_PIN_05 = 0x0305, ///< IO port 3 pin 5
|
||||||
|
IOPORT_PORT_03_PIN_06 = 0x0306, ///< IO port 3 pin 6
|
||||||
|
IOPORT_PORT_03_PIN_07 = 0x0307, ///< IO port 3 pin 7
|
||||||
|
IOPORT_PORT_03_PIN_08 = 0x0308, ///< IO port 3 pin 8
|
||||||
|
IOPORT_PORT_03_PIN_09 = 0x0309, ///< IO port 3 pin 9
|
||||||
|
IOPORT_PORT_03_PIN_10 = 0x030A, ///< IO port 3 pin 10
|
||||||
|
IOPORT_PORT_03_PIN_11 = 0x030B, ///< IO port 3 pin 11
|
||||||
|
IOPORT_PORT_03_PIN_12 = 0x030C, ///< IO port 3 pin 12
|
||||||
|
IOPORT_PORT_03_PIN_13 = 0x030D, ///< IO port 3 pin 13
|
||||||
|
IOPORT_PORT_03_PIN_14 = 0x030E, ///< IO port 3 pin 14
|
||||||
|
IOPORT_PORT_03_PIN_15 = 0x030F, ///< IO port 3 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_04_PIN_00 = 0x0400, ///< IO port 4 pin 0
|
||||||
|
IOPORT_PORT_04_PIN_01 = 0x0401, ///< IO port 4 pin 1
|
||||||
|
IOPORT_PORT_04_PIN_02 = 0x0402, ///< IO port 4 pin 2
|
||||||
|
IOPORT_PORT_04_PIN_03 = 0x0403, ///< IO port 4 pin 3
|
||||||
|
IOPORT_PORT_04_PIN_04 = 0x0404, ///< IO port 4 pin 4
|
||||||
|
IOPORT_PORT_04_PIN_05 = 0x0405, ///< IO port 4 pin 5
|
||||||
|
IOPORT_PORT_04_PIN_06 = 0x0406, ///< IO port 4 pin 6
|
||||||
|
IOPORT_PORT_04_PIN_07 = 0x0407, ///< IO port 4 pin 7
|
||||||
|
IOPORT_PORT_04_PIN_08 = 0x0408, ///< IO port 4 pin 8
|
||||||
|
IOPORT_PORT_04_PIN_09 = 0x0409, ///< IO port 4 pin 9
|
||||||
|
IOPORT_PORT_04_PIN_10 = 0x040A, ///< IO port 4 pin 10
|
||||||
|
IOPORT_PORT_04_PIN_11 = 0x040B, ///< IO port 4 pin 11
|
||||||
|
IOPORT_PORT_04_PIN_12 = 0x040C, ///< IO port 4 pin 12
|
||||||
|
IOPORT_PORT_04_PIN_13 = 0x040D, ///< IO port 4 pin 13
|
||||||
|
IOPORT_PORT_04_PIN_14 = 0x040E, ///< IO port 4 pin 14
|
||||||
|
IOPORT_PORT_04_PIN_15 = 0x040F, ///< IO port 4 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_05_PIN_00 = 0x0500, ///< IO port 5 pin 0
|
||||||
|
IOPORT_PORT_05_PIN_01 = 0x0501, ///< IO port 5 pin 1
|
||||||
|
IOPORT_PORT_05_PIN_02 = 0x0502, ///< IO port 5 pin 2
|
||||||
|
IOPORT_PORT_05_PIN_03 = 0x0503, ///< IO port 5 pin 3
|
||||||
|
IOPORT_PORT_05_PIN_04 = 0x0504, ///< IO port 5 pin 4
|
||||||
|
IOPORT_PORT_05_PIN_05 = 0x0505, ///< IO port 5 pin 5
|
||||||
|
IOPORT_PORT_05_PIN_06 = 0x0506, ///< IO port 5 pin 6
|
||||||
|
IOPORT_PORT_05_PIN_07 = 0x0507, ///< IO port 5 pin 7
|
||||||
|
IOPORT_PORT_05_PIN_08 = 0x0508, ///< IO port 5 pin 8
|
||||||
|
IOPORT_PORT_05_PIN_09 = 0x0509, ///< IO port 5 pin 9
|
||||||
|
IOPORT_PORT_05_PIN_10 = 0x050A, ///< IO port 5 pin 10
|
||||||
|
IOPORT_PORT_05_PIN_11 = 0x050B, ///< IO port 5 pin 11
|
||||||
|
IOPORT_PORT_05_PIN_12 = 0x050C, ///< IO port 5 pin 12
|
||||||
|
IOPORT_PORT_05_PIN_13 = 0x050D, ///< IO port 5 pin 13
|
||||||
|
IOPORT_PORT_05_PIN_14 = 0x050E, ///< IO port 5 pin 14
|
||||||
|
IOPORT_PORT_05_PIN_15 = 0x050F, ///< IO port 5 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_06_PIN_00 = 0x0600, ///< IO port 6 pin 0
|
||||||
|
IOPORT_PORT_06_PIN_01 = 0x0601, ///< IO port 6 pin 1
|
||||||
|
IOPORT_PORT_06_PIN_02 = 0x0602, ///< IO port 6 pin 2
|
||||||
|
IOPORT_PORT_06_PIN_03 = 0x0603, ///< IO port 6 pin 3
|
||||||
|
IOPORT_PORT_06_PIN_04 = 0x0604, ///< IO port 6 pin 4
|
||||||
|
IOPORT_PORT_06_PIN_05 = 0x0605, ///< IO port 6 pin 5
|
||||||
|
IOPORT_PORT_06_PIN_06 = 0x0606, ///< IO port 6 pin 6
|
||||||
|
IOPORT_PORT_06_PIN_07 = 0x0607, ///< IO port 6 pin 7
|
||||||
|
IOPORT_PORT_06_PIN_08 = 0x0608, ///< IO port 6 pin 8
|
||||||
|
IOPORT_PORT_06_PIN_09 = 0x0609, ///< IO port 6 pin 9
|
||||||
|
IOPORT_PORT_06_PIN_10 = 0x060A, ///< IO port 6 pin 10
|
||||||
|
IOPORT_PORT_06_PIN_11 = 0x060B, ///< IO port 6 pin 11
|
||||||
|
IOPORT_PORT_06_PIN_12 = 0x060C, ///< IO port 6 pin 12
|
||||||
|
IOPORT_PORT_06_PIN_13 = 0x060D, ///< IO port 6 pin 13
|
||||||
|
IOPORT_PORT_06_PIN_14 = 0x060E, ///< IO port 6 pin 14
|
||||||
|
IOPORT_PORT_06_PIN_15 = 0x060F, ///< IO port 6 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_07_PIN_00 = 0x0700, ///< IO port 7 pin 0
|
||||||
|
IOPORT_PORT_07_PIN_01 = 0x0701, ///< IO port 7 pin 1
|
||||||
|
IOPORT_PORT_07_PIN_02 = 0x0702, ///< IO port 7 pin 2
|
||||||
|
IOPORT_PORT_07_PIN_03 = 0x0703, ///< IO port 7 pin 3
|
||||||
|
IOPORT_PORT_07_PIN_04 = 0x0704, ///< IO port 7 pin 4
|
||||||
|
IOPORT_PORT_07_PIN_05 = 0x0705, ///< IO port 7 pin 5
|
||||||
|
IOPORT_PORT_07_PIN_06 = 0x0706, ///< IO port 7 pin 6
|
||||||
|
IOPORT_PORT_07_PIN_07 = 0x0707, ///< IO port 7 pin 7
|
||||||
|
IOPORT_PORT_07_PIN_08 = 0x0708, ///< IO port 7 pin 8
|
||||||
|
IOPORT_PORT_07_PIN_09 = 0x0709, ///< IO port 7 pin 9
|
||||||
|
IOPORT_PORT_07_PIN_10 = 0x070A, ///< IO port 7 pin 10
|
||||||
|
IOPORT_PORT_07_PIN_11 = 0x070B, ///< IO port 7 pin 11
|
||||||
|
IOPORT_PORT_07_PIN_12 = 0x070C, ///< IO port 7 pin 12
|
||||||
|
IOPORT_PORT_07_PIN_13 = 0x070D, ///< IO port 7 pin 13
|
||||||
|
IOPORT_PORT_07_PIN_14 = 0x070E, ///< IO port 7 pin 14
|
||||||
|
IOPORT_PORT_07_PIN_15 = 0x070F, ///< IO port 7 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_08_PIN_00 = 0x0800, ///< IO port 8 pin 0
|
||||||
|
IOPORT_PORT_08_PIN_01 = 0x0801, ///< IO port 8 pin 1
|
||||||
|
IOPORT_PORT_08_PIN_02 = 0x0802, ///< IO port 8 pin 2
|
||||||
|
IOPORT_PORT_08_PIN_03 = 0x0803, ///< IO port 8 pin 3
|
||||||
|
IOPORT_PORT_08_PIN_04 = 0x0804, ///< IO port 8 pin 4
|
||||||
|
IOPORT_PORT_08_PIN_05 = 0x0805, ///< IO port 8 pin 5
|
||||||
|
IOPORT_PORT_08_PIN_06 = 0x0806, ///< IO port 8 pin 6
|
||||||
|
IOPORT_PORT_08_PIN_07 = 0x0807, ///< IO port 8 pin 7
|
||||||
|
IOPORT_PORT_08_PIN_08 = 0x0808, ///< IO port 8 pin 8
|
||||||
|
IOPORT_PORT_08_PIN_09 = 0x0809, ///< IO port 8 pin 9
|
||||||
|
IOPORT_PORT_08_PIN_10 = 0x080A, ///< IO port 8 pin 10
|
||||||
|
IOPORT_PORT_08_PIN_11 = 0x080B, ///< IO port 8 pin 11
|
||||||
|
IOPORT_PORT_08_PIN_12 = 0x080C, ///< IO port 8 pin 12
|
||||||
|
IOPORT_PORT_08_PIN_13 = 0x080D, ///< IO port 8 pin 13
|
||||||
|
IOPORT_PORT_08_PIN_14 = 0x080E, ///< IO port 8 pin 14
|
||||||
|
IOPORT_PORT_08_PIN_15 = 0x080F, ///< IO port 8 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_09_PIN_00 = 0x0900, ///< IO port 9 pin 0
|
||||||
|
IOPORT_PORT_09_PIN_01 = 0x0901, ///< IO port 9 pin 1
|
||||||
|
IOPORT_PORT_09_PIN_02 = 0x0902, ///< IO port 9 pin 2
|
||||||
|
IOPORT_PORT_09_PIN_03 = 0x0903, ///< IO port 9 pin 3
|
||||||
|
IOPORT_PORT_09_PIN_04 = 0x0904, ///< IO port 9 pin 4
|
||||||
|
IOPORT_PORT_09_PIN_05 = 0x0905, ///< IO port 9 pin 5
|
||||||
|
IOPORT_PORT_09_PIN_06 = 0x0906, ///< IO port 9 pin 6
|
||||||
|
IOPORT_PORT_09_PIN_07 = 0x0907, ///< IO port 9 pin 7
|
||||||
|
IOPORT_PORT_09_PIN_08 = 0x0908, ///< IO port 9 pin 8
|
||||||
|
IOPORT_PORT_09_PIN_09 = 0x0909, ///< IO port 9 pin 9
|
||||||
|
IOPORT_PORT_09_PIN_10 = 0x090A, ///< IO port 9 pin 10
|
||||||
|
IOPORT_PORT_09_PIN_11 = 0x090B, ///< IO port 9 pin 11
|
||||||
|
IOPORT_PORT_09_PIN_12 = 0x090C, ///< IO port 9 pin 12
|
||||||
|
IOPORT_PORT_09_PIN_13 = 0x090D, ///< IO port 9 pin 13
|
||||||
|
IOPORT_PORT_09_PIN_14 = 0x090E, ///< IO port 9 pin 14
|
||||||
|
IOPORT_PORT_09_PIN_15 = 0x090F, ///< IO port 9 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_10_PIN_00 = 0x0A00, ///< IO port 10 pin 0
|
||||||
|
IOPORT_PORT_10_PIN_01 = 0x0A01, ///< IO port 10 pin 1
|
||||||
|
IOPORT_PORT_10_PIN_02 = 0x0A02, ///< IO port 10 pin 2
|
||||||
|
IOPORT_PORT_10_PIN_03 = 0x0A03, ///< IO port 10 pin 3
|
||||||
|
IOPORT_PORT_10_PIN_04 = 0x0A04, ///< IO port 10 pin 4
|
||||||
|
IOPORT_PORT_10_PIN_05 = 0x0A05, ///< IO port 10 pin 5
|
||||||
|
IOPORT_PORT_10_PIN_06 = 0x0A06, ///< IO port 10 pin 6
|
||||||
|
IOPORT_PORT_10_PIN_07 = 0x0A07, ///< IO port 10 pin 7
|
||||||
|
IOPORT_PORT_10_PIN_08 = 0x0A08, ///< IO port 10 pin 8
|
||||||
|
IOPORT_PORT_10_PIN_09 = 0x0A09, ///< IO port 10 pin 9
|
||||||
|
IOPORT_PORT_10_PIN_10 = 0x0A0A, ///< IO port 10 pin 10
|
||||||
|
IOPORT_PORT_10_PIN_11 = 0x0A0B, ///< IO port 10 pin 11
|
||||||
|
IOPORT_PORT_10_PIN_12 = 0x0A0C, ///< IO port 10 pin 12
|
||||||
|
IOPORT_PORT_10_PIN_13 = 0x0A0D, ///< IO port 10 pin 13
|
||||||
|
IOPORT_PORT_10_PIN_14 = 0x0A0E, ///< IO port 10 pin 14
|
||||||
|
IOPORT_PORT_10_PIN_15 = 0x0A0F, ///< IO port 10 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_11_PIN_00 = 0x0B00, ///< IO port 11 pin 0
|
||||||
|
IOPORT_PORT_11_PIN_01 = 0x0B01, ///< IO port 11 pin 1
|
||||||
|
IOPORT_PORT_11_PIN_02 = 0x0B02, ///< IO port 11 pin 2
|
||||||
|
IOPORT_PORT_11_PIN_03 = 0x0B03, ///< IO port 11 pin 3
|
||||||
|
IOPORT_PORT_11_PIN_04 = 0x0B04, ///< IO port 11 pin 4
|
||||||
|
IOPORT_PORT_11_PIN_05 = 0x0B05, ///< IO port 11 pin 5
|
||||||
|
IOPORT_PORT_11_PIN_06 = 0x0B06, ///< IO port 11 pin 6
|
||||||
|
IOPORT_PORT_11_PIN_07 = 0x0B07, ///< IO port 11 pin 7
|
||||||
|
IOPORT_PORT_11_PIN_08 = 0x0B08, ///< IO port 11 pin 8
|
||||||
|
IOPORT_PORT_11_PIN_09 = 0x0B09, ///< IO port 11 pin 9
|
||||||
|
IOPORT_PORT_11_PIN_10 = 0x0B0A, ///< IO port 11 pin 10
|
||||||
|
IOPORT_PORT_11_PIN_11 = 0x0B0B, ///< IO port 11 pin 11
|
||||||
|
IOPORT_PORT_11_PIN_12 = 0x0B0C, ///< IO port 11 pin 12
|
||||||
|
IOPORT_PORT_11_PIN_13 = 0x0B0D, ///< IO port 11 pin 13
|
||||||
|
IOPORT_PORT_11_PIN_14 = 0x0B0E, ///< IO port 11 pin 14
|
||||||
|
IOPORT_PORT_11_PIN_15 = 0x0B0F, ///< IO port 11 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_12_PIN_00 = 0x0C00, ///< IO port 12 pin 0
|
||||||
|
IOPORT_PORT_12_PIN_01 = 0x0C01, ///< IO port 12 pin 1
|
||||||
|
IOPORT_PORT_12_PIN_02 = 0x0C02, ///< IO port 12 pin 2
|
||||||
|
IOPORT_PORT_12_PIN_03 = 0x0C03, ///< IO port 12 pin 3
|
||||||
|
IOPORT_PORT_12_PIN_04 = 0x0C04, ///< IO port 12 pin 4
|
||||||
|
IOPORT_PORT_12_PIN_05 = 0x0C05, ///< IO port 12 pin 5
|
||||||
|
IOPORT_PORT_12_PIN_06 = 0x0C06, ///< IO port 12 pin 6
|
||||||
|
IOPORT_PORT_12_PIN_07 = 0x0C07, ///< IO port 12 pin 7
|
||||||
|
IOPORT_PORT_12_PIN_08 = 0x0C08, ///< IO port 12 pin 8
|
||||||
|
IOPORT_PORT_12_PIN_09 = 0x0C09, ///< IO port 12 pin 9
|
||||||
|
IOPORT_PORT_12_PIN_10 = 0x0C0A, ///< IO port 12 pin 10
|
||||||
|
IOPORT_PORT_12_PIN_11 = 0x0C0B, ///< IO port 12 pin 11
|
||||||
|
IOPORT_PORT_12_PIN_12 = 0x0C0C, ///< IO port 12 pin 12
|
||||||
|
IOPORT_PORT_12_PIN_13 = 0x0C0D, ///< IO port 12 pin 13
|
||||||
|
IOPORT_PORT_12_PIN_14 = 0x0C0E, ///< IO port 12 pin 14
|
||||||
|
IOPORT_PORT_12_PIN_15 = 0x0C0F, ///< IO port 12 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_13_PIN_00 = 0x0D00, ///< IO port 13 pin 0
|
||||||
|
IOPORT_PORT_13_PIN_01 = 0x0D01, ///< IO port 13 pin 1
|
||||||
|
IOPORT_PORT_13_PIN_02 = 0x0D02, ///< IO port 13 pin 2
|
||||||
|
IOPORT_PORT_13_PIN_03 = 0x0D03, ///< IO port 13 pin 3
|
||||||
|
IOPORT_PORT_13_PIN_04 = 0x0D04, ///< IO port 13 pin 4
|
||||||
|
IOPORT_PORT_13_PIN_05 = 0x0D05, ///< IO port 13 pin 5
|
||||||
|
IOPORT_PORT_13_PIN_06 = 0x0D06, ///< IO port 13 pin 6
|
||||||
|
IOPORT_PORT_13_PIN_07 = 0x0D07, ///< IO port 13 pin 7
|
||||||
|
IOPORT_PORT_13_PIN_08 = 0x0D08, ///< IO port 13 pin 8
|
||||||
|
IOPORT_PORT_13_PIN_09 = 0x0D09, ///< IO port 13 pin 9
|
||||||
|
IOPORT_PORT_13_PIN_10 = 0x0D0A, ///< IO port 13 pin 10
|
||||||
|
IOPORT_PORT_13_PIN_11 = 0x0D0B, ///< IO port 13 pin 11
|
||||||
|
IOPORT_PORT_13_PIN_12 = 0x0D0C, ///< IO port 13 pin 12
|
||||||
|
IOPORT_PORT_13_PIN_13 = 0x0D0D, ///< IO port 13 pin 13
|
||||||
|
IOPORT_PORT_13_PIN_14 = 0x0D0E, ///< IO port 13 pin 14
|
||||||
|
IOPORT_PORT_13_PIN_15 = 0x0D0F, ///< IO port 13 pin 15
|
||||||
|
|
||||||
|
IOPORT_PORT_14_PIN_00 = 0x0E00, ///< IO port 14 pin 0
|
||||||
|
IOPORT_PORT_14_PIN_01 = 0x0E01, ///< IO port 14 pin 1
|
||||||
|
IOPORT_PORT_14_PIN_02 = 0x0E02, ///< IO port 14 pin 2
|
||||||
|
IOPORT_PORT_14_PIN_03 = 0x0E03, ///< IO port 14 pin 3
|
||||||
|
IOPORT_PORT_14_PIN_04 = 0x0E04, ///< IO port 14 pin 4
|
||||||
|
IOPORT_PORT_14_PIN_05 = 0x0E05, ///< IO port 14 pin 5
|
||||||
|
IOPORT_PORT_14_PIN_06 = 0x0E06, ///< IO port 14 pin 6
|
||||||
|
IOPORT_PORT_14_PIN_07 = 0x0E07, ///< IO port 14 pin 7
|
||||||
|
IOPORT_PORT_14_PIN_08 = 0x0E08, ///< IO port 14 pin 8
|
||||||
|
IOPORT_PORT_14_PIN_09 = 0x0E09, ///< IO port 14 pin 9
|
||||||
|
IOPORT_PORT_14_PIN_10 = 0x0E0A, ///< IO port 14 pin 10
|
||||||
|
IOPORT_PORT_14_PIN_11 = 0x0E0B, ///< IO port 14 pin 11
|
||||||
|
IOPORT_PORT_14_PIN_12 = 0x0E0C, ///< IO port 14 pin 12
|
||||||
|
IOPORT_PORT_14_PIN_13 = 0x0E0D, ///< IO port 14 pin 13
|
||||||
|
IOPORT_PORT_14_PIN_14 = 0x0E0E, ///< IO port 14 pin 14
|
||||||
|
IOPORT_PORT_14_PIN_15 = 0x0E0F, ///< IO port 14 pin 15
|
||||||
|
} ioport_port_pin_t;
|
||||||
|
|
||||||
|
/**********************************************************************************************************************
|
||||||
|
* Exported global variables
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/** @cond INC_HEADER_DEFS_SEC */
|
||||||
|
/** Filled in Interface API structure for this Instance. */
|
||||||
|
extern const ioport_api_t g_ioport_on_ioport;
|
||||||
|
|
||||||
|
/** @endcond */
|
||||||
|
|
||||||
|
/***********************************************************************************************************************
|
||||||
|
* Public APIs
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||||
|
fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl);
|
||||||
|
fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg);
|
||||||
|
fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg);
|
||||||
|
fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event);
|
||||||
|
fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value);
|
||||||
|
fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value);
|
||||||
|
fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level);
|
||||||
|
fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl,
|
||||||
|
bsp_io_port_t port,
|
||||||
|
ioport_size_t direction_values,
|
||||||
|
ioport_size_t mask);
|
||||||
|
fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * event_data);
|
||||||
|
fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl,
|
||||||
|
bsp_io_port_t port,
|
||||||
|
ioport_size_t event_data,
|
||||||
|
ioport_size_t mask_value);
|
||||||
|
fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value);
|
||||||
|
fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask);
|
||||||
|
fsp_err_t R_IOPORT_EthernetModeCfg(ioport_ctrl_t * const p_ctrl,
|
||||||
|
ioport_ethernet_channel_t channel,
|
||||||
|
ioport_ethernet_mode_t mode);
|
||||||
|
|
||||||
|
/*******************************************************************************************************************//**
|
||||||
|
* @} (end defgroup IOPORT)
|
||||||
|
**********************************************************************************************************************/
|
||||||
|
|
||||||
|
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
|
||||||
|
FSP_FOOTER
|
||||||
|
|
||||||
|
#endif // R_IOPORT_H
|