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Merge pull request #3 from RT-Thread/master 

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HubretXie 2019-01-12 15:00:18 +08:00 committed by GitHub
parent 0e333a3a10 83b67ec3e2
commit 2f8f8f85e2
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308 changed files with 31602 additions and 2390 deletions
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45
.github/PULL_REQUEST_TEMPLATE.md vendored
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@ -1,35 +1,28 @@
### Summary of this Pull Request (PR) 拉取/合并请求的简述
## 拉取/合并请求描述：(PR description)
**Add description here.** **请在这里加入描述**
请仔细阅读以下文字。请在这里填写您的PR描述，可以包括以下之一的内容：为什么提交这份PR；解决的问题是什么，你的解决方案是什么；
Please read the following carefully. Please fill in your PR description here, which can include one of the following items: why to submit this PR; what is the problem solved and what is your solution;
### Intent for your PR 拉取/合并请求的目的
并确认已经在什么情况或板卡上进行了测试。
And confirm in which case or board have been tested.
Choose one (Mandatory): 必须选择一项
以下的内容请在提交PR后，一项项进行check，没问题后逐条在页面上打钩。
The following contents should be checked item by item after submitted PR, and ticked on the browser one by one after no problem.
- [ ] This PR is for a code-review and is intended to get feedback 本拉取/合并请求是一个草稿版本
- [ ] This PR is mature, and ready to be integrated into the repo 本拉取/合并请求是一个成熟版本
### 当前拉取/合并请求的状态 Intent for your PR
### Reviewers (Mandatory): 代码审阅者（必须指定）
必须选择一项 Choose one (Mandatory):
(@<github.com username(s)> Ex: @user1, @user2)
- [ ] 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
- [ ] 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo
### Code Quality： 代码质量
### 代码质量 Code Quality：
As part of this pull request, I've considered the following:
我在这个拉取/合并请求中已经考虑了：
我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
- [ ] Already check the difference between PR and old code 已经仔细查看过代码改动的对比
- [ ] Style guide is adhered to, including spacing, naming and other style 代码风格正确，包括缩进空格，命名及其他风格
- [ ] All redundant code is removed and cleaned up 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码
- [ ] All modifications are justified and not affect other components or BSP 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP
- [ ] I've commented appropriately where code is tricky 对难懂代码均提供对应的注释
- [ ] Code in this PR is of high quality 本拉取/合并请求代码是高质量的
### Testing：代码测试
I've tested the code using the following test programs (provide list here):
我已经在如下场合跑过对应的测试：
- [ ] application 1
- [ ] application 2
- [ ] ...(add others here)
- [ ] 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
- [ ] 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other style
- [ ] 没有垃圾代码，代码尽量精简，不包含`#if 0`代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
- [ ] 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
- [ ] 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
- [ ] 本拉取/合并请求代码是高质量的 Code in this PR is of high quality

1
.travis.yml
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@ -86,6 +86,7 @@ env:
- RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-armfly-v6' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'

2
bsp/nuvoton_m487/driver/drv_uart.c
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@ -402,4 +402,4 @@ int rt_hw_uart_init(void)
#endif
return 0;
}
}

15
bsp/nuvoton_m487/nuc487_flash.sct Normal file
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@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00080000 { ; load region size_region
ER_IROM1 0x00000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00028000 { ; RW data
.ANY (+RW +ZI)
}
}

2
bsp/nuvoton_m487/rtconfig.py
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@ -3,7 +3,7 @@ import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='gcc'
CROSS_TOOL='keil'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')

1
bsp/qemu-vexpress-a9/SConstruct
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@ -19,6 +19,7 @@ env = Environment(tools = ['mingw'],
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

9
bsp/qemu-vexpress-gemini/SConstruct
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@ -13,11 +13,12 @@ from building import *
TARGET = 'rtthread-vexpress.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

9
bsp/realview-a8/SConstruct
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@ -13,11 +13,12 @@ from building import *
TARGET = 'rtthread-realview.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')

1
bsp/stm32/README.md
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@ -11,6 +11,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
| [stm32f103-fire-arbitrary](stm32f103-fire-arbitrary/) | 野火 F103 霸道开发板 |
| **F4 系列** | |
| [stm32f407-st-discovery](stm32f407-st-discovery/) | ST 官方 stm32f407-discovery 开发板 |
| [stm32f411-st-nucleo](stm32f411-st-nucleo/) | ST 官方 STM32F411-Nucleo-64 开发板 |
| [stm32f407-atk-explorer](stm32f407-atk-explorer/) | 正点原子 F407 探索者开发板 |
| [stm32f429-atk-apollo](stm32f429-atk-apollo/) | 正点原子 F429 阿波罗开发板 |
| [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 |

8
bsp/stm32/libraries/HAL_Drivers/config/f0/adc_config.h
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@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
@ -35,4 +39,8 @@
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

45
bsp/stm32/libraries/HAL_Drivers/config/f0/dma_config.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-01-05 zylx first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
/* DMA1 channel2-3 DMA2 channel1-2 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel3
#define UART1_RX_DMA_IRQ DMA1_Ch2_3_DMA2_Ch1_2_IRQn
#endif
/* DMA1 channel2-3 DMA2 channel1-2 */
/* DMA1 channel4-7 DMA2 channel3-5 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel5
#define UART2_RX_DMA_IRQ DMA1_Ch4_7_DMA2_Ch3_5_IRQn
#endif
/* DMA1 channel4-7 DMA2 channel3-5 */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f0/pwm_config.h
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@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -57,4 +61,8 @@
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f0/spi_config.h
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@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
@ -30,6 +34,10 @@
#define SPI1_DMA_TX_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#endif
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f0/tim_config.h
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@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
@ -56,4 +60,8 @@
#endif /* TIM17_CONFIG */
#endif /* BSP_USING_TIM17 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

60
bsp/stm32/libraries/HAL_Drivers/config/f0/uart_config.h
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@ -13,36 +13,56 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#define USART1_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Ch2_3_DMA2_Ch1_2_IRQn, \
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#define USART2_RX_DMA_ISR DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f1/adc_config.h
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@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
@ -61,4 +65,8 @@
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

99
bsp/stm32/libraries/HAL_Drivers/config/f1/dma_config.h Normal file
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@ -0,0 +1,99 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-01-02 SummerGift first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
/* DMA1 channel2 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
#endif
/* DMA1 channel3 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Channel3
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#endif
/* DMA1 channel4 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
#endif
/* DMA1 channel5 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel5
#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
#endif
/* DMA1 channel6 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Channel6
#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
#endif
/* DMA1 channel7 */
/* DMA2 channel1 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN
#define SPI3_RX_DMA_INSTANCE DMA2_Channel1
#define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn
#endif
/* DMA2 channel2 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN
#define SPI3_TX_DMA_INSTANCE DMA2_Channel2
#define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn
#endif
/* DMA2 channel3 */
/* DMA2 channel4 */
/* DMA2 channel5 */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -57,4 +61,8 @@
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h
View File

@ -14,6 +14,10 @@
#include <rtthread.h>
#include "stm32f1xx_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SDIO
#define SDIO_BUS_CONFIG \
{ \
@ -28,6 +32,10 @@
#endif
#ifdef __cplusplus
}
#endif
#endif /*__SDIO_CONFIG_H__ */

137
bsp/stm32/libraries/HAL_Drivers/config/f1/spi_config.h
View File

@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
* 2019-01-05 SummerGift modify DMA support
*/
#ifndef __SPI_CONFIG_H__
@ -13,56 +14,110 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel2, \
.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
.dma_tx.Instance = DMA1_Channel3, \
.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
}
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel4, \
.dma_rx.dma_irq = DMA1_Channel4_IRQn, \
.dma_tx.Instance = DMA1_Channel5, \
.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#endif
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_rx.Instance = DMA2_Channel1, \
.dma_rx.dma_irq = DMA2_Channel1_IRQn, \
.dma_tx.Instance = DMA2_Channel2, \
.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
@ -67,4 +71,8 @@
#endif /* TIM5_CONFIG */
#endif /* BSP_USING_TIM5 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

153
bsp/stm32/libraries/HAL_Drivers/config/f1/uart_config.h
View File

@ -5,81 +5,130 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 BalanceTWK change to new framework
* 2018-10-30 BalanceTWK first version
* 2019-01-05 SummerGift modify DMA support
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "dma_config.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.channel.Instance = DMA1_Channel5, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel5_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#define USART1_RX_DMA_ISR DMA1_Channel5_IRQHandler
#endif
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.channel.Instance = DMA1_Channel6, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel6_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
#endif
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.channel.Instance = DMA1_Channel3, \
.dma_rcc = RCC_AHBENR_DMA1EN, \
.dma_irq = DMA1_Channel3_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Channel3_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.channel.Instance = DMA2_Channel3, \
.dma_rcc = RCC_AHBENR_DMA2EN, \
.dma_irq = DMA2_Channel3_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA2_Channel3_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.dma_rcc = UART4_RX_DMA_RCC, \
.dma_irq = UART4_RX_DMA_IRQ, \
}
#endif /* UART4_DMA_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.channel.Instance = DMA_NOT_AVAILABLE, \
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = DMA_NOT_AVAILABLE, \
}
#endif /* UART5_DMA_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif

8
bsp/stm32/libraries/HAL_Drivers/config/f4/adc_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
@ -76,4 +80,8 @@
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

217
bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h Normal file
View File

@ -0,0 +1,217 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-01-02 zylx first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 stream0 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART5_RX_DMA_INSTANCE DMA1_Stream0
#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
#endif
/* DMA1 stream1 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Stream1
#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
#endif
/* DMA1 stream2 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART4_RX_DMA_INSTANCE DMA1_Stream2
#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
#endif
/* DMA1 stream3 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
#endif
/* DMA1 stream4 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
#endif
/* DMA1 stream5 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream5
#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
#endif
/* DMA1 stream6 */
/* DMA1 stream7 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
#endif
/* DMA2 stream0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream0
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
#endif
/* DMA2 stream2 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define USART1_RX_DMA_INSTANCE DMA2_Stream2
#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn
#endif
/* DMA2 stream3 */
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream3
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif
/* DMA2 stream5 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define USART1_RX_DMA_INSTANCE DMA2_Stream5
#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
#endif
/* DMA2 stream6 */
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
#endif
/* DMA2 stream7 */
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -57,4 +61,8 @@
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h
View File

@ -14,6 +14,10 @@
#include <rtthread.h>
#include "stm32f4xx_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SDIO
#define SDIO_BUS_CONFIG \
{ \
@ -30,6 +34,10 @@
#endif
#ifdef __cplusplus
}
#endif
#endif /*__SDIO_CONFIG_H__ */

241
bsp/stm32/libraries/HAL_Drivers/config/f4/spi_config.h
View File

@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
* 2019-01-03 zylx modify DMA support
*/
#ifndef __SPI_CONFIG_H__
@ -13,102 +14,182 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream2, \
.dma_rx.channel = DMA_CHANNEL_3, \
.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
.dma_tx.Instance = DMA2_Stream3, \
.dma_tx.channel = DMA_CHANNEL_3, \
.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
}
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream3, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
.dma_tx.Instance = DMA1_Stream4, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#endif
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream0, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
.dma_tx.Instance = DMA1_Stream5, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream5_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
#endif
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream0, \
.dma_rx.channel = DMA_CHANNEL_4, \
.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
.dma_tx.Instance = DMA2_Stream1, \
.dma_tx.channel = DMA_CHANNEL_4, \
.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.dma_irq = SPI4_TX_DMA_IRQ, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#endif
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.dma_irq = SPI4_RX_DMA_IRQ, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream3, \
.dma_rx.channel = DMA_CHANNEL_2, \
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
.dma_tx.Instance = DMA2_Stream4, \
.dma_tx.channel = DMA_CHANNEL_2, \
.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.dma_irq = SPI5_TX_DMA_IRQ, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.dma_irq = SPI5_RX_DMA_IRQ, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
@ -56,4 +60,8 @@
#endif /* TIM14_CONFIG */
#endif /* BSP_USING_TIM14 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

163
bsp/stm32/libraries/HAL_Drivers/config/f4/uart_config.h
View File

@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift change to new framework
* 2018-10-30 SummerGift first version
* 2019-01-03 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
@ -13,79 +14,127 @@
#include <rtthread.h>
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.stream_channel.Instance = DMA2_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Stream5_IRQn, \
}
#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.channel = USART1_RX_DMA_CHANNEL, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream5_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
#endif
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.channel = USART2_RX_DMA_CHANNEL, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream1, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream1_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = USART3_RX_DMA_INSTANCE, \
.channel = USART3_RX_DMA_CHANNEL, \
.dma_rcc = USART3_RX_DMA_RCC, \
.dma_irq = USART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream2, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream2_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = USART4_RX_DMA_INSTANCE, \
.channel = USART4_RX_DMA_CHANNEL, \
.dma_rcc = USART4_RX_DMA_RCC, \
.dma_irq = USART4_RX_DMA_IRQ, \
}
#endif /* UART4_DMA_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream0, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream0_IRQn, \
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = USART5_RX_DMA_INSTANCE, \
.channel = USART5_RX_DMA_CHANNEL, \
.dma_rcc = USART5_RX_DMA_RCC, \
.dma_irq = USART5_RX_DMA_IRQ, \
}
#endif /* UART5_DMA_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif

8
bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
@ -76,4 +80,8 @@
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

229
bsp/stm32/libraries/HAL_Drivers/config/f7/dma_config.h Normal file
View File

@ -0,0 +1,229 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-01-02 zylx first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 stream0 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART5_RX_DMA_INSTANCE DMA1_Stream0
#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
#endif
/* DMA1 stream1 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Stream1
#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
#endif
/* DMA1 stream2 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART4_RX_DMA_INSTANCE DMA1_Stream2
#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
#endif
/* DMA1 stream3 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
#define SPI2_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
#endif
/* DMA1 stream4 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
#define SPI2_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
#endif
/* DMA1 stream5 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream5
#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
#endif
/* DMA1 stream6 */
/* DMA1 stream7 */
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
#endif
/* DMA2 stream0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
#endif
/* DMA2 stream2 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define USART1_RX_DMA_INSTANCE DMA2_Stream2
#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Stream2
#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
#endif
/* DMA2 stream3 */
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif
/* DMA2 stream5 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define USART1_RX_DMA_INSTANCE DMA2_Stream5
#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
#endif
/* DMA2 stream6 */
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
#endif
/* DMA2 stream7 */
#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Stream7
#define QSPI_DMA_CHANNEL DMA_CHANNEL_3
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f7/pwm_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -57,4 +61,8 @@
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

17
bsp/stm32/libraries/HAL_Drivers/config/f7/qspi_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \
@ -24,13 +28,13 @@
}
#endif /* QSPI_BUS_CONFIG */
#endif /* BSP_USING_QSPI */
#ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance = DMA2_Stream7, \
.Init.Channel = DMA_CHANNEL_3, \
.Instance = QSPI_DMA_INSTANCE, \
.Init.Channel = QSPI_DMA_CHANNEL, \
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
.Init.PeriphInc = DMA_PINC_DISABLE, \
.Init.MemInc = DMA_MINC_ENABLE, \
@ -42,10 +46,11 @@
#endif /* QSPI_DMA_CONFIG */
#endif /* BSP_QSPI_USING_DMA */
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE()
#define QSPI_IRQn QUADSPI_IRQn
#define QSPI_DMA_IRQn DMA2_Stream7_IRQn
#define QSPI_IRQHandler QUADSPI_IRQHandler
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
#ifdef __cplusplus
}
#endif
#endif /* __QSPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f7/sdio_config.h
View File

@ -14,6 +14,10 @@
#include <rtthread.h>
#include "stm32f7xx_hal.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SDIO
#define SDIO_BUS_CONFIG \
{ \
@ -30,6 +34,10 @@
#endif
#ifdef __cplusplus
}
#endif
#endif /*__SDIO_CONFIG_H__ */

255
bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h
View File

@ -13,121 +13,182 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream2, \
.dma_rx.channel = DMA_CHANNEL_3, \
.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
.dma_tx.Instance = DMA2_Stream3, \
.dma_tx.channel = DMA_CHANNEL_3, \
.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
}
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream3, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
.dma_tx.Instance = DMA1_Stream4, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.Instance = SPI2, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_TX_DMA_RCC, \
.Instance = SPI2_TX_DMA_INSTANCE, \
.channel = SPI2_TX_DMA_CHANNEL, \
.dma_irq = SPI2_TX_DMA_IRQ, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
#endif
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI2_RX_DMA_RCC, \
.Instance = SPI2_RX_DMA_INSTANCE, \
.channel = SPI2_RX_DMA_CHANNEL, \
.dma_irq = SPI2_RX_DMA_IRQ, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Stream0, \
.dma_rx.channel = DMA_CHANNEL_0, \
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
.dma_tx.Instance = DMA1_Stream7, \
.dma_tx.channel = DMA_CHANNEL_0, \
.dma_tx.dma_irq = DMA1_Stream7_IRQn, \
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.Instance = SPI3, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_TX_DMA_RCC, \
.Instance = SPI3_TX_DMA_INSTANCE, \
.channel = SPI3_TX_DMA_CHANNEL, \
.dma_irq = SPI3_TX_DMA_IRQ, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
#endif
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI3_RX_DMA_RCC, \
.Instance = SPI3_RX_DMA_INSTANCE, \
.channel = SPI3_RX_DMA_CHANNEL, \
.dma_irq = SPI3_RX_DMA_IRQ, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream0, \
.dma_rx.channel = DMA_CHANNEL_4, \
.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
.dma_tx.Instance = DMA2_Stream1, \
.dma_tx.channel = DMA_CHANNEL_4, \
.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.Instance = SPI4, \
.bus_name = "spi4", \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_TX_DMA_RCC, \
.Instance = SPI4_TX_DMA_INSTANCE, \
.channel = SPI4_TX_DMA_CHANNEL, \
.dma_irq = SPI4_TX_DMA_IRQ, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
#endif
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI4_RX_DMA_RCC, \
.Instance = SPI4_RX_DMA_INSTANCE, \
.channel = SPI4_RX_DMA_CHANNEL, \
.dma_irq = SPI4_RX_DMA_IRQ, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream3, \
.dma_rx.channel = DMA_CHANNEL_2, \
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
.dma_tx.Instance = DMA2_Stream4, \
.dma_tx.channel = DMA_CHANNEL_2, \
.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI5, \
.bus_name = "spi5", \
}
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#endif
#ifdef BSP_USING_SPI6
#define SPI5_BUS_CONFIG \
{ \
.Instance = SPI6, \
.bus_name = "spi6", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_rx.Instance = DMA2_Stream6, \
.dma_rx.channel = DMA_CHANNEL_1, \
.dma_rx.dma_irq = DMA2_Stream6_IRQn, \
.dma_tx.Instance = DMA2_Stream5, \
.dma_tx.channel = DMA_CHANNEL_1, \
.dma_tx.dma_irq = DMA2_Stream5_IRQn, \
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_TX_DMA_RCC, \
.Instance = SPI5_TX_DMA_INSTANCE, \
.channel = SPI5_TX_DMA_CHANNEL, \
.dma_irq = SPI5_TX_DMA_IRQ, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler
#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI5_RX_DMA_RCC, \
.Instance = SPI5_RX_DMA_INSTANCE, \
.channel = SPI5_RX_DMA_CHANNEL, \
.dma_irq = SPI5_RX_DMA_IRQ, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/f7/tim_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
@ -56,4 +60,8 @@
#endif /* TIM14_CONFIG */
#endif /* BSP_USING_TIM14 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

163
bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h
View File

@ -5,7 +5,8 @@
*
* Change Logs:
* Date Author Notes
* 2018-10-30 SummerGift change to new framework
* 2018-10-30 SummerGift first version
* 2019-01-05 zylx modify dma support
*/
#ifndef __UART_CONFIG_H__
@ -13,79 +14,127 @@
#include <rtthread.h>
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.stream_channel.Instance = DMA2_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Stream5_IRQn, \
}
#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = USART1_RX_DMA_INSTANCE, \
.channel = USART1_RX_DMA_CHANNEL, \
.dma_rcc = USART1_RX_DMA_RCC, \
.dma_irq = USART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream5, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream5_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
#endif
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = USART2_RX_DMA_INSTANCE, \
.channel = USART2_RX_DMA_CHANNEL, \
.dma_rcc = USART2_RX_DMA_RCC, \
.dma_irq = USART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_USING_UART3)
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream1, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream1_IRQn, \
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
#endif
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_CONFIG
#define UART3_DMA_CONFIG \
{ \
.Instance = USART3_RX_DMA_INSTANCE, \
.channel = USART3_RX_DMA_CHANNEL, \
.dma_rcc = USART3_RX_DMA_RCC, \
.dma_irq = USART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_USING_UART4)
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream2, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream2_IRQn, \
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = UART4, \
.irq_type = UART4_IRQn, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
#endif
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_CONFIG
#define UART4_DMA_CONFIG \
{ \
.Instance = USART4_RX_DMA_INSTANCE, \
.channel = USART4_RX_DMA_CHANNEL, \
.dma_rcc = USART4_RX_DMA_RCC, \
.dma_irq = USART4_RX_DMA_IRQ, \
}
#endif /* UART4_DMA_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_USING_UART5)
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.dma.stream_channel.Instance = DMA1_Stream0, \
.dma.stream_channel.channel = DMA_CHANNEL_4, \
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_irq = DMA1_Stream0_IRQn, \
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_CONFIG
#define UART5_DMA_CONFIG \
{ \
.Instance = USART5_RX_DMA_INSTANCE, \
.channel = USART5_RX_DMA_CHANNEL, \
.dma_rcc = USART5_RX_DMA_RCC, \
.dma_irq = USART5_RX_DMA_IRQ, \
}
#endif /* UART5_DMA_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif

8
bsp/stm32/libraries/HAL_Drivers/config/l4/adc_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
@ -79,4 +83,8 @@
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
#ifdef __cplusplus
}
#endif
#endif /* __ADC_CONFIG_H__ */

135
bsp/stm32/libraries/HAL_Drivers/config/l4/dma_config.h Normal file
View File

@ -0,0 +1,135 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-01-05 zylx first version
* 2019-01-08 SummerGift clean up the code
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
/* DMA1 channel2 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_1
#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
#endif
/* DMA1 channel3 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_1
#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
#endif
/* DMA1 channel4 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART1_TX_DMA_INSTANCE DMA1_Channel4
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
#endif
/* DMA1 channel5 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART1_RX_DMA_INSTANCE DMA1_Channel5
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN
#define QSPI_DMA_INSTANCE DMA1_Channel5
#define QSPI_DMA_REQUEST DMA_REQUEST_5
#define QSPI_DMA_IRQ DMA1_Channel5_IRQn
#endif
/* DMA1 channel6 */
/* DMA1 channel7 */
/* DMA2 channel1 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler
#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART5_TX_DMA_INSTANCE DMA2_Channel1
#define UART5_TX_DMA_REQUEST DMA_REQUEST_2
#define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn
#endif
/* DMA2 channel2 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART5_RX_DMA_INSTANCE DMA2_Channel2
#define UART5_RX_DMA_REQUEST DMA_REQUEST_2
#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn
#endif
/* DMA2 channel3 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_RX_DMA_INSTANCE DMA2_Channel3
#define SPI1_RX_DMA_REQUEST DMA_REQUEST_4
#define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn
#endif
/* DMA2 channel4 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Channel4
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_4
#define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn
#endif
/* DMA2 channel5 */
/* DMA2 channel6 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_TX_DMA_INSTANCE DMA2_Channel6
#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
#define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn
#endif
/* DMA2 channel7 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Channel7
#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
#define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Channel7
#define QSPI_DMA_REQUEST DMA_REQUEST_3
#define QSPI_DMA_IRQ DMA2_Channel7_IRQn
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
@ -57,4 +61,8 @@
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */

15
bsp/stm32/libraries/HAL_Drivers/config/l4/qspi_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \
@ -29,8 +33,8 @@
#ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \
{ \
.Instance = DMA1_Channel5, \
.Init.Request = DMA_REQUEST_5, \
.Instance = QSPI_DMA_INSTANCE, \
.Init.Request = QSPI_DMA_REQUEST, \
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
.Init.PeriphInc = DMA_PINC_DISABLE, \
.Init.MemInc = DMA_MINC_ENABLE, \
@ -42,10 +46,11 @@
#endif /* QSPI_DMA_CONFIG */
#endif /* BSP_QSPI_USING_DMA */
#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE()
#define QSPI_IRQn QUADSPI_IRQn
#define QSPI_DMA_IRQn DMA1_Channel5_IRQn
#define QSPI_IRQHandler QUADSPI_IRQHandler
#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
#ifdef __cplusplus
}
#endif
#endif /* __QSPI_CONFIG_H__ */

64
bsp/stm32/libraries/HAL_Drivers/config/l4/spi_config.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
*/
#ifndef __SPI_CONFIG_H__
@ -13,24 +13,44 @@
#include <rtthread.h>
#ifdef BSP_USING_SPI1
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
.dma_rx.Instance = DMA1_Channel2, \
.dma_rx.request = DMA_REQUEST_1, \
.dma_rx.dma_irq = DMA1_Channel2_IRQn, \
.dma_tx.Instance = DMA1_Channel3, \
.dma_tx.request = DMA_REQUEST_1, \
.dma_tx.dma_irq = DMA1_Channel3_IRQn, \
}
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.Instance = SPI1, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_TX_DMA_RCC, \
.Instance = SPI1_TX_DMA_INSTANCE, \
.request = SPI1_TX_DMA_REQUEST, \
.dma_irq = SPI1_TX_DMA_IRQ, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.dma_rcc = SPI1_RX_DMA_RCC, \
.Instance = SPI1_RX_DMA_INSTANCE, \
.request = SPI1_RX_DMA_REQUEST, \
.dma_irq = SPI1_RX_DMA_IRQ, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#define SPI2_BUS_CONFIG \
{ \
@ -45,8 +65,7 @@
.dma_tx.request = DMA_REQUEST_1, \
.dma_tx.dma_irq = DMA1_Channel5_IRQn, \
}
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
#endif
#ifdef BSP_USING_SPI3
@ -63,8 +82,11 @@
.dma_tx.request = DMA_REQUEST_3, \
.dma_tx.dma_irq = DMA2_Channel2_IRQn, \
}
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
#endif
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */

8
bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h
View File

@ -13,6 +13,10 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
@ -56,4 +60,8 @@
#endif /* TIM17_CONFIG */
#endif /* BSP_USING_TIM17 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */

74
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift change to new framework
* 2018-11-06 SummerGift first version
*/
#ifndef __UART_CONFIG_H__
@ -13,36 +13,58 @@
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.dma.channel_request.Instance = DMA2_Channel7, \
.dma.channel_request.request = DMA_REQUEST_2, \
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
.dma_irq = DMA2_Channel7_IRQn, \
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#define USART1_RX_DMA_ISR DMA2_Channel7_IRQHandler
#endif
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_CONFIG
#define UART1_DMA_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.request = UART1_RX_DMA_REQUEST, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_USING_UART2)
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.dma.channel_request.Instance = DMA1_Channel6, \
.dma.channel_request.request = DMA_REQUEST_2, \
.dma_rcc = RCC_AHB1SMENR_DMA1SMEN, \
.dma_irq = DMA1_Channel6_IRQn, \
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#define USART2_RX_DMA_ISR DMA1_Channel6_IRQHandler
#endif
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_CONFIG
#define UART2_DMA_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.request = UART2_RX_DMA_REQUEST, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif

10
bsp/stm32/libraries/HAL_Drivers/drv_common.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-7 SummerGift change to new framework
* 2018-11-7 SummerGift first version
*/
#ifndef __DRV_COMMON_H__
@ -16,6 +16,10 @@
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *s, int num);
#ifndef Error_Handler
@ -24,4 +28,8 @@ void _Error_Handler(char *s, int num);
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
#ifdef __cplusplus
}
#endif
#endif

13
bsp/stm32/libraries/HAL_Drivers/drv_config.h
View File

@ -14,13 +14,19 @@
#include <board.h>
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SOC_SERIES_STM32F0)
#include "f0/dma_config.h"
#include "f0/uart_config.h"
#include "f0/spi_config.h"
#include "f0/tim_config.h"
#include "f0/pwm_config.h"
#include "f0/adc_config.h"
#elif defined(SOC_SERIES_STM32F1)
#include "f1/dma_config.h"
#include "f1/uart_config.h"
#include "f1/spi_config.h"
#include "f1/adc_config.h"
@ -28,6 +34,7 @@
#include "f1/sdio_config.h"
#include "f1/pwm_config.h"
#elif defined(SOC_SERIES_STM32F4)
#include "f4/dma_config.h"
#include "f4/uart_config.h"
#include "f4/spi_config.h"
#include "f4/adc_config.h"
@ -35,6 +42,7 @@
#include "f4/sdio_config.h"
#include "f4/pwm_config.h"
#elif defined(SOC_SERIES_STM32F7)
#include "f7/dma_config.h"
#include "f7/uart_config.h"
#include "f7/spi_config.h"
#include "f7/qspi_config.h"
@ -43,6 +51,7 @@
#include "f7/sdio_config.h"
#include "f7/pwm_config.h"
#elif defined(SOC_SERIES_STM32L4)
#include "l4/dma_config.h"
#include "l4/uart_config.h"
#include "l4/spi_config.h"
#include "l4/qspi_config.h"
@ -51,4 +60,8 @@
#include "l4/pwm_config.h"
#endif
#ifdef __cplusplus
}
#endif
#endif

11
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-10 SummerGift change to new framework
* 2018-11-10 SummerGift first version
*/
#ifndef __DRV_DMA_H_
@ -16,7 +16,11 @@
#include <rthw.h>
#include <drv_common.h>
#if defined(SOC_SERIES_STM32F0) || (SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
@ -36,5 +40,8 @@ struct dma_config {
#endif
};
#ifdef __cplusplus
}
#endif
#endif /*__DRV_DMA_H_ */

56
bsp/stm32/libraries/HAL_Drivers/drv_eth.c
View File

@ -260,6 +260,9 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
/* TODO Optimize data send speed*/
LOG_D("transmit frame lenth :%d", framelength);
/* wait for unlocked */
while (EthHandle.Lock == HAL_LOCKED);
state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
if (state != HAL_OK)
{
@ -410,6 +413,40 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
LOG_E("eth err");
}
#ifdef PHY_USING_INTERRUPT_MODE
static void eth_phy_isr(void *args)
{
rt_uint32_t status = 0;
static rt_uint8_t link_status = 1;
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
LOG_D("phy interrupt status reg is 0x%X", status);
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
LOG_D("phy basic status reg is 0x%X", status);
if (status & PHY_LINKED_STATUS_MASK)
{
if (link_status == 0)
{
link_status = 1;
LOG_D("link up");
/* send link up. */
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
}
}
else
{
if (link_status == 1)
{
link_status = 0;
LOG_I("link down");
/* send link down. */
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
}
}
}
#endif /* PHY_USING_INTERRUPT_MODE */
static uint8_t phy_speed = 0;
#define PHY_LINK_MASK (1<<0)
static void phy_monitor_thread_entry(void *parameter)
@ -435,12 +472,12 @@ static void phy_monitor_thread_entry(void *parameter)
if (phy_addr == 0xFF)
{
LOG_E("phy not probe!\r\n");
LOG_E("phy not probe!");
return;
}
else
{
LOG_D("found a phy, address:0x%02X\r\n", phy_addr);
LOG_D("found a phy, address:0x%02X", phy_addr);
}
/* RESET PHY */
@ -452,7 +489,7 @@ static void phy_monitor_thread_entry(void *parameter)
while (1)
{
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
LOG_D("PHY BASIC STATUS REG:0x%04X\r\n", status);
LOG_D("PHY BASIC STATUS REG:0x%04X", status);
phy_speed_new = 0;
@ -512,10 +549,21 @@ static void phy_monitor_thread_entry(void *parameter)
/* send link up. */
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
#ifdef PHY_USING_INTERRUPT_MODE
/* configuration intterrupt pin */
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
/* enable phy interrupt */
HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MSAK_REG, PHY_INT_MASK);
break;
#endif
} /* link up. */
else
{
LOG_I("link down\r\n");
LOG_I("link down");
/* send link down. */
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
}

7
bsp/stm32/libraries/HAL_Drivers/drv_eth.h
View File

@ -55,6 +55,13 @@
#define PHY_10M_MASK ((1<<12) || (1<<13))
#define PHY_100M_MASK ((1<<14) || (1<<15))
#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
/* The PHY interrupt source flag register. */
#define PHY_INTERRUPT_FLAG_REG 0x15U
/* The PHY interrupt mask register. */
#define PHY_INTERRUPT_MSAK_REG 0x15U
#define PHY_LINK_CHANGE_FLAG (1<<2)
#define PHY_LINK_CHANGE_MASK (1<<9)
#define PHY_INT_MASK 0
#endif /* PHY_USING_DM9161CEP */

8
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash.h
View File

@ -16,8 +16,16 @@
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int stm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */

4
bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
View File

@ -288,13 +288,13 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
#if defined(SOC_SERIES_STM32L4)
val = HAL_RCC_GetPCLK2Freq() / freq;
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
val = HAL_RCC_GetPCLK2Freq() * 2 / freq;
#endif
}
else
{
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
#elif defined(SOC_SERIES_STM32F0)
val = HAL_RCC_GetPCLK1Freq() / freq;

14
bsp/stm32/libraries/HAL_Drivers/drv_qspi.c
View File

@ -92,11 +92,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
/* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(QSPI_IRQn);
HAL_NVIC_SetPriority(QSPI_DMA_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(QSPI_DMA_IRQn);
HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0);
HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ);
/* init QSPI DMA */
QSPI_DMA_CLK_ENABLE;
if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN)
{
__HAL_RCC_DMA1_CLK_ENABLE();
}
else
{
__HAL_RCC_DMA2_CLK_ENABLE();
}
HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
qspi_bus->hdma_quadspi = hdma_quadspi_config;

514
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
View File

@ -5,19 +5,21 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift change to new framework
* 2018-11-5 SummerGift first version
* 2018-12-11 greedyhao Porting for stm32f7xx
* 2019-01-03 zylx modify DMA initialization and spixfer function
*/
#include "board.h"
#ifdef RT_USING_SPI
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#include "drv_spi.h"
#include "drv_config.h"
#include <string.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.spi"
@ -72,7 +74,7 @@ static struct stm32_spi_config spi_config[] =
#endif
};
static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
{
@ -201,6 +203,10 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
spi_handle->State = HAL_SPI_STATE_RESET;
#ifdef SOC_SERIES_STM32L4
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
#endif
if (HAL_SPI_Init(spi_handle) != HAL_OK)
{
return RT_EIO;
@ -210,204 +216,114 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
#endif
/* DMA configuration */
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
HAL_DMA_Init(&spi_drv->dma.handle_rx);
__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
}
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
HAL_DMA_Init(&spi_drv->dma.handle_tx);
__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
/* NVIC configuration for DMA transfer complete interrupt */
HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
}
__HAL_SPI_ENABLE(spi_handle);
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
#ifdef BSP_SPI_USING_DMA
static uint8_t dummy = 0xFF;
static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_message* message)
{
struct stm32_spi *spi_drv = rt_container_of(spi_bus, struct stm32_spi, spi_bus);
DMA_HandleTypeDef * hdma_tx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_tx;
DMA_HandleTypeDef * hdma_rx = (DMA_HandleTypeDef *)&spi_drv->dma.handle_rx;
HAL_DMA_DeInit(hdma_tx);
HAL_DMA_DeInit(hdma_rx);
/*
* Check if the DMA Stream is disabled before enabling it.
* Note that this step is useful when the same Stream is used multiple times.
*/
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
while (hdma_tx->Instance->CR & DMA_SxCR_EN);
while (hdma_rx->Instance->CR & DMA_SxCR_EN);
#endif
if(message->recv_buf != RT_NULL)
{
hdma_rx->Init.MemInc = DMA_MINC_ENABLE;
}
else
{
message->recv_buf = &dummy;
hdma_rx->Init.MemInc = DMA_MINC_DISABLE;
}
HAL_DMA_Init(hdma_rx);
__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
if(message->send_buf != RT_NULL)
{
hdma_tx->Init.MemInc = DMA_MINC_ENABLE;
}
else
{
dummy = 0xFF;
message->send_buf = &dummy;
hdma_tx->Init.MemInc = DMA_MINC_DISABLE;
}
HAL_DMA_Init(hdma_tx);
/* link DMA with SPI */
__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
LOG_D("%s RX Instance: %x, TX Instance: %x", spi_drv->config->bus_name, hdma_rx->Instance, hdma_tx->Instance);
LOG_D("%s dma config done, TX dma_irq number: %d, RX dma_irq number: %d",
spi_drv->config->bus_name,
spi_drv->config->dma_tx.dma_irq,
spi_drv->config->dma_rx.dma_irq);
/* NVIC configuration for DMA transfer complete interrupt*/
HAL_NVIC_SetPriority(spi_drv->config->dma_tx.dma_irq, 0, 1);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx.dma_irq);
/* NVIC configuration for DMA transfer complete interrupt*/
HAL_NVIC_SetPriority(spi_drv->config->dma_rx.dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx.dma_irq);
}
#endif
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
HAL_StatusTypeDef state;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
SPI_HandleTypeDef * spi_handle = &spi_drv->handle;
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
struct stm32_hw_spi_cs *cs = device->parent.user_data;
rt_int32_t length = message->length;
rt_int32_t data_width = spi_drv->cfg->data_width;
if (message->cs_take)
{
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
}
#ifdef BSP_SPI_USING_DMA
if(message->length > 32)
{
if(data_width <= 8)
{
HAL_StatusTypeDef state;
LOG_D("%s dma transfer prepare and start", spi_drv->config->bus_name);
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
spi_drv->config->bus_name,
(uint32_t)message->send_buf,
(uint32_t)message->recv_buf, message->length);
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
spi_drv->config->bus_name,
(uint32_t)message->send_buf,
(uint32_t)message->recv_buf, message->length);
spi_dma_transfer_prepare(device->bus, message);
/* start once data exchange in DMA mode */
state = HAL_SPI_TransmitReceive_DMA(spi_handle,
(uint8_t*)message->send_buf,
(uint8_t*)message->recv_buf,
message->length);
if (state != HAL_OK)
if (message->length)
{
/* start once data exchange in DMA mode */
if (message->send_buf && message->recv_buf)
{
if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
{
LOG_D("spi flash configuration error : %d", state);
message->length = 0;
//while(1);
state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length);
}
else
{
LOG_D("%s dma transfer done", spi_drv->config->bus_name);
state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)message->send_buf, (uint8_t *)message->recv_buf, message->length, 1000);
}
}
else if (message->send_buf)
{
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)message->send_buf, message->length);
}
else
{
state = HAL_SPI_Transmit(spi_handle, (uint8_t *)message->send_buf, message->length, 1000);
}
/* For simplicity reasons, this example is just waiting till the end of the
transfer, but application may perform other tasks while transfer operation
is ongoing. */
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
LOG_D("%s get state done", spi_drv->config->bus_name);
}
else
{
// TODO
}
} else
#endif
{
if (data_width == 8)
{
const rt_uint8_t * send_ptr = message->send_buf;
rt_uint8_t * recv_ptr = message->recv_buf;
while (length--)
memset(message->recv_buf, 0xff, message->length);
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
rt_uint8_t data = ~0;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
/* send data once */
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
*(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data;
/* receive data once */
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
#endif
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
data = *(volatile rt_uint8_t *)(&spi_handle->Instance->DR);
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)message->recv_buf, message->length);
}
} else
{
const rt_uint16_t * send_ptr = message->send_buf;
rt_uint16_t * recv_ptr = message->recv_buf;
while (length--)
else
{
rt_uint16_t data = ~0;
if(send_ptr != RT_NULL)
{
data = *send_ptr++;
}
/* send data once */
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_TXE) == RESET);
*(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data;
/* receive data once */
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
#endif
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
data = *(volatile rt_uint16_t *)(&spi_handle->Instance->DR);
if(recv_ptr != RT_NULL)
{
*recv_ptr++ = data;
}
state = HAL_SPI_Receive(spi_handle, (uint8_t *)message->recv_buf, message->length, 1000);
}
}
if (state != HAL_OK)
{
LOG_I("spi transfer error : %d", state);
message->length = 0;
spi_handle->State = HAL_SPI_STATE_READY;
}
else
{
LOG_D("%s transfer done", spi_drv->config->bus_name);
}
/* For simplicity reasons, this example is just waiting till the end of the
transfer, but application may perform other tasks while transfer operation
is ongoing. */
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
}
/* Wait until Busy flag is reset before disabling SPI */
while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_BSY) == SET);
if (message->cs_release)
{
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
@ -443,61 +359,81 @@ static int rt_hw_spi_bus_init(void)
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
#ifdef BSP_SPI_USING_DMA
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance;
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel;
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
#elif defined(SOC_SERIES_STM32L4)
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request;
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
#endif
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel;
#elif defined(SOC_SERIES_STM32L4)
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request;
#endif
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
LOG_D("%s DMA clock init done", spi_config[i].bus_name);
#endif /* BSP_SPI_USING_DMA */
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
#elif defined(SOC_SERIES_STM32L4)
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
#endif
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
RT_ASSERT(result == RT_EOK);
@ -511,7 +447,7 @@ static int rt_hw_spi_bus_init(void)
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin)
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
@ -550,7 +486,20 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
return result;
}
#if defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA)
#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
void SPI1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -566,7 +515,9 @@ void SPI1_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -584,7 +535,20 @@ void SPI1_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA)
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
void SPI2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -600,7 +564,9 @@ void SPI2_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -618,7 +584,20 @@ void SPI2_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA)
#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
void SPI3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -634,7 +613,9 @@ void SPI3_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -652,8 +633,20 @@ void SPI3_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
void SPI4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
#if defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA)
HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -669,7 +662,9 @@ void SPI4_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -687,7 +682,20 @@ void SPI4_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA)
#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
void SPI5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -703,7 +711,9 @@ void SPI5_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -721,7 +731,7 @@ void SPI5_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA)
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
/**
* @brief This function handles DMA Rx interrupt request.
* @param None
@ -737,7 +747,9 @@ void SPI6_DMA_RX_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
/**
* @brief This function handles DMA Tx interrupt request.
* @param None
@ -755,8 +767,78 @@ void SPI6_DMA_TX_IRQHandler(void)
}
#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
static void stm32_get_dma_info(void)
{
#ifdef BSP_SPI1_RX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
#endif
#ifdef BSP_SPI1_TX_USING_DMA
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
#endif
#ifdef BSP_SPI2_RX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
#endif
#ifdef BSP_SPI2_TX_USING_DMA
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
#endif
#ifdef BSP_SPI3_RX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
#endif
#ifdef BSP_SPI3_TX_USING_DMA
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
#endif
#ifdef BSP_SPI4_RX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
#endif
#ifdef BSP_SPI4_TX_USING_DMA
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
#endif
#ifdef BSP_SPI5_RX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
#endif
#ifdef BSP_SPI5_TX_USING_DMA
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
#endif
#ifdef BSP_SPI6_RX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
#endif
#ifdef BSP_SPI6_TX_USING_DMA
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
#endif
}
int rt_hw_spi_init(void)
{
stm32_get_dma_info();
return rt_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(rt_hw_spi_init);

14
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift change to new framework
* 2018-11-5 SummerGift first version
*/
#ifndef __DRV_SPI_H_
@ -29,7 +29,7 @@ struct stm32_spi_config
{
SPI_TypeDef *Instance;
char *bus_name;
struct dma_config dma_rx, dma_tx;
struct dma_config *dma_rx, *dma_tx;
};
struct stm32_spi_device
@ -39,21 +39,23 @@ struct stm32_spi_device
char *device_name;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
/* stm32 spi dirver class */
struct stm32_spi
{
SPI_HandleTypeDef handle;
const struct stm32_spi_config *config;
struct stm32_spi_config *config;
struct rt_spi_configuration *cfg;
#ifdef BSP_SPI_USING_DMA
struct
{
DMA_HandleTypeDef handle_rx;
DMA_HandleTypeDef handle_tx;
} dma;
#endif
rt_uint8_t spi_dma_flag;
struct rt_spi_bus spi_bus;
};

100
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
View File

@ -46,7 +46,7 @@ enum
#endif
};
static const struct stm32_uart_config uart_config[] =
static struct stm32_uart_config uart_config[] =
{
#ifdef BSP_USING_UART1
UART1_CONFIG,
@ -65,7 +65,7 @@ static const struct stm32_uart_config uart_config[] =
#endif
};
static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])];
static struct stm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
@ -239,7 +239,7 @@ static void uart_isr(struct rt_serial_device *serial)
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
}
#ifdef RT_SERIAL_USING_DMA
else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) &&
else if ((uart->uart_dma_flag) && (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) &&
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_IDLE) != RESET))
{
level = rt_hw_interrupt_disable();
@ -309,8 +309,8 @@ void USART1_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR)
void USART1_RX_DMA_ISR(void)
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
void USART1_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@ -320,7 +320,7 @@ void USART1_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR) */
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
@ -334,8 +334,8 @@ void USART2_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR)
void USART2_RX_DMA_ISR(void)
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
void USART2_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@ -345,7 +345,7 @@ void USART2_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART2_RX_DMA_ISR) */
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
@ -359,8 +359,8 @@ void USART3_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(USART3_RX_DMA_ISR)
void USART3_RX_DMA_ISR(void)
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
void USART3_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@ -370,7 +370,7 @@ void USART3_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART3_RX_DMA_ISR) */
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
#endif /* BSP_USING_UART3*/
#if defined(BSP_USING_UART4)
@ -384,8 +384,8 @@ void UART4_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(USART1_RX_DMA_ISR)
void USART4_RX_DMA_ISR(void)
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
void USART4_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@ -395,7 +395,7 @@ void USART4_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(USART4_RX_DMA_ISR) */
#endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
#endif /* BSP_USING_UART4*/
#if defined(BSP_USING_UART5)
@ -409,8 +409,8 @@ void UART5_IRQHandler(void)
/* leave interrupt */
rt_interrupt_leave();
}
#if defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR)
void USART5_RX_DMA_ISR(void)
#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
void USART5_DMA_RX_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
@ -420,7 +420,7 @@ void USART5_RX_DMA_ISR(void)
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* defined(RT_SERIAL_USING_DMA) && defined(USART5_RX_DMA_ISR) */
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
#endif /* BSP_USING_UART5*/
#ifdef RT_SERIAL_USING_DMA
@ -437,12 +437,12 @@ static void stm32_dma_config(struct rt_serial_device *serial)
rt_uint32_t tmpreg= 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, uart->config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rcc);
SET_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
SET_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
@ -450,13 +450,13 @@ static void stm32_dma_config(struct rt_serial_device *serial)
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma.handle);
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0)
uart->dma.handle.Instance = uart->config->dma.Instance;
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
uart->dma.handle.Instance = uart->config->dma.Instance;
uart->dma.handle.Init.Channel = uart->config->dma.stream_channel.channel;
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
uart->dma.handle.Init.Channel = uart->config->dma_rx->channel;
#elif defined(SOC_SERIES_STM32L4)
uart->dma.handle.Instance = uart->config->dma.Instance;
uart->dma.handle.Init.Request = uart->config->dma.channel_request.request;
uart->dma.handle.Instance = uart->config->dma_rx->Instance;
uart->dma.handle.Init.Request = uart->config->dma_rx->request;
#endif
uart->dma.handle.Init.Direction = DMA_PERIPH_TO_MEMORY;
uart->dma.handle.Init.PeriphInc = DMA_PINC_DISABLE;
@ -491,8 +491,8 @@ static void stm32_dma_config(struct rt_serial_device *serial)
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
/* enable rx irq */
HAL_NVIC_SetPriority(uart->config->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(uart->config->dma_irq);
HAL_NVIC_SetPriority(uart->config->dma_rx->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(uart->config->dma_rx->dma_irq);
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
@ -547,31 +547,59 @@ void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
}
#endif /* RT_SERIAL_USING_DMA */
static void stm32_uart_get_dma_config(void)
{
#ifdef BSP_UART1_RX_USING_DMA
uart_obj[UART1_INDEX].uart_dma_flag = 1;
static struct dma_config uart1_dma_rx = UART1_DMA_CONFIG;
uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx;
#endif
#ifdef BSP_UART2_RX_USING_DMA
uart_obj[UART2_INDEX].uart_dma_flag = 1;
static struct dma_config uart2_dma_rx = UART2_DMA_CONFIG;
uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx;
#endif
#ifdef BSP_UART3_RX_USING_DMA
uart_obj[UART3_INDEX].uart_dma_flag = 1;
static struct dma_config uart3_dma_rx = UART3_DMA_CONFIG;
uart_config[UART3_INDEX].dma_rx = &uart3_dma_rx;
#endif
#ifdef BSP_UART4_RX_USING_DMA
uart_obj[UART4_INDEX].uart_dma_flag = 1;
static struct dma_config uart4_dma_rx = UART4_DMA_CONFIG;
uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx;
#endif
#ifdef BSP_UART5_RX_USING_DMA
uart_obj[UART5_INDEX].uart_dma_flag = 1;
static struct dma_config uart5_dma_rx = UART5_DMA_CONFIG;
uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx;
#endif
}
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
stm32_uart_get_dma_config();
for (int i = 0; i < obj_num; i++)
{
uart_obj[i].config = &uart_config[i];
uart_obj[i].serial.ops = &stm32_uart_ops;
uart_obj[i].serial.config = config;
/* Determines whether a serial instance supports DMA */
if(uart_obj[i].config->dma.Instance != DMA_NOT_AVAILABLE)
#if defined(RT_SERIAL_USING_DMA)
if(uart_obj[i].uart_dma_flag)
{
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
#if defined(RT_SERIAL_USING_DMA)
| RT_DEVICE_FLAG_DMA_RX
#endif
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX| RT_DEVICE_FLAG_DMA_RX
,&uart_obj[i]);
}
else
#endif
{
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial,uart_obj[i].config->name,

38
bsp/stm32/libraries/HAL_Drivers/drv_usart.h
View File

@ -15,10 +15,10 @@
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#include "drv_dma.h"
int rt_hw_usart_init(void);
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
@ -37,45 +37,15 @@ struct stm32_uart_config
const char *name;
USART_TypeDef *Instance;
IRQn_Type irq_type;
union {
DMA_INSTANCE_TYPE *Instance;
#if defined(SOC_SERIES_STM32F1)
/* the DMA config has channel only, such as on STM32F1xx */
struct {
DMA_INSTANCE_TYPE *Instance;
} channel;
#endif
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
/* the DMA config has stream and channel, such as on STM32F4xx */
struct {
DMA_INSTANCE_TYPE *Instance;
rt_uint32_t channel;
} stream_channel;
#endif
#if defined(SOC_SERIES_STM32L4)
/* the DMA config has channel and request, such as on STM32L4xx */
struct {
DMA_INSTANCE_TYPE *Instance;
rt_uint32_t request;
} channel_request;
#endif
} dma;
rt_uint32_t dma_rcc;
IRQn_Type dma_irq;
struct dma_config *dma_rx;
};
/* stm32 uart dirver class */
struct stm32_uart
{
UART_HandleTypeDef handle;
const struct stm32_uart_config *config;
struct stm32_uart_config *config;
#ifdef RT_SERIAL_USING_DMA
struct
{
@ -83,7 +53,7 @@ struct stm32_uart
rt_size_t last_index;
} dma;
#endif
rt_uint8_t uart_dma_flag;
struct rt_serial_device serial;
};

36
bsp/stm32/libraries/templates/stm32f0xx/.config
View File

@ -281,6 +281,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
@ -295,6 +296,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -309,10 +311,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -321,30 +320,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F0=y
@ -361,9 +338,10 @@ CONFIG_SOC_STM32F091RC=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
#

42
bsp/stm32/libraries/templates/stm32f0xx/board/Kconfig
View File

@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

8
bsp/stm32/libraries/templates/stm32f0xx/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f0xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (256 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -38,4 +42,8 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

2
bsp/stm32/libraries/templates/stm32f0xx/board/linker_scripts/link.icf
View File

@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
place in RAM_region { readwrite, last block CSTACK};

12
bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h
View File

@ -149,19 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F0
@ -174,6 +163,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

16
bsp/stm32/libraries/templates/stm32f10x/.config
View File

@ -296,6 +296,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -310,10 +311,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -322,11 +320,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1=y
@ -343,9 +338,10 @@ CONFIG_SOC_STM32F103RB=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
#

42
bsp/stm32/libraries/templates/stm32f10x/board/Kconfig
View File

@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

8
bsp/stm32/libraries/templates/stm32f10x/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f1xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (128 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -38,4 +42,8 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

2
bsp/stm32/libraries/templates/stm32f10x/board/linker_scripts/link.icf
View File

@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
place in RAM_region { readwrite, last block CSTACK};

6
bsp/stm32/libraries/templates/stm32f10x/rtconfig.h
View File

@ -149,13 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F1
@ -168,6 +163,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

16
bsp/stm32/libraries/templates/stm32f4xx/.config
View File

@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F4=y
@ -344,9 +339,10 @@ CONFIG_SOC_STM32F407ZG=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
#

42
bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig
View File

@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

2
bsp/stm32/libraries/templates/stm32f4xx/board/SConscript
View File

@ -34,4 +34,4 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPDEFINES = ['STM32F407xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
Return('group')

8
bsp/stm32/libraries/templates/stm32f4xx/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f4xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -37,5 +41,9 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif

2
bsp/stm32/libraries/templates/stm32f4xx/board/linker_scripts/link.icf
View File

@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
place in RAM_region { readwrite, last block CSTACK};

6
bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h
View File

@ -149,13 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F4
@ -168,6 +163,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

16
bsp/stm32/libraries/templates/stm32f7xx/.config
View File

@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F7=y
@ -344,9 +339,10 @@ CONFIG_SOC_STM32F767IG=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
#

2
bsp/stm32/libraries/templates/stm32f7xx/SConstruct
View File

@ -38,7 +38,7 @@ objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
SDK_ROOT = os.path.abspath('./')
# include drivers
objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/STM32F4xx_HAL/SConscript'))
objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/STM32F7xx_HAL/SConscript'))
# include libraries
objs.extend(SConscript(os.path.dirname(SDK_ROOT) + '/libraries/HAL_Drivers/SConscript'))

42
bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig
View File

@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

2
bsp/stm32/libraries/templates/stm32f7xx/board/SConscript
View File

@ -24,4 +24,4 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPDEFINES = ['STM32F767xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
Return('group')

8
bsp/stm32/libraries/templates/stm32f7xx/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f7xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (1024 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -37,4 +41,8 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif

2
bsp/stm32/libraries/templates/stm32f7xx/board/linker_scripts/link.icf
View File

@ -25,4 +25,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
place in RAM_region { readwrite, last block CSTACK};

1367
bsp/stm32/libraries/templates/stm32f7xx/project.uvoptx
View File

File diff suppressed because it is too large Load Diff

342
bsp/stm32/libraries/templates/stm32f7xx/project.uvprojx
View File

@ -1,7 +1,10 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rt-thread</TargetName>
@ -11,33 +14,33 @@
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32F407ZGTx</Device>
<Device>STM32F767BGTx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F4xx_DFP.2.11.0</PackID>
<PackID>Keil.STM32F7xx_DFP.2.9.0</PackID>
<PackURL>http://www.keil.com/pack</PackURL>
<Cpu>IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec />
<StartupFile />
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM))</FlashDriverDll>
<Cpu>IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32F407ZGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h</RegisterFile>
<MemoryEnv />
<Cmp />
<Asm />
<Linker />
<OHString />
<InfinionOptionDll />
<SLE66CMisc />
<SLE66AMisc />
<SLE66LinkerMisc />
<SFDFile>$$Device:STM32F407ZGTx$CMSIS\SVD\STM32F40x.svd</SFDFile>
<RegisterFile>$$Device:STM32F767BGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F767BGTx$CMSIS\SVD\STM32F7x7_v1r2.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath />
<IncludePath />
<LibPath />
<RegisterFilePath />
<DBRegisterFilePath />
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
@ -59,8 +62,8 @@
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
@ -69,8 +72,8 @@
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name />
<UserProg2Name />
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
@ -80,14 +83,14 @@
<RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name />
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString />
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
@ -101,19 +104,19 @@
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument />
<IncludeLibraryModules />
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
@ -135,11 +138,11 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4 />
<pFcarmOut />
<pFcarmGrp />
<pFcArmRoot />
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
@ -171,8 +174,8 @@
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName />
<AdsCpuType>"Cortex-M7"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
@ -180,15 +183,16 @@
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsVP>3</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RoSelD>4</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
@ -205,7 +209,7 @@
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
@ -240,8 +244,8 @@
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
<StartAddress>0x20020000</StartAddress>
<Size>0x60000</Size>
</IRAM>
<IROM>
<Type>1</Type>
@ -275,8 +279,8 @@
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
<StartAddress>0x200000</StartAddress>
<Size>0x100000</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
@ -295,16 +299,16 @@
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
<StartAddress>0x20020000</StartAddress>
<Size>0x60000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector />
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
@ -331,9 +335,9 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls />
<MiscControls></MiscControls>
<Define>USE_HAL_DRIVER, STM32F407xx</Define>
<Undefine />
<Undefine></Undefine>
<IncludePath>applications;.;board;board\CubeMX_Config\Inc;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Inc;..\libraries\STM32F4xx_HAL\CMSIS\Device\ST\STM32F4xx\Include;..\libraries\STM32F4xx_HAL\CMSIS\Include</IncludePath>
</VariousControls>
</Cads>
@ -349,10 +353,10 @@
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<Define></Define>
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@ -364,13 +368,13 @@
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<IncludeLibs />
<IncludeLibsPath />
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc> --keep *.o(.rti_fn.*) --keep *.o(FSymTab)</Misc>
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<LinkerInputFile></LinkerInputFile>
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@ -393,36 +397,26 @@
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@ -438,92 +432,66 @@
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</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_sram.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_sram.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_tim_ex.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_usart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_usart.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_hal_wwdg.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_wwdg.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_ll_fmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fmc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_ll_fsmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_fsmc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_ll_sdmmc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\STM32F4xx_HAL\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_sdmmc.c</FilePath>
</File>
</Files>
<Files>
<File>
<FileName>stm32f4xx_ll_usb.c</FileName>
<FileType>1</FileType>
@ -1162,9 +962,11 @@
</Groups>
</Target>
</Targets>
<RTE>
<apis />
<components />
<files />
<apis/>
<components/>
<files/>
</RTE>
</Project>

6
bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h
View File

@ -149,13 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F7
@ -168,6 +163,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

91
bsp/stm32/libraries/templates/stm32f7xx/rtconfig.py
View File

@ -5,6 +5,9 @@ ARCH='arm'
CPU='cortex-m7'
CROSS_TOOL='gcc'
# bsp lib config
BSP_LIBRARY_TYPE = None
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if os.getenv('RTT_ROOT'):
@ -14,7 +17,7 @@ if os.getenv('RTT_ROOT'):
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = '/usr/local/Cellar/arm-none-eabi-gcc/7-2017-q4-major/gcc/bin/'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
@ -31,7 +34,6 @@ if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
CXX = PREFIX + 'g++'
@ -40,56 +42,48 @@ if PLATFORM == 'gcc':
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -std=c99 -g -Wall'
DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -std=c99 -Dgcc'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T rtthread.ld'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2 -Os'
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
# module setting
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
' -shared -fPIC -nostartfiles -static-libgcc'
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
CXX = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M7.fp.sp --fpu=FPv4-SP'
CFLAGS = DEVICE + ' --apcs=interwork '
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread.sct'
DEVICE = ' --cpu Cortex-M7.fp.sp'
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC'
LFLAGS += ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib"'
EXEC_PATH += '/arm/bin40/'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2 -Otime'
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
@ -97,48 +91,45 @@ elif PLATFORM == 'armcc':
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ''
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M7'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
CFLAGS += ' --fpu=VFPv5_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = ''
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M7'
AFLAGS += ' --fpu None'
AFLAGS += ' --fpu VFPv5_sp'
AFLAGS += ' -S'
LFLAGS = ' --config rtthread.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
LFLAGS += ' --silent'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
CXXFLAGS = CFLAGS
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = ''
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'

10
bsp/stm32/libraries/templates/stm32f7xx/template.uvoptx
View File

@ -103,7 +103,7 @@
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
@ -119,13 +119,13 @@
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59400616 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM)</Name>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20020000 -FF0STM32F7x_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM))</Name>
<Key>JL2CM3</Key>
<Name>-U59400616 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>

44
bsp/stm32/libraries/templates/stm32f7xx/template.uvprojx
View File

@ -14,16 +14,16 @@
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>STM32F407ZGTx</Device>
<Device>STM32F767BGTx</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F4xx_DFP.2.13.0</PackID>
<PackID>Keil.STM32F7xx_DFP.2.9.0</PackID>
<PackURL>http://www.keil.com/pack</PackURL>
<Cpu>IRAM(0x20000000,0x20000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<Cpu>IRAM(0x20020000,0x60000) IRAM2(0x20000000,0x20000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F407ZGTx$CMSIS\Flash\STM32F4xx_1024.FLM))</FlashDriverDll>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20020000 -FC1000 -FN1 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F767BGTx$CMSIS\Flash\STM32F7x_1024.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:STM32F407ZGTx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h</RegisterFile>
<RegisterFile>$$Device:STM32F767BGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
@ -33,7 +33,7 @@
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F407ZGTx$CMSIS\SVD\STM32F40x.svd</SFDFile>
<SFDFile>$$Device:STM32F767BGTx$CMSIS\SVD\STM32F7x7_v1r2.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
@ -112,11 +112,11 @@
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
@ -138,7 +138,7 @@
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
@ -174,7 +174,7 @@
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<AdsCpuType>"Cortex-M7"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
@ -183,16 +183,16 @@
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsVP>3</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RoSelD>4</RoSelD>
<RwSelD>4</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
@ -209,7 +209,7 @@
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
@ -244,8 +244,8 @@
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
<StartAddress>0x20020000</StartAddress>
<Size>0x60000</Size>
</IRAM>
<IROM>
<Type>1</Type>
@ -279,8 +279,8 @@
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
<StartAddress>0x200000</StartAddress>
<Size>0x100000</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
@ -299,13 +299,13 @@
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
<StartAddress>0x20020000</StartAddress>
<Size>0x60000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x10000</Size>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>

16
bsp/stm32/libraries/templates/stm32l4xx/.config
View File

@ -297,6 +297,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -311,10 +312,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -323,11 +321,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32L4=y
@ -344,9 +339,10 @@ CONFIG_SOC_STM32L475VE=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
#

40
bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig
View File

@ -16,19 +16,41 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

3
bsp/stm32/libraries/templates/stm32l4xx/board/SConscript
View File

@ -36,4 +36,5 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPDEFINES = ['STM32L475xx']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
Return('group')

8
bsp/stm32/libraries/templates/stm32l4xx/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32l4xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (512 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -28,5 +32,9 @@
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif

2
bsp/stm32/libraries/templates/stm32l4xx/board/linker_scripts/link.icf
View File

@ -26,4 +26,4 @@ do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, last block CSTACK};
place in RAM_region { readwrite, last block CSTACK};

6
bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h
View File

@ -149,13 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32L4
@ -168,6 +163,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

43
bsp/stm32/stm32f091-st-nucleo/.config
View File

@ -281,6 +281,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
#
# peripheral libraries and drivers
@ -295,6 +296,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
#
# miscellaneous packages
@ -309,10 +311,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
#
# sample package
#
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -321,30 +320,8 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F0=y
@ -356,16 +333,24 @@ CONFIG_SOC_STM32F091RC=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART1 is not set
CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_UART2_RX_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
#
# Board extended module Drivers

55
bsp/stm32/stm32f091-st-nucleo/board/Kconfig
View File

@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart2)"
select BSP_USING_UART
select BSP_USING_UART2
default y
@ -21,20 +22,52 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
default n
config BSP_USING_UART2
bool "Enable UART2"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
select RT_USING_SPI
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

8
bsp/stm32/stm32f091-st-nucleo/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f0xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (256 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -38,4 +42,8 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

14
bsp/stm32/stm32f091-st-nucleo/rtconfig.h
View File

@ -149,19 +149,8 @@
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
/* Privated Packages of RealThread */
/* Network Utilities */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32F0
@ -171,9 +160,12 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART2
/* Board extended module Drivers */

8
bsp/stm32/stm32f103-atk-nano/.config
View File

@ -312,6 +312,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -321,6 +322,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1=y
@ -341,14 +343,14 @@ CONFIG_BSP_USING_USB_TO_USART=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set

86
bsp/stm32/stm32f103-atk-nano/board/Kconfig
View File

@ -9,6 +9,7 @@ menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART
select BSP_USING_UART1
default y
@ -19,6 +20,7 @@ menu "Onboard Peripheral Drivers"
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (w25q16 spi2)"
select BSP_USING_SPI
select BSP_USING_SPI2
select RT_USING_SFUD
select RT_SFUD_USING_SFDP
@ -39,20 +41,38 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_UART1
bool "Enable UART1"
select RT_USING_SERIAL
menuconfig BSP_USING_UART
bool "Enable UART"
default y
config BSP_USING_UART2
bool "Enable UART2"
select RT_USING_SERIAL
default n
if BSP_USING_UART
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_USING_UART3
bool "Enable UART3"
select RT_USING_SERIAL
default n
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
@ -90,20 +110,42 @@ menu "On-chip Peripheral Drivers"
default n
endif
endif
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
select RT_USING_SPI
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_SPI_USING_DMA
bool "Enable SPI DMA support"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"

8
bsp/stm32/stm32f103-atk-nano/board/board.h
View File

@ -15,6 +15,10 @@
#include <stm32f1xx.h>
#include "drv_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (128 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
@ -38,4 +42,8 @@ extern int __bss_end;
void SystemClock_Config(void);
#ifdef __cplusplus
}
#endif
#endif /* __BOARD_H__ */

12
bsp/stm32/stm32f103-atk-nano/project.uvoptx
View File

@ -187,7 +187,7 @@
<Group>
<GroupName>Applications</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -207,7 +207,7 @@
<Group>
<GroupName>Drivers</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -287,7 +287,7 @@
<Group>
<GroupName>Kernel</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -487,7 +487,7 @@
<Group>
<GroupName>CORTEX-M3</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -555,7 +555,7 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
@ -671,7 +671,7 @@
<Group>
<GroupName>finsh</GroupName>
<tvExp>0</tvExp>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>

1
bsp/stm32/stm32f103-atk-nano/rtconfig.h
View File

@ -166,6 +166,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
/* Board extended module Drivers */

9
bsp/stm32/stm32f103-fire-arbitrary/.config
View File

@ -312,6 +312,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
#
# samples: kernel and components samples
@ -321,6 +322,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1=y
@ -345,14 +347,13 @@ CONFIG_BSP_USING_USB_TO_USART=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI3 is not set
# CONFIG_BSP_SPI_USING_DMA is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_PWM is not set

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