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Merge pull request #4404 from KyleChenjh/lts-v3.1.x 

[Update] Sync from v4.0.3
This commit is contained in:
Bernard Xiong 2021-03-02 15:00:43 +08:00 committed by GitHub
parent 5f17cf9204 19871ac32e
commit 2c12493ff3
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GPG Key ID: 4AEE18F83AFDEB23
710 changed files with 3471 additions and 9263 deletions
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144
.github/workflows/action.yml vendored Normal file
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@ -0,0 +1,144 @@
name: RT-Thread
# Controls when the action will run. Triggers the workflow on push or pull request
# events but only for the lts-v3.1.x branch
on:
# Runs at 16:00 UTC (BeiJing 00:00) on the 1st of every month
schedule:
- cron: '0 16 1 * *'
push:
branches:
- lts-v3.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
pull_request:
branches:
- lts-v3.1.x
paths-ignore:
- documentation/**
- '**/README.md'
- '**/README_zh.md'
jobs:
build:
runs-on: ubuntu-latest
name: ${{ matrix.legs.RTT_BSP }}
strategy:
fail-fast: false
matrix:
legs:
- {RTT_BSP: "CME_M7", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "apollo2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "asm9260t", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at91sam9260", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "gkipc", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-atk-commander", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-fire-pro", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "imxrt/imxrt1052-nxp-evk", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lm3s8962", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lm4f232", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc43xx/M4", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc178x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc408x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc2148", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc2478", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc5410x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "lpc54114-lite", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "ls1bdev", RTT_TOOL_CHAIN: "sourcery-mips"}
- {RTT_BSP: "ls1cdev", RTT_TOOL_CHAIN: "sourcery-mips"}
- {RTT_BSP: "mb9bf500r", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mb9bf506r", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "qemu-vexpress-gemini", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f072-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f091-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-atk-warshipv3", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-dofly-lyc8", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-dofly-M3S", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-fire-arbitrary", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-hw100k-ibox", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-mini-system", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f411-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f427-robomaster-a", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-armfly-v6", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f429-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f446-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f469-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f746-st-disco", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-fire-challenger", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32f767-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g071-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32g431-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32h743-atk-apollo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32h743-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l4r9-st-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l432-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-atk-pandora", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l475-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l476-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32/stm32l496-ali-developer", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "stm32f20x", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "swm320-lq100", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "zynq7000", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "fh8620", RTT_TOOL_CHAIN: "sourcery-arm"}
steps:
- uses: actions/checkout@v2
- name: Set up Python
uses: actions/setup-python@master
with:
python-version: 3.8
- name: Install Tools
shell: bash
run: |
sudo apt-get update
sudo apt-get -qq install gcc-multilib libsdl-dev scons
echo "RTT_ROOT=${{ github.workspace }}" >> $GITHUB_ENV
echo "RTT_CC=gcc" >> $GITHUB_ENV
- name: Install Arm ToolChains
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
shell: bash
run: |
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
/opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
- name: Install Mips ToolChains
if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}
shell: bash
run: |
wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
sudo tar xjf mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 -C /opt
/opt/mips-2016.05/bin/mips-sde-elf-gcc --version
echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
- name: Bsp Scons Compile
if: ${{ success() }}
shell: bash
env:
RTT_BSP: ${{ matrix.legs.RTT_BSP }}
RTT_TOOL_CHAIN: ${{ matrix.legs.RTT_TOOL_CHAIN }}
run: |
scons -C bsp/$RTT_BSP

80
ChangeLog.md
View File

@ -1,3 +1,83 @@
# RT-Thread v3.1.5 Change Log
Change log since v3.1.4
## Kernel
* Fix the issue when block = NULL in rt_mp_free;
* Fix the software issue when the system timer thread is pending
* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
* Fix an issue with rt_timer_start being broken and destroying the timer list
* Fix bug of rt_memheap_detach
* Fix the bug that the linked list is still mounted when the single timer is not modified
* Fix the delay_until issue
* Add mb mq value overflow-check code
* Fix the rt_event_recv function, if the event met without blocking, assigning thread->event_set/event_info will goes well
* Add the definition of the maximum value of ipc type
* Fix the delay_until issue
* fixed __rt_ffs bug on account of armclang LTO.
* fixed rt_timer_list_next_timeout multi-task safe
* fix the software issue when the system timer thread pending.
* Fix the timer/software timer handling issue if the timeout function starts/stops/deletes this timer.
* The cleanup operation is executed before the current thread exits
* Modify cleanup to resolve the issue of unable to free memory and communication between threads
* Fix double release for thread
* Fix thread control bug about `RT_THREAD_CTRL_CLOSE` command
* Fix the issue of critical protection when `rt_thread_delete` change the status of thread;
* Fix bug in rt_realloc of mem.c, which may cause memory leak
* Use object_find to implement thread_find/device_find
## Components
* Change rt_data_queue_peak to rt_data_queue_peek.
* Add rt_data_queue_deinit and fix bug of dataqueue
* Solve the issue that the do_pollfd function processing the underlying network device returns error -1
* Fix the issue that when the network card device calls to close dhcp, the bottom layer no need to call the dhcp_stop function to close dhcp
* Modify the spelling error of the macro definition, modify the printing error when printing the IMEI number
* Fix the issue that the server closed the connection when web socket requests the data that comes back from the server, and the socket status is incorrectly judged at that point
* Fix the issue of incorrect sal_getaddrinfo release when sal socket supports multiple network cards
* Adjust where the AT socket callback function
* Fix at_client, avoid creating the same client repeatedly and prevent working exceptions and memory leaks.
* Fix the bug that rx_notice out of sync when the data is received after last rt_device_read() is zero
* Change the header file included in some libc files from <rtthread.h> to <rtconfig.h> to narrow the scope of inclusion to prevent recursive compilation
* [jffs2] modify the error check of rt_event_recv()
* [audio] Fix compile warning, undefine var, and fixed re-include of audio
* [serial] Fix the crash caused when the serial port receiving buffer is full and ULOG_USING_ISR_LOG is not turned on
* [spi] Fix "response+1" causing hard fault of unaligned access to SPI memory of STM32 HAL library
* [hwtimer] When getting the timer count, prevent overflow update due to the interruption
* [dirver/i2c] i2c driver supports bus lock, STOP control
* [usb] Fix bug in device descriptor that MAC OS enumeration failed
* Fix the bug that USB cannot recognize composite device normally
* Fix USB host core bugs
* Limit >4 USB ports hubs
* Double free intf
* dname buffer size is too small
* Reset child pointer after detaching instance
## BSP and CPU porting
* Add license info and code cleanup for vexpress-a9 BSP
* Fix spelling mistakes of code
* [allwinner_tina]Fix spi driver bug
* Optimize BSP dist handle process
* fixed a bug that caused system crash by changing the run_mode in low power mode
* drv_flash_f7.c supports single bank mode
* Optimize the pin-index algorithm for stm32
* Fix the clock configuration issue of STM32 hardware timer
* Adjust the interrupt priority configuration of some peripherals of the STM32 series BSP
* Fix stm32 f1 series rtc bug
* Fix PWM timer init about pwm
## Tools
* Fixed python 2.x `cmp`
* Rename GCC_VERSION to GCC_VERSION_STR
* Optimize project group sort by name
* Improve the logic of generating `rtconfig.h` files in scons with command `scons --menuconfig`
* Fixed an issue that *.s src files couldn't be compiled
* Fixed c99/siginfo_t issue caused by gcc_version
# RT-Thread v3.1.4 Change Log
Change log since v3.1.3

1
bsp/allwinner_tina/drivers/drv_gpio.c
View File

@ -538,6 +538,7 @@ static const struct rt_pin_ops ops =
pin_attach_irq,
pin_detach_irq,
pin_irq_enable,
RT_NULL,
};
#endif

4
bsp/allwinner_tina/drivers/drv_uart.c
View File

@ -120,8 +120,8 @@ int rt_hw_uart_init(void)
uart->irqno = UART1_INTERRUPT; // IRQ_UART1;
uart->gpio_rx_port = GPIO_PORT_A;
uart->gpio_tx_port = GPIO_PORT_A;
uart->gpio_rx_pin = GPIO_PIN_3;
uart->gpio_tx_pin = GPIO_PIN_2;
uart->gpio_rx_pin = GPIO_PIN_2;
uart->gpio_tx_pin = GPIO_PIN_3;
uart->gpio_rx_fun = IO_FUN_4;
uart->gpio_tx_fun = IO_FUN_4;

2
bsp/allwinner_tina/drivers/spi/drv_spi.c
View File

@ -483,7 +483,7 @@ static rt_err_t configure(struct rt_spi_device *device,
SPI_SetFirstTransmitBit(spi, SPI_TCTRL_FBS_LSB);
}
switch (configuration->mode)
switch (configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
SPI_SetSclkMode(spi, SPI_SCLK_Mode0);

2
bsp/amebaz/libraries/Kconfig
View File

@ -1,7 +1,7 @@
menu "External Libraries"
config RT_USING_SMARTCONFIG_LIB
bool "Using RT-Thrad SmartConfig Library"
bool "Using RT-Thread SmartConfig Library"
default n
endmenu

1
bsp/apollo2/board/gpio.c
View File

@ -212,6 +212,7 @@ const static struct rt_pin_ops am_pin_ops =
am_pin_attach_irq,
am_pin_dettach_irq,
am_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

4
bsp/beaglebone/drivers/gpio.c
View File

@ -84,6 +84,10 @@ static struct rt_pin_ops am33xx_pin_ops =
am33xx_pin_mode,
am33xx_pin_write,
am33xx_pin_read,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
int rt_hw_gpio_init(void)

2
bsp/efm32/copy_this_file_shell.c
View File

@ -88,7 +88,7 @@ int isprint(unsigned char ch)
#if defined(RT_USING_DFS) && defined(DFS_USING_WORKDIR)
#include <dfs_posix.h>
const char* finsh_get_prompt()
const char* finsh_get_prompt(void)
{
#define _PROMPT "finsh "
static char finsh_prompt[RT_CONSOLEBUF_SIZE + 1] = {_PROMPT};

1
bsp/efm32/rtconfig.h
View File

@ -213,6 +213,7 @@
/* SECTION: Runtime library */
// #define RT_USING_NOLIBC
// #define RT_USING_NEWLIB
#define RT_LIBC_USING_TIME
/* SECTION: Console options */
#define RT_USING_CONSOLE

7
bsp/fh8620/drivers/pwm.c
View File

@ -29,6 +29,7 @@
#include "interrupt.h"
#include "board_info.h"
#include "inc/fh_driverlib.h"
#include <rtthread.h>
#include <rtdevice.h>
#ifdef FH_PWM_DEBUG
#define PRINT_PWM_DBG(fmt, args...) \
@ -185,12 +186,12 @@ int fh_pwm_probe(void *priv_data)
PWM_Enable(pwm_obj, RT_FALSE);
pwm_dev = rt_malloc(sizeof(struct rt_device));
rt_memset(pwm_dev, 0, sizeof(struct rt_device));
pwm_dev = rt_calloc(1,sizeof(struct rt_device));
if (pwm_dev == RT_NULL)
{
rt_kprintf("ERROR: %s rt_device malloc failed\n", __func__);
rt_kprintf("ERROR: %s rt_device calloc failed\n", __func__);
return -RT_ENOMEM;
}
pwm_dev->user_data = &pwm_drv;

1
bsp/gd32303e-eval/drivers/drv_gpio.c
View File

@ -497,6 +497,7 @@ const static struct rt_pin_ops _gd32_pin_ops =
gd32_pin_attach_irq,
gd32_pin_detach_irq,
gd32_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

5
bsp/gd32450z-eval/drivers/drv_enet.c
View File

@ -652,7 +652,10 @@ int rt_hw_gd32_eth_init(void)
/* init tx buffer free semaphore */
rt_sem_init(&gd32_emac_device0.tx_buf_free, "tx_buf0", EMAC_TXBUFNB, RT_IPC_FLAG_FIFO);
eth_device_init(&(gd32_emac_device0.parent), "e0");
/* change device link status */
eth_device_linkchange(&(gd32_emac_device0.parent), RT_TRUE);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_gd32_eth_init);

2
bsp/gd32450z-eval/drivers/drv_spi.c
View File

@ -130,7 +130,7 @@ static rt_err_t configure(struct rt_spi_device* device,
}
} /* baudrate */
switch(configuration->mode)
switch(configuration->mode & RT_SPI_MODE_3)
{
case RT_SPI_MODE_0:
spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;

2
bsp/gd32450z-eval/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/hifive1/drivers/interrupt.c
View File

@ -93,7 +93,7 @@ void rt_hw_interrupt_init(void)
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
{
return (rt_uint32_t)PLIC_claim_interrupt(&g_plic);;
return (rt_uint32_t)PLIC_claim_interrupt(&g_plic);
}
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)

2
bsp/imx6sx/cortex-a9/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/imx6sx/iMX6_Platform_SDK/sdk/drivers/audio/src/snd_card.c
View File

@ -125,7 +125,7 @@ static int32_t snd_card_config(void *priv, audio_dev_para_p para)
return -2;
}
//Set the parameters for codec according para
//if audio controller is mater, the codec should be slave.
//if audio controller is master, the codec should be slave.
if (AUDIO_BUS_MODE_MASTER == para->bus_mode)
para->bus_mode = AUDIO_BUS_MODE_SLAVE;
else if (AUDIO_BUS_MODE_SLAVE == para->bus_mode)

2
bsp/imx6ul/rtconfig.h
View File

@ -63,7 +63,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x30105
#define ARCH_ARM
/* RT_USING_CPU_FFS is not set */
#define ARCH_ARM_CORTEX_A

2
bsp/imxrt/imxrt1052-atk-commander/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/imxrt/imxrt1052-fire-pro/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

6
bsp/imxrt/libraries/drivers/SConscript
View File

@ -1,8 +1,10 @@
from building import *
cwd = GetCurrentDir()
src = []
cwd = []
CPPDEFINES = []
cwd = GetCurrentDir()
if GetDepend('BSP_USING_GPIO'):
src += ['drv_gpio.c']

6
bsp/imxrt/libraries/drivers/drv_can.h
View File

@ -8,9 +8,9 @@
* 2019-06-28 misonyo the first version.
*/
#ifndef DRV_SPI_H__
#define DRV_SPI_H__
#ifndef DRV_CAN_H__
#define DRV_CAN_H__
int rt_hw_can_init(void);
#endif /* DRV_SPI_H__ */
#endif /* DRV_CAN_H__ */

6
bsp/imxrt/libraries/drivers/drv_gpio.c
View File

@ -559,6 +559,9 @@ static rt_err_t imxrt_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt
case PIN_IRQ_MODE_LOW_LEVEL:
int_mode = kGPIO_IntLowLevel;
break;
default:
int_mode = kGPIO_IntRisingEdge;
break;
}
irq_index = (port << 1) + (pin_num >> 4);
GPIO_PinSetInterruptConfig(mask_tab[port].gpio, pin_num, int_mode);
@ -584,7 +587,8 @@ const static struct rt_pin_ops imxrt_pin_ops =
imxrt_pin_read,
imxrt_pin_attach_irq,
imxrt_pin_detach_irq,
imxrt_pin_irq_enable
imxrt_pin_irq_enable,
RT_NULL,
};
int rt_hw_pin_init(void)

2
bsp/imxrt/libraries/templates/imxrt1050xxx/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40001
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/imxrt/libraries/templates/imxrt1064xxx/rtconfig.h
View File

@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40001
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

12
bsp/lpc176x/drivers/sd.c
View File

@ -32,7 +32,7 @@ static uint8_t LPC17xx_SD_SendCmd(uint8_t cmd, uint32_t arg);
static bool LPC17xx_SD_ReadSector(uint32_t sector, uint8_t *buff, uint32_t count);
static bool LPC17xx_SD_ReadDataBlock(uint8_t *buff, uint32_t cnt);
static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_t count);
static bool LPC17xx_SD_WirteDataBlock(const uint8_t *buff, uint8_t token);
static bool LPC17xx_SD_WriteDataBlock(const uint8_t *buff, uint8_t token);
static bool LPC17xx_SD_ReadCfg(SDCFG *cfg);
static bool LPC17xx_SD_WaitForReady(void);
@ -155,7 +155,7 @@ static bool LPC17xx_SD_Init(void)
Send a Command to Flash card and get a Response
cmd: cmd index
arg: argument for the cmd
return the received response of the commond
return the received response of the command
*****************************************************************************/
static uint8_t LPC17xx_SD_SendCmd(uint8_t cmd, uint32_t arg)
{
@ -279,7 +279,7 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_
if (count == 1) /* Single block write */
{
if ((LPC17xx_SD_SendCmd(WRITE_BLOCK, sector) == 0)
&& LPC17xx_SD_WirteDataBlock(buff, TOKEN_SINGLE_BLOCK))
&& LPC17xx_SD_WriteDataBlock(buff, TOKEN_SINGLE_BLOCK))
count = 0;
}
else /* Multiple block write */
@ -289,12 +289,12 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_
{
do
{
if (!LPC17xx_SD_WirteDataBlock(buff, TOKEN_MULTI_BLOCK)) break;
if (!LPC17xx_SD_WriteDataBlock(buff, TOKEN_MULTI_BLOCK)) break;
buff += 512;
}
while (--count);
#if 1
if (!LPC17xx_SD_WirteDataBlock(0, TOKEN_STOP_TRAN)) /* STOP_TRAN token */
if (!LPC17xx_SD_WriteDataBlock(0, TOKEN_STOP_TRAN)) /* STOP_TRAN token */
count = 1;
#else
LPC17xx_SPI_SendByte(TOKEN_STOP_TRAN);
@ -312,7 +312,7 @@ static bool LPC17xx_SD_WriteSector(uint32_t sector, const uint8_t *buff, uint32_
0xFC -> multi block
0xFD -> Stop
*****************************************************************************/
static bool LPC17xx_SD_WirteDataBlock(const uint8_t *buff, uint8_t token)
static bool LPC17xx_SD_WriteDataBlock(const uint8_t *buff, uint8_t token)
{
uint8_t resp, i;

4
bsp/lpc408x/rtconfig.h
View File

@ -40,8 +40,9 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40001
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
@ -109,6 +110,7 @@
/* POSIX layer and C standard library */
#define RT_LIBC_USING_TIME
/* Network */

5
bsp/lpc43xx/M0/applications/vbus_hw.h
View File

@ -7,6 +7,9 @@
* 2015-01-07 Grissiom init commit
*/
#ifndef __VBUS_HW_H__
#define __VBUS_HW_H__
#include <rtthread.h>
#include <board.h>
@ -32,3 +35,5 @@ rt_inline void rt_vbus_smp_mb(void)
{
__DSB();
}
#endif /* __VBUS_HW_H__ */

5
bsp/lpc43xx/M4/applications/vbus_hw.h
View File

@ -7,6 +7,9 @@
* 2015-01-07 Grissiom init commit
*/
#ifndef __VBUS_HW_H__
#define __VBUS_HW_H__
#include <rtthread.h>
#include <board.h>
@ -32,3 +35,5 @@ rt_inline void rt_vbus_smp_mb(void)
{
__DSB();
}
#endif /* __VBUS_HW_H__ */

2
bsp/lpc54114-lite/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4

2
bsp/lpc54608-LPCXpresso/rtconfig.h
View File

@ -43,7 +43,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40002
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M

2
bsp/nrf52832/rtconfig.h
View File

@ -41,7 +41,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/nuvoton_m05x/rtconfig.h
View File

@ -38,7 +38,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

2
bsp/nuvoton_m487/rtconfig.h
View File

@ -37,7 +37,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

4
bsp/qemu-vexpress-a9/applications/SConscript
View File

@ -1,10 +1,8 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)

10
bsp/qemu-vexpress-a9/applications/lcd_init.c
View File

@ -1,3 +1,13 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/12/31 Bernard Add license info
*/
#include <rtthread.h>
#if defined(RT_USING_RTGUI) || defined(PKG_USING_GUIENGINE)

10
bsp/qemu-vexpress-a9/applications/main.c
View File

@ -1,3 +1,13 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/12/31 Bernard Add license info
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>

10
bsp/qemu-vexpress-a9/applications/mnt.c
View File

@ -1,3 +1,13 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020/12/31 Bernard Add license info
*/
#include <rtthread.h>
#ifdef RT_USING_DFS

18
bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_ac97.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

18
bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_ac97.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes

96
bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c
View File

@ -1,21 +1,7 @@
/*
* File : drv_pl041.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -36,7 +22,7 @@
#include <rtdbg.h>
#define FRAME_PERIOD_US (50)
#define PL041_CHANNLE_NUM (4)
#define PL041_CHANNEL_NUM (4)
#define PL041_READ(_a) (*(volatile rt_uint32_t *)(_a))
#define PL041_WRITE(_a, _v) (*(volatile rt_uint32_t *)(_a) = (_v))
@ -47,7 +33,7 @@ struct pl041_irq_def
void *user_data;
};
static struct pl041_irq_def irq_tbl[PL041_CHANNLE_NUM];
static struct pl041_irq_def irq_tbl[PL041_CHANNEL_NUM];
static void aaci_pl041_delay(rt_uint32_t us)
{
@ -169,13 +155,13 @@ rt_uint16_t aaci_ac97_read(rt_uint16_t reg)
return v;
}
int aaci_pl041_channle_disable(int channle)
int aaci_pl041_channel_disable(int channel)
{
rt_uint32_t v;
void *p_rx, *p_tx;
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
v = PL041_READ(p_rx);
v &= ~AACI_CR_EN;
PL041_WRITE(p_rx, v);
@ -185,13 +171,13 @@ int aaci_pl041_channle_disable(int channle)
return 0;
}
int aaci_pl041_channle_enable(int channle)
int aaci_pl041_channel_enable(int channel)
{
rt_uint32_t v;
void *p_rx, *p_tx;
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
v = PL041_READ(p_rx);
v |= AACI_CR_EN;
PL041_WRITE(p_rx, v);
@ -201,13 +187,13 @@ int aaci_pl041_channle_enable(int channle)
return 0;
}
int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count)
{
void *p_data, *p_status;
int i = 0;
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
for (i = 0; (!(PL041_READ(p_status) & AACI_SR_RXFE)) && (i < count); i++)
{
buff[i] = (rt_uint16_t)PL041_READ(p_data);
@ -215,13 +201,13 @@ int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
return i;
}
int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count)
{
void *p_data, *p_status;
int i = 0;
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channel * 0x20);
for (i = 0; (!(PL041_READ(p_status) & AACI_SR_TXFF)) && (i < count); i++)
{
PL041_WRITE(p_data, buff[i]);
@ -229,13 +215,13 @@ int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
return i;
}
int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cgf)
{
rt_uint32_t v;
void *p_rx, *p_tx;
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channel * 0x14);
p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channel * 0x14);
v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->itype;
PL041_WRITE(p_rx, v);
v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->otype;
@ -247,86 +233,86 @@ int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
return 0;
}
void aaci_pl041_irq_enable(int channle, rt_uint32_t vector)
void aaci_pl041_irq_enable(int channel, rt_uint32_t vector)
{
rt_uint32_t v;
void *p_irq;
vector &= vector & 0x7f;
p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
v = PL041_READ(p_irq);
v |= vector;
PL041_WRITE(p_irq, v);
}
void aaci_pl041_irq_disable(int channle, rt_uint32_t vector)
void aaci_pl041_irq_disable(int channel, rt_uint32_t vector)
{
rt_uint32_t v;
void *p_irq;
vector &= vector & 0x7f;
p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channel * 0x14);
v = PL041_READ(p_irq);
v &= ~vector;
PL041_WRITE(p_irq, v);
}
rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data)
rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data)
{
if (channle < 0 || channle >= PL041_CHANNLE_NUM)
if (channel < 0 || channel >= PL041_CHANNEL_NUM)
{
LOG_E("%s channle:%d err.", __FUNCTION__, channle);
LOG_E("%s channel:%d err.", __FUNCTION__, channel);
return -RT_ERROR;
}
irq_tbl[channle].fun = fun;
irq_tbl[channle].user_data = user_data;
irq_tbl[channel].fun = fun;
irq_tbl[channel].user_data = user_data;
return RT_EOK;
}
rt_err_t aaci_pl041_irq_unregister(int channle)
rt_err_t aaci_pl041_irq_unregister(int channel)
{
if (channle < 0 || channle >= PL041_CHANNLE_NUM)
if (channel < 0 || channel >= PL041_CHANNEL_NUM)
{
LOG_E("%s channle:%d err.", __FUNCTION__, channle);
LOG_E("%s channel:%d err.", __FUNCTION__, channel);
return -RT_ERROR;
}
irq_tbl[channle].fun = RT_NULL;
irq_tbl[channle].user_data = RT_NULL;
irq_tbl[channel].fun = RT_NULL;
irq_tbl[channel].user_data = RT_NULL;
return RT_EOK;
}
static void aaci_pl041_irq_handle(int irqno, void *param)
{
rt_uint32_t mask, channle, m;
rt_uint32_t mask, channel, m;
struct pl041_irq_def *_irq = param;
void *p_status;
mask = PL041_READ(&PL041->allints);
PL041_WRITE(&PL041->intclr, mask);
for (channle = 0; (channle < PL041_CHANNLE_NUM) && (mask); channle++)
for (channel = 0; (channel < PL041_CHANNEL_NUM) && (mask); channel++)
{
mask = mask >> 7;
m = mask & 0x7f;
if (m & AACI_ISR_ORINTR)
{
LOG_W("RX overrun on chan %d", channle);
LOG_W("RX overrun on chan %d", channel);
}
if (m & AACI_ISR_RXTOINTR)
{
LOG_W("RX timeout on chan %d", channle);
LOG_W("RX timeout on chan %d", channel);
}
if (mask & AACI_ISR_URINTR)
{
LOG_W("TX underrun on chan %d", channle);
LOG_W("TX underrun on chan %d", channel);
}
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
if (_irq[channle].fun != RT_NULL)
p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channel * 0x14);
if (_irq[channel].fun != RT_NULL)
{
_irq[channle].fun(PL041_READ(p_status), _irq[channle].user_data);
_irq[channel].fun(PL041_READ(p_status), _irq[channel].user_data);
}
}
}

44
bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h
View File

@ -1,21 +1,7 @@
/*
* File : drv_pl041.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
@ -158,10 +144,10 @@
#define MAINFR_TXB (1 << 1) /* transmit busy */
#define MAINFR_RXB (1 << 0) /* receive busy */
#define PL041_CHANNLE_LEFT_DAC (0x1 << 3)
#define PL041_CHANNLE_RIGHT_DAC (0x1 << 3)
#define PL041_CHANNLE_LEFT_ADC (0x1 << 3)
#define PL041_CHANNLE_RIGHT_ADC (0x1 << 3)
#define PL041_CHANNEL_LEFT_DAC (0x1 << 3)
#define PL041_CHANNEL_RIGHT_DAC (0x1 << 3)
#define PL041_CHANNEL_LEFT_ADC (0x1 << 3)
#define PL041_CHANNEL_RIGHT_ADC (0x1 << 3)
struct reg_pl041
{
@ -225,13 +211,13 @@ typedef void (*pl041_irq_fun_t)(rt_uint32_t status, void * user_data);
rt_err_t aaci_pl041_init(void);
void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val);
rt_uint16_t aaci_ac97_read(rt_uint16_t reg);
int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cfg);
int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count);
int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count);
int aaci_pl041_channle_enable(int channle);
int aaci_pl041_channle_disable(int channle);
rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data);
rt_err_t aaci_pl041_irq_unregister(int channle);
void aaci_pl041_irq_disable(int channle, rt_uint32_t vector);
void aaci_pl041_irq_enable(int channle, rt_uint32_t vector);
int aaci_pl041_channel_cfg(int channel, pl041_cfg_t cfg);
int aaci_pl041_channel_write(int channel, rt_uint16_t *buff, int count);
int aaci_pl041_channel_read(int channel, rt_uint16_t *buff, int count);
int aaci_pl041_channel_enable(int channel);
int aaci_pl041_channel_disable(int channel);
rt_err_t aaci_pl041_irq_register(int channel, pl041_irq_fun_t fun, void *user_data);
rt_err_t aaci_pl041_irq_unregister(int channel);
void aaci_pl041_irq_disable(int channel, rt_uint32_t vector);
void aaci_pl041_irq_enable(int channel, rt_uint32_t vector);
#endif

12
bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c
View File

@ -227,13 +227,13 @@ static rt_err_t sound_init(struct rt_audio_device *audio)
aaci_pl041_init();
_cfg.itype = PL041_CHANNLE_LEFT_ADC | PL041_CHANNLE_RIGHT_ADC;
_cfg.otype = PL041_CHANNLE_LEFT_DAC | PL041_CHANNLE_RIGHT_DAC;
_cfg.itype = PL041_CHANNEL_LEFT_ADC | PL041_CHANNEL_RIGHT_ADC;
_cfg.otype = PL041_CHANNEL_LEFT_DAC | PL041_CHANNEL_RIGHT_DAC;
_cfg.vol = snd_dev->volume;
_cfg.rate = snd_dev->replay_config.samplerate;
ac97_reset();
aaci_pl041_channle_cfg(0, &_cfg);
aaci_pl041_channel_cfg(0, &_cfg);
aaci_pl041_irq_register(0, rt_hw_aaci_isr, RT_NULL);
return result;
@ -246,7 +246,7 @@ static rt_err_t sound_start(struct rt_audio_device *audio, int stream)
if (stream == AUDIO_STREAM_REPLAY)
{
LOG_D("open sound device");
aaci_pl041_channle_enable(0);
aaci_pl041_channel_enable(0);
aaci_pl041_irq_enable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
}
@ -263,7 +263,7 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
rt_thread_mdelay(100);
/* disable irq and channels 0 */
aaci_pl041_irq_disable(0, AACI_IE_UR | AACI_IE_TX | AACI_IE_TXC);
aaci_pl041_channle_disable(0);
aaci_pl041_channel_disable(0);
LOG_D("close sound device");
}
@ -295,7 +295,7 @@ static rt_size_t sound_transmit(struct rt_audio_device *audio, const void *write
RT_ASSERT(audio != RT_NULL);
/* write data to channel_0 fifo */
aaci_pl041_channle_write(0, (rt_uint16_t *)writeBuf, size >> 1);
aaci_pl041_channel_write(0, (rt_uint16_t *)writeBuf, size >> 1);
return size;
}

2
bsp/qemu-vexpress-a9/rtconfig.h
View File

@ -47,7 +47,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define ARCH_ARM_CORTEX_A
#define ARCH_ARM_CORTEX_A9

2
bsp/simulator/SConstruct
View File

@ -95,7 +95,7 @@ if GetDepend('RT_USING_MODULE'):
dest='def',
action='store_true',
default=False,
help='create rthread.def of rtthread.dll on windows')
help='create rtthread.def of rtthread.dll on windows')
if GetOption('def'):
if rtconfig.PLATFORM == 'mingw':
env['LINKFLAGS'] = rtconfig.DEFFILE_LFLAGS

2
bsp/simulator/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "console"
#define RT_VER_NUM 0x30104
#define RT_VER_NUM 0x30105
/* RT-Thread Components */

8
bsp/stm32/libraries/HAL_Drivers/SConscript
View File

@ -55,6 +55,9 @@ if GetDepend('BSP_USING_LCD_MIPI'):
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32G0']):
src += ['drv_flash/drv_flash_g0.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
src += ['drv_flash/drv_flash_f0.c']
@ -73,6 +76,8 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
src += ['drv_flash/drv_flash_l4.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
src += ['drv_flash/drv_flash_h7.c']
if GetDepend('RT_USING_HWCRYPTO'):
src += ['drv_crypto.c']
@ -88,6 +93,9 @@ if GetDepend(['BSP_USING_USBD']):
if GetDepend(['BSP_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c']
if GetDepend(['BSP_USING_USBH']):
src += ['drv_usbh.c']
src += ['drv_common.c']
path = [cwd]

11
bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h
View File

@ -17,6 +17,17 @@
extern "C" {
#endif
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.tim_handle.Instance = TIM1, \
.name = "pwm1", \
.channel = 0 \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \

24
bsp/stm32/libraries/HAL_Drivers/config/f4/dma_config.h
View File

@ -157,12 +157,12 @@ extern "C" {
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream0
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_TX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
@ -208,12 +208,12 @@ extern "C" {
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream3
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */

11
bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h
View File

@ -61,6 +61,17 @@ extern "C" {
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM9
#ifndef PWM9_CONFIG
#define PWM9_CONFIG \
{ \
.tim_handle.Instance = TIM9, \
.name = "pwm9", \
.channel = 0 \
}
#endif /* PWM9_CONFIG */
#endif /* BSP_USING_PWM9 */
#ifdef BSP_USING_PWM12
#ifndef PWM12_CONFIG
#define PWM12_CONFIG \

11
bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h
View File

@ -27,6 +27,17 @@ extern "C" {
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CONFIG
#define TIM3_CONFIG \
{ \
.tim_handle.Instance = TIM3, \
.tim_irqn = TIM3_IRQn, \
.name = "timer3", \
}
#endif /* TIM3_CONFIG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM11
#ifndef TIM11_CONFIG
#define TIM11_CONFIG \

96
bsp/stm32/libraries/HAL_Drivers/config/h7/adc_config.h
View File

@ -19,63 +19,69 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.Instance = ADC1, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
#define ADC1_CONFIG \
{ \
.Instance = ADC1, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_16B, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
.Init.OversamplingMode = DISABLE, \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.Instance = ADC2, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
#define ADC2_CONFIG \
{ \
.Instance = ADC2, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_16B, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
.Init.OversamplingMode = DISABLE, \
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.Instance = ADC3, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_12B, \
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
.Init.ScanConvMode = DISABLE, \
.Init.EOCSelection = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 0, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.DMAContinuousRequests = DISABLE, \
#define ADC3_CONFIG \
{ \
.Instance = ADC3, \
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
.Init.Resolution = ADC_RESOLUTION_16B, \
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
.Init.LowPowerAutoWait = DISABLE, \
.Init.ContinuousConvMode = DISABLE, \
.Init.NbrOfConversion = 1, \
.Init.DiscontinuousConvMode = DISABLE, \
.Init.NbrOfDiscConversion = 1, \
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
.Init.OversamplingMode = DISABLE, \
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */

90
bsp/stm32/libraries/HAL_Drivers/config/h7/dma_config.h
View File

@ -19,27 +19,21 @@ extern "C" {
#endif
/* DMA1 stream0 */
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define SPI3_RX_DMA_INSTANCE DMA1_Stream0
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream0_IRQn
#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART5_RX_DMA_INSTANCE DMA1_Stream0
#define UART5_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART5_RX_DMA_IRQ DMA1_Stream0_IRQn
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream0
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
#endif
/* DMA1 stream1 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_DMA_RX_IRQHandler DMA1_Stream1_IRQHandler
#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART3_RX_DMA_INSTANCE DMA1_Stream1
#define UART3_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART3_RX_DMA_IRQ DMA1_Stream1_IRQn
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_TX_DMA_INSTANCE DMA1_Stream1
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
#endif
/* DMA1 stream2 */
@ -49,12 +43,6 @@ extern "C" {
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
#define SPI3_RX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART4_RX_DMA_INSTANCE DMA1_Stream2
#define UART4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART4_RX_DMA_IRQ DMA1_Stream2_IRQn
#endif
/* DMA1 stream3 */
@ -83,12 +71,6 @@ extern "C" {
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
#define SPI3_TX_DMA_CHANNEL DMA_CHANNEL_0
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_DMA_RX_IRQHandler DMA1_Stream5_IRQHandler
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
#define UART2_RX_DMA_INSTANCE DMA1_Stream5
#define UART2_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART2_RX_DMA_IRQ DMA1_Stream5_IRQn
#endif
/* DMA1 stream6 */
@ -109,12 +91,6 @@ extern "C" {
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_4
#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
#endif
/* DMA2 stream1 */
@ -133,18 +109,6 @@ extern "C" {
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Stream2
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
#define QSPI_DMA_INSTANCE DMA2_Stream2
#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
#endif
/* DMA2 stream3 */
@ -154,18 +118,6 @@ extern "C" {
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI1_TX_DMA_INSTANCE DMA2_Stream3
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream3_IRQn
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
#define SPI4_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
#define SPI4_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_RX_DMA_INSTANCE DMA2_Stream3
#define SPI4_RX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_RX_DMA_IRQ DMA2_Stream3_IRQn
#endif
/* DMA2 stream4 */
@ -175,12 +127,6 @@ extern "C" {
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
#define SPI5_TX_DMA_CHANNEL DMA_CHANNEL_2
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
#define SPI4_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI4_TX_DMA_INSTANCE DMA2_Stream4
#define SPI4_TX_DMA_CHANNEL DMA_CHANNEL_5
#define SPI4_TX_DMA_IRQ DMA2_Stream4_IRQn
#endif
/* DMA2 stream5 */
@ -190,18 +136,6 @@ extern "C" {
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define UART1_RX_DMA_INSTANCE DMA2_Stream5
#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
#define SPI5_RX_DMA_INSTANCE DMA2_Stream5
#define SPI5_RX_DMA_CHANNEL DMA_CHANNEL_7
#define SPI5_RX_DMA_IRQ DMA2_Stream5_IRQn
#endif
/* DMA2 stream6 */

63
bsp/stm32/libraries/HAL_Drivers/config/h7/uart_config.h
View File

@ -31,12 +31,12 @@ extern "C" {
#if defined(BSP_UART1_RX_USING_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
#define UART1_DMA_RX_CONFIG \
{ \
.Instance = UART1_RX_DMA_INSTANCE, \
.channel = UART1_RX_DMA_CHANNEL, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
.Instance = UART1_RX_DMA_INSTANCE, \
.request = UART1_RX_DMA_REQUEST, \
.dma_rcc = UART1_RX_DMA_RCC, \
.dma_irq = UART1_RX_DMA_IRQ, \
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
@ -54,16 +54,27 @@ extern "C" {
#if defined(BSP_UART2_RX_USING_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
#define UART2_DMA_RX_CONFIG \
{ \
.Instance = UART2_RX_DMA_INSTANCE, \
.channel = UART2_RX_DMA_CHANNEL, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
.Instance = UART2_RX_DMA_INSTANCE, \
.request = UART2_RX_DMA_REQUEST, \
.dma_rcc = UART2_RX_DMA_RCC, \
.dma_irq = UART2_RX_DMA_IRQ, \
}
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.request = UART2_TX_DMA_REQUEST, \
.dma_rcc = UART2_TX_DMA_RCC, \
.dma_irq = UART2_TX_DMA_IRQ, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
@ -77,12 +88,12 @@ extern "C" {
#if defined(BSP_UART3_RX_USING_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
#define UART3_DMA_RX_CONFIG \
{ \
.Instance = UART3_RX_DMA_INSTANCE, \
.channel = UART3_RX_DMA_CHANNEL, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
.Instance = UART3_RX_DMA_INSTANCE, \
.request = UART3_RX_DMA_REQUEST, \
.dma_rcc = UART3_RX_DMA_RCC, \
.dma_irq = UART3_RX_DMA_IRQ, \
}
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
@ -100,12 +111,12 @@ extern "C" {
#if defined(BSP_UART4_RX_USING_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
#define UART4_DMA_RX_CONFIG \
{ \
.Instance = UART4_RX_DMA_INSTANCE, \
.channel = UART4_RX_DMA_CHANNEL, \
.dma_rcc = UART4_RX_DMA_RCC, \
.dma_irq = UART4_RX_DMA_IRQ, \
.Instance = UART4_RX_DMA_INSTANCE, \
.request = UART4_RX_DMA_REQUEST, \
.dma_rcc = UART4_RX_DMA_RCC, \
.dma_irq = UART4_RX_DMA_IRQ, \
}
#endif /* UART4_DMA_RX_CONFIG */
#endif /* BSP_UART4_RX_USING_DMA */
@ -123,12 +134,12 @@ extern "C" {
#if defined(BSP_UART5_RX_USING_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
#define UART5_DMA_RX_CONFIG \
{ \
.Instance = UART5_RX_DMA_INSTANCE, \
.channel = UART5_RX_DMA_CHANNEL, \
.dma_rcc = UART5_RX_DMA_RCC, \
.dma_irq = UART5_RX_DMA_IRQ, \
.Instance = UART5_RX_DMA_INSTANCE, \
.request = UART5_RX_DMA_REQUEST, \
.dma_rcc = UART5_RX_DMA_RCC, \
.dma_irq = UART5_RX_DMA_IRQ, \
}
#endif /* UART5_DMA_RX_CONFIG */
#endif /* BSP_UART5_RX_USING_DMA */

38
bsp/stm32/libraries/HAL_Drivers/config/l4/uart_config.h
View File

@ -61,7 +61,19 @@ extern "C" {
}
#endif /* UART1_DMA_RX_CONFIG */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.Instance = UART1_TX_DMA_INSTANCE, \
.request = UART1_TX_DMA_REQUEST, \
.dma_rcc = UART1_TX_DMA_RCC, \
.dma_irq = UART1_TX_DMA_IRQ, \
}
#endif /* UART1_DMA_TX_CONFIG */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
@ -85,6 +97,18 @@ extern "C" {
#endif /* UART2_DMA_RX_CONFIG */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.Instance = UART2_TX_DMA_INSTANCE, \
.request = UART2_TX_DMA_REQUEST, \
.dma_rcc = UART2_TX_DMA_RCC, \
.dma_irq = UART2_TX_DMA_IRQ, \
}
#endif /* UART2_DMA_TX_CONFIG */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
@ -108,6 +132,18 @@ extern "C" {
#endif /* UART3_DMA_RX_CONFIG */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.Instance = UART3_TX_DMA_INSTANCE, \
.request = UART3_TX_DMA_REQUEST, \
.dma_rcc = UART3_TX_DMA_RCC, \
.dma_irq = UART3_TX_DMA_IRQ, \
}
#endif /* UART3_DMA_TX_CONFIG */
#endif /* BSP_UART3_TX_USING_DMA */
#ifdef __cplusplus
}
#endif

23
bsp/stm32/libraries/HAL_Drivers/drv_can.c
View File

@ -59,6 +59,19 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
{CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 150)},
{CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 300)}
};
#elif defined (SOC_SERIES_STM32L4)/* APB1 80MHz(max) */
static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
{
{CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ | CAN_BS2_2TQ | 10)},
{CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_14TQ | CAN_BS2_5TQ | 5)},
{CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_7TQ | CAN_BS2_2TQ | 16)},
{CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 20)},
{CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 40)},
{CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 50)},
{CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 100)},
{CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 250)},
{CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_13TQ | CAN_BS2_2TQ | 500)}
};
#endif
#ifdef BSP_USING_CAN1
@ -688,9 +701,9 @@ void CAN1_SCE_IRQHandler(void)
drv_can1.device.status.ackerrcnt++;
if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
@ -806,11 +819,11 @@ void CAN2_SCE_IRQHandler(void)
break;
case RT_CAN_BUS_ACK_ERR:
drv_can2.device.status.ackerrcnt++;
if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK1))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK2))
rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:

8
bsp/stm32/libraries/HAL_Drivers/drv_common.c
View File

@ -102,10 +102,12 @@ void rt_hw_us_delay(rt_uint32_t us)
start = SysTick->VAL;
reload = SysTick->LOAD;
us_tick = SystemCoreClock / 1000000UL;
do {
do
{
now = SysTick->VAL;
delta = start > now ? start - now : reload + start - now;
} while(delta < us_tick * us);
delta = start >= now ? start - now : reload + start - now;
}
while (delta < us_tick * us);
}
/**

3
bsp/stm32/libraries/HAL_Drivers/drv_dma.h
View File

@ -35,7 +35,8 @@ struct dma_config {
rt_uint32_t channel;
#endif
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|| defined(SOC_SERIES_STM32H7)
rt_uint32_t request;
#endif
};

8
bsp/stm32/libraries/HAL_Drivers/drv_eth.c
View File

@ -19,7 +19,7 @@
/*
* Emac driver uses CubeMX tool to generate emac and phy's configuration,
* the configuration files can be found in CubeMX_Config floder.
* the configuration files can be found in CubeMX_Config folder.
*/
/* debug option */
@ -248,7 +248,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
/* Prepare transmit descriptors to give to DMA */
/* TODO Optimize data send speed*/
LOG_D("transmit frame lenth :%d", framelength);
LOG_D("transmit frame length :%d", framelength);
/* wait for unlocked */
while (EthHandle.Lock == HAL_LOCKED);
@ -411,11 +411,11 @@ static void phy_linkchange()
if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
{
rt_uint32_t SR;
rt_uint32_t SR = 0;
phy_speed_new |= PHY_LINK;
SR = HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
LOG_D("phy control status reg is 0x%X", SR);
if (PHY_Status_SPEED_100M(SR))

80
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f1.c
View File

@ -122,16 +122,17 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
}
/**
* Erase data on flash.
* Erase data on flash with bank.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param bank flash bank
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
uint32_t PAGEError = 0;
@ -151,7 +152,8 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
EraseInitStruct.Banks = bank;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
@ -170,6 +172,78 @@ __exit:
return size;
}
/**
* Erase data on flash .
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
#if defined(FLASH_BANK2_END)
rt_err_t result = RT_EOK;
rt_uint32_t addr_bank1 = 0;
rt_uint32_t size_bank1 = 0;
rt_uint32_t addr_bank2 = 0;
rt_uint32_t size_bank2 = 0;
if((addr + size) <= FLASH_BANK1_END)
{
addr_bank1 = addr;
size_bank1 = size;
size_bank2 = 0;
}
else if(addr > FLASH_BANK1_END)
{
size_bank1 = 0;
addr_bank2 = addr;
size_bank2 = size;
}
else
{
addr_bank1 = addr;
size_bank1 = FLASH_BANK1_END + 1 - addr_bank1;
addr_bank2 = FLASH_BANK1_END + 1;
size_bank2 = addr + size - (FLASH_BANK1_END + 1);
}
if(size_bank1)
{
LOG_D("bank1: addr (0x%p), size %d", (void *)addr_bank1, size_bank1);
if(size_bank1 != stm32_flash_erase_bank(FLASH_BANK_1, addr_bank1, size_bank1))
{
result = -RT_ERROR;
goto __exit;
}
}
if(size_bank2)
{
LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
if(size_bank2 != stm32_flash_erase_bank(FLASH_BANK_2, addr_bank2, size_bank2))
{
result = -RT_ERROR;
goto __exit;
}
}
__exit:
if(result != RT_EOK)
{
return result;
}
return size_bank1 + size_bank2;
#else
return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
#endif
}
#if defined(PKG_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);

58
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c
View File

@ -211,6 +211,8 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
rt_uint32_t written_size = 0;
rt_uint32_t write_size = 0;
if ((end_addr) > STM32_FLASH_END_ADDRESS)
{
@ -227,22 +229,61 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
for (size_t i = 0; i < size; i++, addr++, buf++)
while (written_size < size)
{
/* write data to flash */
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr, (rt_uint64_t)(*buf)) == HAL_OK)
if (((addr + written_size) % 4 == 0) && (size - written_size >= 4))
{
if (*(rt_uint8_t *)addr != *buf)
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr + written_size, *((rt_uint32_t *)(buf + written_size))) == HAL_OK)
{
if (*(rt_uint32_t *)(addr + written_size) != *(rt_uint32_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 4;
}
else if (((addr + written_size) % 2 == 0) && (size - written_size >= 2))
{
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_HALFWORD, addr + written_size, *((rt_uint16_t *)(buf + written_size))) == HAL_OK)
{
if (*(rt_uint16_t *)(addr + written_size) != *(rt_uint16_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 2;
}
else
{
result = -RT_ERROR;
break;
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr + written_size, *((rt_uint8_t *)(buf + written_size))) == HAL_OK)
{
if (*(rt_uint8_t *)(addr + written_size) != *(rt_uint8_t *)(buf + written_size))
{
result = -RT_ERROR;
break;
}
}
else
{
result = -RT_ERROR;
break;
}
write_size = 1;
}
written_size += write_size;
}
HAL_FLASH_Lock();
@ -277,6 +318,11 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
return -RT_EINVAL;
}
if (size < 1)
{
return -RT_EINVAL;
}
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;

224
bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c
View File

@ -7,6 +7,7 @@
* Date Author Notes
* 2018-12-5 SummerGift first version
* 2019-3-2 jinsheng add Macro judgment
* 2020-1-6 duminmin support single bank mode
*/
#include "board.h"
@ -22,32 +23,6 @@
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#if defined (FLASH_OPTCR_nDBANK)
#define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 16 Kbytes */
#define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08004000) /* Base address of Sector 1, 16 Kbytes */
#define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08008000) /* Base address of Sector 2, 16 Kbytes */
#define ADDR_FLASH_SECTOR_3 ((rt_uint32_t)0x0800C000) /* Base address of Sector 3, 16 Kbytes */
#define ADDR_FLASH_SECTOR_4 ((rt_uint32_t)0x08010000) /* Base address of Sector 4, 64 Kbytes */
#define ADDR_FLASH_SECTOR_5 ((rt_uint32_t)0x08020000) /* Base address of Sector 5, 128 Kbytes */
#define ADDR_FLASH_SECTOR_6 ((rt_uint32_t)0x08040000) /* Base address of Sector 6, 128 Kbytes */
#define ADDR_FLASH_SECTOR_7 ((rt_uint32_t)0x08060000) /* Base address of Sector 7, 128 Kbytes */
#define ADDR_FLASH_SECTOR_8 ((rt_uint32_t)0x08080000) /* Base address of Sector 8, 128 Kbytes */
#define ADDR_FLASH_SECTOR_9 ((rt_uint32_t)0x080A0000) /* Base address of Sector 9, 128 Kbytes */
#define ADDR_FLASH_SECTOR_10 ((rt_uint32_t)0x080C0000) /* Base address of Sector 10, 128 Kbytes */
#define ADDR_FLASH_SECTOR_11 ((rt_uint32_t)0x080E0000) /* Base address of Sector 11, 128 Kbytes */
#define ADDR_FLASH_SECTOR_12 ((rt_uint32_t)0x08100000) /* Base address of Sector 12, 16 Kbytes */
#define ADDR_FLASH_SECTOR_13 ((rt_uint32_t)0x08104000) /* Base address of Sector 13, 16 Kbytes */
#define ADDR_FLASH_SECTOR_14 ((rt_uint32_t)0x08108000) /* Base address of Sector 14, 16 Kbytes */
#define ADDR_FLASH_SECTOR_15 ((rt_uint32_t)0x0810C000) /* Base address of Sector 15, 16 Kbytes */
#define ADDR_FLASH_SECTOR_16 ((rt_uint32_t)0x08110000) /* Base address of Sector 16, 64 Kbytes */
#define ADDR_FLASH_SECTOR_17 ((rt_uint32_t)0x08120000) /* Base address of Sector 17, 128 Kbytes */
#define ADDR_FLASH_SECTOR_18 ((rt_uint32_t)0x08140000) /* Base address of Sector 18, 128 Kbytes */
#define ADDR_FLASH_SECTOR_19 ((rt_uint32_t)0x08160000) /* Base address of Sector 19, 128 Kbytes */
#define ADDR_FLASH_SECTOR_20 ((rt_uint32_t)0x08180000) /* Base address of Sector 20, 128 Kbytes */
#define ADDR_FLASH_SECTOR_21 ((rt_uint32_t)0x081A0000) /* Base address of Sector 21, 128 Kbytes */
#define ADDR_FLASH_SECTOR_22 ((rt_uint32_t)0x081C0000) /* Base address of Sector 22, 128 Kbytes */
#define ADDR_FLASH_SECTOR_23 ((rt_uint32_t)0x081E0000) /* Base address of Sector 23, 128 Kbytes */
#else
#define ADDR_FLASH_SECTOR_0 ((rt_uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */
#define ADDR_FLASH_SECTOR_1 ((rt_uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */
#define ADDR_FLASH_SECTOR_2 ((rt_uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */
@ -60,7 +35,6 @@
#define ADDR_FLASH_SECTOR_9 ((rt_uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */
#define ADDR_FLASH_SECTOR_10 ((rt_uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */
#define ADDR_FLASH_SECTOR_11 ((rt_uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */
#endif
/**
* @brief Gets the sector of a given address
* @param None
@ -68,8 +42,73 @@
*/
static rt_uint32_t GetSector(rt_uint32_t Address)
{
rt_uint32_t sector = 0;
uint32_t sector = 0;
#if defined (FLASH_OPTCR_nDBANK)
FLASH_OBProgramInitTypeDef OBInit;
uint32_t nbank = 0;
//get duel bank ability:nDBANK(Bit29)
HAL_FLASHEx_OBGetConfig(&OBInit);
nbank = ((OBInit.USERConfig & 0x20000000U) >> 29);
//1:single bank mode
if (1 == nbank)
{
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FLASH_SECTOR_0;
}
else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
{
sector = FLASH_SECTOR_1;
}
else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
{
sector = FLASH_SECTOR_2;
}
else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
{
sector = FLASH_SECTOR_3;
}
else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
{
sector = FLASH_SECTOR_4;
}
else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
{
sector = FLASH_SECTOR_5;
}
else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
{
sector = FLASH_SECTOR_6;
}
else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
{
sector = FLASH_SECTOR_7;
}
else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
{
sector = FLASH_SECTOR_8;
}
else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
{
sector = FLASH_SECTOR_9;
}
else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
{
sector = FLASH_SECTOR_10;
}
else
{
sector = FLASH_SECTOR_11;
}
}
else //0:dual bank mode
{
LOG_E("rtthread doesn't support duel bank mode yet!");
RT_ASSERT(0);
}
#else //no dual bank ability
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FLASH_SECTOR_0;
@ -78,7 +117,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_1;
}
#if (FLASH_SECTOR_TOTAL >= 4)
else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
{
sector = FLASH_SECTOR_2;
@ -87,7 +125,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_3;
}
#elif (FLASH_SECTOR_TOTAL >= 8)
else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
{
sector = FLASH_SECTOR_4;
@ -104,7 +141,6 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_7;
}
#elif (FLASH_SECTOR_TOTAL >= 24)
else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
{
sector = FLASH_SECTOR_8;
@ -117,130 +153,15 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
{
sector = FLASH_SECTOR_10;
}
else if ((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
else
{
sector = FLASH_SECTOR_11;
}
else if ((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
{
sector = FLASH_SECTOR_12;
}
else if ((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13))
{
sector = FLASH_SECTOR_13;
}
else if ((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14))
{
sector = FLASH_SECTOR_14;
}
else if ((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15))
{
sector = FLASH_SECTOR_15;
}
else if ((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16))
{
sector = FLASH_SECTOR_16;
}
else if ((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17))
{
sector = FLASH_SECTOR_17;
}
else if ((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18))
{
sector = FLASH_SECTOR_18;
}
else if ((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19))
{
sector = FLASH_SECTOR_19;
}
else if ((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20))
{
sector = FLASH_SECTOR_20;
}
else if ((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21))
{
sector = FLASH_SECTOR_21;
}
else if ((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22))
{
sector = FLASH_SECTOR_22;
}
#else
else
{
#if (FLASH_SECTOR_TOTAL == 4)
sector = FLASH_SECTOR_4;
#elif (FLASH_SECTOR_TOTAL == 8)
sector = FLASH_SECTOR_8;
#elif (FLASH_SECTOR_TOTAL == 24)
sector = FLASH_SECTOR_23;
#endif
}
#endif
#else
if ((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
{
sector = FLASH_SECTOR_0;
}
else if ((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
{
sector = FLASH_SECTOR_1;
}
#if (FLASH_SECTOR_TOTAL >= 4)
else if ((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
{
sector = FLASH_SECTOR_2;
}
else if ((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
{
sector = FLASH_SECTOR_3;
}
#elif (FLASH_SECTOR_TOTAL >= 8)
else if ((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
{
sector = FLASH_SECTOR_4;
}
else if ((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
{
sector = FLASH_SECTOR_5;
}
else if ((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
{
sector = FLASH_SECTOR_6;
}
else if ((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
{
sector = FLASH_SECTOR_7;
}
#elif (FLASH_SECTOR_TOTAL >= 24)
else if ((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
{
sector = FLASH_SECTOR_8;
}
else if ((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
{
sector = FLASH_SECTOR_9;
}
else if ((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
{
sector = FLASH_SECTOR_10;
}
#else
else
{
#if (FLASH_SECTOR_TOTAL == 4)
sector = FLASH_SECTOR_4;
#elif (FLASH_SECTOR_TOTAL == 8)
sector = FLASH_SECTOR_8;
#elif (FLASH_SECTOR_TOTAL == 24)
sector = FLASH_SECTOR_11;
#endif
}
#endif
#endif
return sector;
}
/**
* Read data from flash.
* @note This operation's units is word.
@ -386,6 +307,13 @@ __exit:
}
#if defined(PKG_USING_FAL)
#define FLASH_SIZE_GRANULARITY_32K (4 * 32 * 1024)
#define FLASH_SIZE_GRANULARITY_128K (128 * 1024)
#define FLASH_SIZE_GRANULARITY_256K (7 * 256 *1024)
#define STM32_FLASH_START_ADRESS_32K (STM32_FLASH_START_ADRESS)
#define STM32_FLASH_START_ADRESS_128K (STM32_FLASH_START_ADRESS_32K + FLASH_SIZE_GRANULARITY_32K)
#define STM32_FLASH_START_ADRESS_256K (STM32_FLASH_START_ADRESS_128K + FLASH_SIZE_GRANULARITY_128K)
static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_read_128k(long offset, rt_uint8_t *buf, size_t size);

404
bsp/stm32/libraries/HAL_Drivers/drv_gpio.c
View File

@ -7,6 +7,7 @@
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2019-04-23 WillianChan Fix GPIO serial number disorder
* 2020-09-18 geniusgogo optimization design pin-index algorithm
*/
#include <board.h>
@ -14,207 +15,43 @@
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
{
#if defined(GPIOA)
__STM32_PIN(0 , A, 0 ),
__STM32_PIN(1 , A, 1 ),
__STM32_PIN(2 , A, 2 ),
__STM32_PIN(3 , A, 3 ),
__STM32_PIN(4 , A, 4 ),
__STM32_PIN(5 , A, 5 ),
__STM32_PIN(6 , A, 6 ),
__STM32_PIN(7 , A, 7 ),
__STM32_PIN(8 , A, 8 ),
__STM32_PIN(9 , A, 9 ),
__STM32_PIN(10, A, 10),
__STM32_PIN(11, A, 11),
__STM32_PIN(12, A, 12),
__STM32_PIN(13, A, 13),
__STM32_PIN(14, A, 14),
__STM32_PIN(15, A, 15),
#if defined(GPIOB)
__STM32_PIN(16, B, 0),
__STM32_PIN(17, B, 1),
__STM32_PIN(18, B, 2),
__STM32_PIN(19, B, 3),
__STM32_PIN(20, B, 4),
__STM32_PIN(21, B, 5),
__STM32_PIN(22, B, 6),
__STM32_PIN(23, B, 7),
__STM32_PIN(24, B, 8),
__STM32_PIN(25, B, 9),
__STM32_PIN(26, B, 10),
__STM32_PIN(27, B, 11),
__STM32_PIN(28, B, 12),
__STM32_PIN(29, B, 13),
__STM32_PIN(30, B, 14),
__STM32_PIN(31, B, 15),
#if defined(GPIOC)
__STM32_PIN(32, C, 0),
__STM32_PIN(33, C, 1),
__STM32_PIN(34, C, 2),
__STM32_PIN(35, C, 3),
__STM32_PIN(36, C, 4),
__STM32_PIN(37, C, 5),
__STM32_PIN(38, C, 6),
__STM32_PIN(39, C, 7),
__STM32_PIN(40, C, 8),
__STM32_PIN(41, C, 9),
__STM32_PIN(42, C, 10),
__STM32_PIN(43, C, 11),
__STM32_PIN(44, C, 12),
__STM32_PIN(45, C, 13),
__STM32_PIN(46, C, 14),
__STM32_PIN(47, C, 15),
#if defined(GPIOD)
__STM32_PIN(48, D, 0),
__STM32_PIN(49, D, 1),
__STM32_PIN(50, D, 2),
__STM32_PIN(51, D, 3),
__STM32_PIN(52, D, 4),
__STM32_PIN(53, D, 5),
__STM32_PIN(54, D, 6),
__STM32_PIN(55, D, 7),
__STM32_PIN(56, D, 8),
__STM32_PIN(57, D, 9),
__STM32_PIN(58, D, 10),
__STM32_PIN(59, D, 11),
__STM32_PIN(60, D, 12),
__STM32_PIN(61, D, 13),
__STM32_PIN(62, D, 14),
__STM32_PIN(63, D, 15),
#if defined(GPIOE)
__STM32_PIN(64, E, 0),
__STM32_PIN(65, E, 1),
__STM32_PIN(66, E, 2),
__STM32_PIN(67, E, 3),
__STM32_PIN(68, E, 4),
__STM32_PIN(69, E, 5),
__STM32_PIN(70, E, 6),
__STM32_PIN(71, E, 7),
__STM32_PIN(72, E, 8),
__STM32_PIN(73, E, 9),
__STM32_PIN(74, E, 10),
__STM32_PIN(75, E, 11),
__STM32_PIN(76, E, 12),
__STM32_PIN(77, E, 13),
__STM32_PIN(78, E, 14),
__STM32_PIN(79, E, 15),
#if defined(GPIOF)
__STM32_PIN(80, F, 0),
__STM32_PIN(81, F, 1),
__STM32_PIN(82, F, 2),
__STM32_PIN(83, F, 3),
__STM32_PIN(84, F, 4),
__STM32_PIN(85, F, 5),
__STM32_PIN(86, F, 6),
__STM32_PIN(87, F, 7),
__STM32_PIN(88, F, 8),
__STM32_PIN(89, F, 9),
__STM32_PIN(90, F, 10),
__STM32_PIN(91, F, 11),
__STM32_PIN(92, F, 12),
__STM32_PIN(93, F, 13),
__STM32_PIN(94, F, 14),
__STM32_PIN(95, F, 15),
#if defined(GPIOG)
__STM32_PIN(96, G, 0),
__STM32_PIN(97, G, 1),
__STM32_PIN(98, G, 2),
__STM32_PIN(99, G, 3),
__STM32_PIN(100, G, 4),
__STM32_PIN(101, G, 5),
__STM32_PIN(102, G, 6),
__STM32_PIN(103, G, 7),
__STM32_PIN(104, G, 8),
__STM32_PIN(105, G, 9),
__STM32_PIN(106, G, 10),
__STM32_PIN(107, G, 11),
__STM32_PIN(108, G, 12),
__STM32_PIN(109, G, 13),
__STM32_PIN(110, G, 14),
__STM32_PIN(111, G, 15),
#if defined(GPIOH)
__STM32_PIN(112, H, 0),
__STM32_PIN(113, H, 1),
__STM32_PIN(114, H, 2),
__STM32_PIN(115, H, 3),
__STM32_PIN(116, H, 4),
__STM32_PIN(117, H, 5),
__STM32_PIN(118, H, 6),
__STM32_PIN(119, H, 7),
__STM32_PIN(120, H, 8),
__STM32_PIN(121, H, 9),
__STM32_PIN(122, H, 10),
__STM32_PIN(123, H, 11),
__STM32_PIN(124, H, 12),
__STM32_PIN(125, H, 13),
__STM32_PIN(126, H, 14),
__STM32_PIN(127, H, 15),
#if defined(GPIOI)
__STM32_PIN(128, I, 0),
__STM32_PIN(129, I, 1),
__STM32_PIN(130, I, 2),
__STM32_PIN(131, I, 3),
__STM32_PIN(132, I, 4),
__STM32_PIN(133, I, 5),
__STM32_PIN(134, I, 6),
__STM32_PIN(135, I, 7),
__STM32_PIN(136, I, 8),
__STM32_PIN(137, I, 9),
__STM32_PIN(138, I, 10),
__STM32_PIN(139, I, 11),
__STM32_PIN(140, I, 12),
__STM32_PIN(141, I, 13),
__STM32_PIN(142, I, 14),
__STM32_PIN(143, I, 15),
#if defined(GPIOJ)
__STM32_PIN(144, J, 0),
__STM32_PIN(145, J, 1),
__STM32_PIN(146, J, 2),
__STM32_PIN(147, J, 3),
__STM32_PIN(148, J, 4),
__STM32_PIN(149, J, 5),
__STM32_PIN(150, J, 6),
__STM32_PIN(151, J, 7),
__STM32_PIN(152, J, 8),
__STM32_PIN(153, J, 9),
__STM32_PIN(154, J, 10),
__STM32_PIN(155, J, 11),
__STM32_PIN(156, J, 12),
__STM32_PIN(157, J, 13),
__STM32_PIN(158, J, 14),
__STM32_PIN(159, J, 15),
#if defined(GPIOK)
__STM32_PIN(160, K, 0),
__STM32_PIN(161, K, 1),
__STM32_PIN(162, K, 2),
__STM32_PIN(163, K, 3),
__STM32_PIN(164, K, 4),
__STM32_PIN(165, K, 5),
__STM32_PIN(166, K, 6),
__STM32_PIN(167, K, 7),
__STM32_PIN(168, K, 8),
__STM32_PIN(169, K, 9),
__STM32_PIN(170, K, 10),
__STM32_PIN(171, K, 11),
__STM32_PIN(172, K, 12),
__STM32_PIN(173, K, 13),
__STM32_PIN(174, K, 14),
__STM32_PIN(175, K, 15),
#endif /* defined(GPIOK) */
#endif /* defined(GPIOJ) */
#endif /* defined(GPIOI) */
#endif /* defined(GPIOH) */
#endif /* defined(GPIOG) */
#endif /* defined(GPIOF) */
#endif /* defined(GPIOE) */
#endif /* defined(GPIOD) */
#endif /* defined(GPIOC) */
#endif /* defined(GPIOB) */
#endif /* defined(GPIOA) */
};
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
#if defined(GPIOZ)
#define __STM32_PORT_MAX 12u
#elif defined(GPIOK)
#define __STM32_PORT_MAX 11u
#elif defined(GPIOJ)
#define __STM32_PORT_MAX 10u
#elif defined(GPIOI)
#define __STM32_PORT_MAX 9u
#elif defined(GPIOH)
#define __STM32_PORT_MAX 8u
#elif defined(GPIOG)
#define __STM32_PORT_MAX 7u
#elif defined(GPIOF)
#define __STM32_PORT_MAX 6u
#elif defined(GPIOE)
#define __STM32_PORT_MAX 5u
#elif defined(GPIOD)
#define __STM32_PORT_MAX 4u
#elif defined(GPIOC)
#define __STM32_PORT_MAX 3u
#elif defined(GPIOB)
#define __STM32_PORT_MAX 2u
#elif defined(GPIOA)
#define __STM32_PORT_MAX 1u
#else
#define __STM32_PORT_MAX 0u
#error Unsupported STM32 GPIO peripheral.
#endif
#define PIN_STPORT_MAX __STM32_PORT_MAX
static const struct pin_irq_map pin_irq_map[] =
{
@ -277,68 +114,48 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
static uint32_t pin_irq_enable_mask=0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
return;
}
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
HAL_GPIO_WritePin(gpio_port, gpio_pin, (GPIO_PinState)value);
}
}
static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
GPIO_TypeDef *gpio_port;
uint16_t gpio_pin;
int value = PIN_LOW;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) < PIN_STPORT_MAX)
{
return value;
gpio_port = PIN_STPORT(pin);
gpio_pin = PIN_STPIN(pin);
value = HAL_GPIO_ReadPin(gpio_port, gpio_pin);
}
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
return value;
}
static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return;
}
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = PIN_STPIN(pin);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@ -374,7 +191,7 @@ static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
GPIO_InitStruct.Pull = GPIO_NOPULL;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
@ -403,16 +220,15 @@ rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -420,9 +236,9 @@ static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
level = rt_hw_interrupt_disable();
if (pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
@ -443,16 +259,15 @@ static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -476,21 +291,19 @@ static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStruct;
index = get_pin(pin);
if (index == RT_NULL)
if (PIN_PORT(pin) >= PIN_STPORT_MAX)
{
return RT_ENOSYS;
return -RT_ENOSYS;
}
if (enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
irqindex = bit2bitno(PIN_STPIN(pin));
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return RT_ENOSYS;
@ -507,7 +320,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = &pin_irq_map[irqindex];
/* Configure GPIO_InitStructure */
GPIO_InitStruct.Pin = index->pin;
GPIO_InitStruct.Pin = PIN_STPIN(pin);
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
switch (pin_irq_hdr_tab[irqindex].mode)
{
@ -524,7 +337,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
break;
}
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
HAL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
HAL_NVIC_EnableIRQ(irqmap->irqno);
@ -534,7 +347,7 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
}
else if (enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
irqmap = get_pin_irq_map(PIN_STPIN(pin));
if (irqmap == RT_NULL)
{
return RT_ENOSYS;
@ -542,57 +355,57 @@ static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
level = rt_hw_interrupt_disable();
HAL_GPIO_DeInit(index->gpio, index->pin);
HAL_GPIO_DeInit(PIN_STPORT(pin), PIN_STPIN(pin));
pin_irq_enable_mask &= ~irqmap->pinbit;
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
if (( irqmap->pinbit>=GPIO_PIN_0 )&&( irqmap->pinbit<=GPIO_PIN_1 ))
if ((irqmap->pinbit >= GPIO_PIN_0) && (irqmap->pinbit <= GPIO_PIN_1))
{
if(!(pin_irq_enable_mask&(GPIO_PIN_0|GPIO_PIN_1)))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_0 | GPIO_PIN_1)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else if (( irqmap->pinbit>=GPIO_PIN_2 )&&( irqmap->pinbit<=GPIO_PIN_3 ))
else if ((irqmap->pinbit >= GPIO_PIN_2) && (irqmap->pinbit <= GPIO_PIN_3))
{
if(!(pin_irq_enable_mask&(GPIO_PIN_2|GPIO_PIN_3)))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_2 | GPIO_PIN_3)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else if (( irqmap->pinbit>=GPIO_PIN_4 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
else if ((irqmap->pinbit >= GPIO_PIN_4) && (irqmap->pinbit <= GPIO_PIN_15))
{
if(!(pin_irq_enable_mask&(GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|
GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
#else
if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 ))
{
if(!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
{
if(!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 |
GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
#endif
rt_hw_interrupt_enable(level);
}
#else
if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
{
if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
}
else
{
HAL_NVIC_DisableIRQ(irqmap->irqno);
}
#endif
rt_hw_interrupt_enable(level);
}
else
{
@ -609,6 +422,7 @@ const static struct rt_pin_ops _stm32_pin_ops =
stm32_pin_attach_irq,
stm32_pin_dettach_irq,
stm32_pin_irq_enable,
};
rt_inline void pin_irq_hdr(int irqno)
@ -736,15 +550,15 @@ int rt_hw_pin_init(void)
#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
__HAL_RCC_GPIOA_CLK_ENABLE();
#endif
#if defined(__HAL_RCC_GPIOB_CLK_ENABLE)
__HAL_RCC_GPIOB_CLK_ENABLE();
#endif
#if defined(__HAL_RCC_GPIOC_CLK_ENABLE)
__HAL_RCC_GPIOC_CLK_ENABLE();
#endif
#if defined(__HAL_RCC_GPIOD_CLK_ENABLE)
__HAL_RCC_GPIOD_CLK_ENABLE();
#endif

26
bsp/stm32/libraries/HAL_Drivers/drv_gpio.h
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2018-11-06 balanceTWK first version
* 2020-09-18 geniusgogo optimization design pin-index algorithm
*/
#ifndef __DRV_GPIO_H__
@ -14,27 +15,14 @@
#include <drv_common.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __STM32_PORT(port) GPIO##port##_BASE
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
#define __STM32_PIN(index, gpio, gpio_index) \
{ \
index, GPIO##gpio, GPIO_PIN_##gpio_index \
}
#define __STM32_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* STM32 GPIO driver */
struct pin_index
{
int index;
GPIO_TypeDef *gpio;
uint32_t pin;
};
struct pin_irq_map
{
@ -44,5 +32,9 @@ struct pin_irq_map
int rt_hw_pin_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */

60
bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2018-12-10 zylx first version
* 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
*/
#include <board.h>
@ -151,9 +152,47 @@ static struct stm32_hwtimer stm32_hwtimer_obj[] =
#endif
};
/* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
static void pclkx_doubler_get(rt_uint32_t *pclk1_doubler, rt_uint32_t *pclk2_doubler)
{
rt_uint32_t flatency = 0;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RT_ASSERT(pclk1_doubler != RT_NULL);
RT_ASSERT(pclk1_doubler != RT_NULL);
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
*pclk1_doubler = 1;
*pclk2_doubler = 1;
#if defined(SOC_SERIES_STM32MP1)
if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
{
*pclk1_doubler = 2;
}
if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
{
*pclk2_doubler = 2;
}
#else
if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
{
*pclk1_doubler = 2;
}
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
{
*pclk2_doubler = 2;
}
#endif
#endif
}
static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
uint32_t prescaler_value = 0;
uint32_t pclk1_doubler, pclk2_doubler;
TIM_HandleTypeDef *tim = RT_NULL;
struct stm32_hwtimer *tim_device = RT_NULL;
@ -163,6 +202,8 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
tim_device = (struct stm32_hwtimer *)timer;
pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
/* time init */
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
@ -173,12 +214,12 @@ static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
#endif
{
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1;
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
#endif
}
else
{
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * 2 / 10000) - 1;
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
}
tim->Init.Period = 10000 - 1;
tim->Init.Prescaler = prescaler_value;
@ -271,6 +312,7 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
TIM_HandleTypeDef *tim = RT_NULL;
rt_err_t result = RT_EOK;
uint32_t pclk1_doubler, pclk2_doubler;
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(arg != RT_NULL);
@ -287,6 +329,8 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
/* set timer frequence */
freq = *((rt_uint32_t *)arg);
pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
#elif defined(SOC_SERIES_STM32L4)
@ -295,19 +339,13 @@ static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
if (0)
#endif
{
#if defined(SOC_SERIES_STM32L4)
val = HAL_RCC_GetPCLK2Freq() / freq;
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
val = HAL_RCC_GetPCLK2Freq() * 2 / freq;
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
#endif
}
else
{
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
val = HAL_RCC_GetPCLK1Freq() / freq;
#endif
val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
}
__HAL_TIM_SET_PRESCALER(tim, val - 1);

7
bsp/stm32/libraries/HAL_Drivers/drv_lcd.c
View File

@ -254,6 +254,11 @@ void turn_on_lcd_backlight(void)
rt_pin_write(LCD_DISP_GPIO_NUM, PIN_HIGH);
rt_pin_write(LCD_BL_GPIO_NUM, PIN_HIGH);
}
#else
void turn_on_lcd_backlight(void)
{
}
#endif
@ -333,7 +338,7 @@ int drv_lcd_hw_init(void)
__exit:
if (result != RT_EOK)
{
rt_sem_delete(&_lcd.lcd_lock);
rt_sem_detach(&_lcd.lcd_lock);
if (_lcd.lcd_info.framebuffer)
{

9
bsp/stm32/libraries/HAL_Drivers/drv_lptim.c
View File

@ -13,15 +13,6 @@
static LPTIM_HandleTypeDef LptimHandle;
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
{
if (hlptim->Instance == LPTIM1)
{
/* Peripheral clock enable */
__HAL_RCC_LPTIM1_CLK_ENABLE();
}
}
void LPTIM1_IRQHandler(void)
{
HAL_LPTIM_IRQHandler(&LptimHandle);

2
bsp/stm32/libraries/HAL_Drivers/drv_pm.c
View File

@ -95,11 +95,13 @@ static void run(struct rt_pm *pm, uint8_t mode)
{
case PM_RUN_MODE_HIGH_SPEED:
case PM_RUN_MODE_NORMAL_SPEED:
HAL_PWREx_DisableLowPowerRunMode();
SystemClock_80M();
/* Configure the main internal regulator output voltage (Range1 by default)*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
break;
case PM_RUN_MODE_MEDIUM_SPEED:
HAL_PWREx_DisableLowPowerRunMode();
SystemClock_24M();
/* Configure the main internal regulator output voltage */
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2);

13
bsp/stm32/libraries/HAL_Drivers/drv_pwm.c
View File

@ -323,9 +323,9 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
#endif
if (HAL_TIM_Base_Init(tim) != HAL_OK)
if (HAL_TIM_PWM_Init(tim) != HAL_OK)
{
LOG_E("%s time base init failed", device->name);
LOG_E("%s pwm init failed", device->name);
result = -RT_ERROR;
goto __exit;
}
@ -338,13 +338,6 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
goto __exit;
}
if (HAL_TIM_PWM_Init(tim) != HAL_OK)
{
LOG_E("%s pwm init failed", device->name);
result = -RT_ERROR;
goto __exit;
}
master_config.MasterOutputTrigger = TIM_TRGO_RESET;
master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
@ -358,6 +351,8 @@ static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
oc_config.Pulse = 0;
oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
oc_config.OCFastMode = TIM_OCFAST_DISABLE;
oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
/* config pwm channel */
if (device->channel & 0x01)

13
bsp/stm32/libraries/HAL_Drivers/drv_qspi.h
View File

@ -8,10 +8,19 @@
* 2018-11-27 zylx first version
*/
#ifndef __DRV_QSPI_H_
#define __DRV_QSPI_H_
#ifndef __DRV_QSPI_H__
#define __DRV_QSPI_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
#ifdef __cplusplus
}
#endif
#endif /* __DRV_QSPI_H__ */

49
bsp/stm32/libraries/HAL_Drivers/drv_rtc.c
View File

@ -37,7 +37,7 @@ static time_t get_rtc_timestamp(void)
{
RTC_TimeTypeDef RTC_TimeStruct = {0};
RTC_DateTypeDef RTC_DateStruct = {0};
struct tm tm_new;
struct tm tm_new = {0};
HAL_RTC_GetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN);
HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
@ -84,6 +84,15 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
LOG_D("set rtc time.");
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
#ifdef SOC_SERIES_STM32F1
/* F1 series does't save year/month/date datas. so keep those datas to bkp reg */
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR2, RTC_DateStruct.Year);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR3, RTC_DateStruct.Month);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR4, RTC_DateStruct.Date);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR5, RTC_DateStruct.WeekDay);
#endif
return RT_EOK;
}
@ -108,6 +117,36 @@ static void rt_rtc_init(void)
HAL_RCC_OscConfig(&RCC_OscInitStruct);
}
#ifdef SOC_SERIES_STM32F1
/* update RTC_BKP_DRx*/
static void rt_rtc_f1_bkp_update(void)
{
RTC_DateTypeDef RTC_DateStruct = {0};
HAL_PWR_EnableBkUpAccess();
__HAL_RCC_BKP_CLK_ENABLE();
RTC_DateStruct.Year = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR2);
RTC_DateStruct.Month = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR3);
RTC_DateStruct.Date = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR4);
RTC_DateStruct.WeekDay = HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR5);
if (HAL_RTC_SetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN) != HAL_OK)
{
Error_Handler();
}
HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
if (HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR4) != RTC_DateStruct.Date)
{
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR2, RTC_DateStruct.Year);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR3, RTC_DateStruct.Month);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR4, RTC_DateStruct.Date);
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR5, RTC_DateStruct.WeekDay);
}
}
#endif
static rt_err_t rt_rtc_config(struct rt_device *dev)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
@ -167,6 +206,14 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
return -RT_ERROR;
}
}
#ifdef SOC_SERIES_STM32F1
else
{
/* F1 series need update by bkp reg datas */
rt_rtc_f1_bkp_update();
}
#endif
return RT_EOK;
}

21
bsp/stm32/libraries/HAL_Drivers/drv_sdio.c
View File

@ -7,7 +7,8 @@
* Date Author Notes
* 2018-06-22 tyx first
* 2018-12-12 balanceTWK first version
* 2019-06-11 WillianChan Add SD card hot plug detection
* 2019-06-11 WillianChan Add SD card hot plug detection
* 2020-11-09 whj4674672 fix sdio non-aligned access problem
*/
#include "board.h"
@ -352,7 +353,7 @@ static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
/**
* @brief This function send sdio request.
* @param sdio rthw_sdio
* @param host rt_mmcsd_host
* @param req request
* @retval None
*/
@ -366,7 +367,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
if (req->cmd != RT_NULL)
{
memset(&pkg, 0, sizeof(pkg));
rt_memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
@ -382,7 +383,7 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
pkg.buff = cache_buf;
if (data->flags & DATA_DIR_WRITE)
{
memcpy(cache_buf, data->buf, size);
rt_memcpy(cache_buf, data->buf, size);
}
}
}
@ -391,13 +392,13 @@ static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
{
memcpy(data->buf, cache_buf, data->blksize * data->blks);
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
}
}
if (req->stop != RT_NULL)
{
memset(&pkg, 0, sizeof(pkg));
rt_memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rthw_sdio_send_command(sdio, &pkg);
}
@ -524,11 +525,11 @@ void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
}
/**
* @brief This function delect sdcard.
* @brief This function detect sdcard.
* @param host rt_mmcsd_host
* @retval 0x01
*/
static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host)
static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
{
LOG_D("try to detect device");
return 0x01;
@ -604,7 +605,7 @@ static const struct rt_mmcsd_host_ops ops =
{
rthw_sdio_request,
rthw_sdio_iocfg,
rthw_sd_delect,
rthw_sd_detect,
rthw_sdio_irq_update,
};
@ -852,7 +853,7 @@ int rt_hw_sdio_init(void)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2)
SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);

35
bsp/stm32/libraries/HAL_Drivers/drv_spi.c
View File

@ -10,12 +10,13 @@
* 2019-01-03 zylx modify DMA initialization and spixfer function
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#ifdef RT_USING_SPI
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#include "drv_spi.h"
#include "drv_config.h"
@ -136,7 +137,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
if (cfg->mode & RT_SPI_NO_CS)
{
spi_handle->Init.NSS = SPI_NSS_SOFT;
spi_handle->Init.NSS = SPI_NSS_HARD_OUTPUT;
}
else
{
@ -147,6 +148,8 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();
#elif defined(SOC_SERIES_STM32H7)
SPI_APB_CLOCK = HAL_RCC_GetSysClockFreq();
#else
SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
#endif
@ -205,6 +208,20 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
spi_handle->State = HAL_SPI_STATE_RESET;
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
#elif defined(SOC_SERIES_STM32H7)
spi_handle->Init.Mode = SPI_MODE_MASTER;
spi_handle->Init.NSS = SPI_NSS_SOFT;
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
spi_handle->Init.CRCPolynomial = 7;
spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA;
#endif
if (HAL_SPI_Init(spi_handle) != HAL_OK)
@ -240,8 +257,6 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
}
__HAL_SPI_ENABLE(spi_handle);
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
@ -263,7 +278,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
struct stm32_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take)
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
{
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
}
@ -318,6 +333,12 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
{
state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
}
if (message->cs_release && (device->config.mode & RT_SPI_3WIRE))
{
/* release the CS by disable SPI when using 3 wires SPI */
__HAL_SPI_DISABLE(spi_handle);
}
}
else
{
@ -328,6 +349,8 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
}
else
{
/* clear the old error flag */
__HAL_SPI_CLEAR_OVRFLAG(spi_handle);
state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
}
}
@ -349,7 +372,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
}
if (message->cs_release)
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
{
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
}

14
bsp/stm32/libraries/HAL_Drivers/drv_spi.h
View File

@ -8,8 +8,8 @@
* 2018-11-5 SummerGift first version
*/
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtthread.h>
#include "rtdevice.h"
@ -17,8 +17,16 @@
#include <drv_common.h>
#include "drv_dma.h"
#ifdef __cplusplus
extern "C" {
#endif
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
#ifdef __cplusplus
}
#endif
struct stm32_hw_spi_cs
{
GPIO_TypeDef* GPIOx;
@ -59,4 +67,4 @@ struct stm32_spi
struct rt_spi_bus spi_bus;
};
#endif /*__DRV_SPI_H_ */
#endif /*__DRV_SPI_H__ */

440
bsp/stm32/libraries/HAL_Drivers/drv_usart.c
View File

@ -146,6 +146,10 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
break;
}
#ifdef RT_SERIAL_USING_DMA
uart->dma_rx.last_index = 0;
#endif
if (HAL_UART_Init(&uart->handle) != HAL_OK)
{
return -RT_ERROR;
@ -172,11 +176,37 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
NVIC_DisableIRQ(uart->config->irq_type);
/* disable interrupt */
__HAL_UART_DISABLE_IT(&(uart->handle), UART_IT_RXNE);
#ifdef RT_SERIAL_USING_DMA
/* disable DMA */
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
{
HAL_NVIC_DisableIRQ(uart->config->dma_rx->dma_irq);
if (HAL_DMA_Abort(&(uart->dma_rx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
if (HAL_DMA_DeInit(&(uart->dma_rx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
}
else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
{
HAL_NVIC_DisableIRQ(uart->config->dma_tx->dma_irq);
if (HAL_DMA_DeInit(&(uart->dma_tx.handle)) != HAL_OK)
{
RT_ASSERT(0);
}
}
#endif
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
NVIC_EnableIRQ(uart->config->irq_type);
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
/* enable interrupt */
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_RXNE);
break;
@ -186,6 +216,14 @@ static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *ar
stm32_dma_config(serial, ctrl_arg);
break;
#endif
case RT_DEVICE_CTRL_CLOSE:
if (HAL_UART_DeInit(&(uart->handle)) != HAL_OK )
{
RT_ASSERT(0)
}
break;
}
return RT_EOK;
}
@ -233,6 +271,7 @@ static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t
{
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(buf != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (size == 0)
@ -254,15 +293,6 @@ static rt_size_t stm32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t
return 0;
}
static const struct rt_uart_ops stm32_uart_ops =
{
.configure = stm32_configure,
.control = stm32_control,
.putc = stm32_putc,
.getc = stm32_getc,
.dma_transmit = stm32_dma_transmit
};
/**
* Uart common interrupt process. This need add to uart ISR.
*
@ -301,16 +331,14 @@ static void uart_isr(struct rt_serial_device *serial)
}
__HAL_UART_CLEAR_IDLEFLAG(&uart->handle);
}
else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
else if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) &&
(__HAL_UART_GET_IT_SOURCE(&(uart->handle), UART_IT_TC) != RESET))
{
if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0)
{
HAL_UART_IRQHandler(&(uart->handle));
}
else
{
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
}
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
}
#endif
else
@ -714,177 +742,6 @@ void LPUART1_DMA_RX_IRQHandler(void)
#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_LPUART1_RX_USING_DMA) */
#endif /* BSP_USING_LPUART1*/
#ifdef RT_SERIAL_USING_DMA
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
{
struct rt_serial_rx_fifo *rx_fifo;
DMA_HandleTypeDef *DMA_Handle;
struct dma_config *dma_config;
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle = &uart->dma_rx.handle;
dma_config = uart->config->dma_rx;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle = &uart->dma_tx.handle;
dma_config = uart->config->dma_tx;
}
LOG_D("%s dma config start", uart->config->name);
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32L0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
|| defined(SOC_SERIES_STM32G4)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#endif
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
}
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
DMA_Handle->Instance = dma_config->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Channel = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Request = dma_config->request;
#endif
DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle->Init.Mode = DMA_CIRCULAR;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle->Init.Mode = DMA_NORMAL;
}
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
/* enable interrupt */
if (flag == RT_DEVICE_FLAG_DMA_RX)
{
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
/* Start DMA transfer */
if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
{
/* Transfer error in reception process */
RT_ASSERT(0);
}
CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
}
/* enable irq */
HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(dma_config->dma_irq);
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
LOG_D("%s dma config done", uart->config->name);
}
/**
* @brief UART error callbacks
* @param huart: UART handle
* @note This example shows a simple way to report transfer error, and you can
* add your own implementation.
* @retval None
*/
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
RT_ASSERT(huart != NULL);
struct stm32_uart *uart = (struct stm32_uart *)huart;
LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
UNUSED(uart);
}
/**
* @brief Rx Transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx transfer, and
* you can add your own implementation.
* @retval None
*/
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
/**
* @brief Rx Half transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx Half transfer,
* and you can add your own implementation.
* @retval None
*/
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
}
#endif /* RT_SERIAL_USING_DMA */
static void stm32_uart_get_dma_config(void)
{
#ifdef BSP_USING_UART1
@ -972,6 +829,217 @@ static void stm32_uart_get_dma_config(void)
#endif
}
#ifdef RT_SERIAL_USING_DMA
static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
{
struct rt_serial_rx_fifo *rx_fifo;
DMA_HandleTypeDef *DMA_Handle;
struct dma_config *dma_config;
struct stm32_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle = &uart->dma_rx.handle;
dma_config = uart->config->dma_rx;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle = &uart->dma_tx.handle;
dma_config = uart->config->dma_tx;
}
LOG_D("%s dma config start", uart->config->name);
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) \
|| defined(SOC_SERIES_STM32L0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
|| defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
tmpreg = READ_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
/* enable DMAMUX clock for L4+ and G4 */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
#elif defined(SOC_SERIES_STM32MP1)
__HAL_RCC_DMAMUX_CLK_ENABLE();
__HAL_RCC_DMA2_CLK_ENABLE();
#endif
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmarx, uart->dma_rx.handle);
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
__HAL_LINKDMA(&(uart->handle), hdmatx, uart->dma_tx.handle);
}
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0)
DMA_Handle->Instance = dma_config->Instance;
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Channel = dma_config->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
DMA_Handle->Instance = dma_config->Instance;
DMA_Handle->Init.Request = dma_config->request;
#endif
DMA_Handle->Init.PeriphInc = DMA_PINC_DISABLE;
DMA_Handle->Init.MemInc = DMA_MINC_ENABLE;
DMA_Handle->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_Handle->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
if (RT_DEVICE_FLAG_DMA_RX == flag)
{
DMA_Handle->Init.Direction = DMA_PERIPH_TO_MEMORY;
DMA_Handle->Init.Mode = DMA_CIRCULAR;
}
else if (RT_DEVICE_FLAG_DMA_TX == flag)
{
DMA_Handle->Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle->Init.Mode = DMA_NORMAL;
}
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
{
RT_ASSERT(0);
}
/* enable interrupt */
if (flag == RT_DEVICE_FLAG_DMA_RX)
{
rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
/* Start DMA transfer */
if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
{
/* Transfer error in reception process */
RT_ASSERT(0);
}
CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE);
__HAL_UART_ENABLE_IT(&(uart->handle), UART_IT_IDLE);
}
/* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */
HAL_NVIC_SetPriority(dma_config->dma_irq, 0, 0);
HAL_NVIC_EnableIRQ(dma_config->dma_irq);
HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0);
HAL_NVIC_EnableIRQ(uart->config->irq_type);
LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance);
LOG_D("%s dma config done", uart->config->name);
}
/**
* @brief UART error callbacks
* @param huart: UART handle
* @note This example shows a simple way to report transfer error, and you can
* add your own implementation.
* @retval None
*/
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
RT_ASSERT(huart != NULL);
struct stm32_uart *uart = (struct stm32_uart *)huart;
LOG_D("%s: %s %d\n", __FUNCTION__, uart->config->name, huart->ErrorCode);
UNUSED(uart);
}
/**
* @brief Rx Transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx transfer, and
* you can add your own implementation.
* @retval None
*/
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
/**
* @brief Rx Half transfer completed callback
* @param huart: UART handle
* @note This example shows a simple way to report end of DMA Rx Half transfer,
* and you can add your own implementation.
* @retval None
*/
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
dma_isr(&uart->serial);
}
static void _dma_tx_complete(struct rt_serial_device *serial)
{
struct stm32_uart *uart;
rt_size_t trans_total_index;
rt_base_t level;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct stm32_uart, serial);
level = rt_hw_interrupt_disable();
trans_total_index = __HAL_DMA_GET_COUNTER(&(uart->dma_tx.handle));
rt_hw_interrupt_enable(level);
if (trans_total_index == 0)
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
}
}
/**
* @brief HAL_UART_TxCpltCallback
* @param huart: UART handle
* @note This callback can be called by two functions, first in UART_EndTransmit_IT when
* UART Tx complete and second in UART_DMATransmitCplt function in DMA Circular mode.
* @retval None
*/
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
struct stm32_uart *uart;
RT_ASSERT(huart != NULL);
uart = (struct stm32_uart *)huart;
_dma_tx_complete(&uart->serial);
}
#endif /* RT_SERIAL_USING_DMA */
static const struct rt_uart_ops stm32_uart_ops =
{
.configure = stm32_configure,
.control = stm32_control,
.putc = stm32_putc,
.getc = stm32_getc,
.dma_transmit = stm32_dma_transmit
};
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct stm32_uart);

6
bsp/stm32/libraries/HAL_Drivers/drv_wdt.c
View File

@ -18,12 +18,12 @@
struct stm32_wdt_obj
{
rt_watchdog_t watchdog;
IWDG_HandleTypeDef hiwdg;
rt_uint16_t is_start;
};
static struct stm32_wdt_obj stm32_wdt;
static struct rt_watchdog_ops ops;
static rt_watchdog_t watchdog;
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
@ -116,9 +116,9 @@ int rt_wdt_init(void)
ops.init = &wdt_init;
ops.control = &wdt_control;
watchdog.ops = &ops;
stm32_wdt.watchdog.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
if (rt_hw_watchdog_register(&stm32_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;

7
bsp/stm32/libraries/Kconfig
View File

@ -30,7 +30,12 @@ config SOC_SERIES_STM32L0
bool
select ARCH_ARM_CORTEX_M0
select SOC_FAMILY_STM32
config SOC_SERIES_STM32L1
bool
select ARCH_ARM_CORTEX_M3
select SOC_FAMILY_STM32
config SOC_SERIES_STM32L4
bool
select ARCH_ARM_CORTEX_M4

1
bsp/stm32/libraries/STM32F0xx_HAL/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h
View File

@ -44,7 +44,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32F0xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h
View File

@ -28,7 +28,6 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32F1xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32F2xx_HAL/STM32F2xx_HAL_Driver/Inc/stm32f2xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f2xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32F2xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32F4xx_HAL/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32F4xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32F7xx_HAL/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32F7xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h
View File

@ -28,7 +28,6 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32G0xx_HAL_Driver
* @{

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g431xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g441xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g471xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g473xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g474xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g483xx.s
View File

@ -79,7 +79,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -97,9 +97,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

6
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32g484xx.s
View File

@ -78,7 +78,7 @@ LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
@ -96,9 +96,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

4
bsp/stm32/libraries/STM32G4xx_HAL/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/startup_stm32gbk1cb.s
View File

@ -93,9 +93,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever

1
bsp/stm32/libraries/STM32H7xx_HAL/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32H7xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32L0xx_HAL/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l0xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32L0xx_HAL_Driver
* @{

1
bsp/stm32/libraries/STM32L4xx_HAL/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h
View File

@ -28,7 +28,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal_conf.h"
#include <rtthread.h>
/** @addtogroup STM32L4xx_HAL_Driver
* @{

2
bsp/stm32/libraries/templates/stm32f0xx/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M0

2
bsp/stm32/libraries/templates/stm32f10x/rtconfig.h
View File

@ -39,7 +39,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3

2
bsp/stm32/libraries/templates/stm32f2xx/rtconfig.h
View File

@ -38,7 +38,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x30105
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3

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