diff --git a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_rtc.c b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_rtc.c index 84ffc72fe5..2490907239 100644 --- a/bsp/acm32/acm32f0x0-nucleo/drivers/drv_rtc.c +++ b/bsp/acm32/acm32f0x0-nucleo/drivers/drv_rtc.c @@ -49,21 +49,21 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) { RTC_TimeTypeDef RTC_TimeStruct = {0}; RTC_DateTypeDef RTC_DateStruct = {0}; - struct tm *p_tm; + struct tm now; - p_tm = gmtime(&time_stamp); - if (p_tm->tm_year < 100) + gmtime_r(&time_stamp, &now); + if (now.tm_year < 100) { return -RT_ERROR; } - RTC_TimeStruct.u8_Seconds = dec2hex(p_tm->tm_sec); - RTC_TimeStruct.u8_Minutes = dec2hex(p_tm->tm_min); - RTC_TimeStruct.u8_Hours = dec2hex(p_tm->tm_hour); - RTC_DateStruct.u8_Date = dec2hex(p_tm->tm_mday); - RTC_DateStruct.u8_Month = dec2hex(p_tm->tm_mon + 1); - RTC_DateStruct.u8_Year = dec2hex(p_tm->tm_year - 100); - RTC_DateStruct.u8_WeekDay = dec2hex(p_tm->tm_wday) + 1; + RTC_TimeStruct.u8_Seconds = dec2hex(now.tm_sec); + RTC_TimeStruct.u8_Minutes = dec2hex(now.tm_min); + RTC_TimeStruct.u8_Hours = dec2hex(now.tm_hour); + RTC_DateStruct.u8_Date = dec2hex(now.tm_mday); + RTC_DateStruct.u8_Month = dec2hex(now.tm_mon + 1); + RTC_DateStruct.u8_Year = dec2hex(now.tm_year - 100); + RTC_DateStruct.u8_WeekDay = dec2hex(now.tm_wday) + 1; HAL_RTC_SetTime(&RTC_TimeStruct); HAL_RTC_SetDate(&RTC_DateStruct); diff --git a/bsp/apollo2/board/rtc.c b/bsp/apollo2/board/rtc.c index 5c8fbb13fe..0eb57aaf84 100644 --- a/bsp/apollo2/board/rtc.c +++ b/bsp/apollo2/board/rtc.c @@ -38,7 +38,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) { time_t *time; struct tm time_temp; - struct tm* time_new; + struct tm time_new; am_hal_rtc_time_t hal_time; RT_ASSERT(dev != RT_NULL); @@ -71,16 +71,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) case RT_DEVICE_CTRL_RTC_SET_TIME: time = (time_t *)args; - time_new = gmtime(time); + gmtime_r(time, &time_new); - hal_time.ui32Hour = time_new->tm_hour; - hal_time.ui32Minute = time_new->tm_min; - hal_time.ui32Second = time_new->tm_sec; + hal_time.ui32Hour = time_new.tm_hour; + hal_time.ui32Minute = time_new.tm_min; + hal_time.ui32Second = time_new.tm_sec; hal_time.ui32Hundredths = 00; - hal_time.ui32Weekday = time_new->tm_wday; - hal_time.ui32DayOfMonth = time_new->tm_mday; - hal_time.ui32Month = time_new->tm_mon + 1; - hal_time.ui32Year = time_new->tm_year + 1900 - 2000; + hal_time.ui32Weekday = time_new.tm_wday; + hal_time.ui32DayOfMonth = time_new.tm_mday; + hal_time.ui32Month = time_new.tm_mon + 1; + hal_time.ui32Year = time_new.tm_year + 1900 - 2000; hal_time.ui32Century = 0; am_hal_rtc_time_set(&hal_time); diff --git a/bsp/at32/libraries/rt_drivers/drv_rtc.c b/bsp/at32/libraries/rt_drivers/drv_rtc.c index 8402e4a0b8..c97a987f0f 100644 --- a/bsp/at32/libraries/rt_drivers/drv_rtc.c +++ b/bsp/at32/libraries/rt_drivers/drv_rtc.c @@ -49,22 +49,22 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp) { #if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \ defined (SOC_SERIES_AT32F415) - struct tm *p_tm; + struct tm now; - p_tm = gmtime(&time_stamp); - if (p_tm->tm_year < 100) + gmtime_r(&time_stamp, &now); + if (now.tm_year < 100) { return -RT_ERROR; } /* set time */ - if(ertc_time_set(p_tm->tm_hour, p_tm->tm_min, p_tm->tm_sec, ERTC_AM) != SUCCESS) + if(ertc_time_set(now.tm_hour, now.tm_min, now.tm_sec, ERTC_AM) != SUCCESS) { return -RT_ERROR; } /* set date */ - if(ertc_date_set(p_tm->tm_year - 100, p_tm->tm_mon + 1, p_tm->tm_mday, p_tm->tm_wday + 1) != SUCCESS) + if(ertc_date_set(now.tm_year - 100, now.tm_mon + 1, now.tm_mday, now.tm_wday + 1) != SUCCESS) { return -RT_ERROR; } diff --git a/bsp/essemi/es32f0654/drivers/drv_rtc.c b/bsp/essemi/es32f0654/drivers/drv_rtc.c index 939538b9c1..69e3db8dfa 100644 --- a/bsp/essemi/es32f0654/drivers/drv_rtc.c +++ b/bsp/essemi/es32f0654/drivers/drv_rtc.c @@ -55,9 +55,7 @@ static void __rtc_init(rtc_init_t *init) static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) { rt_err_t result = RT_EOK; - struct tm time_temp; - struct tm *pNow; rtc_date_t date; rtc_time_t time; @@ -76,15 +74,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) break; case RT_DEVICE_CTRL_RTC_SET_TIME: - - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); - + gmtime_r((const time_t *)args, &time_temp); time.hour = time_temp.tm_hour; time.minute = time_temp.tm_min; time.second = time_temp.tm_sec; diff --git a/bsp/essemi/es32f369x/drivers/drv_rtc.c b/bsp/essemi/es32f369x/drivers/drv_rtc.c index 5e8835680e..5b366d6cfd 100644 --- a/bsp/essemi/es32f369x/drivers/drv_rtc.c +++ b/bsp/essemi/es32f369x/drivers/drv_rtc.c @@ -54,9 +54,7 @@ static void __rtc_init(rtc_init_t *init) static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) { rt_err_t result = RT_EOK; - struct tm time_temp; - struct tm *pNow; rtc_date_t date; rtc_time_t time; @@ -75,15 +73,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args) break; case RT_DEVICE_CTRL_RTC_SET_TIME: - - rt_enter_critical(); - /* converts calendar time time into local time. */ - pNow = gmtime((const time_t *)args); - /* copy the statically located variable */ - memcpy(&time_temp, pNow, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); - + gmtime_r((const time_t *)args, &time_temp); time.hour = time_temp.tm_hour; time.minute = time_temp.tm_min; time.second = time_temp.tm_sec; diff --git a/bsp/imxrt/libraries/drivers/drv_rtc.c b/bsp/imxrt/libraries/drivers/drv_rtc.c index 4896b44b5b..c0667ddbc9 100644 --- a/bsp/imxrt/libraries/drivers/drv_rtc.c +++ b/bsp/imxrt/libraries/drivers/drv_rtc.c @@ -45,18 +45,18 @@ static time_t get_timestamp(void) static int set_timestamp(time_t timestamp) { - struct tm *p_tm; + struct tm now; snvs_hp_rtc_datetime_t rtcDate = {0}; - p_tm = gmtime(×tamp); + gmtime_r(×tamp, &now); - rtcDate.second = p_tm->tm_sec ; - rtcDate.minute = p_tm->tm_min ; - rtcDate.hour = p_tm->tm_hour; + rtcDate.second = now.tm_sec ; + rtcDate.minute = now.tm_min ; + rtcDate.hour = now.tm_hour; - rtcDate.day = p_tm->tm_mday; - rtcDate.month = p_tm->tm_mon + 1; - rtcDate.year = p_tm->tm_year + 1900; + rtcDate.day = now.tm_mday; + rtcDate.month = now.tm_mon + 1; + rtcDate.year = now.tm_year + 1900; if (SNVS_HP_RTC_SetDatetime(SNVS, &rtcDate) != kStatus_Success) { diff --git a/bsp/loongson/ls1bdev/drivers/drv_uart.c b/bsp/loongson/ls1bdev/drivers/drv_uart.c index 8f469f26ed..d5f725a281 100644 --- a/bsp/loongson/ls1bdev/drivers/drv_uart.c +++ b/bsp/loongson/ls1bdev/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -181,19 +181,19 @@ void rt_hw_uart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; #ifdef RT_USING_UART5 - uart = &uart5; - - serial5.ops = &ls1b_uart_ops; - serial5.config = config; - - rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5"); - - /* register UART5 device */ - rt_hw_serial_register(&serial5, - "uart5", - //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); + uart = &uart5; + + serial5.ops = &ls1b_uart_ops; + serial5.config = config; + + rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5"); + + /* register UART5 device */ + rt_hw_serial_register(&serial5, + "uart5", + //RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); #endif /* RT_USING_UART5 */ diff --git a/bsp/loongson/ls1cdev/drivers/display_controller.c b/bsp/loongson/ls1cdev/drivers/display_controller.c index 2a0bfcc619..b1c9f59159 100644 --- a/bsp/loongson/ls1cdev/drivers/display_controller.c +++ b/bsp/loongson/ls1cdev/drivers/display_controller.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2011-08-09 lgnq first version for LS1B DC * 2015-07-06 chinesebear modified for loongson 1c - * 2018-01-06 sundm75 modified for smartloong + * 2018-01-06 sundm75 modified for smartloong */ #include @@ -78,13 +78,13 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) pix_div = (pix_div>>24)&0xff; rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div); - divider_int = pll_clk/(1000000) *PCLK/1000; + divider_int = pll_clk/(1000000) *PCLK/1000; if(divider_int%1000>=500) divider_int = divider_int/1000+1; else divider_int = divider_int/1000; rt_kprintf("divider_int = %d\n", divider_int); - + /* check whether divisor is too small. */ if (divider_int < 1) { rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n"); @@ -102,9 +102,9 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK) regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0 regval &= ~(0x3f<<24); //PIX_DIV 清零 regval |= divider_int << 24; - PLL_DIV_PARAM = regval; + PLL_DIV_PARAM = regval; regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1 - PLL_DIV_PARAM = regval; + PLL_DIV_PARAM = regval; } rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM); rt_thread_delay(10); @@ -115,11 +115,11 @@ static rt_err_t rt_dc_init(rt_device_t dev) { int i, out, mode=-1; int val; - + rt_kprintf("PWM initied\n"); /* Set the back light PWM. */ pwminit(); - + for (i=0; iclose = RT_NULL; dc->control = rt_dc_control; dc->user_data = (void*)&_dc_info; - + /* register Display Controller device to RT-Thread */ rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR); - + rt_device_init(dc); } @@ -250,7 +250,7 @@ int rtgui_lcd_init(void) pin_set_purpose(76, PIN_PURPOSE_OTHER); pin_set_remap(76, PIN_REMAP_DEFAULT); - + /* init Display Controller */ rt_hw_dc_init(); @@ -259,7 +259,7 @@ int rtgui_lcd_init(void) /* set Display Controller device as rtgui graphic driver */ rtgui_graphic_set_device(dc); - + return 0; } diff --git a/bsp/loongson/ls1cdev/drivers/display_controller.h b/bsp/loongson/ls1cdev/drivers/display_controller.h index 39f6ae8d52..7fcec26b66 100644 --- a/bsp/loongson/ls1cdev/drivers/display_controller.h +++ b/bsp/loongson/ls1cdev/drivers/display_controller.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,9 +7,9 @@ * Date Author Notes * 2011-08-08 lgnq first version for LS1B * 2015-07-06 chinesebear modified for loongson 1c - * 2018-01-06 sundm75 modified for smartloong + * 2018-01-06 sundm75 modified for smartloong */ - + #ifndef __DISPLAY_CONTROLLER_H__ #define __DISPLAY_CONTROLLER_H__ @@ -19,31 +19,31 @@ #define DC_BASE 0xBC301240 //Display Controller /* Frame Buffer registers */ -#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) -#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) -#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) -#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) -#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) -#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) -#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) -#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) -#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) -#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) -#define DC_HSYNC __REG32(DC_BASE + 0x1E0) -#define DC_VDISPLAY __REG32(DC_BASE + 0x240) -#define DC_VSYNC __REG32(DC_BASE + 0x260) -#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) +#define DC_FB_CONFIG __REG32(DC_BASE + 0x000) +#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020) +#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040) +#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060) +#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120) +#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140) +#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160) +#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180) +#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0) +#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0) +#define DC_HSYNC __REG32(DC_BASE + 0x1E0) +#define DC_VDISPLAY __REG32(DC_BASE + 0x240) +#define DC_VSYNC __REG32(DC_BASE + 0x260) +#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340) /* Display Controller driver for 1024x768 16bit */ -#define FB_XSIZE 480 -#define FB_YSIZE 272 +#define FB_XSIZE 480 +#define FB_YSIZE 272 #define CONFIG_VIDEO_16BPP -#define OSC 24000000 /* Hz */ +#define OSC 24000000 /* Hz */ -#define K1BASE 0xA0000000 -#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) -#define HW_FB_ADDR KSEG1(_rt_framebuffer) +#define K1BASE 0xA0000000 +#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr))) +#define HW_FB_ADDR KSEG1(_rt_framebuffer) struct vga_struct { diff --git a/bsp/loongson/ls1cdev/drivers/drv_can.c b/bsp/loongson/ls1cdev/drivers/drv_can.c index 66388b4ea8..cf0e00f00a 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_can.c +++ b/bsp/loongson/ls1cdev/drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -40,7 +40,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i rt_int32_t hdr, fbase, foff; CAN_TypeDef* CANx; CANx = pbxcan->reg; - + /*pitem->mode 1-掩码模式; 0- 滤波器模式 SJA1000中使用以下方式*/ /*SJA1000中AFM 1-单滤波器模式; 0- 双滤波器模式 */ @@ -72,7 +72,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i } CAN_FilterInitTypeDef CAN_FilterInitStruct; - unsigned char ide, rtr, id , idmask, mode; + unsigned char ide, rtr, id , idmask, mode; ide = (unsigned char) pitem->ide; rtr = (unsigned char) pitem->rtr; id = pitem->id; @@ -84,7 +84,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i CAN_FilterInitStruct.IDMASK = idmask; CAN_FilterInitStruct.MODE = mode; CAN_FilterInit(CANx, &CAN_FilterInitStruct); - + return RT_EOK; } @@ -109,15 +109,15 @@ static rt_err_t setfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_config static void bxcan0_filter_init(struct rt_can_device *can) { struct ls1c_bxcan *pbxcan; - pbxcan = (struct ls1c_bxcan *) can->parent.user_data; - + pbxcan = (struct ls1c_bxcan *) can->parent.user_data; + } static void bxcan1_filter_init(struct rt_can_device *can) { struct ls1c_bxcan *pbxcan; - pbxcan = (struct ls1c_bxcan *) can->parent.user_data; - + pbxcan = (struct ls1c_bxcan *) can->parent.user_data; + } static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) @@ -161,7 +161,7 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) break; case RT_CAN_MODE_LOOPBACK: CAN_InitStructure.CAN_Mode = CAN_Mode_STM; - + break; case RT_CAN_MODE_LOOPBACKANLISEN: CAN_InitStructure.CAN_Mode = CAN_Mode_STM|CAN_Mode_LOM; @@ -171,37 +171,37 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode) switch (bps) { - case LS1C_CAN1MBaud: + case LS1C_CAN1MBaud: CAN_InitStructure.CAN_Prescaler = 9; CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN800kBaud: + case LS1C_CAN800kBaud: CAN_InitStructure.CAN_Prescaler = 8; CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN500kBaud: + case LS1C_CAN500kBaud: CAN_InitStructure.CAN_Prescaler = 9; CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN250kBaud: + case LS1C_CAN250kBaud: CAN_InitStructure.CAN_Prescaler = 36; CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN125kBaud: + case LS1C_CAN125kBaud: CAN_InitStructure.CAN_Prescaler = 36; CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN100kBaud: + case LS1C_CAN100kBaud: CAN_InitStructure.CAN_Prescaler = 63; CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; break; - case LS1C_CAN50kBaud: + case LS1C_CAN50kBaud: CAN_InitStructure.CAN_Prescaler = 63; CAN_InitStructure.CAN_BS1 = CAN_BS1_16tq; CAN_InitStructure.CAN_BS2 = CAN_BS2_3tq; @@ -244,14 +244,14 @@ static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg) if (pbxcan == CAN0) { #ifdef USING_BXCAN0 - bxcan0_hw_init(); + bxcan0_hw_init(); bxcan_init(pbxcan, cfg->baud_rate, cfg->mode); #endif } else if (pbxcan == CAN1) { #ifdef USING_BXCAN1 - bxcan1_hw_init(); + bxcan1_hw_init(); bxcan_init(pbxcan, cfg->baud_rate, cfg->mode); #endif } @@ -328,7 +328,7 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg) } break; case RT_CAN_CMD_GET_STATUS: - { + { rt_uint32_t errtype; errtype = pbxcan->reg->RXERR; @@ -380,7 +380,7 @@ static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno) pbxcan = ((struct ls1c_bxcan *) can->parent.user_data)->reg; - pmsg->ide = (rt_uint32_t) RxMessage.IDE; + pmsg->ide = (rt_uint32_t) RxMessage.IDE; if(RxMessage.IDE == 1) pmsg->id = RxMessage.ExtId; else @@ -405,37 +405,37 @@ static const struct rt_can_ops canops = #ifdef USING_BXCAN0 struct rt_can_device bxcan0; -void ls1c_can0_irqhandler(int irq, void *param) -{ +void ls1c_can0_irqhandler(int irq, void *param) +{ CAN_TypeDef* CANx; unsigned char status; CANx = CAN0; /*读寄存器清除中断*/ status = CANx->IR; - + /*接收中断*/ - if (( status & CAN_IR_RI) == CAN_IR_RI) + if (( status & CAN_IR_RI) == CAN_IR_RI) { /*清除RI 中断*/ CAN_Receive(CANx, &RxMessage); - CANx->CMR |= CAN_CMR_RRB; - CANx->CMR |= CAN_CMR_CDO; + CANx->CMR |= CAN_CMR_RRB; + CANx->CMR |= CAN_CMR_CDO; rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RX_IND); rt_kprintf("\r\nCan0 int RX happened!\r\n"); } /*发送中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_TI) + else if (( status & CAN_IR_TI) == CAN_IR_TI) { rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_kprintf("\r\nCan0 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_DOI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan0 int RX OF happened!\r\n"); } -} +} static struct ls1c_bxcan bxcan0data = { .reg = CAN0, @@ -445,37 +445,37 @@ static struct ls1c_bxcan bxcan0data = #ifdef USING_BXCAN1 struct rt_can_device bxcan1; -void ls1c_can1_irqhandler(int irq, void *param) -{ +void ls1c_can1_irqhandler(int irq, void *param) +{ CAN_TypeDef* CANx; unsigned char status; CANx = CAN1; /*读寄存器清除中断*/ status = CANx->IR; - + /*接收中断*/ - if (( status & CAN_IR_RI) == CAN_IR_RI) + if (( status & CAN_IR_RI) == CAN_IR_RI) { /*清除RI 中断*/ CAN_Receive(CANx, &RxMessage); - CANx->CMR |= CAN_CMR_RRB; - CANx->CMR |= CAN_CMR_CDO; + CANx->CMR |= CAN_CMR_RRB; + CANx->CMR |= CAN_CMR_CDO; rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RX_IND); rt_kprintf("\r\nCan1 int RX happened!\r\n"); } /*发送中断*/ - else if (( status & CAN_IR_TI) == CAN_IR_TI) + else if (( status & CAN_IR_TI) == CAN_IR_TI) { rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_TX_DONE | 0 << 8); rt_kprintf("\r\nCan1 int TX happened!\r\n"); } /*数据溢出中断*/ - else if (( status & CAN_IR_DOI) == CAN_IR_DOI) + else if (( status & CAN_IR_DOI) == CAN_IR_DOI) { rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RXOF_IND); rt_kprintf("\r\nCan1 int RX OF happened!\r\n"); } -} +} static struct ls1c_bxcan bxcan1data = { .reg = CAN1, @@ -499,9 +499,9 @@ int ls1c_bxcan_init(void) #endif rt_hw_can_register(&bxcan0, "bxcan0", &canops, &bxcan0data); rt_kprintf("\r\ncan0 register! \r\n"); - - rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0"); - rt_hw_interrupt_umask(LS1C_CAN0_IRQ); + + rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0"); + rt_hw_interrupt_umask(LS1C_CAN0_IRQ); #endif #ifdef USING_BXCAN1 bxcan1.config.baud_rate = CAN250kBaud; @@ -515,9 +515,9 @@ int ls1c_bxcan_init(void) #endif rt_hw_can_register(&bxcan1, "bxcan1", &canops, &bxcan1data); rt_kprintf("\r\ncan1 register! \r\n"); - - rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1"); - rt_hw_interrupt_umask(LS1C_CAN1_IRQ); + + rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1"); + rt_hw_interrupt_umask(LS1C_CAN1_IRQ); #endif return RT_EOK; } diff --git a/bsp/loongson/ls1cdev/drivers/drv_gpio.c b/bsp/loongson/ls1cdev/drivers/drv_gpio.c index 14b44c9b6f..02c9c72772 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_gpio.c +++ b/bsp/loongson/ls1cdev/drivers/drv_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -90,7 +90,7 @@ rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin, break; } gpio_set_irq_type(gpio, type); - + rt_sprintf(irq_name, "PIN_%d", gpio); rt_hw_interrupt_install(LS1C_GPIO_TO_IRQ(gpio), (rt_isr_handler_t)hdr, args, irq_name); diff --git a/bsp/loongson/ls1cdev/drivers/drv_pwm.c b/bsp/loongson/ls1cdev/drivers/drv_pwm.c index 779a7e52b9..48b1c21928 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_pwm.c +++ b/bsp/loongson/ls1cdev/drivers/drv_pwm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -59,17 +59,17 @@ static rt_err_t get(struct rt_device_pwm *device, struct rt_pwm_configuration *c { rt_err_t result = RT_EOK; struct rt_ls1c_pwm *ls1c_pwm_device = (struct rt_ls1c_pwm *)device; - + if (configuration->channel > (PWM_CHANNEL_MAX - 1)) { result = -RT_EIO; goto _exit; } - + configuration->period = ls1c_pwm_device->period[configuration->channel]; configuration->pulse = ls1c_pwm_device->pulse[configuration->channel]; rt_kprintf("drv_pwm.c get channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse); - + _exit: return result; } @@ -84,7 +84,7 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) if (cmd == PWM_CMD_ENABLE) { rt_kprintf("PWM_CMD_ENABLE\n"); - + pwm_info_t pwm_info; switch ( configuration->channel) { @@ -107,9 +107,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) default: break; } - pwm_info.mode = PWM_MODE_NORMAL; - pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); - pwm_info.period_ns = configuration->period; + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; pwm_init(&pwm_info); pwm_enable(&pwm_info); } @@ -138,9 +138,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg) default: break; } - pwm_info.mode = PWM_MODE_NORMAL; - pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); - pwm_info.period_ns = configuration->period; + pwm_info.mode = PWM_MODE_NORMAL; + pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period ); + pwm_info.period_ns = configuration->period; pwm_init(&pwm_info); pwm_disable(&pwm_info); } diff --git a/bsp/loongson/ls1cdev/drivers/drv_rtc.c b/bsp/loongson/ls1cdev/drivers/drv_rtc.c index ef1398fe47..89d72a5bb3 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_rtc.c +++ b/bsp/loongson/ls1cdev/drivers/drv_rtc.c @@ -1,10 +1,10 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2018-05-05 sundm75 first version */ @@ -21,56 +21,56 @@ #if defined(RT_USING_RTC) #ifdef RT_RTC_DEBUG -#define rtc_debug(format,args...) rt_kprintf(format, ##args) +#define rtc_debug(format,args...) rt_kprintf(format, ##args) #else #define rtc_debug(format,args...) #endif static struct rt_device rtc; -RTC_TypeDef * RTC_Handler; +RTC_TypeDef * RTC_Handler; -static time_t get_timestamp(void) +static time_t get_timestamp(void) { - struct tm tm_new = {0}; - RTC_TimeTypeDef rtcDate; - - RTC_GetTime(RTC_Handler, &rtcDate); - - tm_new.tm_sec = rtcDate.Seconds; - tm_new.tm_min = rtcDate.Minutes; + struct tm tm_new = {0}; + RTC_TimeTypeDef rtcDate; + + RTC_GetTime(RTC_Handler, &rtcDate); + + tm_new.tm_sec = rtcDate.Seconds; + tm_new.tm_min = rtcDate.Minutes; tm_new.tm_hour = rtcDate.Hours; - - tm_new.tm_mday = rtcDate.Date; - tm_new.tm_mon = rtcDate.Month- 1; - tm_new.tm_year = rtcDate.Year + 2000 - 1900; + + tm_new.tm_mday = rtcDate.Date; + tm_new.tm_mon = rtcDate.Month- 1; + tm_new.tm_year = rtcDate.Year + 2000 - 1900; return timegm(&tm_new); } static int set_timestamp(time_t timestamp) { - struct tm *p_tm; - RTC_TimeTypeDef rtcDate; - - p_tm = gmtime(×tamp); - - rtcDate.Seconds= p_tm->tm_sec ; - rtcDate.Minutes= p_tm->tm_min ; - rtcDate.Hours= p_tm->tm_hour; + struct tm now; + RTC_TimeTypeDef rtcDate; - rtcDate.Date= p_tm->tm_mday; - rtcDate.Month= p_tm->tm_mon + 1; - rtcDate.Year= p_tm->tm_year + 1900 - 2000; - - RTC_SetTime(RTC_Handler, &rtcDate); + gmtime_r(×tamp, &now); + + rtcDate.Seconds= now.tm_sec ; + rtcDate.Minutes= now.tm_min ; + rtcDate.Hours= now.tm_hour; + + rtcDate.Date= now.tm_mday; + rtcDate.Month= now.tm_mon + 1; + rtcDate.Year= now.tm_year + 1900 - 2000; + + RTC_SetTime(RTC_Handler, &rtcDate); rt_kprintf("\r\nrtcDate is %d.%d.%d - %d:%d:%d",rtcDate.Year, rtcDate.Month, rtcDate.Date, rtcDate.Hours, rtcDate.Minutes, rtcDate.Seconds); return RT_EOK; } rt_uint8_t RTC_Init(void) -{ - RTC_Handler = RTC; +{ + RTC_Handler = RTC; return 0; } @@ -90,7 +90,7 @@ static rt_size_t rt_rtc_read( void* buffer, rt_size_t size) { - + return 0; } @@ -109,7 +109,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args) switch (cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: - + *(rt_uint32_t *)args = get_timestamp(); rtc_debug("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); break; diff --git a/bsp/loongson/ls1cdev/drivers/drv_rtc.h b/bsp/loongson/ls1cdev/drivers/drv_rtc.h index cea8ebe633..f28bfeb9cf 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_rtc.h +++ b/bsp/loongson/ls1cdev/drivers/drv_rtc.h @@ -1,18 +1,18 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes + * Date Author Notes * 2018-05-05 sundm75 first version */ - + #ifndef __DRV_RTC_H__ #define __DRV_RTC_H__ -#include -#include +#include +#include int rt_hw_rtc_init(void); diff --git a/bsp/loongson/ls1cdev/drivers/drv_spi.h b/bsp/loongson/ls1cdev/drivers/drv_spi.h index 8b1aa315be..f2533a2062 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_spi.h +++ b/bsp/loongson/ls1cdev/drivers/drv_spi.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ struct ls1c_spi_cs * 初始化并注册龙芯1c的spi总线 * @SPI SPI总线，比如LS1C_SPI_0， LS1C_SPI_1 * @spi_bus_name 总线名字 - * @ret + * @ret */ rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name); diff --git a/bsp/loongson/ls1cdev/drivers/drv_touch.c b/bsp/loongson/ls1cdev/drivers/drv_touch.c index 092260aaed..1d34369a41 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_touch.c +++ b/bsp/loongson/ls1cdev/drivers/drv_touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,7 +9,7 @@ * 2018-10-29 XY * 2019-04-11 sundm75 modify for ls1c300 & RTGUI */ - + #include "drv_touch.h" #define TOUCH_I2C_NAME "i2c1" diff --git a/bsp/loongson/ls1cdev/drivers/drv_touch.h b/bsp/loongson/ls1cdev/drivers/drv_touch.h index 1ae4c71549..252fca988e 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_touch.h +++ b/bsp/loongson/ls1cdev/drivers/drv_touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2018-02-08 Zhangyihong the first version * 2018-10-29 XY */ - + #ifndef __DRV_TOUCH_H__ #define __DRV_TOUCH_H__ diff --git a/bsp/loongson/ls1cdev/drivers/drv_wdt.c b/bsp/loongson/ls1cdev/drivers/drv_wdt.c index 4a42220000..0c450b80a9 100644 --- a/bsp/loongson/ls1cdev/drivers/drv_wdt.c +++ b/bsp/loongson/ls1cdev/drivers/drv_wdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -161,15 +161,15 @@ static rt_err_t watchdog_ctrl(rt_watchdog_t *wdt, int cmd, void *arg) return RT_EOK; } -struct rt_watchdog_ops watchdog_ops = +struct rt_watchdog_ops watchdog_ops = { - .init = &watchdog_init, + .init = &watchdog_init, .control = &watchdog_ctrl, }; -int wdt_exit(void *priv_data) -{ - return 0; +int wdt_exit(void *priv_data) +{ + return 0; } int rt_hw_wdt_init(void) diff --git a/bsp/loongson/ls1cdev/drivers/hw_i2c.c b/bsp/loongson/ls1cdev/drivers/hw_i2c.c index 1f63df1ab9..2498bb5386 100644 --- a/bsp/loongson/ls1cdev/drivers/hw_i2c.c +++ b/bsp/loongson/ls1cdev/drivers/hw_i2c.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,7 +10,7 @@ #include #include -#include "ls1c_i2c.h" +#include "ls1c_i2c.h" #include "../libraries/ls1c_pin.h" #ifdef RT_USING_I2C @@ -26,30 +26,30 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus, rt_uint32_t num) { struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus; - ls1c_i2c_info_t i2c_info; + ls1c_i2c_info_t i2c_info; struct rt_i2c_msg *msg; int i; rt_int32_t ret = RT_EOK; - i2c_info.clock = 50000; // 50kb/s + i2c_info.clock = 50000; // 50kb/s i2c_info.I2Cx = i2c_bus->u32Module; i2c_init(&i2c_info); - + for (i = 0; i < num; i++) { msg = &msgs[i]; if (msg->flags == RT_I2C_RD) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); - i2c_receive_ack(&i2c_info); - i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ); + i2c_receive_ack(&i2c_info); + i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); } else if(msg->flags == RT_I2C_WR) { - i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); - i2c_receive_ack(&i2c_info); - i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); - i2c_send_stop(&i2c_info); + i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE); + i2c_receive_ack(&i2c_info); + i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len); + i2c_send_stop(&i2c_info); } ret++; } @@ -85,7 +85,7 @@ static const struct rt_i2c_bus_device_ops ls1c_i2c_ops = #ifdef RT_USING_I2C0 -static struct ls1c_i2c_bus ls1c_i2c_bus_0 = +static struct ls1c_i2c_bus ls1c_i2c_bus_0 = { {1}, LS1C_I2C_0, @@ -93,7 +93,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_0 = #endif #ifdef RT_USING_I2C1 -static struct ls1c_i2c_bus ls1c_i2c_bus_1 = +static struct ls1c_i2c_bus ls1c_i2c_bus_1 = { {1}, LS1C_I2C_1, @@ -101,7 +101,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_1 = #endif #ifdef RT_USING_I2C2 -static struct ls1c_i2c_bus ls1c_i2c_bus_2 = +static struct ls1c_i2c_bus ls1c_i2c_bus_2 = { {1}, LS1C_I2C_2, diff --git a/bsp/loongson/ls1cdev/drivers/hw_i2c.h b/bsp/loongson/ls1cdev/drivers/hw_i2c.h index cc3e25506f..39b99295b8 100644 --- a/bsp/loongson/ls1cdev/drivers/hw_i2c.h +++ b/bsp/loongson/ls1cdev/drivers/hw_i2c.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,4 +15,4 @@ int rt_i2c_init(void); -#endif +#endif diff --git a/bsp/loongson/ls1cdev/drivers/net/mii.c b/bsp/loongson/ls1cdev/drivers/net/mii.c index 43ade097cf..bbe38157f3 100644 --- a/bsp/loongson/ls1cdev/drivers/net/mii.c +++ b/bsp/loongson/ls1cdev/drivers/net/mii.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,123 +14,123 @@ static inline unsigned int mii_nway_result (unsigned int negotiated) { - unsigned int ret; + unsigned int ret; - if (negotiated & LPA_100FULL) - ret = LPA_100FULL; - else if (negotiated & LPA_100BASE4) - ret = LPA_100BASE4; - else if (negotiated & LPA_100HALF) - ret = LPA_100HALF; - else if (negotiated & LPA_10FULL) - ret = LPA_10FULL; - else - ret = LPA_10HALF; + if (negotiated & LPA_100FULL) + ret = LPA_100FULL; + else if (negotiated & LPA_100BASE4) + ret = LPA_100BASE4; + else if (negotiated & LPA_100HALF) + ret = LPA_100HALF; + else if (negotiated & LPA_10FULL) + ret = LPA_10FULL; + else + ret = LPA_10HALF; - return ret; + return ret; } static int mii_check_gmii_support(struct mii_if_info *mii) { - int reg; + int reg; - reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); - if (reg & BMSR_ESTATEN) { - reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); - if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) - return 1; - } + reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); + if (reg & BMSR_ESTATEN) { + reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS); + if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) + return 1; + } - return 0; + return 0; } static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd) { - struct synopGMACNetworkAdapter * dev = mii->dev; - u32 advert, bmcr, lpa, nego; - u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; + struct synopGMACNetworkAdapter * dev = mii->dev; + u32 advert, bmcr, lpa, nego; + u32 advert2 = 0, bmcr2 = 0, lpa2 = 0; - ecmd->supported = - (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | - SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | - SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); - if (mii->supports_gmii) - ecmd->supported |= SUPPORTED_1000baseT_Half | - SUPPORTED_1000baseT_Full; + ecmd->supported = + (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); + if (mii->supports_gmii) + ecmd->supported |= SUPPORTED_1000baseT_Half | + SUPPORTED_1000baseT_Full; - /* only supports twisted-pair */ - ecmd->port = PORT_MII; + /* only supports twisted-pair */ + ecmd->port = PORT_MII; - /* only supports internal transceiver */ - ecmd->transceiver = XCVR_INTERNAL; + /* only supports internal transceiver */ + ecmd->transceiver = XCVR_INTERNAL; - /* this isn't fully supported at higher layers */ - ecmd->phy_address = mii->phy_id; + /* this isn't fully supported at higher layers */ + ecmd->phy_address = mii->phy_id; - ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; - advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); - if (mii->supports_gmii) - advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); + ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII; + advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE); + if (mii->supports_gmii) + advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); - if (advert & ADVERTISE_10HALF) - ecmd->advertising |= ADVERTISED_10baseT_Half; - if (advert & ADVERTISE_10FULL) - ecmd->advertising |= ADVERTISED_10baseT_Full; - if (advert & ADVERTISE_100HALF) - ecmd->advertising |= ADVERTISED_100baseT_Half; - if (advert & ADVERTISE_100FULL) - ecmd->advertising |= ADVERTISED_100baseT_Full; - if (advert2 & ADVERTISE_1000HALF) - ecmd->advertising |= ADVERTISED_1000baseT_Half; - if (advert2 & ADVERTISE_1000FULL) - ecmd->advertising |= ADVERTISED_1000baseT_Full; + if (advert & ADVERTISE_10HALF) + ecmd->advertising |= ADVERTISED_10baseT_Half; + if (advert & ADVERTISE_10FULL) + ecmd->advertising |= ADVERTISED_10baseT_Full; + if (advert & ADVERTISE_100HALF) + ecmd->advertising |= ADVERTISED_100baseT_Half; + if (advert & ADVERTISE_100FULL) + ecmd->advertising |= ADVERTISED_100baseT_Full; + if (advert2 & ADVERTISE_1000HALF) + ecmd->advertising |= ADVERTISED_1000baseT_Half; + if (advert2 & ADVERTISE_1000FULL) + ecmd->advertising |= ADVERTISED_1000baseT_Full; - bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); - lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); - if (mii->supports_gmii) { - bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); - lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000); - } - if (bmcr & BMCR_ANENABLE) { - ecmd->advertising |= ADVERTISED_Autoneg; - ecmd->autoneg = AUTONEG_ENABLE; - - nego = mii_nway_result(advert & lpa); - if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & - (lpa2 >> 2)) - ecmd->speed = SPEED_1000; - else if (nego == LPA_100FULL || nego == LPA_100HALF) - ecmd->speed = SPEED_100; - else - ecmd->speed = SPEED_10; - if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || - nego == LPA_10FULL) { - ecmd->duplex = DUPLEX_FULL; - mii->full_duplex = 1; - } else { - ecmd->duplex = DUPLEX_HALF; - mii->full_duplex = 0; - } - } else { - ecmd->autoneg = AUTONEG_DISABLE; + bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR); + lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA); + if (mii->supports_gmii) { + bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000); + lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000); + } + if (bmcr & BMCR_ANENABLE) { + ecmd->advertising |= ADVERTISED_Autoneg; + ecmd->autoneg = AUTONEG_ENABLE; - ecmd->speed = ((bmcr & BMCR_SPEED1000 && - (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : - (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); - ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; - } + nego = mii_nway_result(advert & lpa); + if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) & + (lpa2 >> 2)) + ecmd->speed = SPEED_1000; + else if (nego == LPA_100FULL || nego == LPA_100HALF) + ecmd->speed = SPEED_100; + else + ecmd->speed = SPEED_10; + if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL || + nego == LPA_10FULL) { + ecmd->duplex = DUPLEX_FULL; + mii->full_duplex = 1; + } else { + ecmd->duplex = DUPLEX_HALF; + mii->full_duplex = 0; + } + } else { + ecmd->autoneg = AUTONEG_DISABLE; - /* ignore maxtxpkt, maxrxpkt for now */ + ecmd->speed = ((bmcr & BMCR_SPEED1000 && + (bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 : + (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10); + ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; + } - return 0; + /* ignore maxtxpkt, maxrxpkt for now */ + + return 0; } static int mii_link_ok (struct mii_if_info *mii) { - /* first, a dummy read, needed to latch some MII phys */ - mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); - if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) - return 1; - return 0; + /* first, a dummy read, needed to latch some MII phys */ + mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR); + if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS) + return 1; + return 0; } diff --git a/bsp/loongson/ls1cdev/drivers/net/mii.h b/bsp/loongson/ls1cdev/drivers/net/mii.h index 24563834ec..8480bb4a04 100644 --- a/bsp/loongson/ls1cdev/drivers/net/mii.h +++ b/bsp/loongson/ls1cdev/drivers/net/mii.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -24,7 +24,7 @@ #define MII_EXPANSION 0x06 /* Expansion register */ #define MII_CTRL1000 0x09 /* 1000BASE-T control */ #define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_ESTATUS 0x0f /* Extended Status */ #define MII_DCOUNTER 0x12 /* Disconnect counter */ #define MII_FCSCOUNTER 0x13 /* False carrier counter */ #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -39,7 +39,7 @@ /* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ @@ -58,9 +58,9 @@ #define BMSR_RFAULT 0x0010 /* Remote fault detected */ #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ #define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ -#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */ #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ @@ -87,26 +87,26 @@ #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) + ADVERTISE_CSMA) #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) /* Indicates what features are advertised by the interface. */ -#define ADVERTISED_10baseT_Half (1 << 0) -#define ADVERTISED_10baseT_Full (1 << 1) -#define ADVERTISED_100baseT_Half (1 << 2) -#define ADVERTISED_100baseT_Full (1 << 3) -#define ADVERTISED_1000baseT_Half (1 << 4) -#define ADVERTISED_1000baseT_Full (1 << 5) -#define ADVERTISED_Autoneg (1 << 6) -#define ADVERTISED_TP (1 << 7) -#define ADVERTISED_AUI (1 << 8) -#define ADVERTISED_MII (1 << 9) -#define ADVERTISED_FIBRE (1 << 10) -#define ADVERTISED_BNC (1 << 11) -#define ADVERTISED_10000baseT_Full (1 << 12) -#define ADVERTISED_Pause (1 << 13) -#define ADVERTISED_Asym_Pause (1 << 14) +#define ADVERTISED_10baseT_Half (1 << 0) +#define ADVERTISED_10baseT_Full (1 << 1) +#define ADVERTISED_100baseT_Half (1 << 2) +#define ADVERTISED_100baseT_Full (1 << 3) +#define ADVERTISED_1000baseT_Half (1 << 4) +#define ADVERTISED_1000baseT_Full (1 << 5) +#define ADVERTISED_Autoneg (1 << 6) +#define ADVERTISED_TP (1 << 7) +#define ADVERTISED_AUI (1 << 8) +#define ADVERTISED_MII (1 << 9) +#define ADVERTISED_FIBRE (1 << 10) +#define ADVERTISED_BNC (1 << 11) +#define ADVERTISED_10000baseT_Full (1 << 12) +#define ADVERTISED_Pause (1 << 13) +#define ADVERTISED_Asym_Pause (1 << 14) /* Link partner ability register. */ #define LPA_SLCT 0x001f /* Same as advertise selector */ @@ -126,8 +126,8 @@ #define LPA_LPACK 0x4000 /* Link partner acked us */ #define LPA_NPAGE 0x8000 /* Next page bit */ -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) /* Expansion register for auto-negotiation. */ #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ @@ -137,8 +137,8 @@ #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ #define EXPANSION_RESV 0xffe0 /* Unused... */ -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ +#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ +#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ /* N-way test register. */ #define NWAYTEST_RESV1 0x00ff /* Unused... */ @@ -154,78 +154,78 @@ #define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ -#define SUPPORTED_10baseT_Half (1 << 0) -#define SUPPORTED_10baseT_Full (1 << 1) -#define SUPPORTED_100baseT_Half (1 << 2) -#define SUPPORTED_100baseT_Full (1 << 3) -#define SUPPORTED_1000baseT_Half (1 << 4) -#define SUPPORTED_1000baseT_Full (1 << 5) -#define SUPPORTED_Autoneg (1 << 6) -#define SUPPORTED_TP (1 << 7) -#define SUPPORTED_AUI (1 << 8) -#define SUPPORTED_MII (1 << 9) -#define SUPPORTED_FIBRE (1 << 10) -#define SUPPORTED_BNC (1 << 11) -#define SUPPORTED_10000baseT_Full (1 << 12) -#define SUPPORTED_Pause (1 << 13) -#define SUPPORTED_Asym_Pause (1 << 14) +#define SUPPORTED_10baseT_Half (1 << 0) +#define SUPPORTED_10baseT_Full (1 << 1) +#define SUPPORTED_100baseT_Half (1 << 2) +#define SUPPORTED_100baseT_Full (1 << 3) +#define SUPPORTED_1000baseT_Half (1 << 4) +#define SUPPORTED_1000baseT_Full (1 << 5) +#define SUPPORTED_Autoneg (1 << 6) +#define SUPPORTED_TP (1 << 7) +#define SUPPORTED_AUI (1 << 8) +#define SUPPORTED_MII (1 << 9) +#define SUPPORTED_FIBRE (1 << 10) +#define SUPPORTED_BNC (1 << 11) +#define SUPPORTED_10000baseT_Full (1 << 12) +#define SUPPORTED_Pause (1 << 13) +#define SUPPORTED_Asym_Pause (1 << 14) /* Which connector port. */ #define PORT_TP 0x00 #define PORT_AUI 0x01 -#define PORT_MII 0x02 +#define PORT_MII 0x02 #define PORT_FIBRE 0x03 #define PORT_BNC 0x04 /* Which transceiver to use. */ #define XCVR_INTERNAL 0x00 #define XCVR_EXTERNAL 0x01 -#define XCVR_DUMMY1 0x02 -#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 #define XCVR_DUMMY3 0x04 -#define AUTONEG_DISABLE 0x00 -#define AUTONEG_ENABLE 0x01 +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 -#define SPEED_10 10 -#define SPEED_100 100 -#define SPEED_1000 1000 -#define SPEED_2500 2500 -#define SPEED_10000 10000 +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 +#define SPEED_2500 2500 +#define SPEED_10000 10000 -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 struct ethtool_cmd { - u32 cmd; - u32 supported; /* Features this interface supports */ - u32 advertising; /* Features this interface advertises */ - u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ - u8 duplex; /* Duplex, half or full */ - u8 port; /* Which connector port */ - u8 phy_address; - u8 transceiver; /* Which transceiver to use */ - u8 autoneg; /* Enable or disable autonegotiation */ - u32 maxtxpkt; /* Tx pkts before generating tx int */ - u32 maxrxpkt; /* Rx pkts before generating rx int */ - u32 reserved[4]; + u32 cmd; + u32 supported; /* Features this interface supports */ + u32 advertising; /* Features this interface advertises */ + u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ + u8 duplex; /* Duplex, half or full */ + u8 port; /* Which connector port */ + u8 phy_address; + u8 transceiver; /* Which transceiver to use */ + u8 autoneg; /* Enable or disable autonegotiation */ + u32 maxtxpkt; /* Tx pkts before generating tx int */ + u32 maxrxpkt; /* Rx pkts before generating rx int */ + u32 reserved[4]; }; struct mii_if_info { - int phy_id; - int advertising; - int phy_id_mask; - int reg_num_mask; + int phy_id; + int advertising; + int phy_id_mask; + int reg_num_mask; - unsigned int full_duplex : 1; /* is full duplex? */ - unsigned int force_media : 1; /* is autoneg. disabled? */ - unsigned int supports_gmii : 1; /* are GMII registers supported? */ + unsigned int full_duplex : 1; /* is full duplex? */ + unsigned int force_media : 1; /* is autoneg. disabled? */ + unsigned int supports_gmii : 1; /* are GMII registers supported? */ - struct synopGMACNetworkAdapter *dev; - int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location); - void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val); + struct synopGMACNetworkAdapter *dev; + int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location); + void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val); }; #endif diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC.c b/bsp/loongson/ls1cdev/drivers/net/synopGMAC.c index da8c3c89fb..dcdf4afb03 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC.c +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -579,7 +579,7 @@ struct pbuf *rt_eth_rx(rt_device_t device) if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK) { dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE); - len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes + len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n"); rt_memcpy(pbuf->payload, (char *)data1, len); diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC.h index e244c14892..fb669e8c51 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,4 +20,4 @@ int rt_hw_eth_init(void); -#endif /*__SYNOPGMAC__H*/ +#endif /*__SYNOPGMAC__H*/ diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.c b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.c index a41038f35c..4a1c0223a1 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.c +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,13 +7,13 @@ * Date Author Notes * 2017-08-24 chinesebear first version */ - + #include "synopGMAC_Dev.h" #include #include -#define UNUSED 1 +#define UNUSED 1 /** * Function to set the MDC clock for mdio transactiona @@ -24,12 +24,12 @@ */ s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) { - u32 orig_data; - orig_data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); //set the mdc clock to the user defined value - orig_data &= (~ GmiiCsrClkMask); - orig_data |= clk_div_val; - synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr ,orig_data); - return 0; + u32 orig_data; + orig_data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); //set the mdc clock to the user defined value + orig_data &= (~ GmiiCsrClkMask); + orig_data |= clk_div_val; + synopGMACWriteReg(gmacdev->MacBase, GmacGmiiAddr ,orig_data); + return 0; } /** @@ -41,10 +41,10 @@ s32 synopGMAC_set_mdc_clk_div(synopGMACdevice *gmacdev,u32 clk_div_val) */ u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); - data &= GmiiCsrClkMask; - return data; + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacGmiiAddr); + data &= GmiiCsrClkMask; + return data; } @@ -59,34 +59,34 @@ u32 synopGMAC_get_mdc_clk_div(synopGMACdevice *gmacdev) */ s32 synopGMAC_read_phy_reg(u32 RegBase,u32 PhyBase, u32 RegOffset, u16 * data ) { - u32 addr; - u32 loop_variable; - addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) - | GmiiCsrClk3; //sw: add GmiiCsrClk - addr = addr | GmiiBusy ; //Gmii busy bit + u32 addr; + u32 loop_variable; + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) + | GmiiCsrClk3; //sw: add GmiiCsrClk + addr = addr | GmiiBusy ; //Gmii busy bit - synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); - //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip + synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); + //write the address from where the data to be read in GmiiGmiiAddr register of synopGMAC ip - for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ - //Wait till the busy bit gets cleared within a certain amount of time - if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ - break; - } - plat_delay(DEFAULT_DELAY_VARIABLE); - } - if(loop_variable < DEFAULT_LOOP_VARIABLE) - * data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); - else{ - TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; - } - //sw + for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ + //Wait till the busy bit gets cleared within a certain amount of time + if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ + break; + } + plat_delay(DEFAULT_DELAY_VARIABLE); + } + if(loop_variable < DEFAULT_LOOP_VARIABLE) + * data = (u16)(synopGMACReadReg(RegBase,GmacGmiiData) & 0xFFFF); + else{ + TR("Error::: PHY not responding Busy bit didnot get cleared !!!!!!\n"); + return -ESYNOPGMACPHYERR; + } + //sw #if SYNOP_REG_DEBUG - printf("read phy reg: offset = 0x%x\tdata = 0x%x\n",RegOffset,*data); + printf("read phy reg: offset = 0x%x\tdata = 0x%x\n",RegOffset,*data); #endif - return -ESYNOPGMACNOERR; + return -ESYNOPGMACNOERR; } /** @@ -105,14 +105,14 @@ s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data) synopGMACWriteReg(RegBase,GmacGmiiData,data); // write the data in to GmacGmiiData register of synopGMAC ip - addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; //sw: add GmiiCsrclk + addr = ((PhyBase << GmiiDevShift) & GmiiDevMask) | ((RegOffset << GmiiRegShift) & GmiiRegMask) | GmiiWrite | GmiiCsrClk3; //sw: add GmiiCsrclk addr = addr | GmiiBusy ; //set Gmii clk to 20-35 Mhz and Gmii busy bit synopGMACWriteReg(RegBase,GmacGmiiAddr,addr); for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ if (!(synopGMACReadReg(RegBase,GmacGmiiAddr) & GmiiBusy)){ - break; + break; } plat_delay(DEFAULT_DELAY_VARIABLE); } @@ -130,12 +130,12 @@ s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data) } /** - * Function to configure the phy in loopback mode. + * Function to configure the phy in loopback mode. * * @param[in] pointer to synopGMACdevice. * @param[in] enable or disable the loopback. * \return 0 on success else return the error status. - * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) + * \note Don't get confused with mac loop-back synopGMAC_loopback_on(synopGMACdevice *) * and synopGMAC_loopback_off(synopGMACdevice *) functions. */ #if UNUSED @@ -143,13 +143,13 @@ s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback) { s32 status = -ESYNOPGMACNOERR; u16 *temp; - status = synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG,temp); + status = synopGMAC_read_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG,temp); if(loopback) - *temp |= 0x4000; + *temp |= 0x4000; else - *temp = *temp; + *temp = *temp; - status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, *temp); + status = synopGMAC_write_phy_reg(gmacdev->MacBase, gmacdev->PhyBase, PHY_CONTROL_REG, *temp); return status; } @@ -162,36 +162,36 @@ return status; * \return Always return 0. */ -s32 synopGMAC_read_version (synopGMACdevice * gmacdev) -{ - u32 data = 0; - data = synopGMACReadReg(gmacdev->MacBase, GmacVersion ); - gmacdev->Version = data; - return 0; +s32 synopGMAC_read_version (synopGMACdevice * gmacdev) +{ + u32 data = 0; + data = synopGMACReadReg(gmacdev->MacBase, GmacVersion ); + gmacdev->Version = data; + return 0; } /** - * Function to reset the GMAC core. + * Function to reset the GMAC core. * This reests the DMA and GMAC core. After reset all the registers holds their respective reset value * @param[in] pointer to synopGMACdevice. * \return 0 on success else return the error status. */ -s32 synopGMAC_reset (synopGMACdevice * gmacdev) -{ - u32 data = 0; - synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,DmaResetOn); +s32 synopGMAC_reset (synopGMACdevice * gmacdev) +{ + u32 data = 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,DmaResetOn); plat_delay(DEFAULT_LOOP_VARIABLE); - data = synopGMACReadReg(gmacdev->DmaBase, DmaBusMode); - TR("DATA after Reset = %08x\n",data); - - return 0; + data = synopGMACReadReg(gmacdev->DmaBase, DmaBusMode); + TR("DATA after Reset = %08x\n",data); + + return 0; } /** - * Function to program DMA bus mode register. - * + * Function to program DMA bus mode register. + * * The Bus Mode register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. @@ -200,14 +200,14 @@ s32 synopGMAC_reset (synopGMACdevice * gmacdev) */ s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ) { - synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,init_value ); - return 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaBusMode ,init_value ); + return 0; } /** - * Function to program DMA Control register. - * + * Function to program DMA Control register. + * * The Dma Control register is programmed with the value given. The bits to be set are * bit wise or'ed and sent as the second argument to this function. * @param[in] pointer to synopGMACdevice. @@ -216,15 +216,15 @@ s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ) */ s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ) { - synopGMACWriteReg(gmacdev->DmaBase, DmaControl, init_value); - return 0; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, init_value); + return 0; } /*Gmac configuration functions*/ /** - * Enable the watchdog timer on the receiver. + * Enable the watchdog timer on the receiver. * When enabled, Gmac enables Watchdog timer, and GMAC allows no more than * 2048 bytes of data (10,240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. @@ -232,11 +232,11 @@ s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ) */ void synopGMAC_wd_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; } /** - * Disable the watchdog timer on the receiver. + * Disable the watchdog timer on the receiver. * When disabled, Gmac disabled watchdog timer, and can receive frames up to * 16,384 bytes. * @param[in] pointer to synopGMACdevice. @@ -245,24 +245,24 @@ void synopGMAC_wd_enable(synopGMACdevice * gmacdev) void synopGMAC_wd_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacWatchdog); + return; } /** - * Enables the Jabber frame support. + * Enables the Jabber frame support. * When enabled, GMAC disabled the jabber timer, and can transfer 16,384 byte frames. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_jab_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJabber); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; } /** - * Disables the Jabber frame support. - * When disabled, GMAC enables jabber timer. It cuts of transmitter if application + * Disables the Jabber frame support. + * When disabled, GMAC enables jabber timer. It cuts of transmitter if application * sends more than 2048 bytes of data (10240 if Jumbo frame enabled). * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -270,13 +270,13 @@ void synopGMAC_jab_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_jab_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJabber); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJabber); + return; } #endif /** - * Enables Frame bursting (Only in Half Duplex Mode). + * Enables Frame bursting (Only in Half Duplex Mode). * When enabled, GMAC allows frame bursting in GMII Half Duplex mode. * Reserved in 10/100 and Full-Duplex configurations. * @param[in] pointer to synopGMACdevice. @@ -284,11 +284,11 @@ void synopGMAC_jab_disable(synopGMACdevice * gmacdev) */ void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; } /** - * Disables Frame bursting. + * Disables Frame bursting. * When Disabled, frame bursting is not supported. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -296,13 +296,13 @@ void synopGMAC_frame_burst_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacFrameBurst); + return; } #endif /** - * Enable Jumbo frame support. + * Enable Jumbo frame support. * When Enabled GMAC supports jumbo frames of 9018/9022(VLAN tagged). * Giant frame error is not reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -311,12 +311,12 @@ void synopGMAC_frame_burst_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; } #endif /** - * Disable Jumbo frame support. + * Disable Jumbo frame support. * When Disabled GMAC does not supports jumbo frames. * Giant frame error is reported in receive frame status. * @param[in] pointer to synopGMACdevice. @@ -324,12 +324,12 @@ void synopGMAC_jumbo_frame_enable(synopGMACdevice * gmacdev) */ void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacJumboFrame); + return; } /** - * Disable Carrier sense. + * Disable Carrier sense. * When Disabled GMAC ignores CRS signal during frame transmission * in half duplex mode. * @param[in] pointer to synopGMACdevice. @@ -339,49 +339,49 @@ void synopGMAC_jumbo_frame_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_disable_crs(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); + return; } #endif /** - * Selects the GMII port. + * Selects the GMII port. * When called GMII (1000Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_select_gmii(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; } /** - * Selects the MII port. + * Selects the MII port. * When called MII (10/100Mbps) port is selected (programmable only in 10/100/1000 Mbps configuration). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_select_mii(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacMiiGmii); + return; } /** - * Enables Receive Own bit (Only in Half Duplex Mode). + * Enables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC receives all the packets given by phy while transmitting. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; } /** - * Disables Receive Own bit (Only in Half Duplex Mode). + * Disables Receive Own bit (Only in Half Duplex Mode). * When enaled GMAC disables the reception of frames when gmii_txen_o is asserted. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -389,13 +389,13 @@ void synopGMAC_rx_own_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRxOwn); + return; } #endif /** - * Sets the GMAC in loopback mode. + * Sets the GMAC in loopback mode. * When on GMAC operates in loop-back mode at GMII/MII. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -404,66 +404,66 @@ void synopGMAC_rx_own_disable(synopGMACdevice * gmacdev) */ void synopGMAC_loopback_on(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacLoopback); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; } /** - * Sets the GMAC in Normal mode. + * Sets the GMAC in Normal mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_loopback_off(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacLoopback); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacLoopback); + return; } /** - * Sets the GMAC core in Full-Duplex mode. + * Sets the GMAC core in Full-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_full_duplex(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDuplex); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; } /** - * Sets the GMAC core in Half-Duplex mode. + * Sets the GMAC core in Half-Duplex mode. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_set_half_duplex(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDuplex); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDuplex); + return; } /** * GMAC tries retransmission (Only in Half Duplex mode). - * If collision occurs on the GMII/MII, GMAC attempt retries based on the - * back off limit configured. + * If collision occurs on the GMII/MII, GMAC attempt retries based on the + * back off limit configured. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note This function is tightly coupled with synopGMAC_back_off_limit(synopGMACdev *, u32). */ void synopGMAC_retry_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRetry); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; } /** * GMAC tries only one transmission (Only in Half Duplex mode). * If collision occurs on the GMII/MII, GMAC will ignore the current frami - * transmission and report a frame abort with excessive collision in tranmit frame status. + * transmission and report a frame abort with excessive collision in tranmit frame status. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_retry_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRetry); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRetry); + return; } #endif @@ -471,29 +471,29 @@ void synopGMAC_retry_disable(synopGMACdevice * gmacdev) * GMAC strips the Pad/FCS field of incoming frames. * This is true only if the length field value is less than or equal to * 1500 bytes. All received frames with length field greater than or equal to - * 1501 bytes are passed to the application without stripping the Pad/FCS field. + * 1501 bytes are passed to the application without stripping the Pad/FCS field. * @param[in] pointer to synopGMACdevice. * \return returns void. */ #if UNUSED void synopGMAC_pad_crc_strip_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + return; } #endif /** * GMAC doesnot strips the Pad/FCS field of incoming frames. - * GMAC will pass all the incoming frames to Host unmodified. + * GMAC will pass all the incoming frames to Host unmodified. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); - u32 status = synopGMACReadReg(gmacdev->MacBase, GmacConfig); - DEBUG_MES("strips status : %u\n", status & GmacPadCrcStrip); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacPadCrcStrip); + u32 status = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + DEBUG_MES("strips status : %u\n", status & GmacPadCrcStrip); + return; } /** * GMAC programmed with the back off limit value. @@ -503,30 +503,30 @@ void synopGMAC_pad_crc_strip_disable(synopGMACdevice * gmacdev) */ void synopGMAC_back_off_limit(synopGMACdevice * gmacdev, u32 value) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase, GmacConfig); - data &= (~GmacBackoffLimit); - data |= value; - synopGMACWriteReg(gmacdev->MacBase, GmacConfig,data); - return; + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacConfig); + data &= (~GmacBackoffLimit); + data |= value; + synopGMACWriteReg(gmacdev->MacBase, GmacConfig,data); + return; } /** * Enables the Deferral check in GMAC (Only in Half Duplex mode) - * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the + * GMAC issues a Frame Abort Status, along with the excessive deferral error bit set in the * transmit frame status when transmit state machine is deferred for more than - * - 24,288 bit times in 10/100Mbps mode - * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. + * - 24,288 bit times in 10/100Mbps mode + * - 155,680 bit times in 1000Mbps mode or Jumbo frame mode in 10/100Mbps operation. * @param[in] pointer to synopGMACdevice. * \return returns void. * \note Deferral begins when transmitter is ready to transmit, but is prevented because of - * an active CRS (carrier sense) + * an active CRS (carrier sense) */ #if UNUSED void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; } #endif /** @@ -537,8 +537,8 @@ void synopGMAC_deferral_check_enable(synopGMACdevice * gmacdev) */ void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacDeferralCheck); + return; } /** * Enable the reception of frames on GMII/MII. @@ -547,8 +547,8 @@ void synopGMAC_deferral_check_disable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRx); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; } /** * Disable the reception of frames on GMII/MII. @@ -559,8 +559,8 @@ void synopGMAC_rx_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_rx_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRx); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacRx); + return; } #endif /** @@ -570,8 +570,8 @@ void synopGMAC_rx_disable(synopGMACdevice * gmacdev) */ void synopGMAC_tx_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacTx); - return; + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; } /** * Disable the transmission of frames on GMII/MII. @@ -582,8 +582,8 @@ void synopGMAC_tx_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_tx_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacTx); - return; + synopGMACClearBits(gmacdev->MacBase, GmacConfig, GmacTx); + return; } #endif @@ -599,20 +599,20 @@ void synopGMAC_tx_disable(synopGMACdevice * gmacdev) */ void synopGMAC_frame_filter_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; } /** * Disables reception of all the frames to application. - * GMAC passes only those received frames to application which + * GMAC passes only those received frames to application which * pass SA/DA address filtering. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacFilter); + return; } /** @@ -620,13 +620,13 @@ void synopGMAC_frame_filter_disable(synopGMACdevice * gmacdev) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table high register. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data) { - synopGMACWriteReg(gmacdev->MacBase,GmacHashHigh,data); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacHashHigh,data); + return; } #endif @@ -635,71 +635,71 @@ void synopGMAC_write_hash_table_high(synopGMACdevice * gmacdev, u32 data) * This function is called when the Hash filtering is to be enabled. * @param[in] pointer to synopGMACdevice. * @param[in] data to be written to hash table low register. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_write_hash_table_low(synopGMACdevice * gmacdev, u32 data) { - synopGMACWriteReg(gmacdev->MacBase,GmacHashLow,data); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacHashLow,data); + return; } #endif /** * Enables Hash or Perfect filter (only if Hash filter is enabled in H/W). - * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC + * Only frames matching either perfect filtering or Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_hash_perfect_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; } #endif /** * Enables only Hash(only if Hash filter is enabled in H/W). - * Only frames matching Hash Filtering as per HMC and HUC + * Only frames matching Hash Filtering as per HMC and HUC * configuration are sent to application. * @param[in] pointer to synopGMACdevice. - * \return void. + * \return void. */ #if UNUSED void synopGMAC_Hash_filter_only_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacHashPerfectFilter); + return; } #endif /** * Enables Source address filtering. - * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with - * SAMatch bit of RxStatus is set. GMAC drops failed frames. + * When enabled source address filtering is performed. Only frames matching SA filtering are passed to application with + * SAMatch bit of RxStatus is set. GMAC drops failed frames. * @param[in] pointer to synopGMACdevice. * \return void. - * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) + * \note This function is overriden by synopGMAC_frame_filter_disable(synopGMACdevice *) */ #if UNUSED void synopGMAC_src_addr_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; } #endif /** * Disables Source address filtering. - * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. + * When disabled GMAC forwards the received frames with updated SAMatch bit in RxStatus. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacSrcAddrFilter); + return; } /** * Enables Inverse Destination address filtering. @@ -709,8 +709,8 @@ void synopGMAC_src_addr_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; } #endif /** @@ -720,8 +720,8 @@ void synopGMAC_dst_addr_filter_inverse(synopGMACdevice * gmacdev) */ void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacDestAddrFilterNor); + return; } /** @@ -732,13 +732,13 @@ void synopGMAC_dst_addr_filter_normal(synopGMACdevice * gmacdev) * \note Depends on RFE of FlowControlRegister[2] */ void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol) -{ - u32 data; - data = synopGMACReadReg(gmacdev->MacBase, GmacFrameFilter); - data &= (~GmacPassControl); - data |= passcontrol; - synopGMACWriteReg(gmacdev->MacBase,GmacFrameFilter,data); - return; +{ + u32 data; + data = synopGMACReadReg(gmacdev->MacBase, GmacFrameFilter); + data &= (~GmacPassControl); + data |= passcontrol; + synopGMACWriteReg(gmacdev->MacBase,GmacFrameFilter,data); + return; } /** @@ -749,8 +749,8 @@ void synopGMAC_set_pass_control(synopGMACdevice * gmacdev,u32 passcontrol) */ void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast ); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast ); + return; } /** * Disable Broadcast frames. @@ -761,8 +761,8 @@ void synopGMAC_broadcast_enable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacBroadcast); + return; } #endif @@ -775,8 +775,8 @@ void synopGMAC_broadcast_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_multicast_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; } #endif /** @@ -787,8 +787,8 @@ void synopGMAC_multicast_enable(synopGMACdevice * gmacdev) */ void synopGMAC_multicast_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMulticastFilter); + return; } /** @@ -800,21 +800,21 @@ void synopGMAC_multicast_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_multicast_hash_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for multicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacMcastHashFilter); + return; } /** @@ -827,8 +827,8 @@ void synopGMAC_multicast_hash_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_promisc_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; } #endif /** @@ -839,8 +839,8 @@ void synopGMAC_promisc_enable(synopGMACdevice * gmacdev) */ void synopGMAC_promisc_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacPromiscuousMode); + return; } @@ -853,23 +853,23 @@ void synopGMAC_promisc_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_unicast_hash_filter_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; } #endif /** * Disables multicast hash filtering. - * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares + * When disabled GMAC performs perfect destination address filtering for unicast frames, it compares * DA field with the value programmed in DA register. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFrameFilter, GmacUcastHashFilter); + return; } - + /*Flow control configuration functions*/ /** @@ -882,8 +882,8 @@ void synopGMAC_unicast_hash_filter_disable(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; } #endif /** @@ -894,8 +894,8 @@ void synopGMAC_unicast_pause_frame_detect_enable(synopGMACdevice * gmacdev) */ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacUnicastPauseFrame); + return; } /** * Rx flow control enable. @@ -905,8 +905,8 @@ void synopGMAC_unicast_pause_frame_detect_disable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; } /** * Rx flow control disable. @@ -916,60 +916,60 @@ void synopGMAC_rx_flow_control_enable(synopGMACdevice * gmacdev) */ void synopGMAC_rx_flow_control_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacRxFlowControl); + return; } /** * Tx flow control enable. - * When Enabled - * - In full duplex GMAC enables flow control operation to transmit pause frames. - * - In Half duplex GMAC enables the back pressure operation + * When Enabled + * - In full duplex GMAC enables flow control operation to transmit pause frames. + * - In Half duplex GMAC enables the back pressure operation * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_tx_flow_control_enable(synopGMACdevice * gmacdev) { - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; } /** * Tx flow control disable. - * When Disabled - * - In full duplex GMAC will not transmit any pause frames. - * - In Half duplex GMAC disables the back pressure feature. + * When Disabled + * - In full duplex GMAC will not transmit any pause frames. + * - In Half duplex GMAC disables the back pressure feature. * @param[in] pointer to synopGMACdevice. * \return void. */ void synopGMAC_tx_flow_control_disable(synopGMACdevice * gmacdev) { - synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); - return; + synopGMACClearBits(gmacdev->MacBase, GmacFlowControl, GmacTxFlowControl); + return; } /** * Initiate Flowcontrol operation. * When Set - * - In full duplex GMAC initiates pause control frame. - * - In Half duplex GMAC initiates back pressure function. + * - In full duplex GMAC initiates pause control frame. + * - In Half duplex GMAC initiates back pressure function. * @param[in] pointer to synopGMACdevice. * \return void. */ #if UNUSED void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev) { - //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that + //In case of full duplex check for this bit to b'0. if it is read as b'1 indicates that //control frame transmission is in progress. - if(gmacdev->Speed == FULLDUPLEX){ - if(!synopGMACCheckBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } - else{ //if half duplex mode - - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } + if(gmacdev->Speed == FULLDUPLEX){ + if(!synopGMACCheckBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure)) + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + else{ //if half duplex mode - return; + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + + return; } #endif @@ -981,11 +981,11 @@ void synopGMAC_tx_activate_flow_control(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev) { - //In full duplex this bit is automatically cleared after transmitting a pause control frame. - if(gmacdev->Speed == HALFDUPLEX){ - synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); - } - return; + //In full duplex this bit is automatically cleared after transmitting a pause control frame. + if(gmacdev->Speed == HALFDUPLEX){ + synopGMACSetBits(gmacdev->MacBase, GmacFlowControl, GmacFlowControlBackPressure); + } + return; } #endif @@ -998,17 +998,17 @@ void synopGMAC_tx_deactivate_flow_control(synopGMACdevice * gmacdev) */ void synopGMAC_pause_control(synopGMACdevice *gmacdev) { - u32 omr_reg; - u32 mac_flow_control_reg; - omr_reg = synopGMACReadReg(gmacdev->DmaBase,DmaControl); - omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K |DmaEnHwFlowCtrl; - synopGMACWriteReg(gmacdev->DmaBase, DmaControl, omr_reg); + u32 omr_reg; + u32 mac_flow_control_reg; + omr_reg = synopGMACReadReg(gmacdev->DmaBase,DmaControl); + omr_reg |= DmaRxFlowCtrlAct4K | DmaRxFlowCtrlDeact5K |DmaEnHwFlowCtrl; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl, omr_reg); - mac_flow_control_reg = synopGMACReadReg(gmacdev->MacBase,GmacFlowControl); - mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; - synopGMACWriteReg(gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg); + mac_flow_control_reg = synopGMACReadReg(gmacdev->MacBase,GmacFlowControl); + mac_flow_control_reg |= GmacRxFlowControl | GmacTxFlowControl | 0xFFFF0000; + synopGMACWriteReg(gmacdev->MacBase,GmacFlowControl,mac_flow_control_reg); - return; + return; } @@ -1021,126 +1021,126 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev) */ s32 synopGMAC_mac_init(synopGMACdevice * gmacdev) { - u32 PHYreg; - - if(gmacdev->DuplexMode == FULLDUPLEX){ - TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug - synopGMAC_wd_enable(gmacdev); - synopGMAC_jab_enable(gmacdev); - synopGMAC_frame_burst_enable(gmacdev); - synopGMAC_jumbo_frame_disable(gmacdev); - synopGMAC_rx_own_enable(gmacdev); -#if SYNOP_LOOPBACK_MODE - synopGMAC_loopback_on(gmacdev); -#else - synopGMAC_loopback_off(gmacdev); -#endif - synopGMAC_set_full_duplex(gmacdev); //1 - synopGMAC_retry_enable(gmacdev); - synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); - synopGMAC_deferral_check_disable(gmacdev); - - synopGMAC_tx_enable(gmacdev); //according to Tang Dan's commitment - synopGMAC_rx_enable(gmacdev); + u32 PHYreg; - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward );//3 - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); - if(gmacdev->Speed == SPEED1000) - synopGMAC_select_gmii(gmacdev); - else{ - synopGMAC_select_mii(gmacdev); - if(gmacdev->Speed == SPEED100) - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); - else - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10); - } - - - /*Frame Filter Configuration*/ - synopGMAC_frame_filter_enable(gmacdev); //2 - //synopGMAC_frame_filter_disable(gmacdev); //2 - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); - synopGMAC_broadcast_enable(gmacdev); - synopGMAC_src_addr_filter_disable(gmacdev); - synopGMAC_multicast_disable(gmacdev); - //synopGMAC_dst_addr_filter_normal(gmacdev); //scl - synopGMAC_dst_addr_filter_inverse(gmacdev); - synopGMAC_multicast_hash_filter_disable(gmacdev); - synopGMAC_promisc_disable(gmacdev); - synopGMAC_unicast_hash_filter_disable(gmacdev); - - /*Flow Control Configuration*/ - synopGMAC_unicast_pause_frame_detect_disable(gmacdev); - synopGMAC_rx_flow_control_enable(gmacdev); - synopGMAC_tx_flow_control_enable(gmacdev); - } - else{//for Half Duplex configuration - - TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug - synopGMAC_wd_enable(gmacdev ); - synopGMAC_jab_enable(gmacdev); - synopGMAC_frame_burst_enable(gmacdev); - synopGMAC_jumbo_frame_disable(gmacdev); - synopGMAC_rx_own_enable(gmacdev); + if(gmacdev->DuplexMode == FULLDUPLEX){ + TR("\n===phy FULLDUPLEX MODE\n"); //sw: debug + synopGMAC_wd_enable(gmacdev); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); #if SYNOP_LOOPBACK_MODE - synopGMAC_loopback_on(gmacdev); + synopGMAC_loopback_on(gmacdev); #else - synopGMAC_loopback_off(gmacdev); + synopGMAC_loopback_off(gmacdev); #endif - synopGMAC_set_half_duplex(gmacdev); - synopGMAC_retry_enable(gmacdev); - synopGMAC_pad_crc_strip_disable(gmacdev); - synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); - synopGMAC_deferral_check_disable(gmacdev); + synopGMAC_set_full_duplex(gmacdev); //1 + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); + + synopGMAC_tx_enable(gmacdev); //according to Tang Dan's commitment + synopGMAC_rx_enable(gmacdev); + + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward );//3 + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else{ + synopGMAC_select_mii(gmacdev); + if(gmacdev->Speed == SPEED100) + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100); + else + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10); + } + + + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); //2 + //synopGMAC_frame_filter_disable(gmacdev); //2 + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + //synopGMAC_dst_addr_filter_normal(gmacdev); //scl + synopGMAC_dst_addr_filter_inverse(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + synopGMAC_promisc_disable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); + + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_enable(gmacdev); + synopGMAC_tx_flow_control_enable(gmacdev); + } + else{//for Half Duplex configuration + + TR("\n===phy HALFDUPLEX MODE\n"); //sw: debug + synopGMAC_wd_enable(gmacdev ); + synopGMAC_jab_enable(gmacdev); + synopGMAC_frame_burst_enable(gmacdev); + synopGMAC_jumbo_frame_disable(gmacdev); + synopGMAC_rx_own_enable(gmacdev); +#if SYNOP_LOOPBACK_MODE + synopGMAC_loopback_on(gmacdev); +#else + synopGMAC_loopback_off(gmacdev); +#endif + synopGMAC_set_half_duplex(gmacdev); + synopGMAC_retry_enable(gmacdev); + synopGMAC_pad_crc_strip_disable(gmacdev); + synopGMAC_back_off_limit(gmacdev,GmacBackoffLimit0); + synopGMAC_deferral_check_disable(gmacdev); //sw: set efe & tsf - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward ); - synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaStoreAndForward ); + synopGMACSetBits(gmacdev->DmaBase,DmaControl, DmaFwdErrorFrames ); //sw: put it in the end - synopGMAC_tx_enable(gmacdev); - synopGMAC_rx_enable(gmacdev); + synopGMAC_tx_enable(gmacdev); + synopGMAC_rx_enable(gmacdev); - if(gmacdev->Speed == SPEED1000) - synopGMAC_select_gmii(gmacdev); - else{ - synopGMAC_select_mii(gmacdev ); - if(gmacdev->Speed == SPEED100) - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100 ); - else - synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10 ); - } - -// synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); -// synopGMAC_select_gmii(gmacdev); + if(gmacdev->Speed == SPEED1000) + synopGMAC_select_gmii(gmacdev); + else{ + synopGMAC_select_mii(gmacdev ); + if(gmacdev->Speed == SPEED100) + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed100 ); + else + synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacFESpeed10 ); + } - /*Frame Filter Configuration*/ - synopGMAC_frame_filter_enable(gmacdev); -// synopGMAC_frame_filter_disable(gmacdev); +// synopGMACSetBits(gmacdev->MacBase, GmacConfig, GmacDisableCrs); +// synopGMAC_select_gmii(gmacdev); - synopGMAC_set_pass_control(gmacdev,GmacPassControl0); - synopGMAC_broadcast_enable(gmacdev); - synopGMAC_src_addr_filter_disable(gmacdev); - synopGMAC_multicast_disable(gmacdev); - synopGMAC_dst_addr_filter_normal(gmacdev); - synopGMAC_multicast_hash_filter_disable(gmacdev); + /*Frame Filter Configuration*/ + synopGMAC_frame_filter_enable(gmacdev); +// synopGMAC_frame_filter_disable(gmacdev); + + synopGMAC_set_pass_control(gmacdev,GmacPassControl0); + synopGMAC_broadcast_enable(gmacdev); + synopGMAC_src_addr_filter_disable(gmacdev); + synopGMAC_multicast_disable(gmacdev); + synopGMAC_dst_addr_filter_normal(gmacdev); + synopGMAC_multicast_hash_filter_disable(gmacdev); + + synopGMAC_promisc_disable(gmacdev); +// synopGMAC_promisc_enable(gmacdev); + synopGMAC_unicast_hash_filter_disable(gmacdev); - synopGMAC_promisc_disable(gmacdev); -// synopGMAC_promisc_enable(gmacdev); - synopGMAC_unicast_hash_filter_disable(gmacdev); - //sw: loopback mode -// synopGMAC_loopback_on(gmacdev); - - /*Flow Control Configuration*/ - synopGMAC_unicast_pause_frame_detect_disable(gmacdev); - synopGMAC_rx_flow_control_disable(gmacdev); - synopGMAC_tx_flow_control_disable(gmacdev); +// synopGMAC_loopback_on(gmacdev); - /*To set PHY register to enable CRS on Transmit*/ - } - return 0; + /*Flow Control Configuration*/ + synopGMAC_unicast_pause_frame_detect_disable(gmacdev); + synopGMAC_rx_flow_control_disable(gmacdev); + synopGMAC_tx_flow_control_disable(gmacdev); + + /*To set PHY register to enable CRS on Transmit*/ + } + return 0; } @@ -1155,14 +1155,14 @@ s32 synopGMAC_mac_init(synopGMACdevice * gmacdev) */ s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { - u32 data; + u32 data; - data = (MacAddr[5] << 8) | MacAddr[4]; - synopGMACWriteReg(gmacdev->MacBase,MacHigh,data); - data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; - synopGMACWriteReg(gmacdev->MacBase,MacLow,data); + data = (MacAddr[5] << 8) | MacAddr[4]; + synopGMACWriteReg(gmacdev->MacBase,MacHigh,data); + data = (MacAddr[3] << 24) | (MacAddr[2] << 16) | (MacAddr[1] << 8) | MacAddr[0] ; + synopGMACWriteReg(gmacdev->MacBase,MacLow,data); - return 0; + return 0; } @@ -1177,21 +1177,21 @@ s32 synopGMAC_set_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 */ s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 *MacAddr) { - u32 data; - - data = synopGMACReadReg(gmacdev->MacBase,MacHigh); - MacAddr[5] = (data >> 8) & 0xff; - MacAddr[4] = (data) & 0xff; + u32 data; - data = synopGMACReadReg(gmacdev->MacBase,MacLow); - MacAddr[3] = (data >> 24) & 0xff; - MacAddr[2] = (data >> 16) & 0xff; - MacAddr[1] = (data >> 8 ) & 0xff; - MacAddr[0] = (data ) & 0xff; + data = synopGMACReadReg(gmacdev->MacBase,MacHigh); + MacAddr[5] = (data >> 8) & 0xff; + MacAddr[4] = (data) & 0xff; -// rt_kprintf("MacAddr = 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); + data = synopGMACReadReg(gmacdev->MacBase,MacLow); + MacAddr[3] = (data >> 24) & 0xff; + MacAddr[2] = (data >> 16) & 0xff; + MacAddr[1] = (data >> 8 ) & 0xff; + MacAddr[0] = (data ) & 0xff; - return 0; +// rt_kprintf("MacAddr = 0x%x\t0x%x\t0x%x\t0x%x\t0x%x\t0x%x\n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); + + return 0; } @@ -1203,42 +1203,42 @@ s32 synopGMAC_get_mac_addr(synopGMACdevice *gmacdev, u32 MacHigh, u32 MacLow, u8 * @param[in] GMAC IP dma base address. * @param[in] GMAC IP phy base address. * \return 0 upon success. Error code upon failure. - * \note This is important function. No kernel api provided by Synopsys + * \note This is important function. No kernel api provided by Synopsys */ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 phyBase,u8 *mac_addr) { - /*Make sure the Device data strucure is cleared before we proceed further*/ - rt_memset((void *) gmacdev,0,sizeof(synopGMACdevice)); - /*Populate the mac and dma base addresses*/ - gmacdev->MacBase = macBase; - gmacdev->DmaBase = dmaBase; - gmacdev->PhyBase = phyBase; -// rt_kprintf("gmacdev->DmaBase = 0x%x\n", gmacdev->DmaBase); -// rt_kprintf("dmaBase = 0x%x\n", dmaBase); - { - int i,j; - u16 data; - for (i = phyBase,j=0;j<32;i=(i+1)&0x1f,j++) - { - synopGMAC_read_phy_reg(gmacdev->MacBase,i,2,&data); - if(data != 0 && data != 0xffff) break; - synopGMAC_read_phy_reg(gmacdev->MacBase,i,3,&data); - if(data != 0 && data != 0xffff) break; - } + /*Make sure the Device data strucure is cleared before we proceed further*/ + rt_memset((void *) gmacdev,0,sizeof(synopGMACdevice)); + /*Populate the mac and dma base addresses*/ + gmacdev->MacBase = macBase; + gmacdev->DmaBase = dmaBase; + gmacdev->PhyBase = phyBase; +// rt_kprintf("gmacdev->DmaBase = 0x%x\n", gmacdev->DmaBase); +// rt_kprintf("dmaBase = 0x%x\n", dmaBase); + { + int i,j; + u16 data; + for (i = phyBase,j=0;j<32;i=(i+1)&0x1f,j++) + { + synopGMAC_read_phy_reg(gmacdev->MacBase,i,2,&data); + if(data != 0 && data != 0xffff) break; + synopGMAC_read_phy_reg(gmacdev->MacBase,i,3,&data); + if(data != 0 && data != 0xffff) break; + } - if(j==32) { - rt_kprintf("phy_detect: can't find PHY!\n"); - } - gmacdev->PhyBase = i; - } + if(j==32) { + rt_kprintf("phy_detect: can't find PHY!\n"); + } + gmacdev->PhyBase = i; + } -// synopGMAC_get_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); +// synopGMAC_get_mac_addr(gmacdev, GmacAddr0High, GmacAddr0Low, mac_addr); - /* Program/flash in the station/IP's Mac address */ - synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr); + /* Program/flash in the station/IP's Mac address */ + synopGMAC_set_mac_addr(gmacdev,GmacAddr0High,GmacAddr0Low, mac_addr); - return 0; + return 0; } @@ -1246,10 +1246,10 @@ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 p /** * Initialize the rx descriptors for ring or chain mode operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) - * - data1 and data2 set to 0. (note) + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1258,36 +1258,36 @@ s32 synopGMAC_attach (synopGMACdevice * gmacdev, u32 macBase, u32 dmaBase, u32 p */ void synopGMAC_rx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { - desc->status = 0; - desc->length = last_ring_desc ? RxDescEndOfRing : 0; - desc->buffer1 = 0; - desc->buffer2 = 0; - desc->data1 = 0; - desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; + desc->status = 0; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + desc->buffer1 = 0; + desc->buffer2 = 0; + desc->data1 = 0; + desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; - return; + return; } void synopGMAC_rx_desc_recycle(DmaDesc *desc, bool last_ring_desc) { - desc->status = DescOwnByDma; - desc->length = last_ring_desc ? RxDescEndOfRing : 0; - //desc->buffer1 = 0; - //desc->buffer2 = 0; - //desc->data1 = 0; - //desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; + desc->status = DescOwnByDma; + desc->length = last_ring_desc ? RxDescEndOfRing : 0; + //desc->buffer1 = 0; + //desc->buffer2 = 0; + //desc->data1 = 0; + //desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; - return; + return; } /** * Initialize the tx descriptors for ring or chain mode operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) - * - data1 and data2 set to 0. (note) + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0 for ring mode of operation. (note) + * - data1 and data2 set to 0. (note) * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1296,32 +1296,32 @@ void synopGMAC_rx_desc_recycle(DmaDesc *desc, bool last_ring_desc) */ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) { - #ifdef ENH_DESC - desc->status = last_ring_desc? TxDescEndOfRing : 0; - desc->length = 0; - #else - desc->length = last_ring_desc? TxDescEndOfRing : 0; - #endif -//sw - desc->status = 0; + #ifdef ENH_DESC + desc->status = last_ring_desc? TxDescEndOfRing : 0; + desc->length = 0; + #else + desc->length = last_ring_desc? TxDescEndOfRing : 0; + #endif +//sw + desc->status = 0; - desc->buffer1 = 0; - desc->buffer2 = 0; - desc->data1 = 0; - desc->data2 = 0; - desc->dummy1 = 0; - desc->dummy2 = 0; - return; + desc->buffer1 = 0; + desc->buffer2 = 0; + desc->data1 = 0; + desc->data2 = 0; + desc->dummy1 = 0; + desc->dummy2 = 0; + return; } /** * Initialize the rx descriptors for chain mode of operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0. - * - data1 and data2 set to 0. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0. + * - data1 and data2 set to 0. * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. @@ -1329,86 +1329,86 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc) void synopGMAC_rx_desc_init_chain(DmaDesc * desc) { - desc->status = 0; - desc->length = RxDescChain; - desc->buffer1 = 0; - desc->data1 = 0; - return; + desc->status = 0; + desc->length = RxDescChain; + desc->buffer1 = 0; + desc->data1 = 0; + return; } /** * Initialize the rx descriptors for chain mode of operation. - * - Status field is initialized to 0. - * - EndOfRing set for the last descriptor. - * - buffer1 and buffer2 set to 0. - * - data1 and data2 set to 0. + * - Status field is initialized to 0. + * - EndOfRing set for the last descriptor. + * - buffer1 and buffer2 set to 0. + * - data1 and data2 set to 0. * @param[in] pointer to DmaDesc structure. * @param[in] whether end of ring * \return void. */ void synopGMAC_tx_desc_init_chain(DmaDesc * desc) { - #ifdef ENH_DESC - desc->status = TxDescChain; - desc->length = 0; - #else - desc->length = TxDescChain; - #endif - desc->buffer1 = 0; - desc->data1 = 0; - return; + #ifdef ENH_DESC + desc->status = TxDescChain; + desc->length = 0; + #else + desc->length = TxDescChain; + #endif + desc->buffer1 = 0; + desc->data1 = 0; + return; } s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev) { - s32 i; - for(i =0; i < gmacdev -> TxDescCount; i++){ - synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); - } - TR("At line %d\n",__LINE__); - for(i =0; i < gmacdev -> RxDescCount; i++){ - synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); - } - - gmacdev->TxNext = 0; - gmacdev->TxBusy = 0; - gmacdev->RxNext = 0; - gmacdev->RxBusy = 0; - - return -ESYNOPGMACNOERR; + s32 i; + for(i =0; i < gmacdev -> TxDescCount; i++){ + synopGMAC_tx_desc_init_ring(gmacdev->TxDesc + i, i == gmacdev->TxDescCount-1); + } + TR("At line %d\n",__LINE__); + for(i =0; i < gmacdev -> RxDescCount; i++){ + synopGMAC_rx_desc_init_ring(gmacdev->RxDesc + i, i == gmacdev->RxDescCount-1); + } + + gmacdev->TxNext = 0; + gmacdev->TxBusy = 0; + gmacdev->RxNext = 0; + gmacdev->RxBusy = 0; + + return -ESYNOPGMACNOERR; } /** * Programs the DmaRxBaseAddress with the Rx descriptor base address. - * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Rx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Rx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_rx_desc_base(synopGMACdevice *gmacdev) { - DEBUG_MES("gmacdev->RxDescDma = %08x\n", gmacdev->RxDescDma); - synopGMACWriteReg(gmacdev->DmaBase,DmaRxBaseAddr,(u32)gmacdev->RxDescDma ); - return; + DEBUG_MES("gmacdev->RxDescDma = %08x\n", gmacdev->RxDescDma); + synopGMACWriteReg(gmacdev->DmaBase,DmaRxBaseAddr,(u32)gmacdev->RxDescDma ); + return; } /** * Programs the DmaTxBaseAddress with the Tx descriptor base address. - * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the + * Tx Descriptor's base address is available in the gmacdev structure. This function progrms the * Dma Tx Base address with the starting address of the descriptor ring or chain. * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_init_tx_desc_base(synopGMACdevice *gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase,DmaTxBaseAddr,(u32)gmacdev->TxDescDma); - return; + synopGMACWriteReg(gmacdev->DmaBase,DmaTxBaseAddr,(u32)gmacdev->TxDescDma); + return; } -/** +/** * Makes the Dma as owner for this descriptor. * This function sets the own bit of status field of the DMA descriptor, - * indicating the DMA is the owner for this descriptor. + * indicating the DMA is the owner for this descriptor. * @param[in] pointer to DmaDesc structure. * \return returns void. */ @@ -1417,7 +1417,7 @@ void synopGMAC_set_owner_dma(DmaDesc *desc) desc->status |= DescOwnByDma; } -/** +/** * set tx descriptor to indicate SOF. * This Descriptor contains the start of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1433,7 +1433,7 @@ desc->length |= DescTxFirst; } -/** +/** * set tx descriptor to indicate EOF. * This descriptor contains the End of ethernet frame. * @param[in] pointer to DmaDesc structure. @@ -1449,51 +1449,51 @@ desc->length |= DescTxLast; } -/** +/** * checks whether this descriptor contains start of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains a fresh ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_sof_in_rx_desc(DmaDesc *desc) { -return ((desc->status & DescRxFirst) == DescRxFirst); +return ((desc->status & DescRxFirst) == DescRxFirst); } -/** +/** * checks whether this descriptor contains end of frame. - * This function is to check whether the descriptor's data buffer + * This function is to check whether the descriptor's data buffer * contains end of ethernet frame? * @param[in] pointer to DmaDesc structure. * \return returns true if SOF in current descriptor, else returns fail. */ bool synopGMAC_is_eof_in_rx_desc(DmaDesc *desc) { -return ((desc->status & DescRxLast) == DescRxLast); +return ((desc->status & DescRxLast) == DescRxLast); } -/** +/** * checks whether destination address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_da_filter_failed(DmaDesc *desc) { -return ((desc->status & DescDAFilterFail) == DescDAFilterFail); +return ((desc->status & DescDAFilterFail) == DescDAFilterFail); } -/** +/** * checks whether source address filter failed in the rx frame. * @param[in] pointer to DmaDesc structure. * \return returns true if Failed, false if not. */ bool synopGMAC_is_sa_filter_failed(DmaDesc *desc) { -return ((desc->status & DescSAFilterFail) == DescSAFilterFail); +return ((desc->status & DescSAFilterFail) == DescSAFilterFail); } -/** +/** * Checks whether the descriptor is owned by DMA. * If descriptor is owned by DMA then the OWN bit is set to 1. This API is same for both ring and chain mode. * @param[in] pointer to DmaDesc structure. @@ -1512,7 +1512,7 @@ return ((desc->status & DescOwnByDma) == DescOwnByDma ); */ u32 synopGMAC_get_rx_desc_frame_length(u32 status) { - return ((status & DescFrameLengthMask) >> DescFrameLengthShift); + return ((status & DescFrameLengthMask) >> DescFrameLengthShift); } /** @@ -1524,7 +1524,7 @@ u32 synopGMAC_get_rx_desc_frame_length(u32 status) */ bool synopGMAC_is_desc_valid(u32 status) { - return ((status & DescError) == 0); + return ((status & DescError) == 0); } /** @@ -1536,8 +1536,8 @@ bool synopGMAC_is_desc_valid(u32 status) */ bool synopGMAC_is_desc_empty(DmaDesc *desc) { - //if both the buffer1 length and buffer2 length are zero desc is empty - return(((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0) ); + //if both the buffer1 length and buffer2 length are zero desc is empty + return(((desc->length & DescSize1Mask) == 0) && ((desc->length & DescSize2Mask) == 0) ); } @@ -1549,7 +1549,7 @@ bool synopGMAC_is_desc_empty(DmaDesc *desc) */ bool synopGMAC_is_rx_desc_valid(u32 status) { - return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); + return ((status & DescError) == 0) && ((status & DescRxFirst) == DescRxFirst) && ((status & DescRxLast) == DescRxLast); } /** @@ -1559,7 +1559,7 @@ bool synopGMAC_is_rx_desc_valid(u32 status) */ bool synopGMAC_is_tx_aborted(u32 status) { - return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); + return (((status & DescTxLateCollision) == DescTxLateCollision) | ((status & DescTxExcCollisions) == DescTxExcCollisions)); } @@ -1570,7 +1570,7 @@ bool synopGMAC_is_tx_aborted(u32 status) */ bool synopGMAC_is_tx_carrier_error(u32 status) { - return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); + return (((status & DescTxLostCarrier) == DescTxLostCarrier) | ((status & DescTxNoCarrier) == DescTxNoCarrier)); } @@ -1583,11 +1583,11 @@ bool synopGMAC_is_tx_carrier_error(u32 status) */ u32 synopGMAC_get_tx_collision_count(u32 status) { - return ((status & DescTxCollMask) >> DescTxCollShift); + return ((status & DescTxCollMask) >> DescTxCollShift); } u32 synopGMAC_is_exc_tx_collisions(u32 status) { - return ((status & DescTxExcCollisions) == DescTxExcCollisions); + return ((status & DescTxExcCollisions) == DescTxExcCollisions); } @@ -1600,7 +1600,7 @@ u32 synopGMAC_is_exc_tx_collisions(u32 status) bool synopGMAC_is_rx_frame_damaged(u32 status) { //bool synopGMAC_dma_rx_collisions(u32 status) - return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); + return (((status & DescRxDamaged) == DescRxDamaged) | ((status & DescRxCollision) == DescRxCollision)); } /** @@ -1612,7 +1612,7 @@ bool synopGMAC_is_rx_frame_damaged(u32 status) bool synopGMAC_is_rx_frame_collision(u32 status) { //bool synopGMAC_dma_rx_collisions(u32 status) - return ((status & DescRxCollision) == DescRxCollision); + return ((status & DescRxCollision) == DescRxCollision); } /** @@ -1624,7 +1624,7 @@ bool synopGMAC_is_rx_frame_collision(u32 status) bool synopGMAC_is_rx_crc(u32 status) { //u32 synopGMAC_dma_rx_crc(u32 status) - return ((status & DescRxCrc) == DescRxCrc); + return ((status & DescRxCrc) == DescRxCrc); } /** @@ -1636,7 +1636,7 @@ bool synopGMAC_is_rx_crc(u32 status) bool synopGMAC_is_frame_dribbling_errors(u32 status) { //u32 synopGMAC_dma_rx_frame_errors(u32 status) - return ((status & DescRxDribbling) == DescRxDribbling); + return ((status & DescRxDribbling) == DescRxDribbling); } /** @@ -1648,7 +1648,7 @@ bool synopGMAC_is_frame_dribbling_errors(u32 status) bool synopGMAC_is_rx_frame_length_errors(u32 status) { //u32 synopGMAC_dma_rx_length_errors(u32 status) - return((status & DescRxLengthError) == DescRxLengthError); + return((status & DescRxLengthError) == DescRxLengthError); } /** @@ -1677,9 +1677,9 @@ bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) { //bool synopGMAC_is_last_desc(DmaDesc *desc) #ifdef ENH_DESC - return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); + return (((desc->status & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); #else - return (((desc->length & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); + return (((desc->length & TxDescEndOfRing) == TxDescEndOfRing) || ((u32)gmacdev->TxDesc == desc->data2)); #endif } @@ -1691,7 +1691,7 @@ bool synopGMAC_is_last_tx_desc(synopGMACdevice * gmacdev,DmaDesc *desc) */ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc) { - return((desc->length & RxDescChain) == RxDescChain); + return((desc->length & RxDescChain) == RxDescChain); } /** @@ -1703,9 +1703,9 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc) bool synopGMAC_is_tx_desc_chained(DmaDesc * desc) { #ifdef ENH_DESC - return((desc->status & TxDescChain) == TxDescChain); + return((desc->status & TxDescChain) == TxDescChain); #else - return((desc->length & TxDescChain) == TxDescChain); + return((desc->length & TxDescChain) == TxDescChain); #endif } @@ -1726,24 +1726,24 @@ bool synopGMAC_is_tx_desc_chained(DmaDesc * desc) void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2) { - if(Status != 0) - *Status = desc->status; + if(Status != 0) + *Status = desc->status; - if(Buffer1 != 0) - *Buffer1 = desc->buffer1; - if(Length1 != 0) - *Length1 = (desc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = desc->data1; + if(Buffer1 != 0) + *Buffer1 = desc->buffer1; + if(Length1 != 0) + *Length1 = (desc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = desc->data1; - if(Buffer2 != 0) - *Buffer2 = desc->buffer2; - if(Length2 != 0) - *Length2 = (desc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = desc->data2; - - return; + if(Buffer2 != 0) + *Buffer2 = desc->buffer2; + if(Length2 != 0) + *Length2 = (desc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = desc->data2; + + return; } @@ -1752,7 +1752,7 @@ void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * * This function is defined two times. Once when the code is compiled for ENHANCED DESCRIPTOR SUPPORT and Once for Normal descriptor * Get the index and address of Tx desc. * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is * over. This returns the descriptor fields to the caller. * @param[in] pointer to synopGMACdevice. * @param[out] status field of the descriptor. @@ -1768,60 +1768,60 @@ void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) { - u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - - if(synopGMAC_is_desc_owned_by_dma(txdesc)) - return -1; - if(synopGMAC_is_desc_empty(txdesc)) - return -1; + u32 txover = gmacdev->TxBusy; + DmaDesc * txdesc = gmacdev->TxBusyDesc; - (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + if(synopGMAC_is_desc_owned_by_dma(txdesc)) + return -1; + if(synopGMAC_is_desc_empty(txdesc)) + return -1; - if(Status != 0) - *Status = txdesc->status; + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(Ext_Status != 0) - *Ext_Status = txdesc->extstatus; + if(Status != 0) + *Status = txdesc->status; + + if(Ext_Status != 0) + *Ext_Status = txdesc->extstatus; if(Time_Stamp_High != 0) - *Time_Stamp_High = txdesc->timestamphigh; + *Time_Stamp_High = txdesc->timestamphigh; if(Time_Stamp_Low != 0) - *Time_Stamp_High = txdesc->timestamplow; + *Time_Stamp_High = txdesc->timestamplow; - if(Buffer1 != 0) - *Buffer1 = txdesc->buffer1; - if(Length1 != 0) - *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = txdesc->data1; + if(Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if(Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = txdesc->data1; - if(Buffer2 != 0) - *Buffer2 = txdesc->buffer2; - if(Length2 != 0) - *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = txdesc->data2; + if(Buffer2 != 0) + *Buffer2 = txdesc->buffer2; + if(Length2 != 0) + *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = txdesc->data2; - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; - if(synopGMAC_is_tx_desc_chained(txdesc)){ - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; - synopGMAC_tx_desc_init_chain(txdesc); - } - else{ - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + if(synopGMAC_is_tx_desc_chained(txdesc)){ + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + synopGMAC_tx_desc_init_chain(txdesc); + } + else{ + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); - return txover; + return txover; } #else /** * Get the index and address of Tx desc. * This api is same for both ring mode and chain mode. - * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is + * This function tracks the tx descriptor the DMA just closed after the transmission of data from this descriptor is * over. This returns the descriptor fields to the caller. * @param[in] pointer to synopGMACdevice. * @param[out] status field of the descriptor. @@ -1836,74 +1836,74 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 ) { - u32 txover = gmacdev->TxBusy; - DmaDesc * txdesc = gmacdev->TxBusyDesc; - int i; - + u32 txover = gmacdev->TxBusy; + DmaDesc * txdesc = gmacdev->TxBusyDesc; + int i; + //sw: dbg - - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync before get a used tx dma desc!\n"); - printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + printf("Cache sync before get a used tx dma desc!\n"); + printf("\n==%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); #endif - if(synopGMAC_is_desc_owned_by_dma(txdesc)) - { - return -1; - } -// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; -// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - if(synopGMAC_is_desc_empty(txdesc)) - { - return -1; - } - (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + if(synopGMAC_is_desc_owned_by_dma(txdesc)) + { + return -1; + } +// gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; +// gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + if(synopGMAC_is_desc_empty(txdesc)) + { + return -1; + } + (gmacdev->BusyTxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - if(Status != 0) - *Status = txdesc->status; + if(Status != 0) + *Status = txdesc->status; - if(Buffer1 != 0) - *Buffer1 = txdesc->buffer1; - if(Length1 != 0) - *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Data1 != 0) - *Data1 = txdesc->data1; + if(Buffer1 != 0) + *Buffer1 = txdesc->buffer1; + if(Length1 != 0) + *Length1 = (txdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Data1 != 0) + *Data1 = txdesc->data1; - if(Buffer2 != 0) - *Buffer2 = txdesc->buffer2; - if(Length2 != 0) - *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Data1 != 0) - *Data2 = txdesc->data2; + if(Buffer2 != 0) + *Buffer2 = txdesc->buffer2; + if(Length2 != 0) + *Length2 = (txdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Data1 != 0) + *Data2 = txdesc->data2; - gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; + gmacdev->TxBusy = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1; - if(synopGMAC_is_tx_desc_chained(txdesc)){ - gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; - synopGMAC_tx_desc_init_chain(txdesc); - } - else{ - gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); - } - //printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + if(synopGMAC_is_tx_desc_chained(txdesc)){ + gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2; + synopGMAC_tx_desc_init_chain(txdesc); + } + else{ + gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc)); + } + //printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txover,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync after re-init a tx dma desc!\n"); + printf("Cache sync after re-init a tx dma desc!\n"); #endif - return txover; + return txover; } #endif /** * Populate the tx desc structure with the buffer address. - * Once the driver has a packet ready to be transmitted, this function is called with the + * Once the driver has a packet ready to be transmitted, this function is called with the * valid dma-able buffer addresses and their lengths. This function populates the descriptor * and make the DMA the owner for the descriptor. This function also controls whetther Checksum - * offloading to be done in hardware or not. + * offloading to be done in hardware or not. * This api is same for both ring mode and chain mode. * @param[in] pointer to synopGMACdevice. * @param[in] Dma-able buffer1 pointer. @@ -1919,98 +1919,98 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 u32 len; s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed,u32 * index, DmaDesc * Dpr) { - u32 txnext = gmacdev->TxNext; - DmaDesc * txdesc = gmacdev->TxNextDesc; + u32 txnext = gmacdev->TxNext; + DmaDesc * txdesc = gmacdev->TxNextDesc; - *index = txnext; - Dpr = txdesc; + *index = txnext; + Dpr = txdesc; - if(!synopGMAC_is_desc_empty(txdesc)) - { - TR("set tx qptr: desc empty!\n"); - return -1; - } + if(!synopGMAC_is_desc_empty(txdesc)) + { + TR("set tx qptr: desc empty!\n"); + return -1; + } - (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - - if(synopGMAC_is_tx_desc_chained(txdesc)){ - txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif + (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; + if(synopGMAC_is_tx_desc_chained(txdesc)){ + txdesc->length |= ((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); -// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); - } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else - txdesc->status = DescOwnByDma; - #endif + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; - } - else{ -// printf("synopGMAC_set_tx_qptr:in ring mode\n"); - txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC - #else - txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor - #endif + if(offload_needed){ + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); +// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else + txdesc->status = DescOwnByDma; + #endif - txdesc->buffer1 = Buffer1; - txdesc->data1 = Data1; + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2; + } + else{ +// printf("synopGMAC_set_tx_qptr:in ring mode\n"); + txdesc->length |= (((Length1 <status |= (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC + #else + txdesc->length |= (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor + #endif - txdesc->buffer2 = Buffer2; - txdesc->data2 = Data2; + txdesc->buffer1 = Buffer1; + txdesc->data1 = Data1; - if(offload_needed){ - /* - Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, - before calling any of the functions given below. - */ + txdesc->buffer2 = Buffer2; + txdesc->data2 = Data2; + + if(offload_needed){ + /* + Make sure that the OS you are running supports the IP and TCP checkusm offloaidng, + before calling any of the functions given below. + */ //sw: i am not sure about the checksum.so i omit it in the outside - synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); - synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); -// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); - } - #ifdef ENH_DESC - txdesc->status |= DescOwnByDma;//ENH_DESC - #else -// printf("synopGMAC_set_tx_qptr:give the tx descroptor to dma\n"); - txdesc->status = DescOwnByDma; - #endif + synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc); + synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc); +// synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc); + } + #ifdef ENH_DESC + txdesc->status |= DescOwnByDma;//ENH_DESC + #else +// printf("synopGMAC_set_tx_qptr:give the tx descroptor to dma\n"); + txdesc->status = DescOwnByDma; + #endif - gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; - gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); - } + gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1; + gmacdev->TxNextDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1); + } #if SYNOP_TX_DEBUG - printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); + printf("%02d %08x %08x %08x %08x %08x %08x %08x\n",txnext,(u32)txdesc,txdesc->status,txdesc->length,txdesc->buffer1,txdesc->buffer2,txdesc->data1,txdesc->data2); #endif - //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); + //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W); #if SYNOP_TX_DEBUG - printf("Cache sync to set a tx desc!\n"); + printf("Cache sync to set a tx desc!\n"); #endif - //pci_sync_cache(0, (vm_offset_t)(txdesc->data1), 32, SYNC_W); + //pci_sync_cache(0, (vm_offset_t)(txdesc->data1), 32, SYNC_W); #if SYNOP_TX_DEBUG - //printf("Cache sync for data in the buf of the tx desc!\n"); + //printf("Cache sync for data in the buf of the tx desc!\n"); #endif - return txnext; + return txnext; } #ifdef ENH_DESC_8W /** @@ -2027,62 +2027,62 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u * @param[in] u32 data indicating whether the descriptor is in ring mode or chain mode. * \return returns present rx descriptor index on success. Negative value if error. */ -// dma_addr RX_BUF_SIZE skb +// dma_addr RX_BUF_SIZE skb s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->extstatus = 0; - rxdesc->reserved1 = 0; - rxdesc->timestamplow = 0; - rxdesc->timestamphigh = 0; + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; - - rxdesc->status = DescOwnByDma; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <status = DescOwnByDma; - rxdesc->buffer1 = Buffer1; - rxdesc->data1 = Data1; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <extstatus = 0; - rxdesc->reserved1 = 0; - rxdesc->timestamplow = 0; - rxdesc->timestamphigh = 0; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + rxdesc->extstatus = 0; + rxdesc->reserved1 = 0; + rxdesc->timestamplow = 0; + rxdesc->timestamphigh = 0; - rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; + + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; + + rxdesc->status = DescOwnByDma; + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2,rxdesc->dummy1,rxdesc->dummy2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2,rxdesc->dummy1,rxdesc->dummy2); #endif - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - //pci_sync_cache(0, (vm_offset_t)rxdesc,64, SYNC_W); - return rxnext; + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + //pci_sync_cache(0, (vm_offset_t)rxdesc,64, SYNC_W); + return rxnext; } #else @@ -2102,100 +2102,100 @@ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u */ s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - rxdesc->status = DescOwnByDma; + rxdesc->status = DescOwnByDma; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; - rxdesc->status = DescOwnByDma; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } + rxdesc->status = DescOwnByDma; + + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } #if SYNOP_RX_DEBUG - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - return rxnext; + return rxnext; } s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2) { - u32 rxnext = gmacdev->RxNext; - DmaDesc * rxdesc = gmacdev->RxNextDesc; + u32 rxnext = gmacdev->RxNext; + DmaDesc * rxdesc = gmacdev->RxNextDesc; -/* sw - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - return -1; +/* sw + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; */ - if(!synopGMAC_is_desc_empty(rxdesc)) - return -1; + if(!synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - rxdesc->length |= ((Length1 <length |= ((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - rxdesc->status = DescOwnByDma; - rxdesc->status = 0; + rxdesc->status = DescOwnByDma; + rxdesc->status = 0; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; - } - else{ - rxdesc->length |= (((Length1 <RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = (DmaDesc *)rxdesc->data2; + } + else{ + rxdesc->length |= (((Length1 <buffer1 = Buffer1; - rxdesc->data1 = Data1; + rxdesc->buffer1 = Buffer1; + rxdesc->data1 = Data1; - rxdesc->buffer2 = Buffer2; - rxdesc->data2 = Data2; - - if((rxnext % MODULO_INTERRUPT) !=0) - rxdesc->length |= RxDisIntCompl; + rxdesc->buffer2 = Buffer2; + rxdesc->data2 = Data2; - rxdesc->status = DescOwnByDma; - rxdesc->status = 0; + if((rxnext % MODULO_INTERRUPT) !=0) + rxdesc->length |= RxDisIntCompl; - gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); - (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one - return rxnext; + rxdesc->status = DescOwnByDma; + rxdesc->status = 0; + + gmacdev->RxNext = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxNextDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + (gmacdev->BusyRxDesc)++; //One descriptor will be given to Hardware. So busy count incremented by one + return rxnext; } #endif #ifdef ENH_DESC_8W @@ -2204,7 +2204,7 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2219,53 +2219,53 @@ s32 synopGMAC_set_rx_qptr_init(synopGMACdevice * gmacdev, u32 Buffer1, u32 Lengt s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_Low) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - return -1; - if(synopGMAC_is_desc_empty(rxdesc)) - return -1; - + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc * rxdesc = gmacdev->RxBusyDesc; + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + return -1; + if(synopGMAC_is_desc_empty(rxdesc)) + return -1; - if(Status != 0) - *Status = rxdesc->status;// send the status of this descriptor - if(Ext_Status != 0) - *Ext_Status = rxdesc->extstatus; + if(Status != 0) + *Status = rxdesc->status;// send the status of this descriptor + + if(Ext_Status != 0) + *Ext_Status = rxdesc->extstatus; if(Time_Stamp_High != 0) - *Time_Stamp_High = rxdesc->timestamphigh; + *Time_Stamp_High = rxdesc->timestamphigh; if(Time_Stamp_Low != 0) - *Time_Stamp_Low = rxdesc->timestamplow; + *Time_Stamp_Low = rxdesc->timestamplow; - if(Length1 != 0) - *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) - *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) - *Data1 = rxdesc->data1; + if(Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + if(Data1 != 0) + *Data1 = rxdesc->data1; - if(Length2 != 0) - *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) - *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) - *Data2 = rxdesc->data2; + if(Length2 != 0) + *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Buffer2 != 0) + *Buffer2 = rxdesc->buffer2; + if(Data1 != 0) + *Data2 = rxdesc->data2; - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; - synopGMAC_rx_desc_init_chain(rxdesc); - //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0); - } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); - } - TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); - (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now - return(rxnext); + if(synopGMAC_is_rx_desc_chained(rxdesc)){ + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + synopGMAC_rx_desc_init_chain(rxdesc); + //synopGMAC_desc_init_chain(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc),0,0); + } + else{ + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + } + TR("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + (gmacdev->BusyRxDesc)--; //busy tx descriptor is reduced by one as it will be handed over to Processor now + return(rxnext); } #else @@ -2274,7 +2274,7 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 * Get back the descriptor from DMA after data has been received. * When the DMA indicates that the data is received (interrupt is generated), this function should be * called to get the descriptor and hence the data buffers received. With successful return from this - * function caller gets the descriptor fields for processing. check the parameters to understand the + * function caller gets the descriptor fields for processing. check the parameters to understand the * fields returned.` * @param[in] pointer to synopGMACdevice. * @param[out] pointer to hold the status of DMA. @@ -2288,60 +2288,60 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2) { - u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data - //is spread over multiple buffers/descriptors - DmaDesc * rxdesc = gmacdev->RxBusyDesc; + u32 rxnext = gmacdev->RxBusy; // index of descriptor the DMA just completed. May be useful when data + //is spread over multiple buffers/descriptors + DmaDesc * rxdesc = gmacdev->RxBusyDesc; - u32 len; - if(synopGMAC_is_desc_owned_by_dma(rxdesc)) - { - DEBUG_MES("synopGMAC_get_rx_qptr:DMA descriptor is owned by GMAC!\n"); - return -1; - } - - if(synopGMAC_is_desc_empty(rxdesc)) - { - DEBUG_MES("synopGMAC_get_rx_qptr:rx desc is empty!\n"); - return -1; - } + u32 len; + if(synopGMAC_is_desc_owned_by_dma(rxdesc)) + { + DEBUG_MES("synopGMAC_get_rx_qptr:DMA descriptor is owned by GMAC!\n"); + return -1; + } - if(Status != 0) - *Status = rxdesc->status;// send the status of this descriptor + if(synopGMAC_is_desc_empty(rxdesc)) + { + DEBUG_MES("synopGMAC_get_rx_qptr:rx desc is empty!\n"); + return -1; + } - if(Length1 != 0) - *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; - if(Buffer1 != 0) - *Buffer1 = rxdesc->buffer1; - if(Data1 != 0) - *Data1 = rxdesc->data1; - if(Length2 != 0) - *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; - if(Buffer2 != 0) - *Buffer2 = rxdesc->buffer2; - if(Data1 != 0) - *Data2 = rxdesc->data2; + if(Status != 0) + *Status = rxdesc->status;// send the status of this descriptor - len = synopGMAC_get_rx_desc_frame_length(*Status); - DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n",len); - gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; - if(synopGMAC_is_rx_desc_chained(rxdesc)){ - gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; - synopGMAC_rx_desc_init_chain(rxdesc); - } - else{ - gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); -//sw: raw data + if(Length1 != 0) + *Length1 = (rxdesc->length & DescSize1Mask) >> DescSize1Shift; + if(Buffer1 != 0) + *Buffer1 = rxdesc->buffer1; + if(Data1 != 0) + *Data1 = rxdesc->data1; + if(Length2 != 0) + *Length2 = (rxdesc->length & DescSize2Mask) >> DescSize2Shift; + if(Buffer2 != 0) + *Buffer2 = rxdesc->buffer2; + if(Data1 != 0) + *Data2 = rxdesc->data2; + + len = synopGMAC_get_rx_desc_frame_length(*Status); + DEBUG_MES("Cache sync for data buffer in rx dma desc: length = 0x%x\n",len); + gmacdev->RxBusy = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? 0 : rxnext + 1; + if(synopGMAC_is_rx_desc_chained(rxdesc)){ + gmacdev->RxBusyDesc = (DmaDesc *)rxdesc->data2; + synopGMAC_rx_desc_init_chain(rxdesc); + } + else{ + gmacdev->RxBusyDesc = synopGMAC_is_last_rx_desc(gmacdev,rxdesc) ? gmacdev->RxDesc : (rxdesc + 1); +//sw: raw data #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); - } + synopGMAC_rx_desc_init_ring(rxdesc, synopGMAC_is_last_rx_desc(gmacdev,rxdesc)); + } #if SYNOP_RX_DEBUG - DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); + DEBUG_MES("%02d %08x %08x %08x %08x %08x %08x %08x\n",rxnext,(u32)rxdesc,rxdesc->status,rxdesc->length,rxdesc->buffer1,rxdesc->buffer2,rxdesc->data1,rxdesc->data2); #endif - (gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one - return(rxnext); + (gmacdev->BusyRxDesc)--; //This returns one descriptor to processor. So busy count will be decremented by one + return(rxnext); } @@ -2355,13 +2355,13 @@ s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 */ void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x before cleared!\n",data); - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + TR("DMA status reg = 0x%x before cleared!\n",data); + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); // plat_delay(DEFAULT_LOOP_VARIABLE); -// data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - TR("DMA status reg = 0x%x after cleared!\n",data); +// data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); + TR("DMA status reg = 0x%x after cleared!\n",data); } /** @@ -2371,22 +2371,22 @@ void synopGMAC_clear_interrupt(synopGMACdevice *gmacdev) */ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) { - u32 data; - u32 interrupts = 0; - data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - - //data = data & ~0x84; //sw: some bits shoud not be cleaned - synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); //manju: I think this is the appropriate location to clear the interrupts - plat_delay(DEFAULT_LOOP_VARIABLE); - if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; - if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; - if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; - if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; - if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; - if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; - if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + u32 data; + u32 interrupts = 0; + data = synopGMACReadReg(gmacdev->DmaBase, DmaStatus); - return interrupts; + //data = data & ~0x84; //sw: some bits shoud not be cleaned + synopGMACWriteReg(gmacdev->DmaBase, DmaStatus ,data); //manju: I think this is the appropriate location to clear the interrupts + plat_delay(DEFAULT_LOOP_VARIABLE); + if(data & DmaIntErrorMask) interrupts |= synopGMACDmaError; + if(data & DmaIntRxNormMask) interrupts |= synopGMACDmaRxNormal; + if(data & DmaIntRxAbnMask) interrupts |= synopGMACDmaRxAbnormal; + if(data & DmaIntRxStoppedMask) interrupts |= synopGMACDmaRxStopped; + if(data & DmaIntTxNormMask) interrupts |= synopGMACDmaTxNormal; + if(data & DmaIntTxAbnMask) interrupts |= synopGMACDmaTxAbnormal; + if(data & DmaIntTxStoppedMask) interrupts |= synopGMACDmaTxStopped; + + return interrupts; } /** @@ -2397,7 +2397,7 @@ u32 synopGMAC_get_interrupt_type(synopGMACdevice *gmacdev) #if UNUSED u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev) { - return(synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); + return(synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt)); } #endif @@ -2411,8 +2411,8 @@ u32 synopGMAC_get_interrupt_mask(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) { - synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, interrupts); - return; + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; } #endif @@ -2427,10 +2427,10 @@ void synopGMAC_enable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) */ void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) { -// rt_kprintf("dmabase = 0x%x\n",gmacdev->DmaBase); - synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); -// synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt); - return; +// rt_kprintf("dmabase = 0x%x\n",gmacdev->DmaBase); + synopGMACWriteReg(gmacdev->DmaBase, DmaInterrupt, DmaIntDisable); +// synopGMACReadReg(gmacdev->DmaBase, DmaInterrupt); + return; } /** @@ -2443,8 +2443,8 @@ void synopGMAC_disable_interrupt_all(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) { - synopGMACClearBits(gmacdev->DmaBase, DmaInterrupt, interrupts); - return; + synopGMACClearBits(gmacdev->DmaBase, DmaInterrupt, interrupts); + return; } #endif /** @@ -2454,13 +2454,13 @@ void synopGMAC_disable_interrupt(synopGMACdevice *gmacdev, u32 interrupts) */ void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) { -// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaRxStart; - TR0(" ===33334\n"); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); - TR0(" ===33344\n"); +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaRxStart; + TR0(" ===33334\n"); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); + TR0(" ===33344\n"); } /** @@ -2470,11 +2470,11 @@ void synopGMAC_enable_dma_rx(synopGMACdevice * gmacdev) */ void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) { -// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data |= DmaTxStart; - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +// synopGMACSetBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data |= DmaTxStart; + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } @@ -2487,7 +2487,7 @@ void synopGMAC_enable_dma_tx(synopGMACdevice * gmacdev) */ void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 1); + synopGMACWriteReg(gmacdev->DmaBase, DmaTxPollDemand, 1); } /** @@ -2499,7 +2499,7 @@ void synopGMAC_resume_dma_tx(synopGMACdevice * gmacdev) */ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) { - synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); + synopGMACWriteReg(gmacdev->DmaBase, DmaRxPollDemand, 0); } /** @@ -2510,10 +2510,10 @@ void synopGMAC_resume_dma_rx(synopGMACdevice * gmacdev) */ void synopGMAC_take_desc_ownership(DmaDesc * desc) { - if(desc){ - desc->status &= ~DescOwnByDma; //Clear the DMA own bit -// desc->status |= DescError; // Set the error to indicate this descriptor is bad - } + if(desc){ + desc->status &= ~DescOwnByDma; //Clear the DMA own bit +// desc->status |= DescError; // Set the error to indicate this descriptor is bad + } } /** @@ -2527,19 +2527,19 @@ void synopGMAC_take_desc_ownership(DmaDesc * desc) */ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) { - s32 i; - DmaDesc *desc; - desc = gmacdev->RxDesc; - for(i = 0; i < gmacdev->RxDescCount; i++){ - if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode - - synopGMAC_take_desc_ownership(desc); - desc = (DmaDesc *)desc->data2; - } - else{ - synopGMAC_take_desc_ownership(desc + i); - } - } + s32 i; + DmaDesc *desc; + desc = gmacdev->RxDesc; + for(i = 0; i < gmacdev->RxDescCount; i++){ + if(synopGMAC_is_rx_desc_chained(desc)){ //This descriptor is in chain mode + + synopGMAC_take_desc_ownership(desc); + desc = (DmaDesc *)desc->data2; + } + else{ + synopGMAC_take_desc_ownership(desc + i); + } + } } /** @@ -2553,19 +2553,19 @@ void synopGMAC_take_desc_ownership_rx(synopGMACdevice * gmacdev) */ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) { - s32 i; - DmaDesc *desc; - desc = gmacdev->TxDesc; - for(i = 0; i < gmacdev->TxDescCount; i++){ - if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode - synopGMAC_take_desc_ownership(desc); - desc = (DmaDesc *)desc->data2; - } - else{ - synopGMAC_take_desc_ownership(desc + i); - } - } - + s32 i; + DmaDesc *desc; + desc = gmacdev->TxDesc; + for(i = 0; i < gmacdev->TxDescCount; i++){ + if(synopGMAC_is_tx_desc_chained(desc)){ //This descriptor is in chain mode + synopGMAC_take_desc_ownership(desc); + desc = (DmaDesc *)desc->data2; + } + else{ + synopGMAC_take_desc_ownership(desc + i); + } + } + } /** @@ -2575,12 +2575,12 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev) */ void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) -{ -// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaTxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaTxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaTxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } /** * Disable the DMA for Reception. @@ -2588,16 +2588,16 @@ void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev) * \return returns void. */ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) -{ -// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); - u32 data; - data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); - data &= (~DmaRxStart); - synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); +{ +// synopGMACClearBits(gmacdev->DmaBase, DmaControl, DmaRxStart); + u32 data; + data = synopGMACReadReg(gmacdev->DmaBase, DmaControl); + data &= (~DmaRxStart); + synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data); } - + /*******************PMT APIs***************************************/ @@ -2613,7 +2613,7 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev) #if UNUSED void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } #endif @@ -2626,7 +2626,7 @@ void synopGMAC_pmt_int_enable(synopGMACdevice *gmacdev) */ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** @@ -2638,8 +2638,8 @@ void synopGMAC_pmt_int_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; } #endif /** @@ -2652,8 +2652,8 @@ void synopGMAC_power_down_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); - return; + synopGMACClearBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtPowerDown); + return; } #endif /** @@ -2664,7 +2664,7 @@ void synopGMAC_power_down_disable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); } #endif /** @@ -2675,7 +2675,7 @@ void synopGMAC_enable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); } #endif /** @@ -2686,13 +2686,13 @@ void synopGMAC_disable_pmt_interrupt(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtMagicPktEnable); + return; } #endif /** - * Enables GMAC to look for wake up frame. + * Enables GMAC to look for wake up frame. * Wake up frame is defined by the user. * @param[in] pointer to synopGMACdevice. * \return returns void. @@ -2700,8 +2700,8 @@ void synopGMAC_magic_packet_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtWakeupFrameEnable); + return; } #endif @@ -2713,8 +2713,8 @@ void synopGMAC_wakeup_frame_enable(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); - return; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtGlobalUnicast); + return; } #endif /** @@ -2724,9 +2724,9 @@ void synopGMAC_pmt_unicast_enable(synopGMACdevice *gmacdev) */ bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtMagicPktReceived) == GmacPmtMagicPktReceived); } /** * Checks whether the packet received is a wakeup frame?. @@ -2735,9 +2735,9 @@ bool synopGMAC_is_magic_packet_received(synopGMACdevice *gmacdev) */ bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) { - u32 data; - data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); - return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); + u32 data; + data = synopGMACReadReg(gmacdev->MacBase,GmacPmtCtrlStatus); + return((data & GmacPmtWakeupFrameReceived) == GmacPmtWakeupFrameReceived); } /** @@ -2752,12 +2752,12 @@ bool synopGMAC_is_wakeup_frame_received(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filter_contents) { - s32 i; - synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); - plat_delay(10); - for(i =0; iMacBase, GmacWakeupAddr, *(filter_contents + i)); - return; + s32 i; + synopGMACSetBits(gmacdev->MacBase,GmacPmtCtrlStatus,GmacPmtFrmFilterPtrReset); + plat_delay(10); + for(i =0; iMacBase, GmacWakeupAddr, *(filter_contents + i)); + return; } #endif @@ -2774,8 +2774,8 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte #if UNUSED void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + return; } #endif /** @@ -2786,8 +2786,8 @@ void synopGMAC_mmc_counters_stop(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterFreeze); + return; } #endif /** @@ -2799,8 +2799,8 @@ void synopGMAC_mmc_counters_resume(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + return; } #endif /** @@ -2812,8 +2812,8 @@ void synopGMAC_mmc_counters_set_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterResetOnRead); + return; } #endif /** @@ -2825,8 +2825,8 @@ void synopGMAC_mmc_counters_reset_selfclear(synopGMACdevice *gmacdev) #if UNUSED void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + return; } /** * Configures the MMC to rollover. @@ -2836,8 +2836,8 @@ void synopGMAC_mmc_counters_disable_rollover(synopGMACdevice *gmacdev) */ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcCntrl,GmacMmcCounterStopRollover); + return; } /** @@ -2848,7 +2848,7 @@ void synopGMAC_mmc_counters_enable_rollover(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) { - return( synopGMACReadReg(gmacdev->MacBase,counter)); + return( synopGMACReadReg(gmacdev->MacBase,counter)); } #endif /** @@ -2858,7 +2858,7 @@ u32 synopGMAC_read_mmc_counter(synopGMACdevice *gmacdev, u32 counter) */ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrRx)); + return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrRx)); } /** * Read the MMC Tx interrupt status. @@ -2867,7 +2867,7 @@ u32 synopGMAC_read_mmc_rx_int_status(synopGMACdevice *gmacdev) */ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) { - return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrTx)); + return( synopGMACReadReg(gmacdev->MacBase,GmacMmcIntrTx)); } /** * Disable the MMC Tx interrupt. @@ -2878,8 +2878,8 @@ u32 synopGMAC_read_mmc_tx_int_status(synopGMACdevice *gmacdev) */ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + return; } /** * Enable the MMC Tx interrupt. @@ -2891,7 +2891,7 @@ void synopGMAC_disable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); + synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskTx,mask); } #endif /** @@ -2903,8 +2903,8 @@ void synopGMAC_enable_mmc_tx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + return; } /** * Enable the MMC Rx interrupt. @@ -2916,8 +2916,8 @@ void synopGMAC_disable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcIntrMaskRx,mask); + return; } #endif /** @@ -2929,8 +2929,8 @@ void synopGMAC_enable_mmc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) */ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACSetBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); - return; + synopGMACSetBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + return; } /** * Enable the MMC ipc rx checksum offload interrupt. @@ -2942,8 +2942,8 @@ void synopGMAC_disable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) { - synopGMACClearBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacMmcRxIpcIntrMask,mask); + return; } #endif /*******************MMC APIs***************************************/ @@ -2960,8 +2960,8 @@ void synopGMAC_enable_mmc_ipc_rx_interrupt(synopGMACdevice *gmacdev, u32 mask) #if UNUSED void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); - return; + synopGMACSetBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + return; } /** * Disable the ip checksum offloading in receive path. @@ -2971,19 +2971,19 @@ void synopGMAC_enable_rx_chksum_offload(synopGMACdevice *gmacdev) */ void synopGMAC_disable_rx_Ipchecksum_offload(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); + synopGMACClearBits(gmacdev->MacBase,GmacConfig,GmacRxIpcOffload); } /** * Instruct the DMA to drop the packets fails tcp ip checksum. - * This is to instruct the receive DMA engine to drop the recevied packet if they + * This is to instruct the receive DMA engine to drop the recevied packet if they * fails the tcp/ip checksum in hardware. Valid only when full checksum offloading is enabled(type-2). * @param[in] pointer to synopGMACdevice. * \return returns void. */ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); - return; + synopGMACClearBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; } /** * Instruct the DMA not to drop the packets even if it fails tcp ip checksum. @@ -2994,12 +2994,12 @@ void synopGMAC_rx_tcpip_chksum_drop_enable(synopGMACdevice *gmacdev) */ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); - return; + synopGMACSetBits(gmacdev->DmaBase,DmaControl,DmaDisableDropTcpCs); + return; } #endif -/** +/** * When the Enhanced Descriptor is enabled then the bit 0 of RDES0 indicates whether the * Extended Status is available (RDES4). Time Stamp feature and the Checksum Offload Engine2 * makes use of this extended status to provide the status of the received packet. @@ -3016,9 +3016,9 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev) * @param[in] u32 status field of the corresponding descriptor. * \return returns TRUE or FALSE. */ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // extended status present indicates that the RDES4 need to be probed { - return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 + return((status & DescRxEXTsts ) != 0 ); // if extstatus set then it returns 1 } /** * This function returns true if the IP header checksum bit is set in the extended status. @@ -3030,7 +3030,7 @@ bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status) // ext */ bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) // IP header (IPV4) checksum error { - return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 + return((ext_status & DescRxIpHeaderError) != 0 ); // if IPV4 header error return 1 } /** * This function returns true if the Checksum is bypassed in the hardware. @@ -3042,7 +3042,7 @@ bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status) */ bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status) // Hardware engine bypassed the checksum computation/checking { - return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 + return((ext_status & DescRxChkSumBypass ) != 0 ); // if checksum offloading bypassed return 1 } /** * This function returns true if payload checksum error is set in the extended status. @@ -3054,7 +3054,7 @@ bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_statu */ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) // IP payload checksum is in error (UDP/TCP/ICMP checksum error) { - return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 + return((ext_status & DescRxIpPayloadError) != 0 ); // if IP payload error return 1 } #endif @@ -3068,22 +3068,22 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status) */ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) { - if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxLenLT600; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkBypass; - else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxChkBypass; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) - return RxNoChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) - return RxPayLoadChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) - return RxIpHdrChkError; - else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) - return RxIpHdrPayLoadChkError; - else - return RxIpHdrPayLoadRes; + if (((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxLenLT600; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkBypass; + else if(((status & DescRxChkBit5) == 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxChkBypass; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) == 0)) + return RxNoChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) == 0) && ((status & DescRxChkBit0) != 0)) + return RxPayLoadChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) == 0)) + return RxIpHdrChkError; + else if(((status & DescRxChkBit5) != 0) && ((status & DescRxChkBit7) != 0) && ((status & DescRxChkBit0) != 0)) + return RxIpHdrPayLoadChkError; + else + return RxIpHdrPayLoadRes; } /** * Checks if any Ipv4 header checksum error in the frame just transmitted. @@ -3095,7 +3095,7 @@ u32 synopGMAC_is_rx_checksum_error(synopGMACdevice *gmacdev, u32 status) */ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); + return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError); } @@ -3109,7 +3109,7 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta */ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status) { - return((status & DescTxPayChkError) == DescTxPayChkError); + return((status & DescTxPayChkError) == DescTxPayChkError); } /** * The check summ offload engine is bypassed in the tx path. @@ -3120,11 +3120,11 @@ bool synopGMAC_is_tx_payload_checksum_error(synopGMACdevice *gmacdev, u32 status */ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC - #else - desc->length = (desc->length & (~DescTxCisMask)); - #endif + #ifdef ENH_DESC + desc->status = (desc->length & (~DescTxCisMask));//ENH_DESC + #else + desc->length = (desc->length & (~DescTxCisMask)); + #endif } /** @@ -3136,11 +3136,11 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des */ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);//ENH_DESC + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs); + #endif } @@ -3154,11 +3154,11 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->status & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);//ENH_DESC + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs); + #endif } /** @@ -3172,11 +3172,11 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de */ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc *desc) { - #ifdef ENH_DESC - desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #else - desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); - #endif + #ifdef ENH_DESC + desc->status = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + #else + desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpPseudoCs); + #endif } /*******************Ip checksum offloading APIs***************************************/ @@ -3192,7 +3192,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled. * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced * Please make sure you have enabled the Advanced timestamp feature in the hardware and the driver should - * be compiled with the ADV_TME_STAMP feature. + * be compiled with the ADV_TME_STAMP feature. * Some of the APIs provided here may not be valid for all configurations. Please make sure you call the * API with due care. */ @@ -3206,48 +3206,48 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc #if UNUSED void synopGMAC_TS_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENA); + return; } /** - * This function disables the timestamping. + * This function disables the timestamping. * When disabled timestamp is not added to tx and receive frames and timestamp generator is suspended. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask, GmacTSIntMask); - return; + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask, GmacTSIntMask); + return; } /** - * Enable the interrupt to get timestamping interrupt. - * This enables the host to get the interrupt when (1) system time is greater or equal to the + * Enable the interrupt to get timestamping interrupt. + * This enables the host to get the interrupt when (1) system time is greater or equal to the * target time high and low register or (2) there is a overflow in th esecond register. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACClearBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** - * Disable the interrupt to get timestamping interrupt. + * Disable the interrupt to get timestamping interrupt. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); + synopGMACSetBits(gmacdev->MacBase,GmacInterruptMask,GmacPmtIntMask); return; } /** - * Enable MAC address for PTP frame filtering. + * Enable MAC address for PTP frame filtering. * When enabled, uses MAC address (apart from MAC address 0) to filter the PTP frames when * PTP is sent directly over Ethernet. * @param[in] pointer to synopGMACdevice @@ -3255,46 +3255,46 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; } /** - * Disables MAC address for PTP frame filtering. + * Disables MAC address for PTP frame filtering. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENMACADDR); + return; } /** - * Selet the type of clock mode for PTP. + * Selet the type of clock mode for PTP. * Please note to use one of the follwoing as the clk_type argument. - * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock - * GmacTSBouClk = 0x00010000, 01=> Boundary clock - * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock - * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock + * GmacTSOrdClk = 0x00000000, 00=> Ordinary clock + * GmacTSBouClk = 0x00010000, 01=> Boundary clock + * GmacTSEtoEClk = 0x00020000, 10=> End-to-End transparent clock + * GmacTSPtoPClk = 0x00030000, 11=> P-to-P transparent clock * @param[in] pointer to synopGMACdevice * @param[in] u32 value representing one of the above clk value * \return returns void */ void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) { - u32 clkval; - clkval = synopGMACReadReg(gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value - clkval = clkval | clk_type; - synopGMACWriteReg(gmacdev->MacBase,GmacTSControl,clkval); - return; + u32 clkval; + clkval = synopGMACReadReg(gmacdev->MacBase,GmacTSControl); //set the mdc clock to the user defined value + clkval = clkval | clk_type; + synopGMACWriteReg(gmacdev->MacBase,GmacTSControl,clkval); + return; } /** - * Enable Snapshot for messages relevant to Master. - * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant - * to slave node. + * Enable Snapshot for messages relevant to Master. + * When enabled, snapshot is taken for messages relevant to master mode only, else snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3302,13 +3302,13 @@ void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type) */ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; } /** - * Disable Snapshot for messages relevant to Master. - * When disabled, snapshot is taken for messages relevant - * to slave node. + * Disable Snapshot for messages relevant to Master. + * When disabled, snapshot is taken for messages relevant + * to slave node. * Valid only for Ordinary clock and Boundary clock * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3316,11 +3316,11 @@ void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSMSTRENA); + return; } /** - * Enable Snapshot for Event messages. + * Enable Snapshot for Event messages. * When enabled, snapshot is taken for event messages only (SYNC, Delay_Req, Pdelay_Req or Pdelay_Resp) * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected @@ -3329,11 +3329,11 @@ void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; } /** - * Disable Snapshot for Event messages. + * Disable Snapshot for Event messages. * When disabled, snapshot is taken for all messages except Announce, Management and Signaling. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3341,12 +3341,12 @@ void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSEVNTENA); + return; } /** - * Enable time stamp snapshot for IPV4 frames. + * Enable time stamp snapshot for IPV4 frames. * When enabled, time stamp snapshot is taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3354,11 +3354,11 @@ void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; } /** - * Disable time stamp snapshot for IPV4 frames. + * Disable time stamp snapshot for IPV4 frames. * When disabled, time stamp snapshot is not taken for IPV4 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3366,11 +3366,11 @@ void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV4ENA); + return; } // Only for "Advanced Time Stamp" /** - * Enable time stamp snapshot for IPV6 frames. + * Enable time stamp snapshot for IPV6 frames. * When enabled, time stamp snapshot is taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3378,11 +3378,11 @@ void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; } /** - * Disable time stamp snapshot for IPV6 frames. + * Disable time stamp snapshot for IPV6 frames. * When disabled, time stamp snapshot is not taken for IPV6 frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3390,12 +3390,12 @@ void synopGMAC_TS_IPV6_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPV6ENA); + return; } /** - * Enable time stamp snapshot for PTP over Ethernet frames. + * Enable time stamp snapshot for PTP over Ethernet frames. * When enabled, time stamp snapshot is taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3403,11 +3403,11 @@ void synopGMAC_TS_IPV6_disable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; } /** - * Disable time stamp snapshot for PTP over Ethernet frames. + * Disable time stamp snapshot for PTP over Ethernet frames. * When disabled, time stamp snapshot is not taken for PTP over Ethernet frames * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3415,58 +3415,58 @@ void synopGMAC_TS_ptp_over_ethernet_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSIPENA); + return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; } /** - * Snoop PTP packet for version 2 format + * Snoop PTP packet for version 2 format * When set the PTP packets are snooped using the version 2 format. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSVER2ENA); + return; } /** - * Timestamp digital rollover + * Timestamp digital rollover * When set the timestamp low register rolls over after 0x3B9A_C9FF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); - return; -} + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; +} /** - * Timestamp binary rollover + * Timestamp binary rollover * When set the timestamp low register rolls over after 0x7FFF_FFFF value. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCTRLSSR); + return; } /** - * Enable Time Stamp for All frames + * Enable Time Stamp for All frames * When set the timestamp snap shot is enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3474,11 +3474,11 @@ void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; } /** - * Disable Time Stamp for All frames + * Disable Time Stamp for All frames * When reset the timestamp snap shot is not enabled for all frames received by the core. * Reserved when "Advanced Time Stamp" is not selected * @param[in] pointer to synopGMACdevice @@ -3486,11 +3486,11 @@ void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev) */ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSENALL); + return; } /** - * Addend Register Update + * Addend Register Update * This function loads the contents of Time stamp addend register with the supplied 32 value. * This is reserved function when only coarse correction option is selected * @param[in] pointer to synopGMACdevice @@ -3499,25 +3499,25 @@ void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev) */ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSAddend,addend_value);// Load the addend_value in to Addend register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSADDREG)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * time stamp Update + * time stamp Update * This function updates (adds/subtracts) with the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3527,26 +3527,26 @@ return -ESYNOPGMACNOERR; */ s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * time stamp Initialize + * time stamp Initialize * This function Loads/Initializes h the value specified in the Timestamp High Update and * Timestamp Low Update register. * @param[in] pointer to synopGMACdevice @@ -3556,59 +3556,59 @@ return -ESYNOPGMACNOERR; */ s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value) { - u32 loop_variable; + u32 loop_variable; synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time - if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break - break; - } + if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break + break; + } plat_delay(DEFAULT_DELAY_VARIABLE); } if(loop_variable < DEFAULT_LOOP_VARIABLE) synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT); else{ TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n"); - return -ESYNOPGMACPHYERR; + return -ESYNOPGMACPHYERR; } return -ESYNOPGMACNOERR; } /** - * Time Stamp Update Coarse + * Time Stamp Update Coarse * When reset the timestamp update is done using coarse method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev) { - synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); - return; + synopGMACClearBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; } /** - * Time Stamp Update Fine + * Time Stamp Update Fine * When reset the timestamp update is done using Fine method. * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev) { - synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); - return; + synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSCFUPDT); + return; } /** - * Load the Sub Second Increment value in to Sub Second increment register + * Load the Sub Second Increment value in to Sub Second increment register * @param[in] pointer to synopGMACdevice * \return returns void */ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSSubSecIncr,(sub_sec_inc_value & GmacSSINCMsk)); + return; } /** - * Reads the time stamp contents in to the respective pointers + * Reads the time stamp contents in to the respective pointers * These registers are readonly. * This function returns the 48 bit time stamp assuming Version 2 timestamp with higher word is selected. * @param[in] pointer to synopGMACdevice @@ -3616,40 +3616,40 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value * @param[in] pointer to hold 32 bit second register contents * @param[in] pointer to hold 32 bit subnanosecond register contents * \return returns void - * \note Please note that since the atomic access to the timestamp registers is not possible, - * the contents read may be different from the actual time stamp. + * \note Please note that since the atomic access to the timestamp registers is not possible, + * the contents read may be different from the actual time stamp. */ void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh); * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSLow); - return; + return; } /** - * Loads the time stamp higher sec value from the value supplied + * Loads the time stamp higher sec value from the value supplied * @param[in] pointer to synopGMACdevice * @param[in] 16 higher bit second register contents passed as 32 bit value * \return returns void */ void synopGMAC_TS_load_timestamp_higher_val(synopGMACdevice *gmacdev, u32 higher_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSHighWord, (higher_sec_val & GmacTSHighWordMask)); + return; } /** - * Reads the time stamp higher sec value to respective pointers + * Reads the time stamp higher sec value to respective pointers * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold 16 higher bit second register contents * \return returns void */ void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * higher_sec_val) { - * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); - return; + * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask); + return; } /** - * Load the Target time stamp registers + * Load the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] target Timestamp High value @@ -3658,12 +3658,12 @@ void synopGMAC_TS_read_timestamp_higher_val(synopGMACdevice *gmacdev, u16 * high */ void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val) { - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); - synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); - return; + synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeHigh,sec_val); + synopGMACWriteReg(gmacdev->MacBase,GmacTSTargetTimeLow,sub_sec_val); + return; } /** - * Reads the Target time stamp registers + * Reads the Target time stamp registers * This function Loads the target time stamp registers with the values proviced * @param[in] pointer to synopGMACdevice * @param[in] pointer to hold target Timestamp High value @@ -3672,8 +3672,8 @@ void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u */ void synopGMAC_TS_read_target_timestamp(synopGMACdevice *gmacdev, u32 * sec_val, u32 * sub_sec_val) { - * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeHigh); - * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeLow); - return; + * sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeHigh); + * sub_sec_val = synopGMACReadReg(gmacdev->MacBase,GmacTSTargetTimeLow); + return; } #endif diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.h index 74bc850d86..2b1000aed0 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,9 +8,9 @@ * 2017-08-24 chinesebear first version */ - -#define UNUSED 1 - + +#define UNUSED 1 + #ifndef SYNOP_GMAC_DEV_H #define SYNOP_GMAC_DEV_H 1 @@ -31,41 +31,41 @@ #include "synopGMAC_plat.h" #include "synopGMAC_types.h" -//sw: typedef are included in synopGMAC_plat.h -// it is strange that we should add it here again!! +//sw: typedef are included in synopGMAC_plat.h +// it is strange that we should add it here again!! /*SynopGMAC can support up to 32 phys*/ #define GMAC_PHY_BASE 1 #ifdef GMAC_PHY_BASE #define DEFAULT_PHY_BASE GMAC_PHY_BASE #else -#define DEFAULT_PHY_BASE PHY16 //We use First Phy +#define DEFAULT_PHY_BASE PHY16 //We use First Phy #endif -#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 -#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 +#define MACBASE 0x0000 // The Mac Base address offset is 0x0000 +#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 enum GMACPhyBase { - PHY0 = 0, //The device can support 32 phys, but we use first phy only - PHY1 = 1, - PHY16 = 16, - PHY31 = 31, + PHY0 = 0, //The device can support 32 phys, but we use first phy only + PHY1 = 1, + PHY16 = 16, + PHY31 = 31, }; -//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue -//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue -//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue -#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue -#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 256 //Tx Descriptors needed in the Descriptor pool/queue +//#define RECEIVE_DESC_SIZE 256 //Rx Descriptors needed in the Descriptor pool/queue +//#define TRANSMIT_DESC_SIZE 13//256 //Tx Descriptors needed in the Descriptor pool/queue +#define TRANSMIT_DESC_SIZE 36 //48 //Tx Descriptors needed in the Descriptor pool/queue +#define RECEIVE_DESC_SIZE 72 //96 //Rx Descriptors needed in the Descriptor pool/queue -#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type -#define ETHERNET_CRC 4 //Ethernet CRC -#define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA -#define VLAN_TAG 4 //optional 802.1q VLAN Tag +#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type +#define ETHERNET_CRC 4 //Ethernet CRC +#define ETHERNET_EXTRA 2 //Only God knows about this????? +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define VLAN_TAG 4 //optional 802.1q VLAN Tag #define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size #define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size #define JUMBO_FRAME_PAYLOAD 9000 //Jumbo frame payload size @@ -84,80 +84,80 @@ The descriptor is of 4 words, but our structrue contains 6 words where last two words are to hold the virtual address of the network buffer pointers for driver's use From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. -The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal descriptor structure. Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and TX/RX DESC7 provides the upper 32 bits of Timestamp value In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information */ -#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for - // descriptor whose index%MODULO_INTERRUPT is zero +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for + // descriptor whose index%MODULO_INTERRUPT is zero #ifdef ENH_DESC_8W -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ u32 extstatus; /* Extended status of a Rx Descriptor */ u32 reserved1; /* Reserved word */ u32 timestamplow; /* Lower 32 bits of the 64 bit timestamp value */ u32 timestamphigh; /* Higher 32 bits of the 64 bit timestamp value */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else -typedef struct DmaDescStruct -{ - u32 status; /* Status */ - u32 length; /* Buffer 1 and Buffer 2 length */ - u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ - u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ - /* This data below is used only by driver */ - u32 data1; /* This holds virtual address of buffer1, not used by DMA */ - u32 data2; /* This holds virtual address of buffer2, not used by DMA */ +typedef struct DmaDescStruct +{ + u32 status; /* Status */ + u32 length; /* Buffer 1 and Buffer 2 length */ + u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ + u32 buffer2; /* Network Buffer 2 pointer or next descriptor pointer (Dma-able)in chain structure */ + /* This data below is used only by driver */ + u32 data1; /* This holds virtual address of buffer1, not used by DMA */ + u32 data2; /* This holds virtual address of buffer2, not used by DMA */ - u32 dummy1; //sw: for addr align - u32 dummy2; // + u32 dummy1; //sw: for addr align + u32 dummy2; // } DmaDesc; #endif enum DescMode { - RINGMODE = 0x00000001, - CHAINMODE = 0x00000002, + RINGMODE = 0x00000001, + CHAINMODE = 0x00000002, }; enum BufferMode { - SINGLEBUF = 0x00000001, - DUALBUF = 0x00000002, + SINGLEBUF = 0x00000001, + DUALBUF = 0x00000002, }; /* synopGMAC device data */ -typedef struct synopGMACDeviceStruct +typedef struct synopGMACDeviceStruct { - u32 MacBase; /* base address of MAC registers */ - u32 DmaBase; /* base address of DMA registers */ - u32 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ - + u32 MacBase; /* base address of MAC registers */ + u32 DmaBase; /* base address of DMA registers */ + u32 PhyBase; /* PHY device address on MII interface */ + u32 Version; /* Gmac Revision version */ - dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-albe address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ - + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ @@ -169,14 +169,14 @@ typedef struct synopGMACDeviceStruct DmaDesc * RxNextDesc; /* Rx Descriptor address corresponding to the index RxNext */ /*Phy related stuff*/ - u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ + u32 ClockDivMdc; /* Clock divider value programmed in the hardware */ /* The status of the link */ - u32 LinkState0; /* Link status as reported by the Marvel Phy */ - u32 LinkState; /* Link status as reported by the Marvel Phy */ - u32 DuplexMode; /* Duplex mode of the Phy */ - u32 Speed; /* Speed of the Phy */ - u32 LoopBackMode; /* Loopback status of the Phy */ - + u32 LinkState0; /* Link status as reported by the Marvel Phy */ + u32 LinkState; /* Link status as reported by the Marvel Phy */ + u32 DuplexMode; /* Duplex mode of the Phy */ + u32 Speed; /* Speed of the Phy */ + u32 LoopBackMode; /* Loopback status of the Phy */ + // void * FirstTxDesc; // void * FirstRxDesc; // u32 skb_array[RECEIVE_DESC_SIZE]; @@ -184,36 +184,36 @@ typedef struct synopGMACDeviceStruct -/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ enum MiiRegisters { - PHY_CONTROL_REG = 0x0000, /*Control Register*/ - PHY_STATUS_REG = 0x0001, /*Status Register */ - PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ - PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ - PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ - PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ - PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ - PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ - PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ - PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ - PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ - PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ - PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ - PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ - PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ - PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ - PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ - PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ - PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ - PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ - PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ - PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ + PHY_CONTROL_REG = 0x0000, /*Control Register*/ + PHY_STATUS_REG = 0x0001, /*Status Register */ + PHY_ID_HI_REG = 0x0002, /*PHY Identifier High Register*/ + PHY_ID_LOW_REG = 0x0003, /*PHY Identifier High Register*/ + PHY_AN_ADV_REG = 0x0004, /*Auto-Negotiation Advertisement Register*/ + PHY_LNK_PART_ABl_REG = 0x0005, /*Link Partner Ability Register (Base Page)*/ + PHY_AN_EXP_REG = 0x0006, /*Auto-Negotiation Expansion Register*/ + PHY_AN_NXT_PAGE_TX_REG = 0x0007, /*Next Page Transmit Register*/ + PHY_LNK_PART_NXT_PAGE_REG = 0x0008, /*Link Partner Next Page Register*/ + PHY_1000BT_CTRL_REG = 0x0009, /*1000BASE-T Control Register*/ + PHY_1000BT_STATUS_REG = 0x000a, /*1000BASE-T Status Register*/ + PHY_SPECIFIC_CTRL_REG = 0x0010, /*Phy specific control register*/ + PHY_SPECIFIC_STATUS_REG = 0x0011, /*Phy specific status register*/ + PHY_INTERRUPT_ENABLE_REG = 0x0012, /*Phy interrupt enable register*/ + PHY_INTERRUPT_STATUS_REG = 0x0013, /*Phy interrupt status register*/ + PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ + PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ + PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ + PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ + PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ + PHY_CBL_DIAG_REG = 0x001c, /*Cable diagnostic registers*/ }; @@ -221,62 +221,62 @@ enum MiiRegisters */ enum Mii_GEN_CTRL -{ /* Description bits R/W default value */ - Mii_reset = 0x8000, - Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ - Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ - Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ +{ /* Description bits R/W default value */ + Mii_reset = 0x8000, + Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ + Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ + Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ - Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - - Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - - Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ - Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ + Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ + + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ + + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ + Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; enum Mii_Phy_Status { - Mii_phy_status_speed_10 = 0x0000, - Mii_phy_status_speed_100 = 0x4000, - Mii_phy_status_speed_1000 = 0x8000, - - Mii_phy_status_full_duplex = 0x2000, - Mii_phy_status_half_duplex = 0x0000, - - Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy -// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY + Mii_phy_status_speed_10 = 0x0000, + Mii_phy_status_speed_100 = 0x4000, + Mii_phy_status_speed_1000 = 0x8000, + + Mii_phy_status_full_duplex = 0x2000, + Mii_phy_status_half_duplex = 0x0000, + + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy +// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; /* This is Status register layout. Status register is of 16 bit wide. */ enum Mii_GEN_STATUS { - Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ - Mii_Link = 0x0004, /* Link status 2 RW */ + Mii_AutoNegCmplt = 0x0020, /* Autonegotiation completed 5 RW */ + Mii_Link = 0x0004, /* Link status 2 RW */ }; enum Mii_Link_Status { - LINKDOWN = 0, - LINKUP = 1, + LINKDOWN = 0, + LINKUP = 1, }; enum Mii_Duplex_Mode { - HALFDUPLEX = 1, - FULLDUPLEX = 2, + HALFDUPLEX = 1, + FULLDUPLEX = 2, }; enum Mii_Link_Speed { - SPEED10 = 1, - SPEED100 = 2, - SPEED1000 = 3, + SPEED10 = 1, + SPEED100 = 2, + SPEED1000 = 3, }; enum Mii_Loop_Back { - NOLOOPBACK = 0, - LOOPBACK = 1, + NOLOOPBACK = 0, + LOOPBACK = 1, }; @@ -286,107 +286,107 @@ enum Mii_Loop_Back * For Pci based system address is BARx + GmacRegisterBase * For any other system translation is done accordingly **********************************************************/ -enum GmacRegisters +enum GmacRegisters { - GmacConfig = 0x0000, /* Mac config Register */ - GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ - GmacHashHigh = 0x0008, /* Multi-cast hash table high */ - GmacHashLow = 0x000C, /* Multi-cast hash table low */ - GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ - GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ - GmacFlowControl = 0x0018, /* Flow control Register */ - GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - - GmacAddr0High = 0x0040, /* Mac address0 high Register */ - GmacAddr0Low = 0x0044, /* Mac address0 low Register */ - GmacAddr1High = 0x0048, /* Mac address1 high Register */ - GmacAddr1Low = 0x004C, /* Mac address1 low Register */ - GmacAddr2High = 0x0050, /* Mac address2 high Register */ - GmacAddr2Low = 0x0054, /* Mac address2 low Register */ - GmacAddr3High = 0x0058, /* Mac address3 high Register */ - GmacAddr3Low = 0x005C, /* Mac address3 low Register */ - GmacAddr4High = 0x0060, /* Mac address4 high Register */ - GmacAddr4Low = 0x0064, /* Mac address4 low Register */ - GmacAddr5High = 0x0068, /* Mac address5 high Register */ - GmacAddr5Low = 0x006C, /* Mac address5 low Register */ - GmacAddr6High = 0x0070, /* Mac address6 high Register */ - GmacAddr6Low = 0x0074, /* Mac address6 low Register */ - GmacAddr7High = 0x0078, /* Mac address7 high Register */ - GmacAddr7Low = 0x007C, /* Mac address7 low Register */ - GmacAddr8High = 0x0080, /* Mac address8 high Register */ - GmacAddr8Low = 0x0084, /* Mac address8 low Register */ - GmacAddr9High = 0x0088, /* Mac address9 high Register */ - GmacAddr9Low = 0x008C, /* Mac address9 low Register */ + GmacConfig = 0x0000, /* Mac config Register */ + GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ + GmacHashHigh = 0x0008, /* Multi-cast hash table high */ + GmacHashLow = 0x000C, /* Multi-cast hash table low */ + GmacGmiiAddr = 0x0010, /* GMII address Register(ext. Phy) */ + GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ + GmacFlowControl = 0x0018, /* Flow control Register */ + GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + + GmacAddr0High = 0x0040, /* Mac address0 high Register */ + GmacAddr0Low = 0x0044, /* Mac address0 low Register */ + GmacAddr1High = 0x0048, /* Mac address1 high Register */ + GmacAddr1Low = 0x004C, /* Mac address1 low Register */ + GmacAddr2High = 0x0050, /* Mac address2 high Register */ + GmacAddr2Low = 0x0054, /* Mac address2 low Register */ + GmacAddr3High = 0x0058, /* Mac address3 high Register */ + GmacAddr3Low = 0x005C, /* Mac address3 low Register */ + GmacAddr4High = 0x0060, /* Mac address4 high Register */ + GmacAddr4Low = 0x0064, /* Mac address4 low Register */ + GmacAddr5High = 0x0068, /* Mac address5 high Register */ + GmacAddr5Low = 0x006C, /* Mac address5 low Register */ + GmacAddr6High = 0x0070, /* Mac address6 high Register */ + GmacAddr6Low = 0x0074, /* Mac address6 low Register */ + GmacAddr7High = 0x0078, /* Mac address7 high Register */ + GmacAddr7Low = 0x007C, /* Mac address7 low Register */ + GmacAddr8High = 0x0080, /* Mac address8 high Register */ + GmacAddr8Low = 0x0084, /* Mac address8 low Register */ + GmacAddr9High = 0x0088, /* Mac address9 high Register */ + GmacAddr9Low = 0x008C, /* Mac address9 low Register */ GmacAddr10High = 0x0090, /* Mac address10 high Register */ - GmacAddr10Low = 0x0094, /* Mac address10 low Register */ - GmacAddr11High = 0x0098, /* Mac address11 high Register */ - GmacAddr11Low = 0x009C, /* Mac address11 low Register */ - GmacAddr12High = 0x00A0, /* Mac address12 high Register */ - GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ - GmacAddr13High = 0x00A8, /* Mac address13 high Register */ - GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ - GmacAddr14High = 0x00B0, /* Mac address14 high Register */ - GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ - GmacAddr15High = 0x00B8, /* Mac address15 high Register */ - GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ + GmacAddr10Low = 0x0094, /* Mac address10 low Register */ + GmacAddr11High = 0x0098, /* Mac address11 high Register */ + GmacAddr11Low = 0x009C, /* Mac address11 low Register */ + GmacAddr12High = 0x00A0, /* Mac address12 high Register */ + GmacAddr12Low = 0x00A4, /* Mac address12 low Register */ + GmacAddr13High = 0x00A8, /* Mac address13 high Register */ + GmacAddr13Low = 0x00AC, /* Mac address13 low Register */ + GmacAddr14High = 0x00B0, /* Mac address14 high Register */ + GmacAddr14Low = 0x00B4, /* Mac address14 low Register */ + GmacAddr15High = 0x00B8, /* Mac address15 high Register */ + GmacAddr15Low = 0x00BC, /* Mac address15 low Register */ GmacStatus = 0x00d8, /*MAC status*/ /*Time Stamp Register Map*/ - GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ + GmacTSControl = 0x0700, /* Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ - GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSSubSecIncr = 0x0704, /* 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ + GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - - GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ + + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** * GMAC Network interface registers * This explains the Register's Layout - - * FES is Read only by default and is enabled only when Tx + + * FES is Read only by default and is enabled only when Tx * Config Parameter is enabled for RGMII/SGMII interface * during CoreKit Config. - + * DM is Read only with value 1'b1 in Full duplex only Config **********************************************************/ /* GmacConfig = 0x0000, Mac config Register Layout */ -enum GmacConfigReg -{ +enum GmacConfigReg +{ /* Bit description Bits R/W Reset value */ - GmacWatchdog = 0x00800000, + GmacWatchdog = 0x00800000, GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ GmacWatchdogEnable = 0x00000000, /* Enable watchdog timer 0 */ - GmacJabber = 0x00400000, + GmacJabber = 0x00400000, GmacJabberDisable = 0x00400000, /* (JD)Disable jabber timer on Tx 22 RW */ GmacJabberEnable = 0x00000000, /* Enable jabber timer 0 */ GmacFrameBurst = 0x00200000, GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - + GmacJumboFrame = 0x00100000, GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ @@ -399,69 +399,69 @@ enum GmacConfigReg GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - - GmacDisableCrs = 0x00010000, - GmacMiiGmii = 0x00008000, + + GmacDisableCrs = 0x00010000, + GmacMiiGmii = 0x00008000, GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, + GmacRxOwn = 0x00002000, GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - - GmacLoopback = 0x00001000, + + GmacLoopback = 0x00001000, GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ - GmacDuplex = 0x00000800, + GmacDuplex = 0x00000800, GmacFullDuplex = 0x00000800, /* (DM)Full duplex mode 11 RW */ GmacHalfDuplex = 0x00000000, /* Half duplex mode 0 */ - GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ + GmacRxIpcOffload = 0x00000400, /*IPC checksum offload 10 RW 0 */ - GmacRetry = 0x00000200, + GmacRetry = 0x00000200, GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ - - GmacPadCrcStrip = 0x00000080, + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + + GmacPadCrcStrip = 0x00000080, GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - - GmacBackoffLimit = 0x00000060, + + GmacBackoffLimit = 0x00000060, GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ GmacBackoffLimit2 = 0x00000040, /* */ GmacBackoffLimit1 = 0x00000020, /* */ GmacBackoffLimit0 = 0x00000000, /* 00 */ - GmacDeferralCheck = 0x00000010, + GmacDeferralCheck = 0x00000010, GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - - GmacTx = 0x00000008, + + GmacTx = 0x00000008, GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ - GmacRx = 0x00000004, + GmacRx = 0x00000004, GmacRxEnable = 0x00000004, /* (RE)Receiver enable 2 RW */ GmacRxDisable = 0x00000000, /* Receiver disable 0 */ }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ -enum GmacFrameFilterReg +enum GmacFrameFilterReg { - GmacFilter = 0x80000000, + GmacFilter = 0x80000000, GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ GmacFilterOn = 0x00000000, /* Receive filtered packets only 0 */ - GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ + GmacHashPerfectFilter = 0x00000400, /*Hash or Perfect Filter enable 10 RW 0 */ - GmacSrcAddrFilter = 0x00000200, + GmacSrcAddrFilter = 0x00000200, GmacSrcAddrFilterEnable = 0x00000200, /* (SAF)Source Address Filter enable 9 RW */ GmacSrcAddrFilterDisable = 0x00000000, /* 0 */ @@ -469,13 +469,13 @@ enum GmacFrameFilterReg GmacSrcInvAddrFilterEn = 0x00000100, /* (SAIF)Inv Src Addr Filter enable 8 RW */ GmacSrcInvAddrFilterDis = 0x00000000, /* 0 */ - GmacPassControl = 0x000000C0, + GmacPassControl = 0x000000C0, GmacPassControl3 = 0x000000C0, /* (PCS)Forwards ctrl frms that pass AF 7:6 RW */ GmacPassControl2 = 0x00000080, /* Forwards all control frames */ GmacPassControl1 = 0x00000040, /* Does not pass control frames */ GmacPassControl0 = 0x00000000, /* Does not pass control frames 00 */ - GmacBroadcast = 0x00000020, + GmacBroadcast = 0x00000020, GmacBroadcastDisable = 0x00000020, /* (DBF)Disable Rx of broadcast frames 5 RW */ GmacBroadcastEnable = 0x00000000, /* Enable broadcast frames 0 */ @@ -500,17 +500,17 @@ enum GmacFrameFilterReg GmacPromiscuousModeOff = 0x00000000, /* Receive filtered packets only 0 */ }; - + /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ -enum GmacGmiiAddrReg +enum GmacGmiiAddrReg { GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ GmiiDevShift = 11, GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ GmiiRegShift = 6, - - GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ + + GmiiCsrClkMask = 0x0000001C, /*CSR Clock bit Mask 4:2 */ GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ GmiiCsrClk3 = 0x0000000C, /* 35-60 MHz */ @@ -525,19 +525,19 @@ enum GmacGmiiAddrReg }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ -enum GmacGmiiDataReg +enum GmacGmiiDataReg { GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; /*GmacFlowControl = 0x0018, Flow control Register Layout */ -enum GmacFlowControlReg -{ +enum GmacFlowControlReg +{ GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ GmacPauseTimeShift = 16, - - GmacPauseLowThresh = 0x00000030, + + GmacPauseLowThresh = 0x00000030, GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ GmacPauseLowThresh1 = 0x00000010, /* 28 slot time */ @@ -547,11 +547,11 @@ enum GmacFlowControlReg GmacUnicastPauseFrameOn = 0x00000008, /* (UP)Detect pause frame with unicast addr. 3 RW */ GmacUnicastPauseFrameOff = 0x00000000, /* Detect only pause frame with multicast addr. 0 */ - GmacRxFlowControl = 0x00000004, + GmacRxFlowControl = 0x00000004, GmacRxFlowControlEnable = 0x00000004, /* (RFE)Enable Rx flow control 2 RW */ GmacRxFlowControlDisable = 0x00000000, /* Disable Rx flow control 0 */ - GmacTxFlowControl = 0x00000002, + GmacTxFlowControl = 0x00000002, GmacTxFlowControlEnable = 0x00000002, /* (TFE)Enable Tx flow control 1 RW */ GmacTxFlowControlDisable = 0x00000000, /* Disable flow control 0 */ @@ -559,29 +559,29 @@ enum GmacFlowControlReg GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; -/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { - GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ - GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ - GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ - GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ - GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ - GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ - GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ - GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ + GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ + GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ + GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ + GmacPmtIntSts = 0x00000008, /* set whenver magic pkt/wake-on-lan frame is received */ + GmacPcsAnComplete = 0x00000004, /* set when AN is complete in TBI/RTBI/SGMIII phy interface */ + GmacPcsLnkStsChange = 0x00000002, /* set if any lnk status change in TBI/RTBI/SGMII interface */ + GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; -/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { - GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ - GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ - GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ - GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ - GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ + GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ + GmacPmtIntMask = 0x00000008, /* when set Disables the assertion of PMT interrupt */ + GmacPcsAnIntMask = 0x00000004, /* When set disables the assertion of PCS AN complete interrupt */ + GmacPcsLnkStsIntMask = 0x00000002, /* when set disables the assertion of PCS lnk status change interrupt */ + GmacRgmiiIntMask = 0x00000001, /* when set disables the assertion of RGMII int */ }; /********************************************************** @@ -590,7 +590,7 @@ enum GmacInterruptMaskBitDefinition * For any other system translation is done accordingly **********************************************************/ -enum DmaRegisters +enum DmaRegisters { DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ @@ -601,8 +601,8 @@ enum DmaRegisters DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; @@ -612,19 +612,19 @@ enum DmaRegisters **********************************************************/ /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ -enum DmaBusModeReg +enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ @@ -645,20 +645,20 @@ enum DmaBusModeReg DmaDescriptorSkip1 = 0x00000004, /* */ DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ DmaResetOff = 0x00000000, /* 0 */ }; /*DmaStatus = 0x0014, CSR5 - Dma status Register */ -enum DmaStatusReg -{ - /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ +enum DmaStatusReg +{ + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ @@ -700,52 +700,52 @@ enum DmaStatusReg }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ -enum DmaControlReg -{ - DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - +enum DmaControlReg +{ + DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000300, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ @@ -755,7 +755,7 @@ enum DmaControlReg /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg -{ +{ DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ @@ -783,34 +783,34 @@ enum DmaInterruptReg #ifdef ENH_DESC /* **********Enhanced Descritpor structure to support 8K buffer per buffer **************************** - -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address -DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below -Similarly +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------------- - RDES0 |OWN (31)| Status | - -------------------------------------------------------------------------- - RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - RDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- - RDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + RDES0 |OWN (31)| Status | + -------------------------------------------------------------------------- + RDES1 | Ctrl | Res | Byte Count Buffer 2 | Ctrl | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + RDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- + RDES3 | Buffer 2 Address / Next Descriptor Address | + -------------------------------------------------------------------------- -------------------------------------------------------------------------- - TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | - -------------------------------------------------------------------------- - TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | - -------------------------------------------------------------------------- - TDES2 | Buffer 1 Address | - -------------------------------------------------------------------------- + TDES0 |OWN (31)| Ctrl | Res | Ctrl | Res | Status | + -------------------------------------------------------------------------- + TDES1 | Res | Byte Count Buffer 2 | Res | Byte Count Buffer 1 | + -------------------------------------------------------------------------- + TDES2 | Buffer 1 Address | + -------------------------------------------------------------------------- TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------------- + -------------------------------------------------------------------------- */ @@ -819,15 +819,15 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -839,31 +839,31 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ -// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ DescTxDisableCrc = 0x08000000, /* (DC)Tx - Add CRC disabled (first segment only) 27 */ - DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ + DescTxDisablePadd = 0x04000000, /* (DP)disable padding, added by - reyaz 26 */ - DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x00c00000, /* Tx checksum offloading control mask 23:22 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x00400000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x00800000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x00c00000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ - DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ @@ -874,25 +874,25 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- - */ -// DmaDescriptorLength length word of DMA descriptor + */ +// DmaDescriptorLength length word of DMA descriptor - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ @@ -903,12 +903,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescSize1Shift = 0, - /* - This explains the RDES4 Extended Status bits layout - -------------------------------------------------------------------- - RDES4 | Extended Status | - -------------------------------------------------------------------- - */ + /* + This explains the RDES4 Extended Status bits layout + -------------------------------------------------------------------- + RDES4 | Extended Status | + -------------------------------------------------------------------- + */ DescRxPtpAvail = 0x00004000, /* PTP snapshot available 14 */ DescRxPtpVer = 0x00002000, /* When set indicates IEEE1584 Version 2 (else Ver1) 13 */ DescRxPtpFrameType = 0x00001000, /* PTP frame type Indicates PTP sent over ethernet 12 */ @@ -923,12 +923,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 - error or IP datagram version is not consistent + error or IP datagram version is not consistent with Ethernet type value */ DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ @@ -943,38 +943,38 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ /* ********** Default Descritpor structure **************************** -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below -------------------------------------------------------------------- RDES0/TDES0 |OWN (31)| Status | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES2/TDES2 | Buffer 1 Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- RDES3/TDES3 | Buffer 2 Address / Next Descriptor Address | - -------------------------------------------------------------------- + -------------------------------------------------------------------- */ enum DmaDescriptorStatus /* status word of DMA descriptor */ { DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, DescError = 0x00008000, /* (ES)Error summary bit - OR of the follo. bits: 15 */ - /* DE || OE || IPC || LC || RWT || RE || CE */ + /* DE || OE || IPC || LC || RWT || RE || CE */ DescRxTruncated = 0x00004000, /* (DE)Rx - no more descriptors for receive frame 14 */ DescSAFilterFail = 0x00002000, /* (SAF)Rx - SA Filter Fail for the received frame 13 */ - DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ + DescRxLengthError = 0x00001000, /* (LE)Rx - frm size not matching with len field 12 */ DescRxDamaged = 0x00000800, /* (OE)Rx - frm was damaged due to buffer overflow 11 */ DescRxVLANTag = 0x00000400, /* (VLAN)Rx - received frame is a VLAN frame 10 */ DescRxFirst = 0x00000200, /* (FS)Rx - first descriptor of the frame 9 */ @@ -986,16 +986,16 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ //Rx Descriptor Checksum Offload engine (type 2) encoding - //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ + //DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - - DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ - DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - + + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ + DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ + DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ @@ -1005,21 +1005,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - - /* - This explains the RDES1/TDES1 bits layout - -------------------------------------------------------------------- - RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | - -------------------------------------------------------------------- - */ + /* + This explains the RDES1/TDES1 bits layout + -------------------------------------------------------------------- + RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | + -------------------------------------------------------------------- + + */ //DmaDescriptorLength length word of DMA descriptor DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ @@ -1027,46 +1027,46 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxFirst = 0x20000000, /* (FS)Tx - First segment of the frame 29 */ DescTxDisableCrc = 0x04000000, /* (DC)Tx - Add CRC disabled (first segment only) 26 */ - RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ + RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - - DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ + + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ DescSize2Shift = 11, DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ DescSize1Shift = 0, - DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ - DescTxCisBypass = 0x00000000, /* Checksum bypass */ - DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ - DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ - DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + DescTxCisMask = 0x18000000, /* Tx checksum offloading control mask 28:27 */ + DescTxCisBypass = 0x00000000, /* Checksum bypass */ + DescTxCisIpv4HdrCs = 0x08000000, /* IPv4 header checksum */ + DescTxCisTcpOnlyCs = 0x10000000, /* TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present */ + DescTxCisTcpPseudoCs = 0x18000000, /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ }; #endif // Rx Descriptor COE type2 encoding enum RxDescCOEEncode { - RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ - RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ - RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ - RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ - RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ - RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ - RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ - RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ + RxLenLT600 = 0, /* Bit(5:7:0)=>0 IEEE 802.3 type frame Length field is Lessthan 0x0600 */ + RxIpHdrPayLoadChkBypass = 1, /* Bit(5:7:0)=>1 Payload & Ip header checksum bypassed (unsuppported payload) */ + RxIpHdrPayLoadRes = 2, /* Bit(5:7:0)=>2 Reserved */ + RxChkBypass = 3, /* Bit(5:7:0)=>3 Neither IPv4 nor IPV6. So checksum bypassed */ + RxNoChkError = 4, /* Bit(5:7:0)=>4 No IPv4/IPv6 Checksum error detected */ + RxPayLoadChkError = 5, /* Bit(5:7:0)=>5 Payload checksum error detected for Ipv4/Ipv6 frames */ + RxIpHdrChkError = 6, /* Bit(5:7:0)=>6 Ip header checksum error detected for Ipv4 frames */ + RxIpHdrPayLoadChkError = 7, /* Bit(5:7:0)=>7 Payload & Ip header checksum error detected for Ipv4/Ipv6 frames */ }; /********************************************************** * DMA engine interrupt handling functions **********************************************************/ - + enum synopGMACDmaIntEnum /* Intrerrupt types */ { synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ @@ -1089,7 +1089,7 @@ enum InitialRegisters | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, - + /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff @@ -1097,13 +1097,13 @@ enum InitialRegisters | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ - // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast - // Hash filter. + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacPromiscuousModeOff | GmacUcastHashFilterOff, - + /* Full-duplex mode */ GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, @@ -1112,17 +1112,17 @@ enum InitialRegisters /* Half-duplex mode with perfect filter on */ - // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ @@ -1144,13 +1144,13 @@ enum InitialRegisters DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip2 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, - + /* 1000 Mb/s mode */ DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ DmaControlInit100 = DmaStoreAndForward, - + /* 10 Mb/s mode */ DmaControlInit10 = DmaStoreAndForward, @@ -1178,191 +1178,191 @@ enum InitialRegisters enum MMC_ENABLE { - GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ - GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ - GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ - GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ - GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ + GmacMmcCntrl = 0x0100, /* mmc control for operating mode of MMC */ + GmacMmcIntrRx = 0x0104, /* maintains interrupts generated by rx counters */ + GmacMmcIntrTx = 0x0108, /* maintains interrupts generated by tx counters */ + GmacMmcIntrMaskRx = 0x010C, /* mask for interrupts generated from rx counters */ + GmacMmcIntrMaskTx = 0x0110, /* mask for interrupts generated from tx counters */ }; enum MMC_TX { - GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ - GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ - GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ - - GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ - GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ - GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ - GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ - GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ - GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ - GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ - GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ - GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ - GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ - GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ - GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ - GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - - GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ - GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ + GmacMmcTxOctetCountGb = 0x0114, /*Bytes Tx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ + GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ + GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ + + GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ + GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ + GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ + GmacMmcTxUnderFlowError = 0x0148, /*Frames aborted due to Underflow error */ + GmacMmcTxSingleColG = 0x014C, /*Successfully Tx Frames after singel collision in Half duplex mode */ + GmacMmcTxMultiColG = 0x0150, /*Successfully Tx Frames after more than singel collision in Half duplex mode */ + GmacMmcTxDeferred = 0x0154, /*Successfully Tx Frames after a deferral in Half duplex mode */ + GmacMmcTxLateCol = 0x0158, /*Frames aborted due to late collision error */ + GmacMmcTxExessCol = 0x015C, /*Frames aborted due to excessive (16) collision errors */ + GmacMmcTxCarrierError = 0x0160, /*Frames aborted due to carrier sense error (No carrier or Loss of carrier) */ + GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ + GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ + GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ + + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ + GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; enum MMC_RX { - GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ - GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ - GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ - GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ - GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - - GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ - GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ - GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ - GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ - GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ - GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ - - GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ - GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ - GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ - GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ - GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ - GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - - GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ - GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ - GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - - GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ - GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ - GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - - GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ + GmacMmcRxFrameCountGb = 0x0180, /*Frames Rx (Good or Bad) */ + GmacMmcRxOctetCountGb = 0x0184, /*Bytes Rx excl. of preamble and retried bytes (Good or Bad) */ + GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ + GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ + GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ + + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ + GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ + GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ + GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ + GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ + GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ + + GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ + GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ + GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ + GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ + GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ + GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ + + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ + GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ + GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ + + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ + GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ + GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ + + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; enum MMC_IP_RELATED { - GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ - GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - - GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ - GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ - GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ - GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - - GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ - GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ - GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - - GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ + GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ + GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - - GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ - GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ - GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ - GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - - GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ - GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ - GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - - GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ - GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - - GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ - GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - - GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ - GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ + GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ + GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ + GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ + + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ + GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ + GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ + + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ + + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ + GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ + GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ + GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ + + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ + GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ + GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ + + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ + GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ + + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ + GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ + + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ + GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; enum MMC_CNTRL_REG_BIT_DESCRIPTIONS { - GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ - GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ - GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ - GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ - + GmacMmcCounterFreeze = 0x00000008, /* when set MMC counters freeze to current value */ + GmacMmcCounterResetOnRead = 0x00000004, /* when set MMC counters will be reset to 0 after read */ + GmacMmcCounterStopRollover = 0x00000002, /* when set counters will not rollover after max value */ + GmacMmcCounterReset = 0x00000001, /* when set all counters wil be reset (automatically cleared after 1 clk) */ + }; enum MMC_RX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ - GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ - GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ - GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ - GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ - GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ - GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ - GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ - GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ - GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ - GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ - GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ - GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ - GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ - GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ - GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ - GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ - GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ - GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ - GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ - GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ - GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ - GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ + GmacMmcRxWDInt = 0x00800000, /* set when rxwatchdog error reaches half of max value */ + GmacMmcRxVlanInt = 0x00400000, /* set when GmacMmcRxVlanFramesGb counter reaches half of max value */ + GmacMmcRxFifoOverFlowInt = 0x00200000, /* set when GmacMmcRxFifoOverFlow counter reaches half of max value */ + GmacMmcRxPauseFrameInt = 0x00100000, /* set when GmacMmcRxPauseFrames counter reaches half of max value */ + GmacMmcRxOutOfRangeInt = 0x00080000, /* set when GmacMmcRxOutOfRangeType counter reaches half of max value */ + GmacMmcRxLengthErrorInt = 0x00040000, /* set when GmacMmcRxLengthError counter reaches half of max value */ + GmacMmcRxUcFramesInt = 0x00020000, /* set when GmacMmcRxUcFramesG counter reaches half of max value */ + GmacMmcRx1024OctInt = 0x00010000, /* set when GmacMmcRx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcRx512OctInt = 0x00008000, /* set when GmacMmcRx512To1023OctetsGb counter reaches half of max value */ + GmacMmcRx256OctInt = 0x00004000, /* set when GmacMmcRx256To511OctetsGb counter reaches half of max value */ + GmacMmcRx128OctInt = 0x00002000, /* set when GmacMmcRx128To255OctetsGb counter reaches half of max value */ + GmacMmcRx65OctInt = 0x00001000, /* set when GmacMmcRx65To127OctetsG counter reaches half of max value */ + GmacMmcRx64OctInt = 0x00000800, /* set when GmacMmcRx64OctetsGb counter reaches half of max value */ + GmacMmcRxOverSizeInt = 0x00000400, /* set when GmacMmcRxOverSizeG counter reaches half of max value */ + GmacMmcRxUnderSizeInt = 0x00000200, /* set when GmacMmcRxUnderSizeG counter reaches half of max value */ + GmacMmcRxJabberErrorInt = 0x00000100, /* set when GmacMmcRxJabberError counter reaches half of max value */ + GmacMmcRxRuntErrorInt = 0x00000080, /* set when GmacMmcRxRuntError counter reaches half of max value */ + GmacMmcRxAlignErrorInt = 0x00000040, /* set when GmacMmcRxAlignError counter reaches half of max value */ + GmacMmcRxCrcErrorInt = 0x00000020, /* set when GmacMmcRxCrcError counter reaches half of max value */ + GmacMmcRxMcFramesInt = 0x00000010, /* set when GmacMmcRxMcFramesG counter reaches half of max value */ + GmacMmcRxBcFramesInt = 0x00000008, /* set when GmacMmcRxBcFramesG counter reaches half of max value */ + GmacMmcRxOctetGInt = 0x00000004, /* set when GmacMmcRxOctetCountG counter reaches half of max value */ + GmacMmcRxOctetGbInt = 0x00000002, /* set when GmacMmcRxOctetCountGb counter reaches half of max value */ + GmacMmcRxFrameInt = 0x00000001, /* set when GmacMmcRxFrameCountGb counter reaches half of max value */ }; enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS { - GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ - GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ - GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ - GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ - GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ - GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ - GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ - GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ - GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ - GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ - GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ - GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ - GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ - GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ - GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ - GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ - GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ - GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ - GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ - GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ - GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ - GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ - GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ - GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ - GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ - + GmacMmcTxVlanInt = 0x01000000, /* set when GmacMmcTxVlanFramesG counter reaches half of max value */ + GmacMmcTxPauseFrameInt = 0x00800000, /* set when GmacMmcTxPauseFrames counter reaches half of max value */ + GmacMmcTxExessDefInt = 0x00400000, /* set when GmacMmcTxExessDef counter reaches half of max value */ + GmacMmcTxFrameInt = 0x00200000, /* set when GmacMmcTxFrameCount counter reaches half of max value */ + GmacMmcTxOctetInt = 0x00100000, /* set when GmacMmcTxOctetCountG counter reaches half of max value */ + GmacMmcTxCarrierErrorInt = 0x00080000, /* set when GmacMmcTxCarrierError counter reaches half of max value */ + GmacMmcTxExessColInt = 0x00040000, /* set when GmacMmcTxExessCol counter reaches half of max value */ + GmacMmcTxLateColInt = 0x00020000, /* set when GmacMmcTxLateCol counter reaches half of max value */ + GmacMmcTxDeferredInt = 0x00010000, /* set when GmacMmcTxDeferred counter reaches half of max value */ + GmacMmcTxMultiColInt = 0x00008000, /* set when GmacMmcTxMultiColG counter reaches half of max value */ + GmacMmcTxSingleCol = 0x00004000, /* set when GmacMmcTxSingleColG counter reaches half of max value */ + GmacMmcTxUnderFlowErrorInt = 0x00002000, /* set when GmacMmcTxUnderFlowError counter reaches half of max value */ + GmacMmcTxBcFramesGbInt = 0x00001000, /* set when GmacMmcTxBcFramesGb counter reaches half of max value */ + GmacMmcTxMcFramesGbInt = 0x00000800, /* set when GmacMmcTxMcFramesGb counter reaches half of max value */ + GmacMmcTxUcFramesInt = 0x00000400, /* set when GmacMmcTxUcFramesGb counter reaches half of max value */ + GmacMmcTx1024OctInt = 0x00000200, /* set when GmacMmcTx1024ToMaxOctetsGb counter reaches half of max value */ + GmacMmcTx512OctInt = 0x00000100, /* set when GmacMmcTx512To1023OctetsGb counter reaches half of max value */ + GmacMmcTx256OctInt = 0x00000080, /* set when GmacMmcTx256To511OctetsGb counter reaches half of max value */ + GmacMmcTx128OctInt = 0x00000040, /* set when GmacMmcTx128To255OctetsGb counter reaches half of max value */ + GmacMmcTx65OctInt = 0x00000020, /* set when GmacMmcTx65To127OctetsGb counter reaches half of max value */ + GmacMmcTx64OctInt = 0x00000010, /* set when GmacMmcTx64OctetsGb counter reaches half of max value */ + GmacMmcTxMcFramesInt = 0x00000008, /* set when GmacMmcTxMcFramesG counter reaches half of max value */ + GmacMmcTxBcFramesInt = 0x00000004, /* set when GmacMmcTxBcFramesG counter reaches half of max value */ + GmacMmcTxFrameGbInt = 0x00000002, /* set when GmacMmcTxFrameCountGb counter reaches half of max value */ + GmacMmcTxOctetGbInt = 0x00000001, /* set when GmacMmcTxOctetCountGb counter reaches half of max value */ + }; /********************************************************** - * Power Management (PMT) Block + * Power Management (PMT) Block **********************************************************/ /** @@ -1372,36 +1372,36 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS * These enable are in PMT control and Status register and are programmed by apllication. * * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes - * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received * and the corresponding detection is enabled. * - * Driver need not be modified to support this feature. Only Api to put the device in to power + * Driver need not be modified to support this feature. Only Api to put the device in to power * down mode is sufficient */ -#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ +#define WAKEUP_REG_LENGTH 8 /*This is the reg length for wake up register configuration*/ enum GmacPmtCtrlStatusBitDefinition { - GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ - GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ - GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ - GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ - GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ - GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ - GmacPmtPowerDown = 0x00000001, /* Power Down */ + GmacPmtFrmFilterPtrReset = 0x80000000, /* when set remote wake-up frame filter register pointer to 3'b000 */ + GmacPmtGlobalUnicast = 0x00000200, /* When set enables any unicast packet to be a wake-up frame */ + GmacPmtWakeupFrameReceived = 0x00000040, /* Wake up frame received */ + GmacPmtMagicPktReceived = 0x00000020, /* Magic Packet received */ + GmacPmtWakeupFrameEnable = 0x00000004, /* Wake-up frame enable */ + GmacPmtMagicPktEnable = 0x00000002, /* Magic packet enable */ + GmacPmtPowerDown = 0x00000001, /* Power Down */ }; /********************************************************** - * IEEE 1588-2008 Precision Time Protocol (PTP) Support + * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { - SYNC = 0x0, - Delay_Req = 0x1, + SYNC = 0x0, + Delay_Req = 0x1, Pdelay_Req = 0x2, Pdelay_Resp = 0x3, Follow_up = 0x8, @@ -1414,14 +1414,14 @@ enum PTPMessageType -typedef struct TimeStampStruct -{ +typedef struct TimeStampStruct +{ u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSmessagetype; /* Message type associated with this time stamp */ - u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ - u32 TSupper32; /* Most significant 32 bit time stamp value */ - u32 TSlower32; /* Least Significat 32 bit time stamp value */ + u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ + u32 TSupper32; /* Most significant 32 bit time stamp value */ + u32 TSlower32; /* Least Significat 32 bit time stamp value */ } TimeStamp; @@ -1439,9 +1439,9 @@ typedef struct TimeStampStruct /* GmacTSControl = 0x0700, Controls the Timestamp update logic : only when IEEE 1588 time stamping is enabled in corekit */ enum GmacTSControlReg { - GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - - GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ + GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ + + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken 00/01 X 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP @@ -1450,45 +1450,45 @@ enum GmacTSControlReg 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP 10 NA 1 SYNC, FOLLOW_UP 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP - 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ - GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ - GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ - GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ - GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ + GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ + GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ + GmacTSEtoEClk = 0x00020000, /* 10=> End-to-End transparent clock*/ + GmacTSPtoPClk = 0x00030000, /* 11=> P-to-P transparent clock*/ - GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ - GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ - GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ - GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ - GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ - GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ + GmacTSMSTRENA = 0x00008000, /* Ena TS Snapshot for Master Messages 15 RW 0 */ + GmacTSEVNTENA = 0x00004000, /* Ena TS Snapshot for Event Messages 14 RW 0 */ + GmacTSIPV4ENA = 0x00002000, /* Ena TS snapshot for IPv4 13 RW 1 */ + GmacTSIPV6ENA = 0x00001000, /* Ena TS snapshot for IPv6 12 RW 0 */ + GmacTSIPENA = 0x00000800, /* Ena TS snapshot for PTP over E'net 11 RW 0 */ + GmacTSVER2ENA = 0x00000400, /* Ena PTP snooping for version 2 10 RW 0 */ GmacTSCTRLSSR = 0x00000200, /* Digital or Binary Rollover 9 RW 0 */ GmacTSENALL = 0x00000100, /* Enable TS fro all frames (Ver2 only) 8 RW 0 */ - GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ - GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ - GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - - GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ + GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ + GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ + GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ - GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ - GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ - GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ + GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ + GmacTSCUPDTCoarse = 0x00000000, /* 0=> Time Stamp update method is coarse */ + GmacTSCUPDTFine = 0x00000002, /* 1=> Time Stamp update method is fine */ + + GmacTSENA = 0x00000001, /* Time Stamp Enable 0 RW 0 */ }; -/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ +/* GmacTSSubSecIncr = 0x0704, 8 bit value by which sub second register is incremented : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSSubSecIncrReg { GmacSSINCMsk = 0x000000FF, /* Only Lower 8 bits are valid bits 7:0 RW 00 */ }; -/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ +/* GmacTSLow = 0x070C, Indicates whether the timestamp low count is positive or negative; for Adv timestamp it is always zero */ enum GmacTSSign { GmacTSSign = 0x80000000, /* PSNT 31 RW 0 */ @@ -1496,23 +1496,23 @@ enum GmacTSSign GmacTSNegative = 0x80000000, }; -/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ +/*GmacTargetTimeLow = 0x0718, 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ enum GmacTSLowReg { GmacTSDecThr = 0x3B9AC9FF, /*when TSCTRLSSR is set the max value for GmacTargetTimeLowReg and GmacTimeStampLow register is 0x3B9AC9FF at 1ns precision */ }; /* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ -enum GmacTSHighWordReg +enum GmacTSHighWordReg { - GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ + GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ }; /*GmacTSStatus = 0x0728, Time Stamp Status Register */ enum GmacTSStatusReg { GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ -}; +}; /********************************************************** @@ -1527,9 +1527,9 @@ void synopGMAC_TS_int_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev); void synopGMAC_TS_set_clk_type(synopGMACdevice *gmacdev, u32 clk_type); -void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" -void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" +void synopGMAC_TS_master_enable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_master_disable(synopGMACdevice *gmacdev); // Only for Ordinary clock and Boundary clock and "Advanced Time Stamp" +void synopGMAC_TS_event_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_event_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_IPV4_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1540,7 +1540,7 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" -void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1549,11 +1549,11 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value); s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value); -void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled -void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled +void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask -void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided @@ -1571,7 +1571,7 @@ s32 synopGMAC_read_phy_reg(u32 RegBase,u32 PhyBase, u32 RegOffset, u16 * data); s32 synopGMAC_write_phy_reg(u32 RegBase, u32 PhyBase, u32 RegOffset, u16 data); s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ; -s32 synopGMAC_reset (synopGMACdevice * gmacdev ); +s32 synopGMAC_reset (synopGMACdevice * gmacdev ); s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ); s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ); void synopGMAC_wd_enable(synopGMACdevice * gmacdev); @@ -1669,15 +1669,15 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc); bool synopGMAC_is_tx_desc_chained(DmaDesc * desc); void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, - u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, + u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2 ); #endif s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2,u32 offload_needed,u32 * index,DmaDesc *Dpr); s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u32 Data1, u32 Buffer2, u32 Length2, u32 Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u32 * Data1, u32 * Buffer2, u32 * Length2, u32 * Data2); @@ -1698,8 +1698,8 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev); /******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); -bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status); /*******************PMT APIs***************************************/ diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Host.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Host.h index e6d31d551d..1851078701 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Host.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_Host.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,35 +21,35 @@ struct net_device_stats { - unsigned long rx_packets; /* total packets received */ - unsigned long tx_packets; /* total packets transmitted */ - unsigned long rx_bytes; /* total bytes received */ - unsigned long tx_bytes; /* total bytes transmitted */ - unsigned long rx_errors; /* bad packets received */ - unsigned long tx_errors; /* packet transmit problems */ - unsigned long rx_dropped; /* no space in linux buffers */ - unsigned long tx_dropped; /* no space available in linux */ - unsigned long multicast; /* multicast packets received */ - unsigned long collisions; + unsigned long rx_packets; /* total packets received */ + unsigned long tx_packets; /* total packets transmitted */ + unsigned long rx_bytes; /* total bytes received */ + unsigned long tx_bytes; /* total bytes transmitted */ + unsigned long rx_errors; /* bad packets received */ + unsigned long tx_errors; /* packet transmit problems */ + unsigned long rx_dropped; /* no space in linux buffers */ + unsigned long tx_dropped; /* no space available in linux */ + unsigned long multicast; /* multicast packets received */ + unsigned long collisions; - /* detailed rx_errors: */ - unsigned long rx_length_errors; - unsigned long rx_over_errors; /* receiver ring buff overflow */ - unsigned long rx_crc_errors; /* recved pkt with crc error */ - unsigned long rx_frame_errors; /* recv'd frame alignment error */ - unsigned long rx_fifo_errors; /* recv'r fifo overrun */ - unsigned long rx_missed_errors; /* receiver missed packet */ + /* detailed rx_errors: */ + unsigned long rx_length_errors; + unsigned long rx_over_errors; /* receiver ring buff overflow */ + unsigned long rx_crc_errors; /* recved pkt with crc error */ + unsigned long rx_frame_errors; /* recv'd frame alignment error */ + unsigned long rx_fifo_errors; /* recv'r fifo overrun */ + unsigned long rx_missed_errors; /* receiver missed packet */ - /* detailed tx_errors */ - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - - /* for cslip etc */ - unsigned long rx_compressed; - unsigned long tx_compressed; + /* detailed tx_errors */ + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + + /* for cslip etc */ + unsigned long rx_compressed; + unsigned long tx_compressed; }; diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_debug.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_debug.h index 9766587e1a..312105185a 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_debug.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,8 +14,8 @@ //#define GMAC_DEBUG #include -#ifdef GMAC_DEBUG -#define DEBUG_MES rt_kprintf +#ifdef GMAC_DEBUG +#define DEBUG_MES rt_kprintf #else #define DEBUG_MES(...) #endif diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_network_interface.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_network_interface.h index 8ded91d359..0e910b5d1f 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_network_interface.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_network_interface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2017-08-24 chinesebear first version */ - + #ifndef SYNOP_GMAC_NETWORK_INTERFACE_H #define SYNOP_GMAC_NETWORK_INTERFACE_H 1 diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.c b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.c index 3dfbe077d7..45225ba362 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.c +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,7 +8,7 @@ * 2017-08-24 chinesebear first version */ - + #include "synopGMAC_plat.h" #include "synopGMAC_Dev.h" #include @@ -16,58 +16,58 @@ extern void flush_cache(unsigned long start_addr, unsigned long size); dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size) { - return VA_TO_PA (va); - //return UNCACHED_TO_PHYS(va); + return VA_TO_PA (va); + //return UNCACHED_TO_PHYS(va); } /** - * This is a wrapper function for Memory allocation routine. In linux Kernel + * This is a wrapper function for Memory allocation routine. In linux Kernel * it it kmalloc function * @param[in] bytes in bytes to allocate */ -void *plat_alloc_memory(u32 bytes) +void *plat_alloc_memory(u32 bytes) { //return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT); - void *buf = (void*)rt_malloc((u32)bytes); + void *buf = (void*)rt_malloc((u32)bytes); - flush_cache((unsigned long)buf, bytes); - return buf; + flush_cache((unsigned long)buf, bytes); + return buf; } /** - * This is a wrapper function for consistent dma-able Memory allocation routine. + * This is a wrapper function for consistent dma-able Memory allocation routine. * In linux Kernel, it depends on pci dev structure * @param[in] bytes in bytes to allocate */ -//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr) -void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) +//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr) +void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr) { - void *buf; - buf = (void*)rt_malloc((u32)(size+16)); - //CPU_IOFlushDCache( buf,size, SYNC_W); - unsigned long i = (unsigned long)buf; -// rt_kprintf("size = %d\n", size); -// rt_kprintf("bufaddr = %p\n", buf); -// rt_kprintf("i%%16 == %d\n", i%16); - if(i%16 == 8){ - i += 8; - } - else if(i%16 == 4){ - i += 12; - } - else if(i%16 == 12){ - i += 4; - } + void *buf; + buf = (void*)rt_malloc((u32)(size+16)); + //CPU_IOFlushDCache( buf,size, SYNC_W); + unsigned long i = (unsigned long)buf; +// rt_kprintf("size = %d\n", size); +// rt_kprintf("bufaddr = %p\n", buf); +// rt_kprintf("i%%16 == %d\n", i%16); + if(i%16 == 8){ + i += 8; + } + else if(i%16 == 4){ + i += 12; + } + else if(i%16 == 12){ + i += 4; + } - flush_cache(i, size); - *addr =gmac_dmamap(i, size); - buf = (unsigned char *)CACHED_TO_UNCACHED(i); -// rt_kprintf("bufaddr = %p\n", buf); - return buf; + flush_cache(i, size); + *addr =gmac_dmamap(i, size); + buf = (unsigned char *)CACHED_TO_UNCACHED(i); +// rt_kprintf("bufaddr = %p\n", buf); + return buf; } @@ -78,46 +78,46 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3 */ -//void plat_free_consistent_dmaable_memory(void * addr) -void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr) +//void plat_free_consistent_dmaable_memory(void * addr) +void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr) { - rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); + rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr))); return; } /** - * This is a wrapper function for Memory free routine. In linux Kernel + * This is a wrapper function for Memory free routine. In linux Kernel * it it kfree function * @param[in] buffer pointer to be freed */ -void plat_free_memory(void *buffer) +void plat_free_memory(void *buffer) { - rt_free(buffer); - return ; + rt_free(buffer); + return ; } dma_addr_t plat_dma_map_single(void *hwdev, void *ptr, - u32 size) + u32 size) { - unsigned long addr = (unsigned long) ptr; + unsigned long addr = (unsigned long) ptr; //CPU_IOFlushDCache(addr,size, direction); - flush_cache(addr, size); + flush_cache(addr, size); return gmac_dmamap(addr, size); } /** - * This is a wrapper function for platform dependent delay - * Take care while passing the argument to this function + * This is a wrapper function for platform dependent delay + * Take care while passing the argument to this function * @param[in] buffer pointer to be freed */ void plat_delay(u32 delay) { - while (delay--); - return; + while (delay--); + return; } diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.h index 173015a53f..be9dd2606d 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,12 +8,12 @@ * 2017-08-24 chinesebear first version */ - - + + #ifndef SYNOP_GMAC_PLAT_H #define SYNOP_GMAC_PLAT_H 1 -/* sw +/* sw #include #include #include @@ -26,7 +26,7 @@ //#include "GMAC_Pmon.h" //#include "synopGMAC_Host.h" #include -//sw: copy the type define into here +//sw: copy the type define into here #define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1 #define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2 #define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3 @@ -58,18 +58,18 @@ typedef int bool; #define VA_TO_PA(x) UNCACHED_TO_PHYS(x) -/* sw -#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) +/* sw +#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #ifdef DEBUG #undef TR # define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #else -# define TR(fmt, args...) // not debugging: nothing +# define TR(fmt, args...) // not debugging: nothing #endif */ /* -#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) +#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) */ /* @@ -77,21 +77,21 @@ typedef int bool; #undef TR # define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #else -//# define TR(fmt, args...) // not debugging: nothing -#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) +//# define TR(fmt, args...) // not debugging: nothing +#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #endif */ //sw: nothing to display -#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) -#define TR(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR(fmt, args...) //rt_kprintf(fmt, ##args) //#define TR rt_kprintf //typedef int bool; enum synopGMAC_boolean - { + { false = 0, - true = 1 + true = 1 }; @@ -102,9 +102,9 @@ enum synopGMAC_boolean * */ -#define LE32_TO_CPU __le32_to_cpu -#define BE32_TO_CPU __be32_to_cpu -#define CPU_TO_LE32 __cpu_to_le32 +#define LE32_TO_CPU __le32_to_cpu +#define BE32_TO_CPU __be32_to_cpu +#define CPU_TO_LE32 __cpu_to_le32 /* Error Codes */ #define ESYNOPGMACNOERR 0 @@ -114,15 +114,15 @@ enum synopGMAC_boolean struct Network_interface_data { - u32 unit; - u32 addr; - u32 data; + u32 unit; + u32 addr; + u32 data; }; /** * These are the wrapper function prototypes for OS/platform related routines - */ + */ void * plat_alloc_memory(u32 ); void plat_free_memory(void *); @@ -135,10 +135,10 @@ void plat_delay(u32); /** * The Low level function to read register contents from Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * \return Returns the register contents + * \return Returns the register contents */ static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset) { @@ -158,43 +158,43 @@ static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset) /** * The Low level function to write to a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Data to be written - * \return void + * @param[in] Data to be written + * \return void */ static void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData ) { u32 addr; - addr = RegBase + (u32)RegOffset; + addr = RegBase + (u32)RegOffset; // rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData ); #if SYNOP_REG_DEBUG TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData ); #endif - *(volatile u32 *)addr = RegData; + *(volatile u32 *)addr = RegData; - if(addr == 0xbfe1100c) - DEBUG_MES("regdata = %08x\n", RegData); + if(addr == 0xbfe1100c) + DEBUG_MES("regdata = %08x\n", RegData); return; } /** * The Low level function to set bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 - * \return void + * @param[in] Bit mask to set bits to logical 1 + * \return void */ static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos) { //u64 addr = (u64)RegBase + (u64)RegOffset; u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data |= BitPos; + data |= BitPos; synopGMACWriteReg(RegBase, RegOffset, data); // writel(data,(void *)addr); #if SYNOP_REG_DEBUG @@ -206,17 +206,17 @@ static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to clear bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to clear bits to logical 0 - * \return void + * @param[in] Bit mask to clear bits to logical 0 + * \return void */ static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= (~BitPos); + data &= (~BitPos); synopGMACWriteReg(RegBase, RegOffset, data); #if SYNOP_REG_DEBUG TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); @@ -226,21 +226,21 @@ static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to Check the setting of the bits. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 + * @param[in] Bit mask to set bits to logical 1 * \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument. - * + * */ static bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= BitPos; + data &= BitPos; if(data) return true; - else return false; + else return false; } diff --git a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_types.h b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_types.h index 88504eebf7..0961d70190 100644 --- a/bsp/loongson/ls1cdev/drivers/net/synopGMAC_types.h +++ b/bsp/loongson/ls1cdev/drivers/net/synopGMAC_types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,4 +22,4 @@ typedef signed int s32; typedef u32 dma_addr_t; -#endif /*__TYPES__H*/ +#endif /*__TYPES__H*/ diff --git a/bsp/loongson/ls1cdev/drivers/selfboot.h b/bsp/loongson/ls1cdev/drivers/selfboot.h index def9e38229..4f44206110 100644 --- a/bsp/loongson/ls1cdev/drivers/selfboot.h +++ b/bsp/loongson/ls1cdev/drivers/selfboot.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,52 +12,52 @@ #define __RT_LS1C_SELFBOOT_H /* SDRAM PARAM macro */ -#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM) +#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM) /* SDRAM ROW */ -#define ROW_1K 0x7 -#define ROW_2K 0x0 -#define ROW_4K 0x1 -#define ROW_8K 0x2 -#define ROW_16K 0x3 +#define ROW_1K 0x7 +#define ROW_2K 0x0 +#define ROW_4K 0x1 +#define ROW_8K 0x2 +#define ROW_16K 0x3 /* SDRAM COL */ -#define COL_256 0x7 -#define COL_512 0x0 -#define COL_1K 0x1 -#define COL_2K 0x2 -#define COL_4K 0x3 +#define COL_256 0x7 +#define COL_512 0x0 +#define COL_1K 0x1 +#define COL_2K 0x2 +#define COL_4K 0x3 /* SDRAM WIDTH */ -#define WIDTH_8 0x0 -#define WIDTH_16 0x1 -#define WIDTH_32 0x2 +#define WIDTH_8 0x0 +#define WIDTH_16 0x1 +#define WIDTH_32 0x2 -#define TRCD 3 -#define TCL 3 -#define TRP 3 -#define TRFC 8 -#define TRAS 6 -#define TREF 0x818 -#define TWR 2 +#define TRCD 3 +#define TCL 3 +#define TRP 3 +#define TRFC 8 +#define TRAS 6 +#define TREF 0x818 +#define TWR 2 -#define DEF_SEL 0x1 -#define DEF_SEL_N 0x0 -#define HANG_UP 0x1 -#define HANG_UP_N 0x0 -#define CFG_VALID 0x1 +#define DEF_SEL 0x1 +#define DEF_SEL_N 0x0 +#define HANG_UP 0x1 +#define HANG_UP_N 0x0 +#define CFG_VALID 0x1 #include "board.h" -#define SD_PARA0 (0x7f<<25 | \ - (TRAS << 21) | \ - (TRFC << 17) | (TRP << 14) | (TCL << 11) | \ - (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \ - SDRAM_ROW) +#define SD_PARA0 (0x7f<<25 | \ + (TRAS << 21) | \ + (TRFC << 17) | (TRP << 14) | (TCL << 11) | \ + (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \ + SDRAM_ROW) -#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) +#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) -#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \ - (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) +#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \ + (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7)) #define LS1C_CBUS_FIRST1 0xBFE011C4 #define LS1C_UART2_BASE 0xBFE48000 @@ -76,62 +76,62 @@ #define LS1C_UART_MSB_OFFSET (1) /* interrupt enable register */ -#define IER_IRxE 0x1 -#define IER_ITxE 0x2 -#define IER_ILE 0x4 -#define IER_IME 0x8 +#define IER_IRxE 0x1 +#define IER_ITxE 0x2 +#define IER_ILE 0x4 +#define IER_IME 0x8 /* interrupt identification register */ -#define IIR_IMASK 0xf /* mask */ -#define IIR_RXTOUT 0xc /* receive timeout */ -#define IIR_RLS 0x6 /* receive line status */ -#define IIR_RXRDY 0x4 /* receive ready */ -#define IIR_TXRDY 0x2 /* transmit ready */ -#define IIR_NOPEND 0x1 /* nothing */ -#define IIR_MLSC 0x0 /* modem status */ -#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ +#define IIR_IMASK 0xf /* mask */ +#define IIR_RXTOUT 0xc /* receive timeout */ +#define IIR_RLS 0x6 /* receive line status */ +#define IIR_RXRDY 0x4 /* receive ready */ +#define IIR_TXRDY 0x2 /* transmit ready */ +#define IIR_NOPEND 0x1 /* nothing */ +#define IIR_MLSC 0x0 /* modem status */ +#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ /* fifo control register */ -#define FIFO_ENABLE 0x01 /* enable fifo */ -#define FIFO_RCV_RST 0x02 /* reset receive fifo */ -#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ -#define FIFO_DMA_MODE 0x08 /* enable dma mode */ -#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ -#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ -#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ -#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ +#define FIFO_ENABLE 0x01 /* enable fifo */ +#define FIFO_RCV_RST 0x02 /* reset receive fifo */ +#define FIFO_XMT_RST 0x04 /* reset transmit fifo */ +#define FIFO_DMA_MODE 0x08 /* enable dma mode */ +#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ +#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ +#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ +#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ /* character format control register */ -#define CFCR_DLAB 0x80 /* divisor latch */ -#define CFCR_SBREAK 0x40 /* send break */ -#define CFCR_PZERO 0x30 /* zero parity */ -#define CFCR_PONE 0x20 /* one parity */ -#define CFCR_PEVEN 0x10 /* even parity */ -#define CFCR_PODD 0x00 /* odd parity */ -#define CFCR_PENAB 0x08 /* parity enable */ -#define CFCR_STOPB 0x04 /* 2 stop bits */ -#define CFCR_8BITS 0x03 /* 8 data bits */ -#define CFCR_7BITS 0x02 /* 7 data bits */ -#define CFCR_6BITS 0x01 /* 6 data bits */ -#define CFCR_5BITS 0x00 /* 5 data bits */ +#define CFCR_DLAB 0x80 /* divisor latch */ +#define CFCR_SBREAK 0x40 /* send break */ +#define CFCR_PZERO 0x30 /* zero parity */ +#define CFCR_PONE 0x20 /* one parity */ +#define CFCR_PEVEN 0x10 /* even parity */ +#define CFCR_PODD 0x00 /* odd parity */ +#define CFCR_PENAB 0x08 /* parity enable */ +#define CFCR_STOPB 0x04 /* 2 stop bits */ +#define CFCR_8BITS 0x03 /* 8 data bits */ +#define CFCR_7BITS 0x02 /* 7 data bits */ +#define CFCR_6BITS 0x01 /* 6 data bits */ +#define CFCR_5BITS 0x00 /* 5 data bits */ /* modem control register */ -#define MCR_LOOPBACK 0x10 /* loopback */ -#define MCR_IENABLE 0x08 /* output 2 = int enable */ -#define MCR_DRS 0x04 /* output 1 = xxx */ -#define MCR_RTS 0x02 /* enable RTS */ -#define MCR_DTR 0x01 /* enable DTR */ +#define MCR_LOOPBACK 0x10 /* loopback */ +#define MCR_IENABLE 0x08 /* output 2 = int enable */ +#define MCR_DRS 0x04 /* output 1 = xxx */ +#define MCR_RTS 0x02 /* enable RTS */ +#define MCR_DTR 0x01 /* enable DTR */ /* line status register */ -#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ -#define LSR_TSRE 0x40 /* transmitter empty */ -#define LSR_TXRDY 0x20 /* transmitter ready */ -#define LSR_BI 0x10 /* break detected */ -#define LSR_FE 0x08 /* framing error */ -#define LSR_PE 0x04 /* parity error */ -#define LSR_OE 0x02 /* overrun error */ -#define LSR_RXRDY 0x01 /* receiver ready */ -#define LSR_RCV_MASK 0x1f +#define LSR_RCV_FIFO 0x80 /* error in receive fifo */ +#define LSR_TSRE 0x40 /* transmitter empty */ +#define LSR_TXRDY 0x20 /* transmitter ready */ +#define LSR_BI 0x10 /* break detected */ +#define LSR_FE 0x08 /* framing error */ +#define LSR_PE 0x04 /* parity error */ +#define LSR_OE 0x02 /* overrun error */ +#define LSR_RXRDY 0x01 /* receiver ready */ +#define LSR_RCV_MASK 0x1f /* External clock frequency */ diff --git a/bsp/loongson/ls1cdev/drivers/touch.c b/bsp/loongson/ls1cdev/drivers/touch.c index 37a4b19213..31076be5ed 100644 --- a/bsp/loongson/ls1cdev/drivers/touch.c +++ b/bsp/loongson/ls1cdev/drivers/touch.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,13 +7,13 @@ * Date Author Notes * 2017-12-30 Sundm75 first version */ - + #include #include #include #include #include "ls1c.h" -#include "ls1c_gpio.h" +#include "ls1c_gpio.h" #include "ls1c_spi.h" #include "drv_spi.h" #include "touch.h" @@ -44,7 +44,7 @@ TOUCH INT: 84 */ #define IS_TOUCH_UP() gpio_get(TOUCH_INT_PIN) -#define led_gpio 52 // led1指示 +#define led_gpio 52 // led1指示 #define DUMMY 0x00 @@ -88,12 +88,12 @@ s A2-A0 MODE SER/DFR PD1-PD0 #if defined(_ILI_HORIZONTAL_DIRECTION_) #define MIN_X_DEFAULT 2047 #define MAX_X_DEFAULT 47 -#define MIN_Y_DEFAULT 102 -#define MAX_Y_DEFAULT 1939 +#define MIN_Y_DEFAULT 102 +#define MAX_Y_DEFAULT 1939 #else #define MIN_X_DEFAULT 47 #define MAX_X_DEFAULT 2047 -#define MIN_Y_DEFAULT 1939 +#define MIN_Y_DEFAULT 1939 #define MAX_Y_DEFAULT 102 #endif @@ -105,29 +105,29 @@ s A2-A0 MODE SER/DFR PD1-PD0 /*宏定义 */ -#define TOUCH_SPI_X SPI1 -#define TOUCH_INT_PIN 84 -#define TOUCH_CS_PIN 49 +#define TOUCH_SPI_X SPI1 +#define TOUCH_INT_PIN 84 +#define TOUCH_CS_PIN 49 #define TOUCH_SCK_PIN 46 #define TOUCH_MISO_PIN 47 -#define TOUCH_MOSI_PIN 48 +#define TOUCH_MOSI_PIN 48 /*创建结构体将需要用到的东西进行打包*/ -struct rtgui_touch_device +struct rtgui_touch_device { struct rt_device parent; /* 用于注册设备*/ - rt_uint16_t x, y; /* 记录读取到的位置值 */ + rt_uint16_t x, y; /* 记录读取到的位置值 */ - rt_bool_t calibrating; /* 触摸校准标志 */ - rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */ + rt_bool_t calibrating; /* 触摸校准标志 */ + rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */ - rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */ + rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */ rt_uint16_t min_y, max_y; /* 校准后 Y 方向最小 最大值 */ - struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */ - struct rt_event event; /* 事件同步，用于“笔中断” */ + struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */ + struct rt_event event; /* 事件同步，用于“笔中断” */ }; static struct rtgui_touch_device *touch = RT_NULL; @@ -255,14 +255,14 @@ static void rtgui_touch_calculate(void) rt_uint32_t total_x = 0; rt_uint32_t total_y = 0; for(k=0; k<2; k++) - { + { // sorting the ADC value for(i=0; i tmpxy[k][j]) + if (tmpxy[k][min] > tmpxy[k][j]) min=j; } temp = tmpxy[k][i]; @@ -329,11 +329,11 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */ { if(gpio_get(TOUCH_INT_PIN)==0) { - /* 触摸屏按下后操作 */ + /* 触摸屏按下后操作 */ if (gpio_level_low == gpio_get(led_gpio)) - gpio_set(led_gpio, gpio_level_high); + gpio_set(led_gpio, gpio_level_high); else - gpio_set(led_gpio, gpio_level_low); + gpio_set(led_gpio, gpio_level_low); touch_int_cmd(RT_FALSE); rt_event_send(&touch->event, 1); } @@ -341,19 +341,19 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */ /*管脚初始化，配置中断打开SPI1 CS0 设备*/ rt_inline void touch_init(void) -{ +{ unsigned int touch_int_gpio = TOUCH_INT_PIN; // 触摸屏中断 - int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio); - - // 初始化按键中断 - gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING); - rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch"); - rt_hw_interrupt_umask(touch_irq); - gpio_init(touch_int_gpio, gpio_mode_input); - - // 初始化led - gpio_init(led_gpio, gpio_mode_output); - gpio_set(led_gpio, gpio_level_high); + int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio); + + // 初始化按键中断 + gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING); + rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch"); + rt_hw_interrupt_umask(touch_irq); + gpio_init(touch_int_gpio, gpio_mode_input); + + // 初始化led + gpio_init(led_gpio, gpio_mode_output); + gpio_set(led_gpio, gpio_level_high); } @@ -363,7 +363,7 @@ static rt_err_t rtgui_touch_init (rt_device_t dev) rt_uint8_t send; rt_uint8_t recv_buffer[2]; struct rtgui_touch_device * touch_device = (struct rtgui_touch_device *)dev; - + touch_init(); rt_kprintf("touch_init ...\n"); send = START | DIFFERENTIAL | POWER_MODE0; @@ -440,18 +440,18 @@ static void touch_thread_entry(void *parameter) emouse.x = touch->x; emouse.y = touch->y; - if(touch_down != RT_TRUE) - { + if(touch_down != RT_TRUE) + { touch_int_cmd(RT_TRUE); break; - } + } if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL)) { /* 触摸校准处理 */ /* callback function */ touch->calibration_func(emouse.x, emouse.y); - + } else { @@ -482,7 +482,7 @@ static void touch_thread_entry(void *parameter) /* calculation */ rtgui_touch_calculate(); - + /* send mouse event */ emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON; emouse.parent.sender = RT_NULL; @@ -532,7 +532,7 @@ static void touch_thread_entry(void *parameter) rt_err_t rtgui_touch_hw_init(const char * spi_device_name) { - rt_uint32_t arg[2]; + rt_uint32_t arg[2]; struct rt_device * spi_device; struct rt_thread * touch_thread; rt_err_t err; @@ -550,12 +550,12 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) rt_kprintf("Open spi1 failed %08X, exit thread....\n", err); return; } - + /* config spi */ { struct rt_spi_configuration cfg; cfg.data_width = 8; - cfg.mode = RT_SPI_MODE_0; + cfg.mode = RT_SPI_MODE_0; cfg.max_hz = 200 * 1000; /* 200K */ rt_spi_configure((struct rt_spi_device *)spi_device, &cfg); } @@ -573,7 +573,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) touch->min_x = MIN_X_DEFAULT; touch->max_x = MAX_X_DEFAULT; - touch->min_y = MIN_Y_DEFAULT; + touch->min_y = MIN_Y_DEFAULT; touch->max_y = MAX_Y_DEFAULT; /* init device structure */ @@ -584,7 +584,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name) /* register touch device to RT-Thread */ rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR); - + touch_thread = rt_thread_create("touch_thread", touch_thread_entry, RT_NULL, diff --git a/bsp/loongson/ls1cdev/drivers/touch.h b/bsp/loongson/ls1cdev/drivers/touch.h index 5dac833510..71915151c4 100644 --- a/bsp/loongson/ls1cdev/drivers/touch.h +++ b/bsp/loongson/ls1cdev/drivers/touch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,20 +10,20 @@ #ifndef __TOUCH_H__ #define __TOUCH_H__ -#define RT_TOUCH_NORMAL 0 -#define RT_TOUCH_CALIBRATION_DATA 1 -#define RT_TOUCH_CALIBRATION 2 +#define RT_TOUCH_NORMAL 0 +#define RT_TOUCH_CALIBRATION_DATA 1 +#define RT_TOUCH_CALIBRATION 2 //#define SAVE_CALIBRATION - + rt_uint16_t touch_read_x(void); rt_uint16_t touch_read_y(void); void touch_config(void); - + rt_err_t rtgui_touch_hw_init(const char * spi_device_name); - + #endif diff --git a/bsp/loongson/ls2kdev/drivers/drv_rtc.c b/bsp/loongson/ls2kdev/drivers/drv_rtc.c index 3cea0288be..82cb25ddd5 100644 --- a/bsp/loongson/ls2kdev/drivers/drv_rtc.c +++ b/bsp/loongson/ls2kdev/drivers/drv_rtc.c @@ -128,7 +128,6 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args) hw_rtc = dev->user_data; t = (time_t *)args; - time = *gmtime(t); rtctm.sys_toyread0 = hw_rtc->sys_toyread0; rtctm.sys_toyread1 = hw_rtc->sys_toyread1; @@ -141,6 +140,7 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args) *t = timegm(&tmptime); break; case RT_DEVICE_CTRL_RTC_SET_TIME: + gmtime_r(t, &time); tmptime.tm_hour = time.tm_hour; tmptime.tm_min = time.tm_min; tmptime.tm_sec = time.tm_sec; diff --git a/bsp/loongson/ls2kdev/drivers/drv_uart.c b/bsp/loongson/ls2kdev/drivers/drv_uart.c index 5b5c39c595..78286bd3ac 100644 --- a/bsp/loongson/ls2kdev/drivers/drv_uart.c +++ b/bsp/loongson/ls2kdev/drivers/drv_uart.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,15 +18,15 @@ #include "drv_uart.h" #define TRUE 1 #define FALSE 0 -const struct serial_configure config_uart0 = { - BAUD_RATE_115200, /* 921600 bits/s */ - DATA_BITS_8, /* 8 databits */ - STOP_BITS_1, /* 1 stopbit */ - PARITY_NONE, /* No parity */ - BIT_ORDER_LSB, /* LSB first sent */ - NRZ_NORMAL, /* Normal mode */ - RT_SERIAL_RB_BUFSZ, /* Buffer size */ - 0 +const struct serial_configure config_uart0 = { + BAUD_RATE_115200, /* 921600 bits/s */ + DATA_BITS_8, /* 8 databits */ + STOP_BITS_1, /* 1 stopbit */ + PARITY_NONE, /* No parity */ + BIT_ORDER_LSB, /* LSB first sent */ + NRZ_NORMAL, /* Normal mode */ + RT_SERIAL_RB_BUFSZ, /* Buffer size */ + 0 }; struct rt_uart_ls2k { diff --git a/bsp/loongson/ls2kdev/drivers/ls2k1000.h b/bsp/loongson/ls2kdev/drivers/ls2k1000.h index 668d484d9c..2050d280a6 100644 --- a/bsp/loongson/ls2kdev/drivers/ls2k1000.h +++ b/bsp/loongson/ls2kdev/drivers/ls2k1000.h @@ -38,7 +38,7 @@ #define PM1_STS HWREG32(PM1_BASE) #define PM1_EN HWREG32(PM1_BASE + 0x04) #define PM1_CNT HWREG32(PM1_BASE + 0x08) - + /* * Watch Dog Configuration Registers */ diff --git a/bsp/loongson/ls2kdev/drivers/net/mii.h b/bsp/loongson/ls2kdev/drivers/net/mii.h index bc6d6c7a0c..97f156ee59 100644 --- a/bsp/loongson/ls2kdev/drivers/net/mii.h +++ b/bsp/loongson/ls2kdev/drivers/net/mii.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -172,15 +172,15 @@ /* Which connector port. */ #define PORT_TP 0x00 #define PORT_AUI 0x01 -#define PORT_MII 0x02 +#define PORT_MII 0x02 #define PORT_FIBRE 0x03 #define PORT_BNC 0x04 /* Which transceiver to use. */ #define XCVR_INTERNAL 0x00 #define XCVR_EXTERNAL 0x01 -#define XCVR_DUMMY1 0x02 -#define XCVR_DUMMY2 0x03 +#define XCVR_DUMMY1 0x02 +#define XCVR_DUMMY2 0x03 #define XCVR_DUMMY3 0x04 #define AUTONEG_DISABLE 0x00 diff --git a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Dev.h b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Dev.h index f47046d5ba..60acb2e628 100644 --- a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Dev.h +++ b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Dev.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,8 +9,8 @@ * 2020-08-10 lizhirui porting to ls2k */ -#define UNUSED 1 - +#define UNUSED 1 + #ifndef SYNOP_GMAC_DEV_H #define SYNOP_GMAC_DEV_H 1 @@ -41,7 +41,7 @@ #ifdef GMAC_PHY_BASE #define DEFAULT_PHY_BASE GMAC_PHY_BASE #else -#define DEFAULT_PHY_BASE PHY16 //We use First Phy +#define DEFAULT_PHY_BASE PHY16 //We use First Phy #endif #define MACBASE 0x0000 // The Mac Base address offset is 0x0000 #define DMABASE 0x1000 // Dma base address starts with an offset 0x1000 @@ -65,8 +65,8 @@ enum GMACPhyBase #define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type #define ETHERNET_CRC 4 //Ethernet CRC #define ETHERNET_EXTRA 2 //Only God knows about this????? -#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb -#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA +#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb +#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA #define VLAN_TAG 4 //optional 802.1q VLAN Tag #define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size #define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size @@ -86,18 +86,18 @@ The descriptor is of 4 words, but our structrue contains 6 words where last two words are to hold the virtual address of the network buffer pointers for driver's use From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed. -The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal +The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal descriptor structure. Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and TX/RX DESC7 provides the upper 32 bits of Timestamp value In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information */ -#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for +#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for // descriptor whose index%MODULO_INTERRUPT is zero #ifdef ENH_DESC_8W -typedef struct DmaDescStruct -{ +typedef struct DmaDescStruct +{ u32 status; /* Status */ u32 length; /* Buffer 1 and Buffer 2 length */ u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ @@ -111,8 +111,8 @@ typedef struct DmaDescStruct u64 data2; /* This holds virtual address of buffer2, not used by DMA */ } DmaDesc; #else -typedef struct DmaDescStruct -{ +typedef struct DmaDescStruct +{ u32 status; /* Status */ u32 length; /* Buffer 1 and Buffer 2 length */ u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */ @@ -122,7 +122,7 @@ typedef struct DmaDescStruct u64 data2; /* This holds virtual address of buffer2, not used by DMA */ //u32 dummy1; //sw: for addr align - //u32 dummy2; // + //u32 dummy2; // } DmaDesc; #endif @@ -141,24 +141,24 @@ enum BufferMode /* synopGMAC device data */ -typedef struct synopGMACDeviceStruct +typedef struct synopGMACDeviceStruct { u64 MacBase; /* base address of MAC registers */ u64 DmaBase; /* base address of DMA registers */ u64 PhyBase; /* PHY device address on MII interface */ - u32 Version; /* Gmac Revision version */ - + u32 Version; /* Gmac Revision version */ + dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/ - dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ + dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/ DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */ DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */ - u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ - u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ - + u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/ + u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/ + u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */ u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */ - + u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */ u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */ u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */ @@ -182,7 +182,7 @@ typedef struct synopGMACDeviceStruct // u32 skb_array[RECEIVE_DESC_SIZE]; } synopGMACdevice; -/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" +/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver" * Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter. * Since the Phy register map is standard, this map hardly changes to a different Ppy */ @@ -206,7 +206,7 @@ enum MiiRegisters PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/ PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/ PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/ - PHY_LED_CONTROL = 0x0018, /*LED Control*/ + PHY_LED_CONTROL = 0x0018, /*LED Control*/ PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/ PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/ PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/ @@ -217,15 +217,15 @@ enum MiiRegisters */ enum Mii_GEN_CTRL { /* Description bits R/W default value */ - Mii_reset = 0x8000, + Mii_reset = 0x8000, Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */ Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */ Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */ Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */ - + Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */ - + Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */ Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */ }; @@ -235,10 +235,10 @@ enum Mii_Phy_Status Mii_phy_status_speed_10 = 0x0000, Mii_phy_status_speed_100 = 0x4000, Mii_phy_status_speed_1000 = 0x8000, - + Mii_phy_status_full_duplex = 0x2000, Mii_phy_status_half_duplex = 0x0000, - + Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy // Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY }; @@ -279,7 +279,7 @@ enum Mii_Loop_Back * For Pci based system address is BARx + GmacRegisterBase * For any other system translation is done accordingly **********************************************************/ -enum GmacRegisters +enum GmacRegisters { GmacConfig = 0x0000, /* Mac config Register */ GmacFrameFilter = 0x0004, /* Mac frame filtering controls */ @@ -289,14 +289,14 @@ enum GmacRegisters GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */ GmacFlowControl = 0x0018, /* Flow control Register */ GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */ - - GmacVersion = 0x0020, /* GMAC Core Version Register */ - GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ - GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ - - GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ - GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ - + + GmacVersion = 0x0020, /* GMAC Core Version Register */ + GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */ + GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */ + + GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */ + GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */ + GmacAddr0High = 0x0040, /* Mac address0 high Register */ GmacAddr0Low = 0x0044, /* Mac address0 low Register */ GmacAddr1High = 0x0048, /* Mac address1 high Register */ @@ -338,35 +338,35 @@ enum GmacRegisters GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */ - + GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */ GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ //GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */ - + GmacTSStatus = 0x0728, /* Time Stamp Status Register */ }; /********************************************************** * GMAC Network interface registers * This explains the Register's Layout - - * FES is Read only by default and is enabled only when Tx + + * FES is Read only by default and is enabled only when Tx * Config Parameter is enabled for RGMII/SGMII interface * during CoreKit Config. - + * DM is Read only with value 1'b1 in Full duplex only Config **********************************************************/ /* GmacConfig = 0x0000, Mac config Register Layout */ -enum GmacConfigReg -{ +enum GmacConfigReg +{ /* Bit description Bits R/W Reset value */ GmacWatchdog = 0x00800000, GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */ @@ -379,7 +379,7 @@ enum GmacConfigReg GmacFrameBurst = 0x00200000, GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */ GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */ - + GmacJumboFrame = 0x00100000, GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */ GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */ @@ -392,19 +392,19 @@ enum GmacConfigReg GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */ GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */ GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */ - - GmacDisableCrs = 0x00010000, + + GmacDisableCrs = 0x00010000, GmacMiiGmii = 0x00008000, GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */ GmacSelectGmii = 0x00000000, /* GMII mode 0 */ - GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ - GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ + GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */ + GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */ - GmacRxOwn = 0x00002000, + GmacRxOwn = 0x00002000, GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */ GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */ - + GmacLoopback = 0x00001000, GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */ GmacLoopbackOff = 0x00000000, /* Normal mode 0 */ @@ -419,13 +419,13 @@ enum GmacConfigReg GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */ GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */ - GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ - GmacLinkDown = 0x00000100, /* Link Down 0 */ - + GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */ + GmacLinkDown = 0x00000100, /* Link Down 0 */ + GmacPadCrcStrip = 0x00000080, GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */ GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */ - + GmacBackoffLimit = 0x00000060, GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */ GmacBackoffLimit2 = 0x00000040, /* */ @@ -435,7 +435,7 @@ enum GmacConfigReg GmacDeferralCheck = 0x00000010, GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */ GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */ - + GmacTx = 0x00000008, GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */ GmacTxDisable = 0x00000000, /* Transmitter disable 0 */ @@ -446,7 +446,7 @@ enum GmacConfigReg }; /* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/ -enum GmacFrameFilterReg +enum GmacFrameFilterReg { GmacFilter = 0x80000000, GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */ @@ -494,14 +494,14 @@ enum GmacFrameFilterReg }; /*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */ -enum GmacGmiiAddrReg +enum GmacGmiiAddrReg { GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */ GmiiDevShift = 11, GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */ GmiiRegShift = 6, - + GmiiCsrClkMask = 0x0000001C, /* CSR Clock bit Mask 4:2 */ GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */ GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */ @@ -517,17 +517,17 @@ enum GmacGmiiAddrReg }; /* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */ -enum GmacGmiiDataReg +enum GmacGmiiDataReg { GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */ }; /*GmacFlowControl = 0x0018, Flow control Register Layout */ -enum GmacFlowControlReg -{ +enum GmacFlowControlReg +{ GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */ GmacPauseTimeShift = 16, - + GmacPauseLowThresh = 0x00000030, GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */ GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */ @@ -550,11 +550,11 @@ enum GmacFlowControlReg GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */ }; -/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ +/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */ enum GmacInterruptStatusBitDefinition { GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/ - GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ + GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */ GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */ GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */ GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */ @@ -564,7 +564,7 @@ enum GmacInterruptStatusBitDefinition GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */ }; -/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ +/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */ enum GmacInterruptMaskBitDefinition { GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */ @@ -579,7 +579,7 @@ enum GmacInterruptMaskBitDefinition * For Pci based system address is BARx + GmaDmaBase * For any other system translation is done accordingly **********************************************************/ -enum DmaRegisters +enum DmaRegisters { DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */ DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */ @@ -590,8 +590,8 @@ enum DmaRegisters DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */ DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */ DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */ - DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ - DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ + DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */ + DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */ DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */ DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */ }; @@ -601,19 +601,19 @@ enum DmaRegisters **********************************************************/ /*DmaBusMode = 0x0000, CSR0 - Bus Mode */ -enum DmaBusModeReg +enum DmaBusModeReg { /* Bit description Bits R/W Reset value */ DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */ DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */ - DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ - DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ - DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ - DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ - - DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ - - DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ + DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */ + DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */ + DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */ + DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */ + + DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */ + + DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */ DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */ DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */ DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */ @@ -634,19 +634,19 @@ enum DmaBusModeReg DmaDescriptorSkip1 = 0x00000004, /* */ DmaDescriptorSkip0 = 0x00000000, /* 0x00 */ - DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ - DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ - + DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */ + DmaArbitPr = 0x00000002, /* Rx has priority over Tx */ + DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */ DmaResetOff = 0x00000000, /* 0 */ }; /*DmaStatus = 0x0014, CSR5 - Dma status Register */ -enum DmaStatusReg -{ - /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ - GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ - GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ +enum DmaStatusReg +{ + /*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/ + GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */ + GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */ GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */ DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */ @@ -688,52 +688,52 @@ enum DmaStatusReg }; /*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */ -enum DmaControlReg -{ +enum DmaControlReg +{ DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */ - + DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */ - DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ - - DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ - DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ - DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ - DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ - DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ - DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ - DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ - DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ - DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ - + DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */ + + DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */ + DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */ + DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */ + DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */ + DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */ + DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */ + DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */ + DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */ + DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */ + DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */ - DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ - DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ - DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ - - DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ - DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ - DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ - DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ - - DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ - DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ - DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ - DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ - DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */ + DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */ + DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */ + + DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */ + DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */ + DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */ + DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */ + + DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */ + DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */ + DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */ + DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */ + DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */ + + DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ + DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */ - DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */ - DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */ DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */ DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */ @@ -743,7 +743,7 @@ enum DmaControlReg /*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */ enum DmaInterruptReg -{ +{ DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */ DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */ @@ -771,12 +771,12 @@ enum DmaInterruptReg #ifdef ENH_DESC /* **********Enhanced Descritpor structure to support 8K buffer per buffer **************************** - -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address -DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below -Similarly +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a +32 bit Data bus is as shown below + +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below @@ -807,7 +807,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, @@ -827,10 +827,10 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ -// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ +// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + + DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */ - DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */ DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */ DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */ @@ -845,12 +845,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */ TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */ - + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - - DescRxTSavail = 0x00000080, /* Time stamp available 7 */ + + DescRxTSavail = 0x00000080, /* Time stamp available 7 */ DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ @@ -862,10 +862,10 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ @@ -875,7 +875,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | -------------------------------------------------------------------- */ -// DmaDescriptorLength length word of DMA descriptor +// DmaDescriptorLength length word of DMA descriptor RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */ RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */ @@ -904,12 +904,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */ DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */ DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */ - + DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5 is bypassed */ DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */ DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3 - error or IP datagram version is not consistent + error or IP datagram version is not consistent with Ethernet type value */ DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0 in IPdatagram processed by COE (Rx) */ @@ -924,11 +924,11 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ /* ********** Default Descritpor structure **************************** -DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address +DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a -32 bit Data bus is as shown below +32 bit Data bus is as shown below -Similarly +Similarly DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a 32 bit Data bus is as shown below @@ -947,7 +947,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */ DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */ - + DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */ DescFrameLengthShift = 16, @@ -967,16 +967,16 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */ DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */ DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */ - DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ + DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */ //Rx Descriptor Checksum Offload engine (type 2) encoding -//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ +//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */ //DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ - + DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */ DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */ DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */ - + DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */ DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */ DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */ @@ -986,21 +986,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */ DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */ DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */ - + DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */ DescTxCollShift = 3, - + DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */ DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */ DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */ - + /* This explains the RDES1/TDES1 bits layout -------------------------------------------------------------------- RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 | -------------------------------------------------------------------- - */ + */ //DmaDescriptorLength length word of DMA descriptor DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */ DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */ @@ -1010,12 +1010,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */ RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */ RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - + DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */ TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */ TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */ - + DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */ DescSize2Shift = 11, DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */ @@ -1045,7 +1045,7 @@ enum RxDescCOEEncode /********************************************************** * DMA engine interrupt handling functions **********************************************************/ - + enum synopGMACDmaIntEnum /* Intrerrupt types */ { synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */ @@ -1068,7 +1068,7 @@ enum InitialRegisters | GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff | GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, - + /* Full-duplex mode with perfect filter on */ GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff @@ -1076,13 +1076,13 @@ enum InitialRegisters | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Full-duplex mode */ - // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast - // Hash filter. + // CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast + // Hash filter. /* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */ GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable | GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff | GmacPromiscuousModeOff | GmacUcastHashFilterOff, - + /* Full-duplex mode */ GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable, @@ -1091,17 +1091,17 @@ enum InitialRegisters /* Half-duplex mode with perfect filter on */ - // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, + // CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip, /*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/ GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode with perfect filter on */ GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable | GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff - | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable + | GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable | GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable, /* Half-duplex mode */ @@ -1121,13 +1121,13 @@ enum InitialRegisters DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff, // DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff, - + /* 1000 Mb/s mode */ DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame , /* 100 Mb/s mode */ DmaControlInit100 = DmaStoreAndForward, - + /* 10 Mb/s mode */ DmaControlInit10 = DmaStoreAndForward, @@ -1167,14 +1167,14 @@ enum MMC_TX GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */ GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */ GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */ - + GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */ GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - + GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */ GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */ GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */ @@ -1188,7 +1188,7 @@ enum MMC_TX GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */ GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */ GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/ - + GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */ GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */ }; @@ -1199,29 +1199,29 @@ enum MMC_RX GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */ GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */ GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */ - + GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */ GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */ GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */ GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */ GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */ GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */ - + GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */ GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */ GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */ GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */ GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */ GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */ - + GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */ GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */ GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */ - + GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */ GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */ GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */ - + GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */ }; @@ -1229,42 +1229,42 @@ enum MMC_IP_RELATED { GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */ GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */ - + GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */ GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */ GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */ GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */ - + GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */ GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */ GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */ - + GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */ GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */ - + GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */ GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */ GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */ GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */ - + GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */ GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */ GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */ GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */ - + GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */ GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */ GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */ - + GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */ GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */ - + GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */ GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */ - + GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */ GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */ }; @@ -1338,7 +1338,7 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS /********************************************************** - * Power Management (PMT) Block + * Power Management (PMT) Block **********************************************************/ /** @@ -1348,10 +1348,10 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS * These enable are in PMT control and Status register and are programmed by apllication. * * When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes - * out of power down mode only when either Magic packe tor a Remote wake-up frame is received + * out of power down mode only when either Magic packe tor a Remote wake-up frame is received * and the corresponding detection is enabled. * - * Driver need not be modified to support this feature. Only Api to put the device in to power + * Driver need not be modified to support this feature. Only Api to put the device in to power * down mode is sufficient */ @@ -1369,7 +1369,7 @@ enum GmacPmtCtrlStatusBitDefinition }; /********************************************************** - * IEEE 1588-2008 Precision Time Protocol (PTP) Support + * IEEE 1588-2008 Precision Time Protocol (PTP) Support **********************************************************/ enum PTPMessageType { @@ -1385,10 +1385,10 @@ enum PTPMessageType Management = 0xD, }; -typedef struct TimeStampStruct -{ +typedef struct TimeStampStruct +{ u32 TSversion; /* PTP Version 1 or PTP version2 */ - u32 TSmessagetype; /* Message type associated with this time stamp */ + u32 TSmessagetype; /* Message type associated with this time stamp */ u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */ u32 TSupper32; /* Most significant 32 bit time stamp value */ @@ -1411,7 +1411,7 @@ typedef struct TimeStampStruct enum GmacTSControlReg { GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */ - + GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */ /* TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken @@ -1421,7 +1421,7 @@ enum GmacTSControlReg 10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP 10 NA 1 SYNC, FOLLOW_UP 11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP - 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP + 11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP */ GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/ GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/ @@ -1442,7 +1442,7 @@ enum GmacTSControlReg GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */ GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */ GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */ - + GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */ GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */ @@ -1474,7 +1474,7 @@ enum GmacTSLowReg }; /* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */ -enum GmacTSHighWordReg +enum GmacTSHighWordReg { GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */ }; @@ -1483,7 +1483,7 @@ enum GmacTSStatusReg { GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */ GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */ -}; +}; /********************************************************** * Time stamp related functions @@ -1510,7 +1510,7 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); // void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" -void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); +void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev); void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp" @@ -1523,7 +1523,7 @@ void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask -void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, +void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided @@ -1541,7 +1541,7 @@ s32 synopGMAC_read_phy_reg(u64 RegBase,u32 PhyBase, u32 RegOffset, u16 * data); s32 synopGMAC_write_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 data); s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback); s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ; -s32 synopGMAC_reset (synopGMACdevice * gmacdev ); +s32 synopGMAC_reset (synopGMACdevice * gmacdev ); s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value ); s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value ); void synopGMAC_wd_enable(synopGMACdevice * gmacdev); @@ -1639,7 +1639,7 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc); bool synopGMAC_is_tx_desc_chained(DmaDesc * desc); void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, +s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2 ); @@ -1647,7 +1647,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1 s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2,u32 offload_needed,u32 * index,DmaDesc *Dpr); s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2); #ifdef ENH_DESC_8W -s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, +s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2, u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low); #else s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2); @@ -1668,8 +1668,8 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev); void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev); /******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/ -bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); -bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); +bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status); +bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status); bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status); /*******************PMT APIs***************************************/ diff --git a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Host.h b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Host.h index b81b0c29f0..7f1de48567 100644 --- a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Host.h +++ b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_Host.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,7 +42,7 @@ struct net_device_stats unsigned long tx_fifo_errors; unsigned long tx_heartbeat_errors; unsigned long tx_window_errors; - + /* for cslip etc */ unsigned long rx_compressed; unsigned long tx_compressed; diff --git a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_debug.h b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_debug.h index c5387d00d8..666cc975e8 100644 --- a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_debug.h +++ b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ //#define GMAC_DEBUG #include -#ifdef GMAC_DEBUG +#ifdef GMAC_DEBUG #define DEBUG_MES rt_kprintf #else #define DEBUG_MES(...) diff --git a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_plat.h b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_plat.h index 3b6eaca197..5565f2bf07 100644 --- a/bsp/loongson/ls2kdev/drivers/net/synopGMAC_plat.h +++ b/bsp/loongson/ls2kdev/drivers/net/synopGMAC_plat.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2022, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -57,17 +57,17 @@ typedef int bool; #define VA_TO_PA(x) CACHED_TO_PHYS(x) /* sw -#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) +#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #ifdef DEBUG #undef TR # define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args) #else -# define TR(fmt, args...) // not debugging: nothing +# define TR(fmt, args...) // not debugging: nothing #endif */ /* -#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) +#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args) */ /* @@ -75,20 +75,20 @@ typedef int bool; #undef TR # define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #else -//# define TR(fmt, args...) // not debugging: nothing -#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) +//# define TR(fmt, args...) // not debugging: nothing +#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args) #endif */ //sw: nothing to display -#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) -#define TR(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR0(fmt, args...) //rt_kprintf(fmt, ##args) +#define TR(fmt, args...) //rt_kprintf(fmt, ##args) //typedef int bool; enum synopGMAC_boolean - { + { false = 0, - true = 1 + true = 1 }; #define DEFAULT_DELAY_VARIABLE 10 @@ -117,7 +117,7 @@ struct Network_interface_data /** * These are the wrapper function prototypes for OS/platform related routines - */ + */ void * plat_alloc_memory(u32 ); void plat_free_memory(void *); @@ -128,10 +128,10 @@ void plat_delay(u32); /** * The Low level function to read register contents from Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * \return Returns the register contents + * \return Returns the register contents */ static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset) { @@ -151,11 +151,11 @@ static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset) /** * The Low level function to write to a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Data to be written - * \return void + * @param[in] Data to be written + * \return void */ static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData ) { @@ -173,18 +173,18 @@ static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData ) /** * The Low level function to set bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 - * \return void + * @param[in] Bit mask to set bits to logical 1 + * \return void */ static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos) { //u64 addr = (u64)RegBase + (u64)RegOffset; u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data |= BitPos; + data |= BitPos; synopGMACWriteReg(RegBase, RegOffset, data); // writel(data,(void *)addr); #if SYNOP_REG_DEBUG @@ -196,17 +196,17 @@ static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to clear bits of a register in Hardware. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to clear bits to logical 0 - * \return void + * @param[in] Bit mask to clear bits to logical 0 + * \return void */ static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= (~BitPos); + data &= (~BitPos); synopGMACWriteReg(RegBase, RegOffset, data); #if SYNOP_REG_DEBUG TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data ); @@ -216,24 +216,24 @@ static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos) /** * The Low level function to Check the setting of the bits. - * - * @param[in] pointer to the base of register map + * + * @param[in] pointer to the base of register map * @param[in] Offset from the base - * @param[in] Bit mask to set bits to logical 1 + * @param[in] Bit mask to set bits to logical 1 * \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument. - * + * */ static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos) { u32 data; data = synopGMACReadReg(RegBase, RegOffset); - data &= BitPos; + data &= BitPos; - if(data) + if(data) { return true; } - else + else { return false; } diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c index fc49389566..e04cd9f11c 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_rtc.c @@ -43,18 +43,18 @@ static time_t get_timestamp(void) static int set_timestamp(time_t timestamp) { - struct tm *p_tm; + struct tm now; rtc_datetime_t rtcDate; - p_tm = gmtime(×tamp); + gmtime_r(×tamp, &now); - rtcDate.second = p_tm->tm_sec ; - rtcDate.minute = p_tm->tm_min ; - rtcDate.hour = p_tm->tm_hour; + rtcDate.second = now.tm_sec ; + rtcDate.minute = now.tm_min ; + rtcDate.hour = now.tm_hour; - rtcDate.day = p_tm->tm_mday; - rtcDate.month = p_tm->tm_mon + 1; - rtcDate.year = p_tm->tm_year + 1900; + rtcDate.day = now.tm_mday; + rtcDate.month = now.tm_mon + 1; + rtcDate.year = now.tm_year + 1900; /* RTC time counter has to be stopped before setting the date & time in the TSR register */ RTC_StopTimer(RTC); diff --git a/bsp/nuvoton/libraries/m031/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m031/rtt_port/drv_rtc.c index 96471765e8..e280b1c3b8 100644 --- a/bsp/nuvoton/libraries/m031/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/m031/rtt_port/drv_rtc.c @@ -200,7 +200,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t) /* Register rt-thread device.control() entry. */ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm_out, *tm_in; + struct tm tm_out, tm_in; time_t *time; S_RTC_TIME_DATA_T hw_time; @@ -236,13 +236,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) if (nu_rtc_is_date_valid(*time) != RT_EOK) return -(RT_ERROR); - tm_in = gmtime(time); - hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); - hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon); - hw_time.u32Day = tm_in->tm_mday; - hw_time.u32Hour = tm_in->tm_hour; - hw_time.u32Minute = tm_in->tm_min; - hw_time.u32Second = tm_in->tm_sec; + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; hw_time.u32TimeScale = RTC_CLOCK_24; hw_time.u32AmPm = 0; diff --git a/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c index 0a915ef5f1..e2badc01b4 100644 --- a/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c @@ -203,7 +203,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t) /* Register rt-thread device.control() entry. */ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm_out, *tm_in; + struct tm tm_out, tm_in; time_t *time; S_RTC_TIME_DATA_T hw_time; @@ -239,13 +239,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) if (nu_rtc_is_date_valid(*time) != RT_EOK) return -(RT_ERROR); - tm_in = gmtime(time); - hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); - hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon); - hw_time.u32Day = tm_in->tm_mday; - hw_time.u32Hour = tm_in->tm_hour; - hw_time.u32Minute = tm_in->tm_min; - hw_time.u32Second = tm_in->tm_sec; + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; hw_time.u32TimeScale = RTC_CLOCK_24; hw_time.u32AmPm = 0; diff --git a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c index 4c6f029241..49a0bc2a47 100644 --- a/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c @@ -202,7 +202,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t) /* Register rt-thread device.control() entry. */ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm_out, *tm_in; + struct tm tm_out, tm_in; time_t *time; S_RTC_TIME_DATA_T hw_time; @@ -238,13 +238,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) if (nu_rtc_is_date_valid(*time) != RT_EOK) return -(RT_ERROR); - tm_in = gmtime(time); - hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); - hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon); - hw_time.u32Day = tm_in->tm_mday; - hw_time.u32Hour = tm_in->tm_hour; - hw_time.u32Minute = tm_in->tm_min; - hw_time.u32Second = tm_in->tm_sec; + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; hw_time.u32TimeScale = RTC_CLOCK_24; hw_time.u32AmPm = 0; diff --git a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_rtc.c index 917753f275..dde3b75ebf 100644 --- a/bsp/nuvoton/libraries/n9h30/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/n9h30/rtt_port/drv_rtc.c @@ -221,7 +221,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t) /* Register rt-thread device.control() entry. */ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm_out, *tm_in; + struct tm tm_out, tm_in; time_t *time; S_RTC_TIME_DATA_T hw_time = {0}; @@ -261,14 +261,14 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) if (nu_rtc_is_date_valid(*time) != RT_EOK) return -(RT_ERROR); - tm_in = gmtime(time); - hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); - hw_time.u32cMonth = CONV_FROM_TM_MON(tm_in->tm_mon); - hw_time.u32cDay = tm_in->tm_mday; - hw_time.u32cHour = tm_in->tm_hour; - hw_time.u32cMinute = tm_in->tm_min; - hw_time.u32cSecond = tm_in->tm_sec; - hw_time.u32cDayOfWeek = tm_in->tm_wday; + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32cMonth = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32cDay = tm_in.tm_mday; + hw_time.u32cHour = tm_in.tm_hour; + hw_time.u32cMinute = tm_in.tm_min; + hw_time.u32cSecond = tm_in.tm_sec; + hw_time.u32cDayOfWeek = tm_in.tm_wday; hw_time.u8cClockDisplay = RTC_CLOCK_24; hw_time.u8cAmPm = 0; diff --git a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c index 74118e6c21..fc0a2dc7bb 100644 --- a/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c +++ b/bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c @@ -203,7 +203,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t) /* Register rt-thread device.control() entry. */ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm_out, *tm_in; + struct tm tm_out, tm_in; time_t *time; S_RTC_TIME_DATA_T hw_time; @@ -239,13 +239,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args) if (nu_rtc_is_date_valid(*time) != RT_EOK) return -(RT_ERROR); - tm_in = gmtime(time); - hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year); - hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon); - hw_time.u32Day = tm_in->tm_mday; - hw_time.u32Hour = tm_in->tm_hour; - hw_time.u32Minute = tm_in->tm_min; - hw_time.u32Second = tm_in->tm_sec; + gmtime_r(time, &tm_in); + hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year); + hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon); + hw_time.u32Day = tm_in.tm_mday; + hw_time.u32Hour = tm_in.tm_hour; + hw_time.u32Minute = tm_in.tm_min; + hw_time.u32Second = tm_in.tm_sec; hw_time.u32TimeScale = RTC_CLOCK_24; hw_time.u32AmPm = 0; diff --git a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c index 3d7b97e8ac..139f6f3abd 100644 --- a/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c @@ -193,16 +193,16 @@ static time_t raspi_get_timestamp(void) static int raspi_set_timestamp(time_t timestamp) { - struct tm *tblock; - tblock = gmtime(×tamp); + struct tm tblock; + gmtime_r(×tamp, &tblock); buf[0] = 0; - buf[1] = tblock->tm_sec; - buf[2] = tblock->tm_min; - buf[3] = tblock->tm_hour; - buf[4] = tblock->tm_wday; - buf[5] = tblock->tm_mday; - buf[6] = tblock->tm_mon; - buf[7] = tblock->tm_year; + buf[1] = tblock.tm_sec; + buf[2] = tblock.tm_min; + buf[3] = tblock.tm_hour; + buf[4] = tblock.tm_wday; + buf[5] = tblock.tm_mday; + buf[6] = tblock.tm_mon; + buf[7] = tblock.tm_year; i2c_write(buf, 8); diff --git a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c index 5d43c39073..55848c22bc 100644 --- a/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c +++ b/bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c @@ -40,16 +40,16 @@ static time_t raspi_get_timestamp(void) static int raspi_set_timestamp(time_t timestamp) { - struct tm *tblock; - tblock = gmtime(×tamp); + struct tm tblock; + gmtime_r(×tamp, &tblock); buf[0] = 0; - buf[1] = tblock->tm_sec; - buf[2] = tblock->tm_min; - buf[3] = tblock->tm_hour; - buf[4] = tblock->tm_wday; - buf[5] = tblock->tm_mday; - buf[6] = tblock->tm_mon; - buf[7] = tblock->tm_year; + buf[1] = tblock.tm_sec; + buf[2] = tblock.tm_min; + buf[3] = tblock.tm_hour; + buf[4] = tblock.tm_wday; + buf[5] = tblock.tm_mday; + buf[6] = tblock.tm_mon; + buf[7] = tblock.tm_year; bcm283x_i2c_write((PER_BASE + BCM283X_BSC0_BASE) ,buf, 8); return RT_EOK; } diff --git a/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c b/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c index 379213fd93..6eb1a9bdae 100644 --- a/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c +++ b/bsp/renesas/libraries/HAL_Drivers/drv_rtc.c @@ -69,24 +69,22 @@ static rt_err_t ra_get_secs(void *args) static rt_err_t set_rtc_time_stamp(time_t time_stamp) { - struct tm *p_tm; + struct tm now; rtc_time_t g_current_time = {0}; - p_tm = gmtime(&time_stamp); - if (p_tm->tm_year < 100) + gmtime_r(&time_stamp, &now); + if (now.tm_year < 100) { return -RT_ERROR; } - g_current_time.tm_sec = p_tm->tm_sec ; - g_current_time.tm_min = p_tm->tm_min ; - g_current_time.tm_hour = p_tm->tm_hour; - - g_current_time.tm_mday = p_tm->tm_mday; - g_current_time.tm_mon = p_tm->tm_mon; - g_current_time.tm_year = p_tm->tm_year; - - g_current_time.tm_wday = p_tm->tm_wday; - g_current_time.tm_yday = p_tm->tm_yday; + g_current_time.tm_sec = now.tm_sec ; + g_current_time.tm_min = now.tm_min ; + g_current_time.tm_hour = now.tm_hour; + g_current_time.tm_mday = now.tm_mday; + g_current_time.tm_mon = now.tm_mon; + g_current_time.tm_year = now.tm_year; + g_current_time.tm_wday = now.tm_wday; + g_current_time.tm_yday = now.tm_yday; if (R_RTC_CalendarTimeSet(&g_rtc_ctrl, &g_current_time) != FSP_SUCCESS) { diff --git a/bsp/swm320/drivers/drv_rtc.c b/bsp/swm320/drivers/drv_rtc.c index 74d41a2752..debe3645ee 100644 --- a/bsp/swm320/drivers/drv_rtc.c +++ b/bsp/swm320/drivers/drv_rtc.c @@ -63,17 +63,16 @@ static time_t swm_get_rtc_time_stamp(void) static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp) { RTC_DateTime set_datetime = {0}; - struct tm *p_tm; + struct tm now; - p_tm = gmtime(&time_stamp); - - set_datetime.Second = p_tm->tm_sec; - set_datetime.Minute = p_tm->tm_min; - set_datetime.Hour = p_tm->tm_hour; - set_datetime.Date = p_tm->tm_mday; - set_datetime.Month = p_tm->tm_mon; - set_datetime.Year = p_tm->tm_year; - // set_datetime.Day = p_tm->tm_wday; + gmtime_r(&time_stamp, &now); + set_datetime.Second = now.tm_sec; + set_datetime.Minute = now.tm_min; + set_datetime.Hour = now.tm_hour; + set_datetime.Date = now.tm_mday; + set_datetime.Month = now.tm_mon; + set_datetime.Year = now.tm_year; + // set_datetime.Day = now.tm_wday; RTC_Stop(RTC); while (RTC->CFGABLE == 0) diff --git a/bsp/w60x/drivers/drv_rtc.c b/bsp/w60x/drivers/drv_rtc.c index 38da5aec58..552f4fb46f 100644 --- a/bsp/w60x/drivers/drv_rtc.c +++ b/bsp/w60x/drivers/drv_rtc.c @@ -50,23 +50,23 @@ static int wm_set_timestamp(time_t timestamp) int ctrl1 = 0; int ctrl2 = 0; - struct tm *tblock; + struct tm tblock; - tblock = gmtime(×tamp); + gmtime_r(×tamp, &tblock); ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* disable */ ctrl2 &= ~(1 << 16); tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2); - ctrl1 |= tblock->tm_sec; - ctrl1 |= tblock->tm_min << 8; - ctrl1 |= tblock->tm_hour << 16; - ctrl1 |= tblock->tm_mday << 24; + ctrl1 |= tblock.tm_sec; + ctrl1 |= tblock.tm_min << 8; + ctrl1 |= tblock.tm_hour << 16; + ctrl1 |= tblock.tm_mday << 24; tls_reg_write32(HR_PMU_RTC_CTRL1, ctrl1); ctrl2 = 0; - ctrl2 |= tblock->tm_mon; - ctrl2 |= tblock->tm_year << 8; + ctrl2 |= tblock.tm_mon; + ctrl2 |= tblock.tm_year << 8; tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2); ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2);/* enable */ @@ -80,21 +80,21 @@ static int wm_alarm_set_timestamp(struct rt_rtc_wkalarm *wkalarm) { int ctrl1 = 0; int ctrl2 = 0; - struct tm *tblock; + struct tm tblock; time_t timestamp = 0; timestamp = wm_get_timestamp(); - tblock = gmtime(×tamp); + gmtime_r(×tamp, &tblock); tls_irq_enable(PMU_RTC_INT); ctrl1 |= wkalarm->tm_sec; ctrl1 |= wkalarm->tm_min << 8; ctrl1 |= wkalarm->tm_hour << 16; - ctrl1 |= tblock->tm_mday << 24; + ctrl1 |= tblock.tm_mday << 24; - ctrl2 |= tblock->tm_mon; - ctrl2 |= tblock->tm_year << 8; + ctrl2 |= tblock.tm_mon; + ctrl2 |= tblock.tm_year << 8; tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2 | BIT(16)); diff --git a/components/dfs/filesystems/elmfat/dfs_elm.c b/components/dfs/filesystems/elmfat/dfs_elm.c index eb57034061..adcb3e0ac5 100644 --- a/components/dfs/filesystems/elmfat/dfs_elm.c +++ b/components/dfs/filesystems/elmfat/dfs_elm.c @@ -944,22 +944,11 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff) DWORD get_fattime(void) { DWORD fat_time = 0; - time_t now; - struct tm *p_tm; struct tm tm_now; - /* get current time */ now = time(RT_NULL); - - /* lock scheduler. */ - rt_enter_critical(); - /* converts calendar time time into local time. */ - p_tm = gmtime(&now); - /* copy the statically located variable */ - rt_memcpy(&tm_now, p_tm, sizeof(struct tm)); - /* unlock scheduler. */ - rt_exit_critical(); + gmtime_r(&now, &tm_now); fat_time = (DWORD)(tm_now.tm_year - 80) << 25 | (DWORD)(tm_now.tm_mon + 1) << 21 | diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 5d374dfadf..b7bbba9a55 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -126,7 +126,7 @@ static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm, *tm_ptr; + struct tm tmp; time_t *time; RT_ASSERT(dev != RT_NULL); @@ -135,14 +135,14 @@ static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) { case RT_DEVICE_CTRL_RTC_GET_TIME: /* read device */ - rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = timegm(&tm); + rt_hw_rtc_get(&tmp); + *((rt_time_t *)args) = timegm(&tmp); break; case RT_DEVICE_CTRL_RTC_SET_TIME: /* write device */ - tm_ptr = gmtime(time); - rt_hw_rtc_set(tm_ptr); + gmtime_r(time, &tmp); + rt_hw_rtc_set(&tmp); break; }