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[rtc] use gmtime_r to replace gmtime (#6012) 

* [rtc] use gmtime_r to replace gmtime
This commit is contained in:
Man, Jianting (Meco) 2022-06-22 01:41:06 -04:00 committed by GitHub
parent 4f1f8566f4
commit 2c10d5ad01
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
56 changed files with 2873 additions and 2907 deletions
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20
bsp/acm32/acm32f0x0-nucleo/drivers/drv_rtc.c
View File

@ -49,21 +49,21 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
{
RTC_TimeTypeDef RTC_TimeStruct = {0};
RTC_DateTypeDef RTC_DateStruct = {0};
struct tm *p_tm;
struct tm now;
p_tm = gmtime(&time_stamp);
if (p_tm->tm_year < 100)
gmtime_r(&time_stamp, &now);
if (now.tm_year < 100)
{
return -RT_ERROR;
}
RTC_TimeStruct.u8_Seconds = dec2hex(p_tm->tm_sec);
RTC_TimeStruct.u8_Minutes = dec2hex(p_tm->tm_min);
RTC_TimeStruct.u8_Hours = dec2hex(p_tm->tm_hour);
RTC_DateStruct.u8_Date = dec2hex(p_tm->tm_mday);
RTC_DateStruct.u8_Month = dec2hex(p_tm->tm_mon + 1);
RTC_DateStruct.u8_Year = dec2hex(p_tm->tm_year - 100);
RTC_DateStruct.u8_WeekDay = dec2hex(p_tm->tm_wday) + 1;
RTC_TimeStruct.u8_Seconds = dec2hex(now.tm_sec);
RTC_TimeStruct.u8_Minutes = dec2hex(now.tm_min);
RTC_TimeStruct.u8_Hours = dec2hex(now.tm_hour);
RTC_DateStruct.u8_Date = dec2hex(now.tm_mday);
RTC_DateStruct.u8_Month = dec2hex(now.tm_mon + 1);
RTC_DateStruct.u8_Year = dec2hex(now.tm_year - 100);
RTC_DateStruct.u8_WeekDay = dec2hex(now.tm_wday) + 1;
HAL_RTC_SetTime(&RTC_TimeStruct);
HAL_RTC_SetDate(&RTC_DateStruct);

18
bsp/apollo2/board/rtc.c
View File

@ -38,7 +38,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
time_t *time;
struct tm time_temp;
struct tm* time_new;
struct tm time_new;
am_hal_rtc_time_t hal_time;
RT_ASSERT(dev != RT_NULL);
@ -71,16 +71,16 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
case RT_DEVICE_CTRL_RTC_SET_TIME:
time = (time_t *)args;
time_new = gmtime(time);
gmtime_r(time, &time_new);
hal_time.ui32Hour = time_new->tm_hour;
hal_time.ui32Minute = time_new->tm_min;
hal_time.ui32Second = time_new->tm_sec;
hal_time.ui32Hour = time_new.tm_hour;
hal_time.ui32Minute = time_new.tm_min;
hal_time.ui32Second = time_new.tm_sec;
hal_time.ui32Hundredths = 00;
hal_time.ui32Weekday = time_new->tm_wday;
hal_time.ui32DayOfMonth = time_new->tm_mday;
hal_time.ui32Month = time_new->tm_mon + 1;
hal_time.ui32Year = time_new->tm_year + 1900 - 2000;
hal_time.ui32Weekday = time_new.tm_wday;
hal_time.ui32DayOfMonth = time_new.tm_mday;
hal_time.ui32Month = time_new.tm_mon + 1;
hal_time.ui32Year = time_new.tm_year + 1900 - 2000;
hal_time.ui32Century = 0;
am_hal_rtc_time_set(&hal_time);

10
bsp/at32/libraries/rt_drivers/drv_rtc.c
View File

@ -49,22 +49,22 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
{
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F415)
struct tm *p_tm;
struct tm now;
p_tm = gmtime(&time_stamp);
if (p_tm->tm_year < 100)
gmtime_r(&time_stamp, &now);
if (now.tm_year < 100)
{
return -RT_ERROR;
}
/* set time */
if(ertc_time_set(p_tm->tm_hour, p_tm->tm_min, p_tm->tm_sec, ERTC_AM) != SUCCESS)
if(ertc_time_set(now.tm_hour, now.tm_min, now.tm_sec, ERTC_AM) != SUCCESS)
{
return -RT_ERROR;
}
/* set date */
if(ertc_date_set(p_tm->tm_year - 100, p_tm->tm_mon + 1, p_tm->tm_mday, p_tm->tm_wday + 1) != SUCCESS)
if(ertc_date_set(now.tm_year - 100, now.tm_mon + 1, now.tm_mday, now.tm_wday + 1) != SUCCESS)
{
return -RT_ERROR;
}

12
bsp/essemi/es32f0654/drivers/drv_rtc.c
View File

@ -55,9 +55,7 @@ static void __rtc_init(rtc_init_t *init)
static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
struct tm time_temp;
struct tm *pNow;
rtc_date_t date;
rtc_time_t time;
@ -76,15 +74,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
rt_enter_critical();
/* converts calendar time time into local time. */
pNow = gmtime((const time_t *)args);
/* copy the statically located variable */
memcpy(&time_temp, pNow, sizeof(struct tm));
/* unlock scheduler. */
rt_exit_critical();
gmtime_r((const time_t *)args, &time_temp);
time.hour = time_temp.tm_hour;
time.minute = time_temp.tm_min;
time.second = time_temp.tm_sec;

12
bsp/essemi/es32f369x/drivers/drv_rtc.c
View File

@ -54,9 +54,7 @@ static void __rtc_init(rtc_init_t *init)
static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t result = RT_EOK;
struct tm time_temp;
struct tm *pNow;
rtc_date_t date;
rtc_time_t time;
@ -75,15 +73,7 @@ static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
rt_enter_critical();
/* converts calendar time time into local time. */
pNow = gmtime((const time_t *)args);
/* copy the statically located variable */
memcpy(&time_temp, pNow, sizeof(struct tm));
/* unlock scheduler. */
rt_exit_critical();
gmtime_r((const time_t *)args, &time_temp);
time.hour = time_temp.tm_hour;
time.minute = time_temp.tm_min;
time.second = time_temp.tm_sec;

16
bsp/imxrt/libraries/drivers/drv_rtc.c
View File

@ -45,18 +45,18 @@ static time_t get_timestamp(void)
static int set_timestamp(time_t timestamp)
{
struct tm *p_tm;
struct tm now;
snvs_hp_rtc_datetime_t rtcDate = {0};
p_tm = gmtime(&timestamp);
gmtime_r(&timestamp, &now);
rtcDate.second = p_tm->tm_sec ;
rtcDate.minute = p_tm->tm_min ;
rtcDate.hour = p_tm->tm_hour;
rtcDate.second = now.tm_sec ;
rtcDate.minute = now.tm_min ;
rtcDate.hour = now.tm_hour;
rtcDate.day = p_tm->tm_mday;
rtcDate.month = p_tm->tm_mon + 1;
rtcDate.year = p_tm->tm_year + 1900;
rtcDate.day = now.tm_mday;
rtcDate.month = now.tm_mon + 1;
rtcDate.year = now.tm_year + 1900;
if (SNVS_HP_RTC_SetDatetime(SNVS, &rtcDate) != kStatus_Success)
{

28
bsp/loongson/ls1bdev/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -181,19 +181,19 @@ void rt_hw_uart_init(void)
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART5
uart = &uart5;
serial5.ops = &ls1b_uart_ops;
serial5.config = config;
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
/* register UART5 device */
rt_hw_serial_register(&serial5,
"uart5",
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
uart = &uart5;
serial5.ops = &ls1b_uart_ops;
serial5.config = config;
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
/* register UART5 device */
rt_hw_serial_register(&serial5,
"uart5",
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART5 */

34
bsp/loongson/ls1cdev/drivers/display_controller.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,7 +7,7 @@
* Date Author Notes
* 2011-08-09 lgnq first version for LS1B DC
* 2015-07-06 chinesebear modified for loongson 1c
* 2018-01-06 sundm75 modified for smartloong
* 2018-01-06 sundm75 modified for smartloong
*/
#include <rtthread.h>
@ -78,13 +78,13 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK)
pix_div = (pix_div>>24)&0xff;
rt_kprintf("old pll_clk=%d, pix_div=%d\n", pll_clk, pix_div);
divider_int = pll_clk/(1000000) *PCLK/1000;
divider_int = pll_clk/(1000000) *PCLK/1000;
if(divider_int%1000>=500)
divider_int = divider_int/1000+1;
else
divider_int = divider_int/1000;
rt_kprintf("divider_int = %d\n", divider_int);
/* check whether divisor is too small. */
if (divider_int < 1) {
rt_kprintf("Warning: clock source is too slow.Try smaller resolution\n");
@ -102,9 +102,9 @@ int caclulate_freq(rt_uint32_t XIN, rt_uint32_t PCLK)
regval &= ~0x80000030; //PIX_DIV_VALID PIX_SEL 置0
regval &= ~(0x3f<<24); //PIX_DIV 清零
regval |= divider_int << 24;
PLL_DIV_PARAM = regval;
PLL_DIV_PARAM = regval;
regval |= 0x80000030; //PIX_DIV_VALID PIX_SEL 置1
PLL_DIV_PARAM = regval;
PLL_DIV_PARAM = regval;
}
rt_kprintf("new PLL_FREQ=0x%x, PLL_DIV_PARAM=0x%x\n", PLL_FREQ, PLL_DIV_PARAM);
rt_thread_delay(10);
@ -115,11 +115,11 @@ static rt_err_t rt_dc_init(rt_device_t dev)
{
int i, out, mode=-1;
int val;
rt_kprintf("PWM initied\n");
/* Set the back light PWM. */
pwminit();
for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
{
if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
@ -140,7 +140,7 @@ static rt_err_t rt_dc_init(rt_device_t dev)
DC_FB_CONFIG = 0x0;
DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
DC_DITHER_CONFIG = 0x0; //颜色抖动配置寄存器
DC_DITHER_TABLE_LOW = 0x0; //颜色抖动查找表低位寄存器
DC_DITHER_TABLE_LOW = 0x0; //颜色抖动查找表低位寄存器
DC_DITHER_TABLE_HIGH = 0x0; //颜色抖动查找表高位寄存器
DC_PANEL_CONFIG = 0x80001311; //液晶面板配置寄存器
DC_PANEL_TIMING = 0x0;
@ -165,10 +165,10 @@ static rt_err_t rt_dc_init(rt_device_t dev)
#elif defined(CONFIG_VIDEO_12BPP)
DC_FB_CONFIG = 0x00100101;
DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
#else
#else
DC_FB_CONFIG = 0x00100104;
DC_FB_BUFFER_STRIDE = (FB_XSIZE*4+255)&(~255);
#endif
#endif
return RT_EOK;
}
@ -200,7 +200,7 @@ static rt_err_t rt_dc_control(rt_device_t dev, int cmd, void *args)
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_dc_info, sizeof(_dc_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
@ -213,7 +213,7 @@ static rt_err_t rt_dc_control(rt_device_t dev, int cmd, void *args)
void rt_hw_dc_init(void)
{
rt_device_t dc = rt_malloc(sizeof(struct rt_device));
if (dc == RT_NULL)
if (dc == RT_NULL)
{
rt_kprintf("dc == RT_NULL\n");
return; /* no memory yet */
@ -232,10 +232,10 @@ void rt_hw_dc_init(void)
dc->close = RT_NULL;
dc->control = rt_dc_control;
dc->user_data = (void*)&_dc_info;
/* register Display Controller device to RT-Thread */
rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
rt_device_init(dc);
}
@ -250,7 +250,7 @@ int rtgui_lcd_init(void)
pin_set_purpose(76, PIN_PURPOSE_OTHER);
pin_set_remap(76, PIN_REMAP_DEFAULT);
/* init Display Controller */
rt_hw_dc_init();
@ -259,7 +259,7 @@ int rtgui_lcd_init(void)
/* set Display Controller device as rtgui graphic driver */
rtgui_graphic_set_device(dc);
return 0;
}

46
bsp/loongson/ls1cdev/drivers/display_controller.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,9 +7,9 @@
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
* 2015-07-06 chinesebear modified for loongson 1c
* 2018-01-06 sundm75 modified for smartloong
* 2018-01-06 sundm75 modified for smartloong
*/
#ifndef __DISPLAY_CONTROLLER_H__
#define __DISPLAY_CONTROLLER_H__
@ -19,31 +19,31 @@
#define DC_BASE 0xBC301240 //Display Controller
/* Frame Buffer registers */
#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
#define DC_VSYNC __REG32(DC_BASE + 0x260)
#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
#define DC_VSYNC __REG32(DC_BASE + 0x260)
#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
/* Display Controller driver for 1024x768 16bit */
#define FB_XSIZE 480
#define FB_YSIZE 272
#define FB_XSIZE 480
#define FB_YSIZE 272
#define CONFIG_VIDEO_16BPP
#define OSC 24000000 /* Hz */
#define OSC 24000000 /* Hz */
#define K1BASE 0xA0000000
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
#define K1BASE 0xA0000000
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
struct vga_struct
{

88
bsp/loongson/ls1cdev/drivers/drv_can.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -40,7 +40,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i
rt_int32_t hdr, fbase, foff;
CAN_TypeDef* CANx;
CANx = pbxcan->reg;
/*pitem->mode 1-掩码模式; 0- 滤波器模式 SJA1000中使用以下方式*/
/*SJA1000中AFM 1-单滤波器模式; 0- 双滤波器模式 */
@ -72,7 +72,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i
}
CAN_FilterInitTypeDef CAN_FilterInitStruct;
unsigned char ide, rtr, id , idmask, mode;
unsigned char ide, rtr, id , idmask, mode;
ide = (unsigned char) pitem->ide;
rtr = (unsigned char) pitem->rtr;
id = pitem->id;
@ -84,7 +84,7 @@ static rt_err_t bxmodifyfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_i
CAN_FilterInitStruct.IDMASK = idmask;
CAN_FilterInitStruct.MODE = mode;
CAN_FilterInit(CANx, &CAN_FilterInitStruct);
return RT_EOK;
}
@ -109,15 +109,15 @@ static rt_err_t setfilter(struct ls1c_bxcan *pbxcan, struct rt_can_filter_config
static void bxcan0_filter_init(struct rt_can_device *can)
{
struct ls1c_bxcan *pbxcan;
pbxcan = (struct ls1c_bxcan *) can->parent.user_data;
pbxcan = (struct ls1c_bxcan *) can->parent.user_data;
}
static void bxcan1_filter_init(struct rt_can_device *can)
{
struct ls1c_bxcan *pbxcan;
pbxcan = (struct ls1c_bxcan *) can->parent.user_data;
pbxcan = (struct ls1c_bxcan *) can->parent.user_data;
}
static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode)
@ -161,7 +161,7 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode)
break;
case RT_CAN_MODE_LOOPBACK:
CAN_InitStructure.CAN_Mode = CAN_Mode_STM;
break;
case RT_CAN_MODE_LOOPBACKANLISEN:
CAN_InitStructure.CAN_Mode = CAN_Mode_STM|CAN_Mode_LOM;
@ -171,37 +171,37 @@ static void bxcan_init(CAN_TypeDef *pcan, rt_uint32_t baud, rt_uint32_t mode)
switch (bps)
{
case LS1C_CAN1MBaud:
case LS1C_CAN1MBaud:
CAN_InitStructure.CAN_Prescaler = 9;
CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN800kBaud:
case LS1C_CAN800kBaud:
CAN_InitStructure.CAN_Prescaler = 8;
CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN500kBaud:
case LS1C_CAN500kBaud:
CAN_InitStructure.CAN_Prescaler = 9;
CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN250kBaud:
case LS1C_CAN250kBaud:
CAN_InitStructure.CAN_Prescaler = 36;
CAN_InitStructure.CAN_BS1 = CAN_BS1_4tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN125kBaud:
case LS1C_CAN125kBaud:
CAN_InitStructure.CAN_Prescaler = 36;
CAN_InitStructure.CAN_BS1 = CAN_BS1_11tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN100kBaud:
case LS1C_CAN100kBaud:
CAN_InitStructure.CAN_Prescaler = 63;
CAN_InitStructure.CAN_BS1 = CAN_BS1_7tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq;
break;
case LS1C_CAN50kBaud:
case LS1C_CAN50kBaud:
CAN_InitStructure.CAN_Prescaler = 63;
CAN_InitStructure.CAN_BS1 = CAN_BS1_16tq;
CAN_InitStructure.CAN_BS2 = CAN_BS2_3tq;
@ -244,14 +244,14 @@ static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg)
if (pbxcan == CAN0)
{
#ifdef USING_BXCAN0
bxcan0_hw_init();
bxcan0_hw_init();
bxcan_init(pbxcan, cfg->baud_rate, cfg->mode);
#endif
}
else if (pbxcan == CAN1)
{
#ifdef USING_BXCAN1
bxcan1_hw_init();
bxcan1_hw_init();
bxcan_init(pbxcan, cfg->baud_rate, cfg->mode);
#endif
}
@ -328,7 +328,7 @@ static rt_err_t control(struct rt_can_device *can, int cmd, void *arg)
}
break;
case RT_CAN_CMD_GET_STATUS:
{
{
rt_uint32_t errtype;
errtype = pbxcan->reg->RXERR;
@ -380,7 +380,7 @@ static int recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
pbxcan = ((struct ls1c_bxcan *) can->parent.user_data)->reg;
pmsg->ide = (rt_uint32_t) RxMessage.IDE;
pmsg->ide = (rt_uint32_t) RxMessage.IDE;
if(RxMessage.IDE == 1)
pmsg->id = RxMessage.ExtId;
else
@ -405,37 +405,37 @@ static const struct rt_can_ops canops =
#ifdef USING_BXCAN0
struct rt_can_device bxcan0;
void ls1c_can0_irqhandler(int irq, void *param)
{
void ls1c_can0_irqhandler(int irq, void *param)
{
CAN_TypeDef* CANx;
unsigned char status;
CANx = CAN0;
/*读寄存器清除中断*/
status = CANx->IR;
/*接收中断*/
if (( status & CAN_IR_RI) == CAN_IR_RI)
if (( status & CAN_IR_RI) == CAN_IR_RI)
{
/*清除RI 中断*/
CAN_Receive(CANx, &RxMessage);
CANx->CMR |= CAN_CMR_RRB;
CANx->CMR |= CAN_CMR_CDO;
CANx->CMR |= CAN_CMR_RRB;
CANx->CMR |= CAN_CMR_CDO;
rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RX_IND);
rt_kprintf("\r\nCan0 int RX happened!\r\n");
}
/*发送中断*/
else if (( status & CAN_IR_TI) == CAN_IR_TI)
else if (( status & CAN_IR_TI) == CAN_IR_TI)
{
rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_TX_DONE | 0 << 8);
rt_kprintf("\r\nCan0 int TX happened!\r\n");
}
/*数据溢出中断*/
else if (( status & CAN_IR_DOI) == CAN_IR_DOI)
else if (( status & CAN_IR_DOI) == CAN_IR_DOI)
{
rt_hw_can_isr(&bxcan0, RT_CAN_EVENT_RXOF_IND);
rt_kprintf("\r\nCan0 int RX OF happened!\r\n");
}
}
}
static struct ls1c_bxcan bxcan0data =
{
.reg = CAN0,
@ -445,37 +445,37 @@ static struct ls1c_bxcan bxcan0data =
#ifdef USING_BXCAN1
struct rt_can_device bxcan1;
void ls1c_can1_irqhandler(int irq, void *param)
{
void ls1c_can1_irqhandler(int irq, void *param)
{
CAN_TypeDef* CANx;
unsigned char status;
CANx = CAN1;
/*读寄存器清除中断*/
status = CANx->IR;
/*接收中断*/
if (( status & CAN_IR_RI) == CAN_IR_RI)
if (( status & CAN_IR_RI) == CAN_IR_RI)
{
/*清除RI 中断*/
CAN_Receive(CANx, &RxMessage);
CANx->CMR |= CAN_CMR_RRB;
CANx->CMR |= CAN_CMR_CDO;
CANx->CMR |= CAN_CMR_RRB;
CANx->CMR |= CAN_CMR_CDO;
rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RX_IND);
rt_kprintf("\r\nCan1 int RX happened!\r\n");
}
/*发送中断*/
else if (( status & CAN_IR_TI) == CAN_IR_TI)
else if (( status & CAN_IR_TI) == CAN_IR_TI)
{
rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_TX_DONE | 0 << 8);
rt_kprintf("\r\nCan1 int TX happened!\r\n");
}
/*数据溢出中断*/
else if (( status & CAN_IR_DOI) == CAN_IR_DOI)
else if (( status & CAN_IR_DOI) == CAN_IR_DOI)
{
rt_hw_can_isr(&bxcan1, RT_CAN_EVENT_RXOF_IND);
rt_kprintf("\r\nCan1 int RX OF happened!\r\n");
}
}
}
static struct ls1c_bxcan bxcan1data =
{
.reg = CAN1,
@ -499,9 +499,9 @@ int ls1c_bxcan_init(void)
#endif
rt_hw_can_register(&bxcan0, "bxcan0", &canops, &bxcan0data);
rt_kprintf("\r\ncan0 register! \r\n");
rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0");
rt_hw_interrupt_umask(LS1C_CAN0_IRQ);
rt_hw_interrupt_install(LS1C_CAN0_IRQ,( rt_isr_handler_t)bxcan0data.irq , RT_NULL, "can0");
rt_hw_interrupt_umask(LS1C_CAN0_IRQ);
#endif
#ifdef USING_BXCAN1
bxcan1.config.baud_rate = CAN250kBaud;
@ -515,9 +515,9 @@ int ls1c_bxcan_init(void)
#endif
rt_hw_can_register(&bxcan1, "bxcan1", &canops, &bxcan1data);
rt_kprintf("\r\ncan1 register! \r\n");
rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1");
rt_hw_interrupt_umask(LS1C_CAN1_IRQ);
rt_hw_interrupt_install(LS1C_CAN1_IRQ,( rt_isr_handler_t)bxcan1data.irq , RT_NULL, "can1");
rt_hw_interrupt_umask(LS1C_CAN1_IRQ);
#endif
return RT_EOK;
}

4
bsp/loongson/ls1cdev/drivers/drv_gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -90,7 +90,7 @@ rt_err_t ls1c_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
break;
}
gpio_set_irq_type(gpio, type);
rt_sprintf(irq_name, "PIN_%d", gpio);
rt_hw_interrupt_install(LS1C_GPIO_TO_IRQ(gpio), (rt_isr_handler_t)hdr, args, irq_name);

22
bsp/loongson/ls1cdev/drivers/drv_pwm.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -59,17 +59,17 @@ static rt_err_t get(struct rt_device_pwm *device, struct rt_pwm_configuration *c
{
rt_err_t result = RT_EOK;
struct rt_ls1c_pwm *ls1c_pwm_device = (struct rt_ls1c_pwm *)device;
if (configuration->channel > (PWM_CHANNEL_MAX - 1))
{
result = -RT_EIO;
goto _exit;
}
configuration->period = ls1c_pwm_device->period[configuration->channel];
configuration->pulse = ls1c_pwm_device->pulse[configuration->channel];
rt_kprintf("drv_pwm.c get channel %d: period: %d, pulse: %d\n", configuration->channel, configuration->period, configuration->pulse);
_exit:
return result;
}
@ -84,7 +84,7 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg)
if (cmd == PWM_CMD_ENABLE)
{
rt_kprintf("PWM_CMD_ENABLE\n");
pwm_info_t pwm_info;
switch ( configuration->channel)
{
@ -107,9 +107,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg)
default:
break;
}
pwm_info.mode = PWM_MODE_NORMAL;
pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period );
pwm_info.period_ns = configuration->period;
pwm_info.mode = PWM_MODE_NORMAL;
pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period );
pwm_info.period_ns = configuration->period;
pwm_init(&pwm_info);
pwm_enable(&pwm_info);
}
@ -138,9 +138,9 @@ static rt_err_t control(struct rt_device_pwm *device, int cmd, void *arg)
default:
break;
}
pwm_info.mode = PWM_MODE_NORMAL;
pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period );
pwm_info.period_ns = configuration->period;
pwm_info.mode = PWM_MODE_NORMAL;
pwm_info.duty = ( (float)configuration->pulse ) / ((float)configuration->period );
pwm_info.period_ns = configuration->period;
pwm_init(&pwm_info);
pwm_disable(&pwm_info);
}

66
bsp/loongson/ls1cdev/drivers/drv_rtc.c
View File

@ -1,10 +1,10 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2018-05-05 sundm75 first version
*/
@ -21,56 +21,56 @@
#if defined(RT_USING_RTC)
#ifdef RT_RTC_DEBUG
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#define rtc_debug(format,args...) rt_kprintf(format, ##args)
#else
#define rtc_debug(format,args...)
#endif
static struct rt_device rtc;
RTC_TypeDef * RTC_Handler;
RTC_TypeDef * RTC_Handler;
static time_t get_timestamp(void)
static time_t get_timestamp(void)
{
struct tm tm_new = {0};
RTC_TimeTypeDef rtcDate;
RTC_GetTime(RTC_Handler, &rtcDate);
tm_new.tm_sec = rtcDate.Seconds;
tm_new.tm_min = rtcDate.Minutes;
struct tm tm_new = {0};
RTC_TimeTypeDef rtcDate;
RTC_GetTime(RTC_Handler, &rtcDate);
tm_new.tm_sec = rtcDate.Seconds;
tm_new.tm_min = rtcDate.Minutes;
tm_new.tm_hour = rtcDate.Hours;
tm_new.tm_mday = rtcDate.Date;
tm_new.tm_mon = rtcDate.Month- 1;
tm_new.tm_year = rtcDate.Year + 2000 - 1900;
tm_new.tm_mday = rtcDate.Date;
tm_new.tm_mon = rtcDate.Month- 1;
tm_new.tm_year = rtcDate.Year + 2000 - 1900;
return timegm(&tm_new);
}
static int set_timestamp(time_t timestamp)
{
struct tm *p_tm;
RTC_TimeTypeDef rtcDate;
p_tm = gmtime(&timestamp);
rtcDate.Seconds= p_tm->tm_sec ;
rtcDate.Minutes= p_tm->tm_min ;
rtcDate.Hours= p_tm->tm_hour;
struct tm now;
RTC_TimeTypeDef rtcDate;
rtcDate.Date= p_tm->tm_mday;
rtcDate.Month= p_tm->tm_mon + 1;
rtcDate.Year= p_tm->tm_year + 1900 - 2000;
RTC_SetTime(RTC_Handler, &rtcDate);
gmtime_r(&timestamp, &now);
rtcDate.Seconds= now.tm_sec ;
rtcDate.Minutes= now.tm_min ;
rtcDate.Hours= now.tm_hour;
rtcDate.Date= now.tm_mday;
rtcDate.Month= now.tm_mon + 1;
rtcDate.Year= now.tm_year + 1900 - 2000;
RTC_SetTime(RTC_Handler, &rtcDate);
rt_kprintf("\r\nrtcDate is %d.%d.%d - %d:%d:%d",rtcDate.Year, rtcDate.Month, rtcDate.Date, rtcDate.Hours, rtcDate.Minutes, rtcDate.Seconds);
return RT_EOK;
}
rt_uint8_t RTC_Init(void)
{
RTC_Handler = RTC;
{
RTC_Handler = RTC;
return 0;
}
@ -90,7 +90,7 @@ static rt_size_t rt_rtc_read(
void* buffer,
rt_size_t size)
{
return 0;
}
@ -109,7 +109,7 @@ static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = get_timestamp();
rtc_debug("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
break;

10
bsp/loongson/ls1cdev/drivers/drv_rtc.h
View File

@ -1,18 +1,18 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* Date Author Notes
* 2018-05-05 sundm75 first version
*/
#ifndef __DRV_RTC_H__
#define __DRV_RTC_H__
#include <rtthread.h>
#include <rtdevice.h>
#include <rtthread.h>
#include <rtdevice.h>
int rt_hw_rtc_init(void);

4
bsp/loongson/ls1cdev/drivers/drv_spi.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -32,7 +32,7 @@ struct ls1c_spi_cs
* 初始化并注册龙芯1c的spi总线
* @SPI SPI总线，比如LS1C_SPI_0， LS1C_SPI_1
* @spi_bus_name 总线名字
* @ret
* @ret
*/
rt_err_t ls1c_spi_bus_register(rt_uint8_t SPI, const char *spi_bus_name);

4
bsp/loongson/ls1cdev/drivers/drv_touch.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -9,7 +9,7 @@
* 2018-10-29 XY
* 2019-04-11 sundm75 modify for ls1c300 & RTGUI
*/
#include "drv_touch.h"
#define TOUCH_I2C_NAME "i2c1"

4
bsp/loongson/ls1cdev/drivers/drv_touch.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,7 +8,7 @@
* 2018-02-08 Zhangyihong the first version
* 2018-10-29 XY
*/
#ifndef __DRV_TOUCH_H__
#define __DRV_TOUCH_H__

12
bsp/loongson/ls1cdev/drivers/drv_wdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -161,15 +161,15 @@ static rt_err_t watchdog_ctrl(rt_watchdog_t *wdt, int cmd, void *arg)
return RT_EOK;
}
struct rt_watchdog_ops watchdog_ops =
struct rt_watchdog_ops watchdog_ops =
{
.init = &watchdog_init,
.init = &watchdog_init,
.control = &watchdog_ctrl,
};
int wdt_exit(void *priv_data)
{
return 0;
int wdt_exit(void *priv_data)
{
return 0;
}
int rt_hw_wdt_init(void)

32
bsp/loongson/ls1cdev/drivers/hw_i2c.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -10,7 +10,7 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "ls1c_i2c.h"
#include "ls1c_i2c.h"
#include "../libraries/ls1c_pin.h"
#ifdef RT_USING_I2C
@ -26,30 +26,30 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
rt_uint32_t num)
{
struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus;
ls1c_i2c_info_t i2c_info;
ls1c_i2c_info_t i2c_info;
struct rt_i2c_msg *msg;
int i;
rt_int32_t ret = RT_EOK;
i2c_info.clock = 50000; // 50kb/s
i2c_info.clock = 50000; // 50kb/s
i2c_info.I2Cx = i2c_bus->u32Module;
i2c_init(&i2c_info);
for (i = 0; i < num; i++)
{
msg = &msgs[i];
if (msg->flags == RT_I2C_RD)
{
i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ);
i2c_receive_ack(&i2c_info);
i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
i2c_send_stop(&i2c_info);
i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ);
i2c_receive_ack(&i2c_info);
i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
i2c_send_stop(&i2c_info);
}
else if(msg->flags == RT_I2C_WR)
{
i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE);
i2c_receive_ack(&i2c_info);
i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
i2c_send_stop(&i2c_info);
i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE);
i2c_receive_ack(&i2c_info);
i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
i2c_send_stop(&i2c_info);
}
ret++;
}
@ -85,7 +85,7 @@ static const struct rt_i2c_bus_device_ops ls1c_i2c_ops =
#ifdef RT_USING_I2C0
static struct ls1c_i2c_bus ls1c_i2c_bus_0 =
static struct ls1c_i2c_bus ls1c_i2c_bus_0 =
{
{1},
LS1C_I2C_0,
@ -93,7 +93,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_0 =
#endif
#ifdef RT_USING_I2C1
static struct ls1c_i2c_bus ls1c_i2c_bus_1 =
static struct ls1c_i2c_bus ls1c_i2c_bus_1 =
{
{1},
LS1C_I2C_1,
@ -101,7 +101,7 @@ static struct ls1c_i2c_bus ls1c_i2c_bus_1 =
#endif
#ifdef RT_USING_I2C2
static struct ls1c_i2c_bus ls1c_i2c_bus_2 =
static struct ls1c_i2c_bus ls1c_i2c_bus_2 =
{
{1},
LS1C_I2C_2,

4
bsp/loongson/ls1cdev/drivers/hw_i2c.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -15,4 +15,4 @@
int rt_i2c_init(void);
#endif
#endif

186
bsp/loongson/ls1cdev/drivers/net/mii.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,123 +14,123 @@
static inline unsigned int mii_nway_result (unsigned int negotiated)
{
unsigned int ret;
unsigned int ret;
if (negotiated & LPA_100FULL)
ret = LPA_100FULL;
else if (negotiated & LPA_100BASE4)
ret = LPA_100BASE4;
else if (negotiated & LPA_100HALF)
ret = LPA_100HALF;
else if (negotiated & LPA_10FULL)
ret = LPA_10FULL;
else
ret = LPA_10HALF;
if (negotiated & LPA_100FULL)
ret = LPA_100FULL;
else if (negotiated & LPA_100BASE4)
ret = LPA_100BASE4;
else if (negotiated & LPA_100HALF)
ret = LPA_100HALF;
else if (negotiated & LPA_10FULL)
ret = LPA_10FULL;
else
ret = LPA_10HALF;
return ret;
return ret;
}
static int mii_check_gmii_support(struct mii_if_info *mii)
{
int reg;
int reg;
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (reg & BMSR_ESTATEN) {
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
return 1;
}
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (reg & BMSR_ESTATEN) {
reg = mii->mdio_read(mii->dev, mii->phy_id, MII_ESTATUS);
if (reg & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF))
return 1;
}
return 0;
return 0;
}
static int mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)
{
struct synopGMACNetworkAdapter * dev = mii->dev;
u32 advert, bmcr, lpa, nego;
u32 advert2 = 0, bmcr2 = 0, lpa2 = 0;
struct synopGMACNetworkAdapter * dev = mii->dev;
u32 advert, bmcr, lpa, nego;
u32 advert2 = 0, bmcr2 = 0, lpa2 = 0;
ecmd->supported =
(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
if (mii->supports_gmii)
ecmd->supported |= SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
ecmd->supported =
(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
if (mii->supports_gmii)
ecmd->supported |= SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
/* only supports twisted-pair */
ecmd->port = PORT_MII;
/* only supports twisted-pair */
ecmd->port = PORT_MII;
/* only supports internal transceiver */
ecmd->transceiver = XCVR_INTERNAL;
/* only supports internal transceiver */
ecmd->transceiver = XCVR_INTERNAL;
/* this isn't fully supported at higher layers */
ecmd->phy_address = mii->phy_id;
/* this isn't fully supported at higher layers */
ecmd->phy_address = mii->phy_id;
ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
if (mii->supports_gmii)
advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
ecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
advert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);
if (mii->supports_gmii)
advert2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
if (advert & ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
if (advert & ADVERTISE_10FULL)
ecmd->advertising |= ADVERTISED_10baseT_Full;
if (advert & ADVERTISE_100HALF)
ecmd->advertising |= ADVERTISED_100baseT_Half;
if (advert & ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
if (advert2 & ADVERTISE_1000HALF)
ecmd->advertising |= ADVERTISED_1000baseT_Half;
if (advert2 & ADVERTISE_1000FULL)
ecmd->advertising |= ADVERTISED_1000baseT_Full;
if (advert & ADVERTISE_10HALF)
ecmd->advertising |= ADVERTISED_10baseT_Half;
if (advert & ADVERTISE_10FULL)
ecmd->advertising |= ADVERTISED_10baseT_Full;
if (advert & ADVERTISE_100HALF)
ecmd->advertising |= ADVERTISED_100baseT_Half;
if (advert & ADVERTISE_100FULL)
ecmd->advertising |= ADVERTISED_100baseT_Full;
if (advert2 & ADVERTISE_1000HALF)
ecmd->advertising |= ADVERTISED_1000baseT_Half;
if (advert2 & ADVERTISE_1000FULL)
ecmd->advertising |= ADVERTISED_1000baseT_Full;
bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
if (mii->supports_gmii) {
bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
}
if (bmcr & BMCR_ANENABLE) {
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->autoneg = AUTONEG_ENABLE;
nego = mii_nway_result(advert & lpa);
if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) &
(lpa2 >> 2))
ecmd->speed = SPEED_1000;
else if (nego == LPA_100FULL || nego == LPA_100HALF)
ecmd->speed = SPEED_100;
else
ecmd->speed = SPEED_10;
if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
nego == LPA_10FULL) {
ecmd->duplex = DUPLEX_FULL;
mii->full_duplex = 1;
} else {
ecmd->duplex = DUPLEX_HALF;
mii->full_duplex = 0;
}
} else {
ecmd->autoneg = AUTONEG_DISABLE;
bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
lpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);
if (mii->supports_gmii) {
bmcr2 = mii->mdio_read(dev, mii->phy_id, MII_CTRL1000);
lpa2 = mii->mdio_read(dev, mii->phy_id, MII_STAT1000);
}
if (bmcr & BMCR_ANENABLE) {
ecmd->advertising |= ADVERTISED_Autoneg;
ecmd->autoneg = AUTONEG_ENABLE;
ecmd->speed = ((bmcr & BMCR_SPEED1000 &&
(bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
(bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
}
nego = mii_nway_result(advert & lpa);
if ((bmcr2 & (ADVERTISE_1000HALF | ADVERTISE_1000FULL)) &
(lpa2 >> 2))
ecmd->speed = SPEED_1000;
else if (nego == LPA_100FULL || nego == LPA_100HALF)
ecmd->speed = SPEED_100;
else
ecmd->speed = SPEED_10;
if ((lpa2 & LPA_1000FULL) || nego == LPA_100FULL ||
nego == LPA_10FULL) {
ecmd->duplex = DUPLEX_FULL;
mii->full_duplex = 1;
} else {
ecmd->duplex = DUPLEX_HALF;
mii->full_duplex = 0;
}
} else {
ecmd->autoneg = AUTONEG_DISABLE;
/* ignore maxtxpkt, maxrxpkt for now */
ecmd->speed = ((bmcr & BMCR_SPEED1000 &&
(bmcr & BMCR_SPEED100) == 0) ? SPEED_1000 :
(bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10);
ecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
}
return 0;
/* ignore maxtxpkt, maxrxpkt for now */
return 0;
}
static int mii_link_ok (struct mii_if_info *mii)
{
/* first, a dummy read, needed to latch some MII phys */
mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
return 1;
return 0;
/* first, a dummy read, needed to latch some MII phys */
mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);
if (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)
return 1;
return 0;
}

150
bsp/loongson/ls1cdev/drivers/net/mii.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -24,7 +24,7 @@
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
@ -39,7 +39,7 @@
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
@ -58,9 +58,9 @@
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100FULL2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100HALF2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
@ -87,26 +87,26 @@
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Indicates what features are advertised by the interface. */
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
#define ADVERTISED_Pause (1 << 13)
#define ADVERTISED_Asym_Pause (1 << 14)
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
#define ADVERTISED_Pause (1 << 13)
#define ADVERTISED_Asym_Pause (1 << 14)
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
@ -126,8 +126,8 @@
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
@ -137,8 +137,8 @@
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
@ -154,78 +154,78 @@
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define SUPPORTED_Pause (1 << 13)
#define SUPPORTED_Asym_Pause (1 << 14)
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define SUPPORTED_Pause (1 << 13)
#define SUPPORTED_Asym_Pause (1 << 14)
/* Which connector port. */
#define PORT_TP 0x00
#define PORT_AUI 0x01
#define PORT_MII 0x02
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
#define PORT_BNC 0x04
/* Which transceiver to use. */
#define XCVR_INTERNAL 0x00
#define XCVR_EXTERNAL 0x01
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY3 0x04
#define AUTONEG_DISABLE 0x00
#define AUTONEG_ENABLE 0x01
#define AUTONEG_DISABLE 0x00
#define AUTONEG_ENABLE 0x01
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_10000 10000
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_10000 10000
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
struct ethtool_cmd {
u32 cmd;
u32 supported; /* Features this interface supports */
u32 advertising; /* Features this interface advertises */
u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
u8 duplex; /* Duplex, half or full */
u8 port; /* Which connector port */
u8 phy_address;
u8 transceiver; /* Which transceiver to use */
u8 autoneg; /* Enable or disable autonegotiation */
u32 maxtxpkt; /* Tx pkts before generating tx int */
u32 maxrxpkt; /* Rx pkts before generating rx int */
u32 reserved[4];
u32 cmd;
u32 supported; /* Features this interface supports */
u32 advertising; /* Features this interface advertises */
u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */
u8 duplex; /* Duplex, half or full */
u8 port; /* Which connector port */
u8 phy_address;
u8 transceiver; /* Which transceiver to use */
u8 autoneg; /* Enable or disable autonegotiation */
u32 maxtxpkt; /* Tx pkts before generating tx int */
u32 maxrxpkt; /* Rx pkts before generating rx int */
u32 reserved[4];
};
struct mii_if_info {
int phy_id;
int advertising;
int phy_id_mask;
int reg_num_mask;
int phy_id;
int advertising;
int phy_id_mask;
int reg_num_mask;
unsigned int full_duplex : 1; /* is full duplex? */
unsigned int force_media : 1; /* is autoneg. disabled? */
unsigned int supports_gmii : 1; /* are GMII registers supported? */
unsigned int full_duplex : 1; /* is full duplex? */
unsigned int force_media : 1; /* is autoneg. disabled? */
unsigned int supports_gmii : 1; /* are GMII registers supported? */
struct synopGMACNetworkAdapter *dev;
int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location);
void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val);
struct synopGMACNetworkAdapter *dev;
int (*mdio_read) (struct synopGMACNetworkAdapter *dev, int phy_id, int location);
void (*mdio_write) (struct synopGMACNetworkAdapter *dev, int phy_id, int location, int val);
};
#endif

4
bsp/loongson/ls1cdev/drivers/net/synopGMAC.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -579,7 +579,7 @@ struct pbuf *rt_eth_rx(rt_device_t device)
if (synopGMAC_is_rx_desc_valid(status) || SYNOP_PHY_LOOPBACK)
{
dma_addr1 = plat_dma_map_single(gmacdev, (void *)data1, RX_BUF_SIZE);
len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes
len = synopGMAC_get_rx_desc_frame_length(status)-4; //Not interested in Ethernet CRC bytes
pbuf = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
if (pbuf == 0) rt_kprintf("===error in pbuf_alloc\n");
rt_memcpy(pbuf->payload, (char *)data1, len);

4
bsp/loongson/ls1cdev/drivers/net/synopGMAC.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -20,4 +20,4 @@
int rt_hw_eth_init(void);
#endif /*__SYNOPGMAC__H*/
#endif /*__SYNOPGMAC__H*/

2440
bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.c
View File

File diff suppressed because it is too large Load Diff

1270
bsp/loongson/ls1cdev/drivers/net/synopGMAC_Dev.h
View File

File diff suppressed because it is too large Load Diff

56
bsp/loongson/ls1cdev/drivers/net/synopGMAC_Host.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -21,35 +21,35 @@
struct net_device_stats
{
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_errors; /* bad packets received */
unsigned long tx_errors; /* packet transmit problems */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long multicast; /* multicast packets received */
unsigned long collisions;
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed rx_errors: */
unsigned long rx_length_errors;
unsigned long rx_over_errors; /* receiver ring buff overflow */
unsigned long rx_crc_errors; /* recved pkt with crc error */
unsigned long rx_frame_errors; /* recv'd frame alignment error */
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
unsigned long rx_missed_errors; /* receiver missed packet */
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
/* detailed tx_errors */
unsigned long tx_aborted_errors;
unsigned long tx_carrier_errors;
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;
};

6
bsp/loongson/ls1cdev/drivers/net/synopGMAC_debug.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -14,8 +14,8 @@
//#define GMAC_DEBUG
#include <rtthread.h>
#ifdef GMAC_DEBUG
#define DEBUG_MES rt_kprintf
#ifdef GMAC_DEBUG
#define DEBUG_MES rt_kprintf
#else
#define DEBUG_MES(...)
#endif

4
bsp/loongson/ls1cdev/drivers/net/synopGMAC_network_interface.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,7 +8,7 @@
* 2017-08-24 chinesebear first version
*/
#ifndef SYNOP_GMAC_NETWORK_INTERFACE_H
#define SYNOP_GMAC_NETWORK_INTERFACE_H 1

94
bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,7 +8,7 @@
* 2017-08-24 chinesebear first version
*/
#include "synopGMAC_plat.h"
#include "synopGMAC_Dev.h"
#include <rthw.h>
@ -16,58 +16,58 @@
extern void flush_cache(unsigned long start_addr, unsigned long size);
dma_addr_t __attribute__((weak)) gmac_dmamap(unsigned long va,u32 size)
{
return VA_TO_PA (va);
//return UNCACHED_TO_PHYS(va);
return VA_TO_PA (va);
//return UNCACHED_TO_PHYS(va);
}
/**
* This is a wrapper function for Memory allocation routine. In linux Kernel
* This is a wrapper function for Memory allocation routine. In linux Kernel
* it it kmalloc function
* @param[in] bytes in bytes to allocate
*/
void *plat_alloc_memory(u32 bytes)
void *plat_alloc_memory(u32 bytes)
{
//return (void*)malloc((size_t)bytes, M_DEVBUF, M_DONTWAIT);
void *buf = (void*)rt_malloc((u32)bytes);
void *buf = (void*)rt_malloc((u32)bytes);
flush_cache((unsigned long)buf, bytes);
return buf;
flush_cache((unsigned long)buf, bytes);
return buf;
}
/**
* This is a wrapper function for consistent dma-able Memory allocation routine.
* This is a wrapper function for consistent dma-able Memory allocation routine.
* In linux Kernel, it depends on pci dev structure
* @param[in] bytes in bytes to allocate
*/
//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr)
void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr)
//void *plat_alloc_consistent_dmaable_memory(struct synopGMACdevice *dev, u32 size, u32 *addr)
void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u32 *addr)
{
void *buf;
buf = (void*)rt_malloc((u32)(size+16));
//CPU_IOFlushDCache( buf,size, SYNC_W);
unsigned long i = (unsigned long)buf;
// rt_kprintf("size = %d\n", size);
// rt_kprintf("bufaddr = %p\n", buf);
// rt_kprintf("i%%16 == %d\n", i%16);
if(i%16 == 8){
i += 8;
}
else if(i%16 == 4){
i += 12;
}
else if(i%16 == 12){
i += 4;
}
void *buf;
buf = (void*)rt_malloc((u32)(size+16));
//CPU_IOFlushDCache( buf,size, SYNC_W);
unsigned long i = (unsigned long)buf;
// rt_kprintf("size = %d\n", size);
// rt_kprintf("bufaddr = %p\n", buf);
// rt_kprintf("i%%16 == %d\n", i%16);
if(i%16 == 8){
i += 8;
}
else if(i%16 == 4){
i += 12;
}
else if(i%16 == 12){
i += 4;
}
flush_cache(i, size);
*addr =gmac_dmamap(i, size);
buf = (unsigned char *)CACHED_TO_UNCACHED(i);
// rt_kprintf("bufaddr = %p\n", buf);
return buf;
flush_cache(i, size);
*addr =gmac_dmamap(i, size);
buf = (unsigned char *)CACHED_TO_UNCACHED(i);
// rt_kprintf("bufaddr = %p\n", buf);
return buf;
}
@ -78,46 +78,46 @@ void *plat_alloc_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, u3
*/
//void plat_free_consistent_dmaable_memory(void * addr)
void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr)
//void plat_free_consistent_dmaable_memory(void * addr)
void plat_free_consistent_dmaable_memory(synopGMACdevice *pcidev, u32 size, void * addr,u32 dma_addr)
{
rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr)));
rt_free((void*)PHYS_TO_CACHED(UNCACHED_TO_PHYS(addr)));
return;
}
/**
* This is a wrapper function for Memory free routine. In linux Kernel
* This is a wrapper function for Memory free routine. In linux Kernel
* it it kfree function
* @param[in] buffer pointer to be freed
*/
void plat_free_memory(void *buffer)
void plat_free_memory(void *buffer)
{
rt_free(buffer);
return ;
rt_free(buffer);
return ;
}
dma_addr_t plat_dma_map_single(void *hwdev, void *ptr,
u32 size)
u32 size)
{
unsigned long addr = (unsigned long) ptr;
unsigned long addr = (unsigned long) ptr;
//CPU_IOFlushDCache(addr,size, direction);
flush_cache(addr, size);
flush_cache(addr, size);
return gmac_dmamap(addr, size);
}
/**
* This is a wrapper function for platform dependent delay
* Take care while passing the argument to this function
* This is a wrapper function for platform dependent delay
* Take care while passing the argument to this function
* @param[in] buffer pointer to be freed
*/
void plat_delay(u32 delay)
{
while (delay--);
return;
while (delay--);
return;
}

98
bsp/loongson/ls1cdev/drivers/net/synopGMAC_plat.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -8,12 +8,12 @@
* 2017-08-24 chinesebear first version
*/
#ifndef SYNOP_GMAC_PLAT_H
#define SYNOP_GMAC_PLAT_H 1
/* sw
/* sw
#include <linux/kernel.h>
#include <asm/io.h>
#include <linux/gfp.h>
@ -26,7 +26,7 @@
//#include "GMAC_Pmon.h"
//#include "synopGMAC_Host.h"
#include <rtthread.h>
//sw: copy the type define into here
//sw: copy the type define into here
#define IOCTL_READ_REGISTER SIOCDEVPRIVATE+1
#define IOCTL_WRITE_REGISTER SIOCDEVPRIVATE+2
#define IOCTL_READ_IPSTRUCT SIOCDEVPRIVATE+3
@ -58,18 +58,18 @@ typedef int bool;
#define VA_TO_PA(x) UNCACHED_TO_PHYS(x)
/* sw
#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
/* sw
#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#ifdef DEBUG
#undef TR
# define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#else
# define TR(fmt, args...) // not debugging: nothing
# define TR(fmt, args...) // not debugging: nothing
#endif
*/
/*
#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
*/
/*
@ -77,21 +77,21 @@ typedef int bool;
#undef TR
# define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#else
//# define TR(fmt, args...) // not debugging: nothing
#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
//# define TR(fmt, args...) // not debugging: nothing
#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#endif
*/
//sw: nothing to display
#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
//#define TR rt_kprintf
//typedef int bool;
enum synopGMAC_boolean
{
{
false = 0,
true = 1
true = 1
};
@ -102,9 +102,9 @@ enum synopGMAC_boolean
*
*/
#define LE32_TO_CPU __le32_to_cpu
#define BE32_TO_CPU __be32_to_cpu
#define CPU_TO_LE32 __cpu_to_le32
#define LE32_TO_CPU __le32_to_cpu
#define BE32_TO_CPU __be32_to_cpu
#define CPU_TO_LE32 __cpu_to_le32
/* Error Codes */
#define ESYNOPGMACNOERR 0
@ -114,15 +114,15 @@ enum synopGMAC_boolean
struct Network_interface_data
{
u32 unit;
u32 addr;
u32 data;
u32 unit;
u32 addr;
u32 data;
};
/**
* These are the wrapper function prototypes for OS/platform related routines
*/
*/
void * plat_alloc_memory(u32 );
void plat_free_memory(void *);
@ -135,10 +135,10 @@ void plat_delay(u32);
/**
* The Low level function to read register contents from Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* \return Returns the register contents
* \return Returns the register contents
*/
static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset)
{
@ -158,43 +158,43 @@ static u32 synopGMACReadReg(u32 RegBase, u32 RegOffset)
/**
* The Low level function to write to a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Data to be written
* \return void
* @param[in] Data to be written
* \return void
*/
static void synopGMACWriteReg(u32 RegBase, u32 RegOffset, u32 RegData )
{
u32 addr;
addr = RegBase + (u32)RegOffset;
addr = RegBase + (u32)RegOffset;
// rt_kprintf("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
#if SYNOP_REG_DEBUG
TR("%s RegBase = 0x%08x RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__,(u32) RegBase, RegOffset, RegData );
#endif
*(volatile u32 *)addr = RegData;
*(volatile u32 *)addr = RegData;
if(addr == 0xbfe1100c)
DEBUG_MES("regdata = %08x\n", RegData);
if(addr == 0xbfe1100c)
DEBUG_MES("regdata = %08x\n", RegData);
return;
}
/**
* The Low level function to set bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* \return void
* @param[in] Bit mask to set bits to logical 1
* \return void
*/
static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos)
{
//u64 addr = (u64)RegBase + (u64)RegOffset;
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data |= BitPos;
data |= BitPos;
synopGMACWriteReg(RegBase, RegOffset, data);
// writel(data,(void *)addr);
#if SYNOP_REG_DEBUG
@ -206,17 +206,17 @@ static void synopGMACSetBits(u32 RegBase, u32 RegOffset, u32 BitPos)
/**
* The Low level function to clear bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to clear bits to logical 0
* \return void
* @param[in] Bit mask to clear bits to logical 0
* \return void
*/
static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= (~BitPos);
data &= (~BitPos);
synopGMACWriteReg(RegBase, RegOffset, data);
#if SYNOP_REG_DEBUG
TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
@ -226,21 +226,21 @@ static void synopGMACClearBits(u32 RegBase, u32 RegOffset, u32 BitPos)
/**
* The Low level function to Check the setting of the bits.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* @param[in] Bit mask to set bits to logical 1
* \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
*
*
*/
static bool synopGMACCheckBits(u32 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= BitPos;
data &= BitPos;
if(data) return true;
else return false;
else return false;
}

4
bsp/loongson/ls1cdev/drivers/net/synopGMAC_types.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -22,4 +22,4 @@ typedef signed int s32;
typedef u32 dma_addr_t;
#endif /*__TYPES__H*/
#endif /*__TYPES__H*/

162
bsp/loongson/ls1cdev/drivers/selfboot.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -12,52 +12,52 @@
#define __RT_LS1C_SELFBOOT_H
/* SDRAM PARAM macro */
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
/* SDRAM ROW */
#define ROW_1K 0x7
#define ROW_2K 0x0
#define ROW_4K 0x1
#define ROW_8K 0x2
#define ROW_16K 0x3
#define ROW_1K 0x7
#define ROW_2K 0x0
#define ROW_4K 0x1
#define ROW_8K 0x2
#define ROW_16K 0x3
/* SDRAM COL */
#define COL_256 0x7
#define COL_512 0x0
#define COL_1K 0x1
#define COL_2K 0x2
#define COL_4K 0x3
#define COL_256 0x7
#define COL_512 0x0
#define COL_1K 0x1
#define COL_2K 0x2
#define COL_4K 0x3
/* SDRAM WIDTH */
#define WIDTH_8 0x0
#define WIDTH_16 0x1
#define WIDTH_32 0x2
#define WIDTH_8 0x0
#define WIDTH_16 0x1
#define WIDTH_32 0x2
#define TRCD 3
#define TCL 3
#define TRP 3
#define TRFC 8
#define TRAS 6
#define TREF 0x818
#define TWR 2
#define TRCD 3
#define TCL 3
#define TRP 3
#define TRFC 8
#define TRAS 6
#define TREF 0x818
#define TWR 2
#define DEF_SEL 0x1
#define DEF_SEL_N 0x0
#define HANG_UP 0x1
#define HANG_UP_N 0x0
#define CFG_VALID 0x1
#define DEF_SEL 0x1
#define DEF_SEL_N 0x0
#define HANG_UP 0x1
#define HANG_UP_N 0x0
#define CFG_VALID 0x1
#include "board.h"
#define SD_PARA0 (0x7f<<25 | \
(TRAS << 21) | \
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
SDRAM_ROW)
#define SD_PARA0 (0x7f<<25 | \
(TRAS << 21) | \
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
SDRAM_ROW)
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
#define LS1C_CBUS_FIRST1 0xBFE011C4
#define LS1C_UART2_BASE 0xBFE48000
@ -76,62 +76,62 @@
#define LS1C_UART_MSB_OFFSET (1)
/* interrupt enable register */
#define IER_IRxE 0x1
#define IER_ITxE 0x2
#define IER_ILE 0x4
#define IER_IME 0x8
#define IER_IRxE 0x1
#define IER_ITxE 0x2
#define IER_ILE 0x4
#define IER_IME 0x8
/* interrupt identification register */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
#define IIR_IMASK 0xf /* mask */
#define IIR_RXTOUT 0xc /* receive timeout */
#define IIR_RLS 0x6 /* receive line status */
#define IIR_RXRDY 0x4 /* receive ready */
#define IIR_TXRDY 0x2 /* transmit ready */
#define IIR_NOPEND 0x1 /* nothing */
#define IIR_MLSC 0x0 /* modem status */
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
/* fifo control register */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
#define FIFO_ENABLE 0x01 /* enable fifo */
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
/* character format control register */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
#define CFCR_DLAB 0x80 /* divisor latch */
#define CFCR_SBREAK 0x40 /* send break */
#define CFCR_PZERO 0x30 /* zero parity */
#define CFCR_PONE 0x20 /* one parity */
#define CFCR_PEVEN 0x10 /* even parity */
#define CFCR_PODD 0x00 /* odd parity */
#define CFCR_PENAB 0x08 /* parity enable */
#define CFCR_STOPB 0x04 /* 2 stop bits */
#define CFCR_8BITS 0x03 /* 8 data bits */
#define CFCR_7BITS 0x02 /* 7 data bits */
#define CFCR_6BITS 0x01 /* 6 data bits */
#define CFCR_5BITS 0x00 /* 5 data bits */
/* modem control register */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
#define MCR_LOOPBACK 0x10 /* loopback */
#define MCR_IENABLE 0x08 /* output 2 = int enable */
#define MCR_DRS 0x04 /* output 1 = xxx */
#define MCR_RTS 0x02 /* enable RTS */
#define MCR_DTR 0x01 /* enable DTR */
/* line status register */
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
#define LSR_TSRE 0x40 /* transmitter empty */
#define LSR_TXRDY 0x20 /* transmitter ready */
#define LSR_BI 0x10 /* break detected */
#define LSR_FE 0x08 /* framing error */
#define LSR_PE 0x04 /* parity error */
#define LSR_OE 0x02 /* overrun error */
#define LSR_RXRDY 0x01 /* receiver ready */
#define LSR_RCV_MASK 0x1f
/* External clock frequency */

92
bsp/loongson/ls1cdev/drivers/touch.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -7,13 +7,13 @@
* Date Author Notes
* 2017-12-30 Sundm75 first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <stdbool.h>
#include <drivers/spi.h>
#include "ls1c.h"
#include "ls1c_gpio.h"
#include "ls1c_gpio.h"
#include "ls1c_spi.h"
#include "drv_spi.h"
#include "touch.h"
@ -44,7 +44,7 @@ TOUCH INT: 84
*/
#define IS_TOUCH_UP() gpio_get(TOUCH_INT_PIN)
#define led_gpio 52 // led1指示
#define led_gpio 52 // led1指示
#define DUMMY 0x00
@ -88,12 +88,12 @@ s A2-A0 MODE SER/DFR PD1-PD0
#if defined(_ILI_HORIZONTAL_DIRECTION_)
#define MIN_X_DEFAULT 2047
#define MAX_X_DEFAULT 47
#define MIN_Y_DEFAULT 102
#define MAX_Y_DEFAULT 1939
#define MIN_Y_DEFAULT 102
#define MAX_Y_DEFAULT 1939
#else
#define MIN_X_DEFAULT 47
#define MAX_X_DEFAULT 2047
#define MIN_Y_DEFAULT 1939
#define MIN_Y_DEFAULT 1939
#define MAX_Y_DEFAULT 102
#endif
@ -105,29 +105,29 @@ s A2-A0 MODE SER/DFR PD1-PD0
/*宏定义 */
#define TOUCH_SPI_X SPI1
#define TOUCH_INT_PIN 84
#define TOUCH_CS_PIN 49
#define TOUCH_SPI_X SPI1
#define TOUCH_INT_PIN 84
#define TOUCH_CS_PIN 49
#define TOUCH_SCK_PIN 46
#define TOUCH_MISO_PIN 47
#define TOUCH_MOSI_PIN 48
#define TOUCH_MOSI_PIN 48
/*创建结构体将需要用到的东西进行打包*/
struct rtgui_touch_device
struct rtgui_touch_device
{
struct rt_device parent; /* 用于注册设备*/
rt_uint16_t x, y; /* 记录读取到的位置值 */
rt_uint16_t x, y; /* 记录读取到的位置值 */
rt_bool_t calibrating; /* 触摸校准标志 */
rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */
rt_bool_t calibrating; /* 触摸校准标志 */
rt_touch_calibration_func_t calibration_func;/* 触摸函数 函数指针 */
rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */
rt_uint16_t min_x, max_x; /* 校准后 X 方向最小 最大值 */
rt_uint16_t min_y, max_y; /* 校准后 Y 方向最小 最大值 */
struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */
struct rt_event event; /* 事件同步，用于“笔中断” */
struct rt_spi_device * spi_device; /* SPI 设备 用于通信 */
struct rt_event event; /* 事件同步，用于“笔中断” */
};
static struct rtgui_touch_device *touch = RT_NULL;
@ -255,14 +255,14 @@ static void rtgui_touch_calculate(void)
rt_uint32_t total_x = 0;
rt_uint32_t total_y = 0;
for(k=0; k<2; k++)
{
{
// sorting the ADC value
for(i=0; i<SAMP_CNT-1; i++)
{
min=i;
for (j=i+1; j<SAMP_CNT; j++)
{
if (tmpxy[k][min] > tmpxy[k][j])
if (tmpxy[k][min] > tmpxy[k][j])
min=j;
}
temp = tmpxy[k][i];
@ -329,11 +329,11 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */
{
if(gpio_get(TOUCH_INT_PIN)==0)
{
/* 触摸屏按下后操作 */
/* 触摸屏按下后操作 */
if (gpio_level_low == gpio_get(led_gpio))
gpio_set(led_gpio, gpio_level_high);
gpio_set(led_gpio, gpio_level_high);
else
gpio_set(led_gpio, gpio_level_low);
gpio_set(led_gpio, gpio_level_low);
touch_int_cmd(RT_FALSE);
rt_event_send(&touch->event, 1);
}
@ -341,19 +341,19 @@ void ls1c_touch_irqhandler(void) /* TouchScreen */
/*管脚初始化，配置中断打开SPI1 CS0 设备*/
rt_inline void touch_init(void)
{
{
unsigned int touch_int_gpio = TOUCH_INT_PIN; // 触摸屏中断
int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio);
// 初始化按键中断
gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING);
rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch");
rt_hw_interrupt_umask(touch_irq);
gpio_init(touch_int_gpio, gpio_mode_input);
// 初始化led
gpio_init(led_gpio, gpio_mode_output);
gpio_set(led_gpio, gpio_level_high);
int touch_irq = LS1C_GPIO_TO_IRQ(touch_int_gpio);
// 初始化按键中断
gpio_set_irq_type(touch_int_gpio, IRQ_TYPE_EDGE_FALLING);
rt_hw_interrupt_install(touch_irq, ls1c_touch_irqhandler, RT_NULL, "touch");
rt_hw_interrupt_umask(touch_irq);
gpio_init(touch_int_gpio, gpio_mode_input);
// 初始化led
gpio_init(led_gpio, gpio_mode_output);
gpio_set(led_gpio, gpio_level_high);
}
@ -363,7 +363,7 @@ static rt_err_t rtgui_touch_init (rt_device_t dev)
rt_uint8_t send;
rt_uint8_t recv_buffer[2];
struct rtgui_touch_device * touch_device = (struct rtgui_touch_device *)dev;
touch_init();
rt_kprintf("touch_init ...\n");
send = START | DIFFERENTIAL | POWER_MODE0;
@ -440,18 +440,18 @@ static void touch_thread_entry(void *parameter)
emouse.x = touch->x;
emouse.y = touch->y;
if(touch_down != RT_TRUE)
{
if(touch_down != RT_TRUE)
{
touch_int_cmd(RT_TRUE);
break;
}
}
if ((touch->calibrating == RT_TRUE) && (touch->calibration_func != RT_NULL))
{
/* 触摸校准处理 */
/* callback function */
touch->calibration_func(emouse.x, emouse.y);
}
else
{
@ -482,7 +482,7 @@ static void touch_thread_entry(void *parameter)
/* calculation */
rtgui_touch_calculate();
/* send mouse event */
emouse.parent.type = RTGUI_EVENT_MOUSE_BUTTON;
emouse.parent.sender = RT_NULL;
@ -532,7 +532,7 @@ static void touch_thread_entry(void *parameter)
rt_err_t rtgui_touch_hw_init(const char * spi_device_name)
{
rt_uint32_t arg[2];
rt_uint32_t arg[2];
struct rt_device * spi_device;
struct rt_thread * touch_thread;
rt_err_t err;
@ -550,12 +550,12 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name)
rt_kprintf("Open spi1 failed %08X, exit thread....\n", err);
return;
}
/* config spi */
{
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MODE_0;
cfg.mode = RT_SPI_MODE_0;
cfg.max_hz = 200 * 1000; /* 200K */
rt_spi_configure((struct rt_spi_device *)spi_device, &cfg);
}
@ -573,7 +573,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name)
touch->min_x = MIN_X_DEFAULT;
touch->max_x = MAX_X_DEFAULT;
touch->min_y = MIN_Y_DEFAULT;
touch->min_y = MIN_Y_DEFAULT;
touch->max_y = MAX_Y_DEFAULT;
/* init device structure */
@ -584,7 +584,7 @@ rt_err_t rtgui_touch_hw_init(const char * spi_device_name)
/* register touch device to RT-Thread */
rt_device_register(&(touch->parent), "touch", RT_DEVICE_FLAG_RDWR);
touch_thread = rt_thread_create("touch_thread",
touch_thread_entry, RT_NULL,

14
bsp/loongson/ls1cdev/drivers/touch.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -10,20 +10,20 @@
#ifndef __TOUCH_H__
#define __TOUCH_H__
#define RT_TOUCH_NORMAL 0
#define RT_TOUCH_CALIBRATION_DATA 1
#define RT_TOUCH_CALIBRATION 2
#define RT_TOUCH_NORMAL 0
#define RT_TOUCH_CALIBRATION_DATA 1
#define RT_TOUCH_CALIBRATION 2
//#define SAVE_CALIBRATION
rt_uint16_t touch_read_x(void);
rt_uint16_t touch_read_y(void);
void touch_config(void);
rt_err_t rtgui_touch_hw_init(const char * spi_device_name);
#endif

2
bsp/loongson/ls2kdev/drivers/drv_rtc.c
View File

@ -128,7 +128,6 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
hw_rtc = dev->user_data;
t = (time_t *)args;
time = *gmtime(t);
rtctm.sys_toyread0 = hw_rtc->sys_toyread0;
rtctm.sys_toyread1 = hw_rtc->sys_toyread1;
@ -141,6 +140,7 @@ static rt_err_t rt_rtc_ioctl(rt_device_t dev, int cmd, void *args)
*t = timegm(&tmptime);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
gmtime_r(t, &time);
tmptime.tm_hour = time.tm_hour;
tmptime.tm_min = time.tm_min;
tmptime.tm_sec = time.tm_sec;

20
bsp/loongson/ls2kdev/drivers/drv_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -18,15 +18,15 @@
#include "drv_uart.h"
#define TRUE 1
#define FALSE 0
const struct serial_configure config_uart0 = {
BAUD_RATE_115200, /* 921600 bits/s */
DATA_BITS_8, /* 8 databits */
STOP_BITS_1, /* 1 stopbit */
PARITY_NONE, /* No parity */
BIT_ORDER_LSB, /* LSB first sent */
NRZ_NORMAL, /* Normal mode */
RT_SERIAL_RB_BUFSZ, /* Buffer size */
0
const struct serial_configure config_uart0 = {
BAUD_RATE_115200, /* 921600 bits/s */
DATA_BITS_8, /* 8 databits */
STOP_BITS_1, /* 1 stopbit */
PARITY_NONE, /* No parity */
BIT_ORDER_LSB, /* LSB first sent */
NRZ_NORMAL, /* Normal mode */
RT_SERIAL_RB_BUFSZ, /* Buffer size */
0
};
struct rt_uart_ls2k
{

2
bsp/loongson/ls2kdev/drivers/ls2k1000.h
View File

@ -38,7 +38,7 @@
#define PM1_STS HWREG32(PM1_BASE)
#define PM1_EN HWREG32(PM1_BASE + 0x04)
#define PM1_CNT HWREG32(PM1_BASE + 0x08)
/*
* Watch Dog Configuration Registers
*/

8
bsp/loongson/ls2kdev/drivers/net/mii.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -172,15 +172,15 @@
/* Which connector port. */
#define PORT_TP 0x00
#define PORT_AUI 0x01
#define PORT_MII 0x02
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
#define PORT_BNC 0x04
/* Which transceiver to use. */
#define XCVR_INTERNAL 0x00
#define XCVR_EXTERNAL 0x01
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY1 0x02
#define XCVR_DUMMY2 0x03
#define XCVR_DUMMY3 0x04
#define AUTONEG_DISABLE 0x00

414
bsp/loongson/ls2kdev/drivers/net/synopGMAC_Dev.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -9,8 +9,8 @@
* 2020-08-10 lizhirui porting to ls2k
*/
#define UNUSED 1
#define UNUSED 1
#ifndef SYNOP_GMAC_DEV_H
#define SYNOP_GMAC_DEV_H 1
@ -41,7 +41,7 @@
#ifdef GMAC_PHY_BASE
#define DEFAULT_PHY_BASE GMAC_PHY_BASE
#else
#define DEFAULT_PHY_BASE PHY16 //We use First Phy
#define DEFAULT_PHY_BASE PHY16 //We use First Phy
#endif
#define MACBASE 0x0000 // The Mac Base address offset is 0x0000
#define DMABASE 0x1000 // Dma base address starts with an offset 0x1000
@ -65,8 +65,8 @@ enum GMACPhyBase
#define ETHERNET_HEADER 14 //6 byte Dest addr, 6 byte Src addr, 2 byte length/type
#define ETHERNET_CRC 4 //Ethernet CRC
#define ETHERNET_EXTRA 2 //Only God knows about this?????
#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb
#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA
#define ETHERNET_PACKET_COPY 250 // Maximum length when received data is copied on to a new skb
#define ETHERNET_PACKET_EXTRA 18 // Preallocated length for the rx packets is MTU + ETHERNET_PACKET_EXTRA
#define VLAN_TAG 4 //optional 802.1q VLAN Tag
#define MIN_ETHERNET_PAYLOAD 46 //Minimum Ethernet payload size
#define MAX_ETHERNET_PAYLOAD 1500 //Maximum Ethernet payload size
@ -86,18 +86,18 @@ The descriptor is of 4 words, but our structrue contains 6 words where
last two words are to hold the virtual address of the network buffer pointers
for driver's use
From the GMAC core release 3.50a onwards, the Enhanced Descriptor structure got changed.
The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal
The descriptor (both transmit and receive) are of 8 words each rather the 4 words of normal
descriptor structure.
Whenever IEEE 1588 Timestamping is enabled TX/RX DESC6 provides the lower 32 bits of Timestamp value and
TX/RX DESC7 provides the upper 32 bits of Timestamp value
In addition to this whenever extended status bit is set (RX DESC0 bit 0), RX DESC4 contains the extended status information
*/
#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for
#define MODULO_INTERRUPT 1 // if it is set to 1, interrupt is available for all the descriptors or else interrupt is available only for
// descriptor whose index%MODULO_INTERRUPT is zero
#ifdef ENH_DESC_8W
typedef struct DmaDescStruct
{
typedef struct DmaDescStruct
{
u32 status; /* Status */
u32 length; /* Buffer 1 and Buffer 2 length */
u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */
@ -111,8 +111,8 @@ typedef struct DmaDescStruct
u64 data2; /* This holds virtual address of buffer2, not used by DMA */
} DmaDesc;
#else
typedef struct DmaDescStruct
{
typedef struct DmaDescStruct
{
u32 status; /* Status */
u32 length; /* Buffer 1 and Buffer 2 length */
u32 buffer1; /* Network Buffer 1 pointer (Dma-able) */
@ -122,7 +122,7 @@ typedef struct DmaDescStruct
u64 data2; /* This holds virtual address of buffer2, not used by DMA */
//u32 dummy1; //sw: for addr align
//u32 dummy2; //
//u32 dummy2; //
} DmaDesc;
#endif
@ -141,24 +141,24 @@ enum BufferMode
/* synopGMAC device data */
typedef struct synopGMACDeviceStruct
typedef struct synopGMACDeviceStruct
{
u64 MacBase; /* base address of MAC registers */
u64 DmaBase; /* base address of DMA registers */
u64 PhyBase; /* PHY device address on MII interface */
u32 Version; /* Gmac Revision version */
u32 Version; /* Gmac Revision version */
dma_addr_t TxDescDma; /* Dma-able address of first tx descriptor either in ring or chain mode, this is used by the GMAC device*/
dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
dma_addr_t RxDescDma; /* Dma-able address of first rx descriptor either in ring or chain mode, this is used by the GMAC device*/
DmaDesc *TxDesc; /* start address of TX descriptors ring or chain, this is used by the driver */
DmaDesc *RxDesc; /* start address of RX descriptors ring or chain, this is used by the driver */
u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/
u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/
u32 BusyTxDesc; /* Number of Tx Descriptors owned by DMA at any given time*/
u32 BusyRxDesc; /* Number of Rx Descriptors owned by DMA at any given time*/
u32 RxDescCount; /* number of rx descriptors in the tx descriptor queue/pool */
u32 TxDescCount; /* number of tx descriptors in the rx descriptor queue/pool */
u32 TxBusy; /* index of the tx descriptor owned by DMA, is obtained by synopGMAC_get_tx_qptr() */
u32 TxNext; /* index of the tx descriptor next available with driver, given to DMA by synopGMAC_set_tx_qptr() */
u32 RxBusy; /* index of the rx descriptor owned by DMA, obtained by synopGMAC_get_rx_qptr() */
@ -182,7 +182,7 @@ typedef struct synopGMACDeviceStruct
// u32 skb_array[RECEIVE_DESC_SIZE];
} synopGMACdevice;
/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
/* Below is "88E1011/88E1011S Integrated 10/100/1000 Gigabit Ethernet Transceiver"
* Register and their layouts. This Phy has been used in the Dot Aster GMAC Phy daughter.
* Since the Phy register map is standard, this map hardly changes to a different Ppy
*/
@ -206,7 +206,7 @@ enum MiiRegisters
PHY_EXT_PHY_SPC_CTRL = 0x0014, /*Extended Phy specific control*/
PHY_RX_ERR_COUNTER = 0x0015, /*Receive Error Counter*/
PHY_EXT_ADDR_CBL_DIAG = 0x0016, /*Extended address for cable diagnostic register*/
PHY_LED_CONTROL = 0x0018, /*LED Control*/
PHY_LED_CONTROL = 0x0018, /*LED Control*/
PHY_MAN_LED_OVERIDE = 0x0019, /*Manual LED override register*/
PHY_EXT_PHY_SPC_CTRL2 = 0x001a, /*Extended Phy specific control 2*/
PHY_EXT_PHY_SPC_STATUS = 0x001b, /*Extended Phy specific status*/
@ -217,15 +217,15 @@ enum MiiRegisters
*/
enum Mii_GEN_CTRL
{ /* Description bits R/W default value */
Mii_reset = 0x8000,
Mii_reset = 0x8000,
Mii_Speed_10 = 0x0000, /* 10 Mbps 6:13 RW */
Mii_Speed_100 = 0x2000, /* 100 Mbps 6:13 RW */
Mii_Speed_1000 = 0x0040, /* 1000 Mbit/s 6:13 RW */
Mii_Duplex = 0x0100, /* Full Duplex mode 8 RW */
Mii_Manual_Master_Config = 0x0800, /* Manual Master Config 11 RW */
Mii_Loopback = 0x4000, /* Enable Loop back 14 RW */
Mii_NoLoopback = 0x0000, /* Enable Loop back 14 RW */
};
@ -235,10 +235,10 @@ enum Mii_Phy_Status
Mii_phy_status_speed_10 = 0x0000,
Mii_phy_status_speed_100 = 0x4000,
Mii_phy_status_speed_1000 = 0x8000,
Mii_phy_status_full_duplex = 0x2000,
Mii_phy_status_half_duplex = 0x0000,
Mii_phy_status_link_up = 0x0400, //lyf:rtl 8211 phy
// Mii_phy_status_link_up = 0x0100, //sw: broadcom BCM5461 PHY
};
@ -279,7 +279,7 @@ enum Mii_Loop_Back
* For Pci based system address is BARx + GmacRegisterBase
* For any other system translation is done accordingly
**********************************************************/
enum GmacRegisters
enum GmacRegisters
{
GmacConfig = 0x0000, /* Mac config Register */
GmacFrameFilter = 0x0004, /* Mac frame filtering controls */
@ -289,14 +289,14 @@ enum GmacRegisters
GmacGmiiData = 0x0014, /* GMII data Register(ext. Phy) */
GmacFlowControl = 0x0018, /* Flow control Register */
GmacVlan = 0x001C, /* VLAN tag Register (IEEE 802.1Q) */
GmacVersion = 0x0020, /* GMAC Core Version Register */
GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */
GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */
GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */
GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */
GmacVersion = 0x0020, /* GMAC Core Version Register */
GmacWakeupAddr = 0x0028, /* GMAC wake-up frame filter adrress reg */
GmacPmtCtrlStatus = 0x002C, /* PMT control and status register */
GmacInterruptStatus = 0x0038, /* Mac Interrupt ststus register */
GmacInterruptMask = 0x003C, /* Mac Interrupt Mask register */
GmacAddr0High = 0x0040, /* Mac address0 high Register */
GmacAddr0Low = 0x0044, /* Mac address0 low Register */
GmacAddr1High = 0x0048, /* Mac address1 high Register */
@ -338,35 +338,35 @@ enum GmacRegisters
GmacTSHigh = 0x0708, /* 32 bit seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */
GmacTSLow = 0x070C, /* 32 bit nano seconds(MS) : only when IEEE 1588 time stamping without external timestamp input */
GmacTSHighUpdate = 0x0710, /* 32 bit seconds(MS) to be written/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */
GmacTSLowUpdate = 0x0714, /* 32 bit nano seconds(MS) to be writeen/added/subtracted : only when IEEE 1588 time stamping without external timestamp input */
GmacTSAddend = 0x0718, /* Used by Software to readjust the clock frequency linearly : only when IEEE 1588 time stamping without external timestamp input */
GmacTSTargetTimeHigh = 0x071C, /* 32 bit seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
GmacTSTargetTimeLow = 0x0720, /* 32 bit nano seconds(MS) to be compared with system time : only when IEEE 1588 time stamping without external timestamp input */
GmacTSHighWord = 0x0724, /* Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */
//GmacTSHighWordUpdate = 0x072C, /* Time Stamp Higher Word Update Register (Version 2 only); only lower 16 bits are valid */
GmacTSStatus = 0x0728, /* Time Stamp Status Register */
};
/**********************************************************
* GMAC Network interface registers
* This explains the Register's Layout
* FES is Read only by default and is enabled only when Tx
* FES is Read only by default and is enabled only when Tx
* Config Parameter is enabled for RGMII/SGMII interface
* during CoreKit Config.
* DM is Read only with value 1'b1 in Full duplex only Config
**********************************************************/
/* GmacConfig = 0x0000, Mac config Register Layout */
enum GmacConfigReg
{
enum GmacConfigReg
{
/* Bit description Bits R/W Reset value */
GmacWatchdog = 0x00800000,
GmacWatchdogDisable = 0x00800000, /* (WD)Disable watchdog timer on Rx 23 RW */
@ -379,7 +379,7 @@ enum GmacConfigReg
GmacFrameBurst = 0x00200000,
GmacFrameBurstEnable = 0x00200000, /* (BE)Enable frame bursting during Tx 21 RW */
GmacFrameBurstDisable = 0x00000000, /* Disable frame bursting 0 */
GmacJumboFrame = 0x00100000,
GmacJumboFrameEnable = 0x00100000, /* (JE)Enable jumbo frame for Tx 20 RW */
GmacJumboFrameDisable = 0x00000000, /* Disable jumbo frame 0 */
@ -392,19 +392,19 @@ enum GmacConfigReg
GmacInterFrameGap2 = 0x00020000, /* (IFG) Config2 - 80 bit times */
GmacInterFrameGap1 = 0x00010000, /* (IFG) Config1 - 88 bit times */
GmacInterFrameGap0 = 0x00000000, /* (IFG) Config0 - 96 bit times 000 */
GmacDisableCrs = 0x00010000,
GmacDisableCrs = 0x00010000,
GmacMiiGmii = 0x00008000,
GmacSelectMii = 0x00008000, /* (PS)Port Select-MII mode 15 RW */
GmacSelectGmii = 0x00000000, /* GMII mode 0 */
GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */
GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */
GmacFESpeed100 = 0x00004000, /*(FES)Fast Ethernet speed 100Mbps 14 RW */
GmacFESpeed10 = 0x00000000, /* 10Mbps 0 */
GmacRxOwn = 0x00002000,
GmacRxOwn = 0x00002000,
GmacDisableRxOwn = 0x00002000, /* (DO)Disable receive own packets 13 RW */
GmacEnableRxOwn = 0x00000000, /* Enable receive own packets 0 */
GmacLoopback = 0x00001000,
GmacLoopbackOn = 0x00001000, /* (LM)Loopback mode for GMII/MII 12 RW */
GmacLoopbackOff = 0x00000000, /* Normal mode 0 */
@ -419,13 +419,13 @@ enum GmacConfigReg
GmacRetryDisable = 0x00000200, /* (DR)Disable Retry 9 RW */
GmacRetryEnable = 0x00000000, /* Enable retransmission as per BL 0 */
GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */
GmacLinkDown = 0x00000100, /* Link Down 0 */
GmacLinkUp = 0x00000100, /* (LUD)Link UP 8 RW */
GmacLinkDown = 0x00000100, /* Link Down 0 */
GmacPadCrcStrip = 0x00000080,
GmacPadCrcStripEnable = 0x00000080, /* (ACS) Automatic Pad/Crc strip enable 7 RW */
GmacPadCrcStripDisable = 0x00000000, /* Automatic Pad/Crc stripping disable 0 */
GmacBackoffLimit = 0x00000060,
GmacBackoffLimit3 = 0x00000060, /* (BL)Back-off limit in HD mode 6:5 RW */
GmacBackoffLimit2 = 0x00000040, /* */
@ -435,7 +435,7 @@ enum GmacConfigReg
GmacDeferralCheck = 0x00000010,
GmacDeferralCheckEnable = 0x00000010, /* (DC)Deferral check enable in HD mode 4 RW */
GmacDeferralCheckDisable = 0x00000000, /* Deferral check disable 0 */
GmacTx = 0x00000008,
GmacTxEnable = 0x00000008, /* (TE)Transmitter enable 3 RW */
GmacTxDisable = 0x00000000, /* Transmitter disable 0 */
@ -446,7 +446,7 @@ enum GmacConfigReg
};
/* GmacFrameFilter = 0x0004, Mac frame filtering controls Register Layout*/
enum GmacFrameFilterReg
enum GmacFrameFilterReg
{
GmacFilter = 0x80000000,
GmacFilterOff = 0x80000000, /* (RA)Receive all incoming packets 31 RW */
@ -494,14 +494,14 @@ enum GmacFrameFilterReg
};
/*GmacGmiiAddr = 0x0010, GMII address Register(ext. Phy) Layout */
enum GmacGmiiAddrReg
enum GmacGmiiAddrReg
{
GmiiDevMask = 0x0000F800, /* (PA)GMII device address 15:11 RW 0x00 */
GmiiDevShift = 11,
GmiiRegMask = 0x000007C0, /* (GR)GMII register in selected Phy 10:6 RW 0x00 */
GmiiRegShift = 6,
GmiiCsrClkMask = 0x0000001C, /* CSR Clock bit Mask 4:2 */
GmiiCsrClk5 = 0x00000014, /* (CR)CSR Clock Range 250-300 MHz 4:2 RW 000 */
GmiiCsrClk4 = 0x00000010, /* 150-250 MHz */
@ -517,17 +517,17 @@ enum GmacGmiiAddrReg
};
/* GmacGmiiData = 0x0014, GMII data Register(ext. Phy) Layout */
enum GmacGmiiDataReg
enum GmacGmiiDataReg
{
GmiiDataMask = 0x0000FFFF, /* (GD)GMII Data 15:0 RW 0x0000 */
};
/*GmacFlowControl = 0x0018, Flow control Register Layout */
enum GmacFlowControlReg
{
enum GmacFlowControlReg
{
GmacPauseTimeMask = 0xFFFF0000, /* (PT) PAUSE TIME field in the control frame 31:16 RW 0x0000 */
GmacPauseTimeShift = 16,
GmacPauseLowThresh = 0x00000030,
GmacPauseLowThresh3 = 0x00000030, /* (PLT)thresh for pause tmr 256 slot time 5:4 RW */
GmacPauseLowThresh2 = 0x00000020, /* 144 slot time */
@ -550,11 +550,11 @@ enum GmacFlowControlReg
GmacSendPauseFrame = 0x00000001, /* (FCB/PBA)send pause frm/Apply back pressure 0 RW 0 */
};
/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */
/* GmacInterruptStatus = 0x0038, Mac Interrupt ststus register */
enum GmacInterruptStatusBitDefinition
{
GmacTSIntSts = 0x00000200, /* set if int generated due to TS (Read Time Stamp Status Register to know details)*/
GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */
GmacMmcRxChksumOffload = 0x00000080, /* set if int generated in MMC RX CHECKSUM OFFLOAD int register */
GmacMmcTxIntSts = 0x00000040, /* set if int generated in MMC TX Int register */
GmacMmcRxIntSts = 0x00000020, /* set if int generated in MMC RX Int register */
GmacMmcIntSts = 0x00000010, /* set if any of the above bit [7:5] is set */
@ -564,7 +564,7 @@ enum GmacInterruptStatusBitDefinition
GmacRgmiiIntSts = 0x00000001, /* set if any change in lnk status of RGMII interface */
};
/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */
/* GmacInterruptMask = 0x003C, Mac Interrupt Mask register */
enum GmacInterruptMaskBitDefinition
{
GmacTSIntMask = 0x00000200, /* when set disables the time stamp interrupt generation */
@ -579,7 +579,7 @@ enum GmacInterruptMaskBitDefinition
* For Pci based system address is BARx + GmaDmaBase
* For any other system translation is done accordingly
**********************************************************/
enum DmaRegisters
enum DmaRegisters
{
DmaBusMode = 0x0000, /* CSR0 - Bus Mode Register */
DmaTxPollDemand = 0x0004, /* CSR1 - Transmit Poll Demand Register */
@ -590,8 +590,8 @@ enum DmaRegisters
DmaControl = 0x0018, /* CSR6 - Dma Operation Mode Register */
DmaInterrupt = 0x001C, /* CSR7 - Interrupt enable */
DmaMissedFr = 0x0020, /* CSR8 - Missed Frame & Buffer overflow Counter */
DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */
DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */
DmaTxCurrDesc = 0x0048, /* - Current host Tx Desc Register */
DmaRxCurrDesc = 0x004C, /* - Current host Rx Desc Register */
DmaTxCurrAddr = 0x0050, /* CSR20 - Current host transmit buffer address */
DmaRxCurrAddr = 0x0054, /* CSR21 - Current host receive buffer address */
};
@ -601,19 +601,19 @@ enum DmaRegisters
**********************************************************/
/*DmaBusMode = 0x0000, CSR0 - Bus Mode */
enum DmaBusModeReg
enum DmaBusModeReg
{ /* Bit description Bits R/W Reset value */
DmaFixedBurstEnable = 0x00010000, /* (FB)Fixed Burst SINGLE, INCR4, INCR8 or INCR16 16 RW */
DmaFixedBurstDisable = 0x00000000, /* SINGLE, INCR 0 */
DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */
DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */
DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */
DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */
DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */
DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */
DmaTxPriorityRatio11 = 0x00000000, /* (PR)TX:RX DMA priority ratio 1:1 15:14 RW 00 */
DmaTxPriorityRatio21 = 0x00004000, /* (PR)TX:RX DMA priority ratio 2:1 */
DmaTxPriorityRatio31 = 0x00008000, /* (PR)TX:RX DMA priority ratio 3:1 */
DmaTxPriorityRatio41 = 0x0000C000, /* (PR)TX:RX DMA priority ratio 4:1 */
DmaBurstLengthx8 = 0x01000000, /* When set mutiplies the PBL by 8 24 RW 0 */
DmaBurstLength256 = 0x01002000, /*(DmaBurstLengthx8 | DmaBurstLength32) = 256 [24]:13:8 */
DmaBurstLength128 = 0x01001000, /*(DmaBurstLengthx8 | DmaBurstLength16) = 128 [24]:13:8 */
DmaBurstLength64 = 0x01000800, /*(DmaBurstLengthx8 | DmaBurstLength8) = 64 [24]:13:8 */
DmaBurstLength32 = 0x00002000, /* (PBL) programmable Dma burst length = 32 13:8 RW */
@ -634,19 +634,19 @@ enum DmaBusModeReg
DmaDescriptorSkip1 = 0x00000004, /* */
DmaDescriptorSkip0 = 0x00000000, /* 0x00 */
DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */
DmaArbitPr = 0x00000002, /* Rx has priority over Tx */
DmaArbitRr = 0x00000000, /* (DA) DMA RR arbitration 1 RW 0 */
DmaArbitPr = 0x00000002, /* Rx has priority over Tx */
DmaResetOn = 0x00000001, /* (SWR)Software Reset DMA engine 0 RW */
DmaResetOff = 0x00000000, /* 0 */
};
/*DmaStatus = 0x0014, CSR5 - Dma status Register */
enum DmaStatusReg
{
/*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/
GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */
GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */
enum DmaStatusReg
{
/*Bit 28 27 and 26 indicate whether the interrupt due to PMT GMACMMC or GMAC LINE Remaining bits are DMA interrupts*/
GmacPmtIntr = 0x10000000, /* (GPI)Gmac subsystem interrupt 28 RO 0 */
GmacMmcIntr = 0x08000000, /* (GMI)Gmac MMC subsystem interrupt 27 RO 0 */
GmacLineIntfIntr = 0x04000000, /* Line interface interrupt 26 RO 0 */
DmaErrorBit2 = 0x02000000, /* (EB)Error bits 0-data buffer, 1-desc. access 25 RO 0 */
@ -688,52 +688,52 @@ enum DmaStatusReg
};
/*DmaControl = 0x0018, CSR6 - Dma Operation Mode Register */
enum DmaControlReg
{
enum DmaControlReg
{
DmaDisableDropTcpCs = 0x04000000, /* (DT) Dis. drop. of tcp/ip CS error frames 26 RW 0 */
DmaStoreAndForward = 0x02200000, /* (SF)Store and forward 21 RW 0 */
DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */
DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */
DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */
DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */
DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */
DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */
DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */
DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */
DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */
DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */
DmaFlushTxFifo = 0x00100000, /* (FTF)Tx FIFO controller is reset to default 20 RW 0 */
DmaTxThreshCtrl = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16:14 RW */
DmaTxThreshCtrl16 = 0x0001C000, /* (TTC)Controls thre Threh of MTL tx Fifo 16 16:14 RW */
DmaTxThreshCtrl24 = 0x00018000, /* (TTC)Controls thre Threh of MTL tx Fifo 24 16:14 RW */
DmaTxThreshCtrl32 = 0x00014000, /* (TTC)Controls thre Threh of MTL tx Fifo 32 16:14 RW */
DmaTxThreshCtrl40 = 0x00010000, /* (TTC)Controls thre Threh of MTL tx Fifo 40 16:14 RW */
DmaTxThreshCtrl256 = 0x0000c000, /* (TTC)Controls thre Threh of MTL tx Fifo 256 16:14 RW */
DmaTxThreshCtrl192 = 0x00008000, /* (TTC)Controls thre Threh of MTL tx Fifo 192 16:14 RW */
DmaTxThreshCtrl128 = 0x00004000, /* (TTC)Controls thre Threh of MTL tx Fifo 128 16:14 RW */
DmaTxThreshCtrl64 = 0x00000000, /* (TTC)Controls thre Threh of MTL tx Fifo 64 16:14 RW 000 */
DmaTxStart = 0x00002000, /* (ST)Start/Stop transmission 13 RW 0 */
DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */
DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */
DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */
DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */
DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */
DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */
DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */
DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */
DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */
DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */
DmaRxFlowCtrlDeact = 0x00401800, /* (RFD)Rx flow control deact. threhold [22]:12:11 RW */
DmaRxFlowCtrlDeact1K = 0x00000000, /* (RFD)Rx flow control deact. threhold (1kbytes) [22]:12:11 RW 00 */
DmaRxFlowCtrlDeact2K = 0x00000800, /* (RFD)Rx flow control deact. threhold (2kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact3K = 0x00001000, /* (RFD)Rx flow control deact. threhold (3kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact4K = 0x00001800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact5K = 0x00400000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact6K = 0x00400800, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlDeact7K = 0x00401000, /* (RFD)Rx flow control deact. threhold (4kbytes) [22]:12:11 RW */
DmaRxFlowCtrlAct = 0x00800600, /* (RFA)Rx flow control Act. threhold [23]:10:09 RW */
DmaRxFlowCtrlAct1K = 0x00000000, /* (RFA)Rx flow control Act. threhold (1kbytes) [23]:10:09 RW 00 */
DmaRxFlowCtrlAct2K = 0x00000200, /* (RFA)Rx flow control Act. threhold (2kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct3K = 0x00000400, /* (RFA)Rx flow control Act. threhold (3kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct4K = 0x00000600, /* (RFA)Rx flow control Act. threhold (4kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct5K = 0x00800000, /* (RFA)Rx flow control Act. threhold (5kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct6K = 0x00800200, /* (RFA)Rx flow control Act. threhold (6kbytes) [23]:10:09 RW */
DmaRxFlowCtrlAct7K = 0x00800400, /* (RFA)Rx flow control Act. threhold (7kbytes) [23]:10:09 RW */
DmaRxThreshCtrl = 0x00000018, /* (RTC)Controls thre Threh of MTL rx Fifo 4:3 RW */
DmaRxThreshCtrl64 = 0x00000000, /* (RTC)Controls thre Threh of MTL tx Fifo 64 4:3 RW */
DmaRxThreshCtrl32 = 0x00000008, /* (RTC)Controls thre Threh of MTL tx Fifo 32 4:3 RW */
DmaRxThreshCtrl96 = 0x00000010, /* (RTC)Controls thre Threh of MTL tx Fifo 96 4:3 RW */
DmaRxThreshCtrl128 = 0x00000018, /* (RTC)Controls thre Threh of MTL tx Fifo 128 4:3 RW */
DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */
DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */
DmaEnHwFlowCtrl = 0x00000100, /* (EFC)Enable HW flow control 8 RW */
DmaDisHwFlowCtrl = 0x00000000, /* Disable HW flow control 0 */
DmaFwdErrorFrames = 0x00000080, /* (FEF)Forward error frames 7 RW 0 */
DmaFwdUnderSzFrames = 0x00000040, /* (FUF)Forward undersize frames 6 RW 0 */
DmaTxSecondFrame = 0x00000004, /* (OSF)Operate on second frame 4 RW 0 */
@ -743,7 +743,7 @@ enum DmaControlReg
/*DmaInterrupt = 0x001C, CSR7 - Interrupt enable Register Layout */
enum DmaInterruptReg
{
{
DmaIeNormal = DmaIntNormal , /* Normal interrupt enable RW 0 */
DmaIeAbnormal = DmaIntAbnormal , /* Abnormal interrupt enable RW 0 */
@ -771,12 +771,12 @@ enum DmaInterruptReg
#ifdef ENH_DESC
/*
**********Enhanced Descritpor structure to support 8K buffer per buffer ****************************
DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address
DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
32 bit Data bus is as shown below
Similarly
DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address
DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
32 bit Data bus is as shown below
Similarly
DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address
DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
32 bit Data bus is as shown below
@ -807,7 +807,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */
DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */
DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */
DescFrameLengthShift = 16,
@ -827,10 +827,10 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */
DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */
DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */
// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
// DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */
DescRxEXTsts = 0x00000001, /* Extended Status Available (RDES4) 0 */
DescTxIntEnable = 0x40000000, /* (IC)Tx - interrupt on completion 30 */
DescTxLast = 0x20000000, /* (LS)Tx - Last segment of the frame 29 */
DescTxFirst = 0x10000000, /* (FS)Tx - First segment of the frame 28 */
@ -845,12 +845,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
TxDescEndOfRing = 0x00200000, /* (TER)End of descriptors ring 21 */
TxDescChain = 0x00100000, /* (TCH)Second buffer address is chain address 20 */
DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */
DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
DescRxTSavail = 0x00000080, /* Time stamp available 7 */
DescRxTSavail = 0x00000080, /* Time stamp available 7 */
DescRxFrameType = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */
@ -862,10 +862,10 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */
DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */
DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */
DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */
DescTxCollShift = 3,
DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */
DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */
DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */
@ -875,7 +875,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 |
--------------------------------------------------------------------
*/
// DmaDescriptorLength length word of DMA descriptor
// DmaDescriptorLength length word of DMA descriptor
RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */
RxDescEndOfRing = 0x00008000, /* (TER)End of descriptors ring 15 */
RxDescChain = 0x00004000, /* (TCH)Second buffer address is chain address 14 */
@ -904,12 +904,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescRxPtpPdelayRespFP = 0x00000700, /* 0111 => Pdealy_Resp_Follow_Up (in P to P trans clk) or Signaling in Ord and Bound clk */
DescRxPtpIPV6 = 0x00000080, /* Received Packet is in IPV6 Packet 7 */
DescRxPtpIPV4 = 0x00000040, /* Received Packet is in IPV4 Packet 6 */
DescRxChkSumBypass = 0x00000020, /* When set indicates checksum offload engine 5
is bypassed */
DescRxIpPayloadError = 0x00000010, /* When set indicates 16bit IP payload CS is in error 4 */
DescRxIpHeaderError = 0x00000008, /* When set indicates 16bit IPV4 header CS is in 3
error or IP datagram version is not consistent
error or IP datagram version is not consistent
with Ethernet type value */
DescRxIpPayloadType = 0x00000007, /* Indicate the type of payload encapsulated 2:0
in IPdatagram processed by COE (Rx) */
@ -924,11 +924,11 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
/*
********** Default Descritpor structure ****************************
DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address
DmaRxBaseAddr = 0x000C, CSR3 - Receive Descriptor list base address
DmaRxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
32 bit Data bus is as shown below
32 bit Data bus is as shown below
Similarly
Similarly
DmaTxBaseAddr = 0x0010, CSR4 - Transmit Descriptor list base address
DmaTxBaseAddr is the pointer to the first Rx Descriptors. the Descriptor format in Little endian with a
32 bit Data bus is as shown below
@ -947,7 +947,7 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescOwnByDma = 0x80000000, /* (OWN)Descriptor is owned by DMA engine 31 RW */
DescDAFilterFail = 0x40000000, /* (AFM)Rx - DA Filter Fail for the rx frame 30 */
DescFrameLengthMask = 0x3FFF0000, /* (FL)Receive descriptor frame length 29:16 */
DescFrameLengthShift = 16,
@ -967,16 +967,16 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescRxMiiError = 0x00000008, /* (RE)Rx - error reported by MII interface 3 */
DescRxDribbling = 0x00000004, /* (DE)Rx - frame contains non int multiple of 8 bits 2 */
DescRxCrc = 0x00000002, /* (CE)Rx - CRC error 1 */
DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
DescRxMacMatch = 0x00000001, /* (RX MAC Address) Rx mac address reg(1 to 15)match 0 */
//Rx Descriptor Checksum Offload engine (type 2) encoding
//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */
//DescRxPayChkError = 0x00000001, /* () Rx - Rx Payload Checksum Error 0 */
//DescRxIpv4ChkError = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
DescRxChkBit0 = 0x00000001, /*() Rx - Rx Payload Checksum Error 0 */
DescRxChkBit7 = 0x00000080, /* (IPC CS ERROR)Rx - Ipv4 header checksum error 7 */
DescRxChkBit5 = 0x00000020, /* (FT)Rx - Frame type - Ethernet, otherwise 802.3 5 */
DescTxIpv4ChkError = 0x00010000, /* (IHE) Tx Ip header error 16 */
DescTxTimeout = 0x00004000, /* (JT)Tx - Transmit jabber timeout 14 */
DescTxFrameFlushed = 0x00002000, /* (FF)Tx - DMA/MTL flushed the frame due to SW flush 13 */
@ -986,21 +986,21 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
DescTxLateCollision = 0x00000200, /* (LC)Tx - transmission aborted due to collision 9 */
DescTxExcCollisions = 0x00000100, /* (EC)Tx - transmission aborted after 16 collisions 8 */
DescTxVLANFrame = 0x00000080, /* (VF)Tx - VLAN-type frame 7 */
DescTxCollMask = 0x00000078, /* (CC)Tx - Collision count 6:3 */
DescTxCollShift = 3,
DescTxExcDeferral = 0x00000004, /* (ED)Tx - excessive deferral 2 */
DescTxUnderflow = 0x00000002, /* (UF)Tx - late data arrival from the memory 1 */
DescTxDeferred = 0x00000001, /* (DB)Tx - frame transmision deferred 0 */
/*
This explains the RDES1/TDES1 bits layout
--------------------------------------------------------------------
RDES1/TDES1 | Control Bits | Byte Count Buffer 2 | Byte Count Buffer 1 |
--------------------------------------------------------------------
*/
*/
//DmaDescriptorLength length word of DMA descriptor
DescTxIntEnable = 0x80000000, /* (IC)Tx - interrupt on completion 31 */
DescTxLast = 0x40000000, /* (LS)Tx - Last segment of the frame 30 */
@ -1010,12 +1010,12 @@ enum DmaDescriptorStatus /* status word of DMA descriptor */
RxDisIntCompl = 0x80000000, /* (Disable Rx int on completion) 31 */
RxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */
RxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */
DescTxDisablePadd = 0x00800000, /* (DP)disable padding, added by - reyaz 23 */
TxDescEndOfRing = 0x02000000, /* (TER)End of descriptors ring */
TxDescChain = 0x01000000, /* (TCH)Second buffer address is chain address 24 */
DescSize2Mask = 0x003FF800, /* (TBS2) Buffer 2 size 21:11 */
DescSize2Shift = 11,
DescSize1Mask = 0x000007FF, /* (TBS1) Buffer 1 size 10:0 */
@ -1045,7 +1045,7 @@ enum RxDescCOEEncode
/**********************************************************
* DMA engine interrupt handling functions
**********************************************************/
enum synopGMACDmaIntEnum /* Intrerrupt types */
{
synopGMACDmaRxNormal = 0x01, /* normal receiver interrupt */
@ -1068,7 +1068,7 @@ enum InitialRegisters
| GmacSelectGmii | GmacEnableRxOwn | GmacLoopbackOff
| GmacFullDuplex | GmacRetryEnable | GmacPadCrcStripDisable
| GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
/* Full-duplex mode with perfect filter on */
GmacConfigInitFdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
| GmacSelectMii | GmacEnableRxOwn | GmacLoopbackOff
@ -1076,13 +1076,13 @@ enum InitialRegisters
| GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
/* Full-duplex mode */
// CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast
// Hash filter.
// CHANGED: Pass control config, dest addr filter normal, added source address filter, multicast & unicast
// Hash filter.
/* = GmacFilterOff | GmacPassControlOff | GmacBroadcastEnable */
GmacFrameFilterInitFdx = GmacFilterOn | GmacPassControl0 | GmacBroadcastEnable | GmacSrcAddrFilterDisable
| GmacMulticastFilterOn | GmacDestAddrFilterNor | GmacMcastHashFilterOff
| GmacPromiscuousModeOff | GmacUcastHashFilterOff,
/* Full-duplex mode */
GmacFlowControlInitFdx = GmacUnicastPauseFrameOff | GmacRxFlowControlEnable | GmacTxFlowControlEnable,
@ -1091,17 +1091,17 @@ enum InitialRegisters
/* Half-duplex mode with perfect filter on */
// CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip,
// CHANGED: Removed Endian configuration, added single bit config for PAD/CRC strip,
/*| GmacSelectMii | GmacLittleEndian | GmacDisableRxOwn | GmacLoopbackOff*/
GmacConfigInitHdx1000 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
| GmacSelectGmii | GmacDisableRxOwn | GmacLoopbackOff
| GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
| GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
| GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
/* Half-duplex mode with perfect filter on */
GmacConfigInitHdx110 = GmacWatchdogEnable | GmacJabberEnable | GmacFrameBurstEnable | GmacJumboFrameDisable
| GmacSelectMii | GmacDisableRxOwn | GmacLoopbackOff
| GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
| GmacHalfDuplex | GmacRetryEnable | GmacPadCrcStripDisable
| GmacBackoffLimit0 | GmacDeferralCheckDisable | GmacTxEnable | GmacRxEnable,
/* Half-duplex mode */
@ -1121,13 +1121,13 @@ enum InitialRegisters
DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip1 | DmaResetOff,
// DmaBusModeInit = DmaFixedBurstEnable | DmaBurstLength8 | DmaDescriptorSkip4 | DmaResetOff,
/* 1000 Mb/s mode */
DmaControlInit1000 = DmaStoreAndForward,// | DmaTxSecondFrame ,
/* 100 Mb/s mode */
DmaControlInit100 = DmaStoreAndForward,
/* 10 Mb/s mode */
DmaControlInit10 = DmaStoreAndForward,
@ -1167,14 +1167,14 @@ enum MMC_TX
GmacMmcTxFrameCountGb = 0x0118, /*Frames Tx excl. of retried frames (Good or Bad) */
GmacMmcTxBcFramesG = 0x011C, /*Broadcast Frames Tx (Good) */
GmacMmcTxMcFramesG = 0x0120, /*Multicast Frames Tx (Good) */
GmacMmcTx64OctetsGb = 0x0124, /*Tx with len 64 bytes excl. of pre and retried (Good or Bad) */
GmacMmcTx65To127OctetsGb = 0x0128, /*Tx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */
GmacMmcTx128To255OctetsGb = 0x012C, /*Tx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */
GmacMmcTx256To511OctetsGb = 0x0130, /*Tx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */
GmacMmcTx512To1023OctetsGb = 0x0134, /*Tx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */
GmacMmcTx1024ToMaxOctetsGb = 0x0138, /*Tx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */
GmacMmcTxUcFramesGb = 0x013C, /*Unicast Frames Tx (Good or Bad) */
GmacMmcTxMcFramesGb = 0x0140, /*Multicast Frames Tx (Good and Bad) */
GmacMmcTxBcFramesGb = 0x0144, /*Broadcast Frames Tx (Good and Bad) */
@ -1188,7 +1188,7 @@ enum MMC_TX
GmacMmcTxOctetCountG = 0x0164, /*Bytes Tx excl. of preamble and retried bytes (Good) */
GmacMmcTxFrameCountG = 0x0168, /*Frames Tx (Good) */
GmacMmcTxExessDef = 0x016C, /*Frames aborted due to excessive deferral errors (deferred for more than 2 max-sized frame times)*/
GmacMmcTxPauseFrames = 0x0170, /*Number of good pause frames Tx. */
GmacMmcTxVlanFramesG = 0x0174, /*Number of good Vlan frames Tx excl. retried frames */
};
@ -1199,29 +1199,29 @@ enum MMC_RX
GmacMmcRxOctetCountG = 0x0188, /*Bytes Rx excl. of preamble and retried bytes (Good) */
GmacMmcRxBcFramesG = 0x018C, /*Broadcast Frames Rx (Good) */
GmacMmcRxMcFramesG = 0x0190, /*Multicast Frames Rx (Good) */
GmacMmcRxCrcError = 0x0194, /*Number of frames received with CRC error */
GmacMmcRxAlignError = 0x0198, /*Number of frames received with alignment (dribble) error. Only in 10/100mode */
GmacMmcRxRuntError = 0x019C, /*Number of frames received with runt (<64 bytes and CRC error) error */
GmacMmcRxJabberError = 0x01A0, /*Number of frames rx with jabber (>1518/1522 or >9018/9022 and CRC) */
GmacMmcRxUnderSizeG = 0x01A4, /*Number of frames received with <64 bytes without any error */
GmacMmcRxOverSizeG = 0x01A8, /*Number of frames received with >1518/1522 bytes without any error */
GmacMmcRx64OctetsGb = 0x01AC, /*Rx with len 64 bytes excl. of pre and retried (Good or Bad) */
GmacMmcRx65To127OctetsGb = 0x01B0, /*Rx with len >64 bytes <=127 excl. of pre and retried (Good or Bad) */
GmacMmcRx128To255OctetsGb = 0x01B4, /*Rx with len >128 bytes <=255 excl. of pre and retried (Good or Bad) */
GmacMmcRx256To511OctetsGb = 0x01B8, /*Rx with len >256 bytes <=511 excl. of pre and retried (Good or Bad) */
GmacMmcRx512To1023OctetsGb = 0x01BC, /*Rx with len >512 bytes <=1023 excl. of pre and retried (Good or Bad) */
GmacMmcRx1024ToMaxOctetsGb = 0x01C0, /*Rx with len >1024 bytes <=MaxSize excl. of pre and retried (Good or Bad) */
GmacMmcRxUcFramesG = 0x01C4, /*Unicast Frames Rx (Good) */
GmacMmcRxLengthError = 0x01C8, /*Number of frames received with Length type field != frame size */
GmacMmcRxOutOfRangeType = 0x01CC, /*Number of frames received with length field != valid frame size */
GmacMmcRxPauseFrames = 0x01D0, /*Number of good pause frames Rx. */
GmacMmcRxFifoOverFlow = 0x01D4, /*Number of missed rx frames due to FIFO overflow */
GmacMmcRxVlanFramesGb = 0x01D8, /*Number of good Vlan frames Rx */
GmacMmcRxWatchdobError = 0x01DC, /*Number of frames rx with error due to watchdog timeout error */
};
@ -1229,42 +1229,42 @@ enum MMC_IP_RELATED
{
GmacMmcRxIpcIntrMask = 0x0200, /*Maintains the mask for interrupt generated from rx IPC statistic counters */
GmacMmcRxIpcIntr = 0x0208, /*Maintains the interrupt that rx IPC statistic counters generate */
GmacMmcRxIpV4FramesG = 0x0210, /*Good IPV4 datagrams received */
GmacMmcRxIpV4HdrErrFrames = 0x0214, /*Number of IPV4 datagrams received with header errors */
GmacMmcRxIpV4NoPayFrames = 0x0218, /*Number of IPV4 datagrams received which didnot have TCP/UDP/ICMP payload */
GmacMmcRxIpV4FragFrames = 0x021C, /*Number of IPV4 datagrams received with fragmentation */
GmacMmcRxIpV4UdpChkDsblFrames = 0x0220, /*Number of IPV4 datagrams received that had a UDP payload checksum disabled */
GmacMmcRxIpV6FramesG = 0x0224, /*Good IPV6 datagrams received */
GmacMmcRxIpV6HdrErrFrames = 0x0228, /*Number of IPV6 datagrams received with header errors */
GmacMmcRxIpV6NoPayFrames = 0x022C, /*Number of IPV6 datagrams received which didnot have TCP/UDP/ICMP payload */
GmacMmcRxUdpFramesG = 0x0230, /*Number of good IP datagrams with good UDP payload */
GmacMmcRxUdpErrorFrames = 0x0234, /*Number of good IP datagrams with UDP payload having checksum error */
GmacMmcRxTcpFramesG = 0x0238, /*Number of good IP datagrams with good TDP payload */
GmacMmcRxTcpErrorFrames = 0x023C, /*Number of good IP datagrams with TCP payload having checksum error */
GmacMmcRxIcmpFramesG = 0x0240, /*Number of good IP datagrams with good Icmp payload */
GmacMmcRxIcmpErrorFrames = 0x0244, /*Number of good IP datagrams with Icmp payload having checksum error */
GmacMmcRxIpV4OctetsG = 0x0250, /*Good IPV4 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */
GmacMmcRxIpV4HdrErrorOctets = 0x0254, /*Number of bytes in IPV4 datagram with header errors */
GmacMmcRxIpV4NoPayOctets = 0x0258, /*Number of bytes in IPV4 datagram with no TCP/UDP/ICMP payload */
GmacMmcRxIpV4FragOctets = 0x025C, /*Number of bytes received in fragmented IPV4 datagrams */
GmacMmcRxIpV4UdpChkDsblOctets = 0x0260, /*Number of bytes received in UDP segment that had UDP checksum disabled */
GmacMmcRxIpV6OctetsG = 0x0264, /*Good IPV6 datagrams received excl. Ethernet hdr,FCS,Pad,Ip Pad bytes */
GmacMmcRxIpV6HdrErrorOctets = 0x0268, /*Number of bytes in IPV6 datagram with header errors */
GmacMmcRxIpV6NoPayOctets = 0x026C, /*Number of bytes in IPV6 datagram with no TCP/UDP/ICMP payload */
GmacMmcRxUdpOctetsG = 0x0270, /*Number of bytes in IP datagrams with good UDP payload */
GmacMmcRxUdpErrorOctets = 0x0274, /*Number of bytes in IP datagrams with UDP payload having checksum error */
GmacMmcRxTcpOctetsG = 0x0278, /*Number of bytes in IP datagrams with good TDP payload */
GmacMmcRxTcpErrorOctets = 0x027C, /*Number of bytes in IP datagrams with TCP payload having checksum error */
GmacMmcRxIcmpOctetsG = 0x0280, /*Number of bytes in IP datagrams with good Icmp payload */
GmacMmcRxIcmpErrorOctets = 0x0284, /*Number of bytes in IP datagrams with Icmp payload having checksum error */
};
@ -1338,7 +1338,7 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
/**********************************************************
* Power Management (PMT) Block
* Power Management (PMT) Block
**********************************************************/
/**
@ -1348,10 +1348,10 @@ enum MMC_TX_INTR_MASK_AND_STATUS_BIT_DESCRIPTIONS
* These enable are in PMT control and Status register and are programmed by apllication.
*
* When power down mode is enabled in PMT, all rx frames are dropped by the core. Core comes
* out of power down mode only when either Magic packe tor a Remote wake-up frame is received
* out of power down mode only when either Magic packe tor a Remote wake-up frame is received
* and the corresponding detection is enabled.
*
* Driver need not be modified to support this feature. Only Api to put the device in to power
* Driver need not be modified to support this feature. Only Api to put the device in to power
* down mode is sufficient
*/
@ -1369,7 +1369,7 @@ enum GmacPmtCtrlStatusBitDefinition
};
/**********************************************************
* IEEE 1588-2008 Precision Time Protocol (PTP) Support
* IEEE 1588-2008 Precision Time Protocol (PTP) Support
**********************************************************/
enum PTPMessageType
{
@ -1385,10 +1385,10 @@ enum PTPMessageType
Management = 0xD,
};
typedef struct TimeStampStruct
{
typedef struct TimeStampStruct
{
u32 TSversion; /* PTP Version 1 or PTP version2 */
u32 TSmessagetype; /* Message type associated with this time stamp */
u32 TSmessagetype; /* Message type associated with this time stamp */
u16 TShighest16; /* Highest 16 bit time stamp value, Valid onley when ADV_TIME_HIGH_WORD configured in corekit */
u32 TSupper32; /* Most significant 32 bit time stamp value */
@ -1411,7 +1411,7 @@ typedef struct TimeStampStruct
enum GmacTSControlReg
{
GmacTSENMACADDR = 0x00040000, /* Enable Mac Addr for PTP filtering 18 RW 0 */
GmacTSCLKTYPE = 0x00030000, /* Select the type of clock node 17:16 RW 00 */
/*
TSCLKTYPE TSMSTRENA TSEVNTENA Messages for wihich TS snapshot is taken
@ -1421,7 +1421,7 @@ enum GmacTSControlReg
10 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP
10 NA 1 SYNC, FOLLOW_UP
11 NA 0 SYNC, FOLLOW_UP, DELAY_REQ, DELAY_RESP, PDELAY_REQ, PDELAY_RESP
11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP
11 NA 1 SYNC, PDELAY_REQ, PDELAY_RESP
*/
GmacTSOrdClk = 0x00000000, /* 00=> Ordinary clock*/
GmacTSBouClk = 0x00010000, /* 01=> Boundary clock*/
@ -1442,7 +1442,7 @@ enum GmacTSControlReg
GmacTSADDREG = 0x00000020, /* Addend Register Update 5 RW_SC 0 */
GmacTSUPDT = 0x00000008, /* Time Stamp Update 3 RW_SC 0 */
GmacTSINT = 0x00000004, /* Time Atamp Initialize 2 RW_SC 0 */
GmacTSTRIG = 0x00000010, /* Time stamp interrupt Trigger Enable 4 RW_SC 0 */
GmacTSCFUPDT = 0x00000002, /* Time Stamp Fine/Coarse 1 RW 0 */
@ -1474,7 +1474,7 @@ enum GmacTSLowReg
};
/* GmacTSHighWord = 0x0724, Time Stamp Higher Word Register (Version 2 only); only lower 16 bits are valid */
enum GmacTSHighWordReg
enum GmacTSHighWordReg
{
GmacTSHighWordMask = 0x0000FFFF, /* Time Stamp Higher work register has only lower 16 bits valid */
};
@ -1483,7 +1483,7 @@ enum GmacTSStatusReg
{
GmacTSTargTimeReached = 0x00000002, /* Time Stamp Target Time Reached 1 RO 0 */
GmacTSSecondsOverflow = 0x00000001, /* Time Stamp Seconds Overflow 0 RO 0 */
};
};
/**********************************************************
* Time stamp related functions
@ -1510,7 +1510,7 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev); //
void synopGMAC_TS_pkt_snoop_ver2(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
void synopGMAC_TS_pkt_snoop_ver1(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev);
void synopGMAC_TS_digital_rollover_enable(synopGMACdevice *gmacdev);
void synopGMAC_TS_binary_rollover_enable(synopGMACdevice *gmacdev);
void synopGMAC_TS_all_frames_enable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
void synopGMAC_TS_all_frames_disable(synopGMACdevice *gmacdev); // Only for "Advanced Time Stamp"
@ -1523,7 +1523,7 @@ void synopGMAC_TS_coarse_update(synopGMACdevice *gmacdev); // Only if
void synopGMAC_TS_fine_update(synopGMACdevice *gmacdev); // Only if "fine correction" enabled
void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_val); // Update should happen making use of subsecond mask
void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val,
void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val,
u32 * sec_val, u32 * sub_sec_val); // Reads the timestamp low,high and higher(Ver2) registers in the the struct pointer; readonly contents
void synopGMAC_TS_load_target_timestamp(synopGMACdevice *gmacdev, u32 sec_val, u32 sub_sec_val); //Loads the timestamp target register with the values provided
@ -1541,7 +1541,7 @@ s32 synopGMAC_read_phy_reg(u64 RegBase,u32 PhyBase, u32 RegOffset, u16 * data);
s32 synopGMAC_write_phy_reg(u64 RegBase, u32 PhyBase, u32 RegOffset, u16 data);
s32 synopGMAC_phy_loopback(synopGMACdevice *gmacdev, bool loopback);
s32 synopGMAC_read_version (synopGMACdevice * gmacdev) ;
s32 synopGMAC_reset (synopGMACdevice * gmacdev );
s32 synopGMAC_reset (synopGMACdevice * gmacdev );
s32 synopGMAC_dma_bus_mode_init(synopGMACdevice * gmacdev, u32 init_value );
s32 synopGMAC_dma_control_init(synopGMACdevice * gmacdev, u32 init_value );
void synopGMAC_wd_enable(synopGMACdevice * gmacdev);
@ -1639,7 +1639,7 @@ bool synopGMAC_is_rx_desc_chained(DmaDesc * desc);
bool synopGMAC_is_tx_desc_chained(DmaDesc * desc);
void synopGMAC_get_desc_data(DmaDesc * desc, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2);
#ifdef ENH_DESC_8W
s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2,
s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2,
u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
#else
s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2 );
@ -1647,7 +1647,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2,u32 offload_needed,u32 * index,DmaDesc *Dpr);
s32 synopGMAC_set_rx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u64 Data1, u32 Buffer2, u32 Length2, u64 Data2);
#ifdef ENH_DESC_8W
s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2,
s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2,
u32 * Ext_Status, u32 * Time_Stamp_High, u32 * Time_Stamp_low);
#else
s32 synopGMAC_get_rx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1, u32 * Length1, u64 * Data1, u32 * Buffer2, u32 * Length2, u64 * Data2);
@ -1668,8 +1668,8 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev);
void synopGMAC_disable_dma_tx(synopGMACdevice * gmacdev);
void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev);
/******Following APIs are valid only for Enhanced Descriptor from 3.50a release onwards*******/
bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status);
bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status);
bool synopGMAC_is_ext_status(synopGMACdevice *gmacdev,u32 status);
bool synopGMAC_ES_is_IP_header_error(synopGMACdevice *gmacdev,u32 ext_status);
bool synopGMAC_ES_is_rx_checksum_bypassed(synopGMACdevice *gmacdev,u32 ext_status);
bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status);
/*******************PMT APIs***************************************/

4
bsp/loongson/ls2kdev/drivers/net/synopGMAC_Host.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -42,7 +42,7 @@ struct net_device_stats
unsigned long tx_fifo_errors;
unsigned long tx_heartbeat_errors;
unsigned long tx_window_errors;
/* for cslip etc */
unsigned long rx_compressed;
unsigned long tx_compressed;

4
bsp/loongson/ls2kdev/drivers/net/synopGMAC_debug.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -13,7 +13,7 @@
//#define GMAC_DEBUG
#include <rtthread.h>
#ifdef GMAC_DEBUG
#ifdef GMAC_DEBUG
#define DEBUG_MES rt_kprintf
#else
#define DEBUG_MES(...)

70
bsp/loongson/ls2kdev/drivers/net/synopGMAC_plat.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -57,17 +57,17 @@ typedef int bool;
#define VA_TO_PA(x) CACHED_TO_PHYS(x)
/* sw
#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#define TR0(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#ifdef DEBUG
#undef TR
# define TR(fmt, args...) printk(KERN_CRIT "SynopGMAC: " fmt, ##args)
#else
# define TR(fmt, args...) // not debugging: nothing
# define TR(fmt, args...) // not debugging: nothing
#endif
*/
/*
#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#define TR0(fmt, args...) printf("SynopGMAC: " fmt, ##args)
*/
/*
@ -75,20 +75,20 @@ typedef int bool;
#undef TR
# define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#else
//# define TR(fmt, args...) // not debugging: nothing
#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
//# define TR(fmt, args...) // not debugging: nothing
#define TR(fmt, args...) printf("SynopGMAC: " fmt, ##args)
#endif
*/
//sw: nothing to display
#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR0(fmt, args...) //rt_kprintf(fmt, ##args)
#define TR(fmt, args...) //rt_kprintf(fmt, ##args)
//typedef int bool;
enum synopGMAC_boolean
{
{
false = 0,
true = 1
true = 1
};
#define DEFAULT_DELAY_VARIABLE 10
@ -117,7 +117,7 @@ struct Network_interface_data
/**
* These are the wrapper function prototypes for OS/platform related routines
*/
*/
void * plat_alloc_memory(u32 );
void plat_free_memory(void *);
@ -128,10 +128,10 @@ void plat_delay(u32);
/**
* The Low level function to read register contents from Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* \return Returns the register contents
* \return Returns the register contents
*/
static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset)
{
@ -151,11 +151,11 @@ static u32 synopGMACReadReg(u64 RegBase, u32 RegOffset)
/**
* The Low level function to write to a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Data to be written
* \return void
* @param[in] Data to be written
* \return void
*/
static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData )
{
@ -173,18 +173,18 @@ static void synopGMACWriteReg(u64 RegBase, u32 RegOffset, u32 RegData )
/**
* The Low level function to set bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* \return void
* @param[in] Bit mask to set bits to logical 1
* \return void
*/
static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
//u64 addr = (u64)RegBase + (u64)RegOffset;
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data |= BitPos;
data |= BitPos;
synopGMACWriteReg(RegBase, RegOffset, data);
// writel(data,(void *)addr);
#if SYNOP_REG_DEBUG
@ -196,17 +196,17 @@ static void synopGMACSetBits(u64 RegBase, u32 RegOffset, u32 BitPos)
/**
* The Low level function to clear bits of a register in Hardware.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to clear bits to logical 0
* \return void
* @param[in] Bit mask to clear bits to logical 0
* \return void
*/
static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= (~BitPos);
data &= (~BitPos);
synopGMACWriteReg(RegBase, RegOffset, data);
#if SYNOP_REG_DEBUG
TR("%s !!!!!!!!!!!!! RegOffset = 0x%08x RegData = 0x%08x\n", __FUNCTION__, RegOffset, data );
@ -216,24 +216,24 @@ static void synopGMACClearBits(u64 RegBase, u32 RegOffset, u32 BitPos)
/**
* The Low level function to Check the setting of the bits.
*
* @param[in] pointer to the base of register map
*
* @param[in] pointer to the base of register map
* @param[in] Offset from the base
* @param[in] Bit mask to set bits to logical 1
* @param[in] Bit mask to set bits to logical 1
* \return returns TRUE if set to '1' returns FALSE if set to '0'. Result undefined there are no bit set in the BitPos argument.
*
*
*/
static bool synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos)
{
u32 data;
data = synopGMACReadReg(RegBase, RegOffset);
data &= BitPos;
data &= BitPos;
if(data)
if(data)
{
return true;
}
else
else
{
return false;
}

16
bsp/lpc55sxx/Libraries/drivers/drv_rtc.c
View File

@ -43,18 +43,18 @@ static time_t get_timestamp(void)
static int set_timestamp(time_t timestamp)
{
struct tm *p_tm;
struct tm now;
rtc_datetime_t rtcDate;
p_tm = gmtime(&timestamp);
gmtime_r(&timestamp, &now);
rtcDate.second = p_tm->tm_sec ;
rtcDate.minute = p_tm->tm_min ;
rtcDate.hour = p_tm->tm_hour;
rtcDate.second = now.tm_sec ;
rtcDate.minute = now.tm_min ;
rtcDate.hour = now.tm_hour;
rtcDate.day = p_tm->tm_mday;
rtcDate.month = p_tm->tm_mon + 1;
rtcDate.year = p_tm->tm_year + 1900;
rtcDate.day = now.tm_mday;
rtcDate.month = now.tm_mon + 1;
rtcDate.year = now.tm_year + 1900;
/* RTC time counter has to be stopped before setting the date & time in the TSR register */
RTC_StopTimer(RTC);

16
bsp/nuvoton/libraries/m031/rtt_port/drv_rtc.c
View File

@ -200,7 +200,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t)
/* Register rt-thread device.control() entry. */
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm_out, *tm_in;
struct tm tm_out, tm_in;
time_t *time;
S_RTC_TIME_DATA_T hw_time;
@ -236,13 +236,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
if (nu_rtc_is_date_valid(*time) != RT_EOK)
return -(RT_ERROR);
tm_in = gmtime(time);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
hw_time.u32Day = tm_in->tm_mday;
hw_time.u32Hour = tm_in->tm_hour;
hw_time.u32Minute = tm_in->tm_min;
hw_time.u32Second = tm_in->tm_sec;
gmtime_r(time, &tm_in);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon);
hw_time.u32Day = tm_in.tm_mday;
hw_time.u32Hour = tm_in.tm_hour;
hw_time.u32Minute = tm_in.tm_min;
hw_time.u32Second = tm_in.tm_sec;
hw_time.u32TimeScale = RTC_CLOCK_24;
hw_time.u32AmPm = 0;

16
bsp/nuvoton/libraries/m2354/rtt_port/drv_rtc.c
View File

@ -203,7 +203,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t)
/* Register rt-thread device.control() entry. */
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm_out, *tm_in;
struct tm tm_out, tm_in;
time_t *time;
S_RTC_TIME_DATA_T hw_time;
@ -239,13 +239,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
if (nu_rtc_is_date_valid(*time) != RT_EOK)
return -(RT_ERROR);
tm_in = gmtime(time);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
hw_time.u32Day = tm_in->tm_mday;
hw_time.u32Hour = tm_in->tm_hour;
hw_time.u32Minute = tm_in->tm_min;
hw_time.u32Second = tm_in->tm_sec;
gmtime_r(time, &tm_in);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon);
hw_time.u32Day = tm_in.tm_mday;
hw_time.u32Hour = tm_in.tm_hour;
hw_time.u32Minute = tm_in.tm_min;
hw_time.u32Second = tm_in.tm_sec;
hw_time.u32TimeScale = RTC_CLOCK_24;
hw_time.u32AmPm = 0;

16
bsp/nuvoton/libraries/m480/rtt_port/drv_rtc.c
View File

@ -202,7 +202,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t)
/* Register rt-thread device.control() entry. */
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm_out, *tm_in;
struct tm tm_out, tm_in;
time_t *time;
S_RTC_TIME_DATA_T hw_time;
@ -238,13 +238,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
if (nu_rtc_is_date_valid(*time) != RT_EOK)
return -(RT_ERROR);
tm_in = gmtime(time);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
hw_time.u32Day = tm_in->tm_mday;
hw_time.u32Hour = tm_in->tm_hour;
hw_time.u32Minute = tm_in->tm_min;
hw_time.u32Second = tm_in->tm_sec;
gmtime_r(time, &tm_in);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon);
hw_time.u32Day = tm_in.tm_mday;
hw_time.u32Hour = tm_in.tm_hour;
hw_time.u32Minute = tm_in.tm_min;
hw_time.u32Second = tm_in.tm_sec;
hw_time.u32TimeScale = RTC_CLOCK_24;
hw_time.u32AmPm = 0;

18
bsp/nuvoton/libraries/n9h30/rtt_port/drv_rtc.c
View File

@ -221,7 +221,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t)
/* Register rt-thread device.control() entry. */
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm_out, *tm_in;
struct tm tm_out, tm_in;
time_t *time;
S_RTC_TIME_DATA_T hw_time = {0};
@ -261,14 +261,14 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
if (nu_rtc_is_date_valid(*time) != RT_EOK)
return -(RT_ERROR);
tm_in = gmtime(time);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
hw_time.u32cMonth = CONV_FROM_TM_MON(tm_in->tm_mon);
hw_time.u32cDay = tm_in->tm_mday;
hw_time.u32cHour = tm_in->tm_hour;
hw_time.u32cMinute = tm_in->tm_min;
hw_time.u32cSecond = tm_in->tm_sec;
hw_time.u32cDayOfWeek = tm_in->tm_wday;
gmtime_r(time, &tm_in);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year);
hw_time.u32cMonth = CONV_FROM_TM_MON(tm_in.tm_mon);
hw_time.u32cDay = tm_in.tm_mday;
hw_time.u32cHour = tm_in.tm_hour;
hw_time.u32cMinute = tm_in.tm_min;
hw_time.u32cSecond = tm_in.tm_sec;
hw_time.u32cDayOfWeek = tm_in.tm_wday;
hw_time.u8cClockDisplay = RTC_CLOCK_24;
hw_time.u8cAmPm = 0;

16
bsp/nuvoton/libraries/nuc980/rtt_port/drv_rtc.c
View File

@ -203,7 +203,7 @@ static rt_err_t nu_rtc_is_date_valid(const time_t t)
/* Register rt-thread device.control() entry. */
static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm_out, *tm_in;
struct tm tm_out, tm_in;
time_t *time;
S_RTC_TIME_DATA_T hw_time;
@ -239,13 +239,13 @@ static rt_err_t nu_rtc_control(rt_device_t dev, int cmd, void *args)
if (nu_rtc_is_date_valid(*time) != RT_EOK)
return -(RT_ERROR);
tm_in = gmtime(time);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in->tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in->tm_mon);
hw_time.u32Day = tm_in->tm_mday;
hw_time.u32Hour = tm_in->tm_hour;
hw_time.u32Minute = tm_in->tm_min;
hw_time.u32Second = tm_in->tm_sec;
gmtime_r(time, &tm_in);
hw_time.u32Year = CONV_FROM_TM_YEAR(tm_in.tm_year);
hw_time.u32Month = CONV_FROM_TM_MON(tm_in.tm_mon);
hw_time.u32Day = tm_in.tm_mday;
hw_time.u32Hour = tm_in.tm_hour;
hw_time.u32Minute = tm_in.tm_min;
hw_time.u32Second = tm_in.tm_sec;
hw_time.u32TimeScale = RTC_CLOCK_24;
hw_time.u32AmPm = 0;

18
bsp/raspberry-pi/raspi3-32/driver/drv_rtc.c
View File

@ -193,16 +193,16 @@ static time_t raspi_get_timestamp(void)
static int raspi_set_timestamp(time_t timestamp)
{
struct tm *tblock;
tblock = gmtime(&timestamp);
struct tm tblock;
gmtime_r(&timestamp, &tblock);
buf[0] = 0;
buf[1] = tblock->tm_sec;
buf[2] = tblock->tm_min;
buf[3] = tblock->tm_hour;
buf[4] = tblock->tm_wday;
buf[5] = tblock->tm_mday;
buf[6] = tblock->tm_mon;
buf[7] = tblock->tm_year;
buf[1] = tblock.tm_sec;
buf[2] = tblock.tm_min;
buf[3] = tblock.tm_hour;
buf[4] = tblock.tm_wday;
buf[5] = tblock.tm_mday;
buf[6] = tblock.tm_mon;
buf[7] = tblock.tm_year;
i2c_write(buf, 8);

18
bsp/raspberry-pi/raspi3-64/driver/drv_rtc.c
View File

@ -40,16 +40,16 @@ static time_t raspi_get_timestamp(void)
static int raspi_set_timestamp(time_t timestamp)
{
struct tm *tblock;
tblock = gmtime(&timestamp);
struct tm tblock;
gmtime_r(&timestamp, &tblock);
buf[0] = 0;
buf[1] = tblock->tm_sec;
buf[2] = tblock->tm_min;
buf[3] = tblock->tm_hour;
buf[4] = tblock->tm_wday;
buf[5] = tblock->tm_mday;
buf[6] = tblock->tm_mon;
buf[7] = tblock->tm_year;
buf[1] = tblock.tm_sec;
buf[2] = tblock.tm_min;
buf[3] = tblock.tm_hour;
buf[4] = tblock.tm_wday;
buf[5] = tblock.tm_mday;
buf[6] = tblock.tm_mon;
buf[7] = tblock.tm_year;
bcm283x_i2c_write((PER_BASE + BCM283X_BSC0_BASE) ,buf, 8);
return RT_EOK;
}

24
bsp/renesas/libraries/HAL_Drivers/drv_rtc.c
View File

@ -69,24 +69,22 @@ static rt_err_t ra_get_secs(void *args)
static rt_err_t set_rtc_time_stamp(time_t time_stamp)
{
struct tm *p_tm;
struct tm now;
rtc_time_t g_current_time = {0};
p_tm = gmtime(&time_stamp);
if (p_tm->tm_year < 100)
gmtime_r(&time_stamp, &now);
if (now.tm_year < 100)
{
return -RT_ERROR;
}
g_current_time.tm_sec = p_tm->tm_sec ;
g_current_time.tm_min = p_tm->tm_min ;
g_current_time.tm_hour = p_tm->tm_hour;
g_current_time.tm_mday = p_tm->tm_mday;
g_current_time.tm_mon = p_tm->tm_mon;
g_current_time.tm_year = p_tm->tm_year;
g_current_time.tm_wday = p_tm->tm_wday;
g_current_time.tm_yday = p_tm->tm_yday;
g_current_time.tm_sec = now.tm_sec ;
g_current_time.tm_min = now.tm_min ;
g_current_time.tm_hour = now.tm_hour;
g_current_time.tm_mday = now.tm_mday;
g_current_time.tm_mon = now.tm_mon;
g_current_time.tm_year = now.tm_year;
g_current_time.tm_wday = now.tm_wday;
g_current_time.tm_yday = now.tm_yday;
if (R_RTC_CalendarTimeSet(&g_rtc_ctrl, &g_current_time) != FSP_SUCCESS)
{

19
bsp/swm320/drivers/drv_rtc.c
View File

@ -63,17 +63,16 @@ static time_t swm_get_rtc_time_stamp(void)
static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
{
RTC_DateTime set_datetime = {0};
struct tm *p_tm;
struct tm now;
p_tm = gmtime(&time_stamp);
set_datetime.Second = p_tm->tm_sec;
set_datetime.Minute = p_tm->tm_min;
set_datetime.Hour = p_tm->tm_hour;
set_datetime.Date = p_tm->tm_mday;
set_datetime.Month = p_tm->tm_mon;
set_datetime.Year = p_tm->tm_year;
// set_datetime.Day = p_tm->tm_wday;
gmtime_r(&time_stamp, &now);
set_datetime.Second = now.tm_sec;
set_datetime.Minute = now.tm_min;
set_datetime.Hour = now.tm_hour;
set_datetime.Date = now.tm_mday;
set_datetime.Month = now.tm_mon;
set_datetime.Year = now.tm_year;
// set_datetime.Day = now.tm_wday;
RTC_Stop(RTC);
while (RTC->CFGABLE == 0)

26
bsp/w60x/drivers/drv_rtc.c
View File

@ -50,23 +50,23 @@ static int wm_set_timestamp(time_t timestamp)
int ctrl1 = 0;
int ctrl2 = 0;
struct tm *tblock;
struct tm tblock;
tblock = gmtime(&timestamp);
gmtime_r(&timestamp, &tblock);
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* disable */
ctrl2 &= ~(1 << 16);
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl1 |= tblock->tm_sec;
ctrl1 |= tblock->tm_min << 8;
ctrl1 |= tblock->tm_hour << 16;
ctrl1 |= tblock->tm_mday << 24;
ctrl1 |= tblock.tm_sec;
ctrl1 |= tblock.tm_min << 8;
ctrl1 |= tblock.tm_hour << 16;
ctrl1 |= tblock.tm_mday << 24;
tls_reg_write32(HR_PMU_RTC_CTRL1, ctrl1);
ctrl2 = 0;
ctrl2 |= tblock->tm_mon;
ctrl2 |= tblock->tm_year << 8;
ctrl2 |= tblock.tm_mon;
ctrl2 |= tblock.tm_year << 8;
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2);
ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2);/* enable */
@ -80,21 +80,21 @@ static int wm_alarm_set_timestamp(struct rt_rtc_wkalarm *wkalarm)
{
int ctrl1 = 0;
int ctrl2 = 0;
struct tm *tblock;
struct tm tblock;
time_t timestamp = 0;
timestamp = wm_get_timestamp();
tblock = gmtime(&timestamp);
gmtime_r(&timestamp, &tblock);
tls_irq_enable(PMU_RTC_INT);
ctrl1 |= wkalarm->tm_sec;
ctrl1 |= wkalarm->tm_min << 8;
ctrl1 |= wkalarm->tm_hour << 16;
ctrl1 |= tblock->tm_mday << 24;
ctrl1 |= tblock.tm_mday << 24;
ctrl2 |= tblock->tm_mon;
ctrl2 |= tblock->tm_year << 8;
ctrl2 |= tblock.tm_mon;
ctrl2 |= tblock.tm_year << 8;
tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2 | BIT(16));

13
components/dfs/filesystems/elmfat/dfs_elm.c
View File

@ -944,22 +944,11 @@ DRESULT disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
DWORD get_fattime(void)
{
DWORD fat_time = 0;
time_t now;
struct tm *p_tm;
struct tm tm_now;
/* get current time */
now = time(RT_NULL);
/* lock scheduler. */
rt_enter_critical();
/* converts calendar time time into local time. */
p_tm = gmtime(&now);
/* copy the statically located variable */
rt_memcpy(&tm_now, p_tm, sizeof(struct tm));
/* unlock scheduler. */
rt_exit_critical();
gmtime_r(&now, &tm_now);
fat_time = (DWORD)(tm_now.tm_year - 80) << 25 |
(DWORD)(tm_now.tm_mon + 1) << 21 |

10
libcpu/arm/s3c24x0/rtc.c
View File

@ -126,7 +126,7 @@ static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t
static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args)
{
struct tm tm, *tm_ptr;
struct tm tmp;
time_t *time;
RT_ASSERT(dev != RT_NULL);
@ -135,14 +135,14 @@ static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
/* read device */
rt_hw_rtc_get(&tm);
*((rt_time_t *)args) = timegm(&tm);
rt_hw_rtc_get(&tmp);
*((rt_time_t *)args) = timegm(&tmp);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
/* write device */
tm_ptr = gmtime(time);
rt_hw_rtc_set(tm_ptr);
gmtime_r(time, &tmp);
rt_hw_rtc_set(&tmp);
break;
}