[libcpu] Add unified RISC-V libcpu porting.
This commit is contained in:
Bernard Xiong
parent
94e6c349a6
commit
2a7d814f77
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# RT-Thread BSP for RV32M1 VEGA board
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# RV32M1_VEGA 板级支持包
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## 1. 简介
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RV32M1_VEGA开发板是一款多核异构的RISC-V 32开发板，包含了两个RISC-V 32位核心，同时也包括了BLE外设。
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| 硬件 | 描述 |
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| -- | -- |
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|芯片型号| RV32M1 |
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|CPU| RV32IMC, with extensons for post-incrementing load and stores, |
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| | multiply-accumulate extensions, ALU extensions, hardware loops. |
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| | RV32IEMC |
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|主频| 48MHz或72MHz |
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| | 48MHz或72MHz |
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|片内SRAM| 256kB + 128kB |
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|片内Flash| 1MB + 256kB |
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## 2. 编译说明
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当前测试的工具链是以标准的GNU GCC 7.2.0 & newlib 2.5.0方式，并以标准的RV32IMC构架进行编译，所以RV32M1的扩展指令未支持，RT-Thread ENV版本是1.0。
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Windows上编译推荐使用[env工具][1]，可以在console下进入到`bsp/rv32m1_vega/ri5cy`目录中，运行以下命令：
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scons
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来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
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## 3. 烧写及执行
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请使用JLink接入到RV32M1_VEGA开发板的RISC-V核的JTAG接口上，同时把JLink在PC上的驱动更改为WinUSB模式。JTAG接口位于RV32M1芯片和天线座子旁边，小的20pin JTAG接口。
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使用USB线连接到标记了SDA的USB口上，在PC上会出现一个串口设备，可以使用115200-N-8-1的配置方式打开这个串口。设备使用的串口引脚是：`[PTC7/PTC8]`
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当正确编译产生出rtthread.bin映像文件后，可以使用gdb连接到openocd，并以`load`命令烧写到flash中。
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关于更多使用JTAG，使用gdb调试RV32M1_VEGA开发板的情况，建议参考开发板的[开发环境搭建](https://github.com/open-isa-org/open-isa.org/blob/master/RV32M1_Vega_Develop_Environment_Setup.pdf)的文档。
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### 3.1 运行结果
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如果编译 & 烧写无误，当按`SW1`复位按钮复位设备后，会在串口上看到RT-Thread的启动logo信息：
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``` text
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.0 build Dec 5 2018
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2006 - 2018 Copyright by rt-thread team
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File System initialized!
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Hello RT-Thread!
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msh />
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```
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## 4. 驱动支持情况及计划
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| 驱动 | 支持情况 | 备注 |
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| ------ | ---- | :------ |
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| UART | 支持 | UART0, RX(PTC7), TX(PTC8) |
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| | 未支持 | UART1, RX(PTA25), TX(PTA26) |
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| clock | 支持 | |
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| GPIO | 支持（列表可能不完善，同时也需要按照使用到的IO调整pinmux、clock） | |
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| MMC/SD | 支持 | |
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### 4.1 IO在板级支持包中的映射情况
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| IO号 | 板级代码中的定义 |
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| -- | -- |
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| PTA22 | LED_BLUE |
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| PTA23 | LED_GREEN |
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| PTA24 | LED_RED |
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| PTA24 | LED_STS |
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| PTE8 | BTN_SW3 |
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| PTE9 | BTN_SW4 |
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| PTE12 | BTN_SW5 |
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| PTA0 | BTN_SW2/BTN_NMI |
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## 5. 参考
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* [开发板用户手册](https://github.com/open-isa-org/open-isa.org/blob/master/RV32M1_VEGA_Board_User_Guide.pdf)
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* 芯片[数据手册](https://github.com/open-isa-org/open-isa.org/blob/master/Reference%20Manual%20and%20Data%20Sheet/RV32M1DS_Rev.1.1.pdf)
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* [open-isa链接](https://github.com/open-isa-org/open-isa.org)
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[1]: https://www.rt-thread.org/page/download.html
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@ -2,30 +2,37 @@ Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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arch = rtconfig.ARCH
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comm = rtconfig.ARCH + '/common'
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path = rtconfig.ARCH + '/' + rtconfig.CPU
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src = []
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ASFLAGS = ''
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# The set of source files associated with this SConscript file.
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if rtconfig.PLATFORM == 'armcc':
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src = Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + Glob(comm + '/*.c')
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src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S')
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src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S')
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if rtconfig.PLATFORM == 'gcc':
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src = Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + Glob(comm + '/*.c') + Glob(path + '/*_init.S')
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src += Glob(path + '/*_init.S')
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src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S')
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src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S')
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if rtconfig.PLATFORM == 'iar':
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src = Glob(path + '/*.c') + Glob(path + '/*_iar.S') + Glob(comm + '/*.c')
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src += Glob(path + '/*.c') + Glob(path + '/*_iar.S')
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src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S')
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if rtconfig.PLATFORM == 'cl':
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src = Glob(path + '/*.c')
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src = Glob(path + '/*.c')
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if rtconfig.PLATFORM == 'mingw':
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src = Glob(path + '/*.c')
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src = Glob(path + '/*.c')
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if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926':
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ASFLAGS = ' --cpreproc'
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CPPPATH = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/common']
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CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common']
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group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
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Return('group')
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@ -0,0 +1,180 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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*/
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#include "cpuport.h"
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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csrrci a0, mstatus, 8
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrw mstatus, a0
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ret
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/*
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* void rt_hw_context_switch_to(rt_ubase_t to)
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* a0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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/* load epc from stack */
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LOAD a0, 0 * REGBYTES(sp)
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csrw mepc, a0
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LOAD x1, 1 * REGBYTES(sp)
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/* load mstatus from stack */
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LOAD a0, 2 * REGBYTES(sp)
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csrw mstatus, a0
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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mret
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/*
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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/* saved from thread context
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* x1/ra -> sp(0)
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* x1/ra -> sp(1)
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* mstatus.mie -> sp(2)
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* x(i) -> sp(i-4)
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*/
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addi sp, sp, -32 * REGBYTES
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STORE sp, (a0)
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STORE x1, 0 * REGBYTES(sp)
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STORE x1, 1 * REGBYTES(sp)
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csrr a0, mstatus
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andi a0, a0, 8
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beqz a0, save_mpie
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li a0, 0x80
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save_mpie:
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STORE a0, 2 * REGBYTES(sp)
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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LOAD sp, (a1)
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/* resw ra to mepc */
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LOAD a1, 0 * REGBYTES(sp)
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csrw mepc, a1
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LOAD x1, 1 * REGBYTES(sp)
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/* force to machin mode(MPP=11) */
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li a1, 0x00001800;
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csrs mstatus, a1
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LOAD a1, 2 * REGBYTES(sp)
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csrs mstatus, a1
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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addi sp, sp, 32 * REGBYTES
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mret
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@ -0,0 +1,105 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "cpuport.h"
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /* epc - epc - program counter */
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rt_ubase_t ra; /* x1 - ra - return address for jumps */
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rt_ubase_t mstatus; /* - machine status register */
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rt_ubase_t gp; /* x3 - gp - global pointer */
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rt_ubase_t tp; /* x4 - tp - thread pointer */
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rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /* x9 - s1 - saved register 1 */
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rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /* x12 - a2 - function argument 2 */
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rt_ubase_t a3; /* x13 - a3 - function argument 3 */
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rt_ubase_t a4; /* x14 - a4 - function argument 4 */
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rt_ubase_t a5; /* x15 - a5 - function argument 5 */
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rt_ubase_t a6; /* x16 - a6 - function argument 6 */
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rt_ubase_t a7; /* x17 - s7 - function argument 7 */
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rt_ubase_t s2; /* x18 - s2 - saved register 2 */
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rt_ubase_t s3; /* x19 - s3 - saved register 3 */
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rt_ubase_t s4; /* x20 - s4 - saved register 4 */
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rt_ubase_t s5; /* x21 - s5 - saved register 5 */
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rt_ubase_t s6; /* x22 - s6 - saved register 6 */
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rt_ubase_t s7; /* x23 - s7 - saved register 7 */
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rt_ubase_t s8; /* x24 - s8 - saved register 8 */
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rt_ubase_t s9; /* x25 - s9 - saved register 9 */
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rt_ubase_t s10; /* x26 - s10 - saved register 10 */
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rt_ubase_t s11; /* x27 - s11 - saved register 11 */
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rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
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};
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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||||
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
|
||||
stk -= sizeof(struct rt_hw_stack_frame);
|
||||
|
||||
frame = (struct rt_hw_stack_frame *)stk;
|
||||
|
||||
for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
|
||||
{
|
||||
((rt_ubase_t *)frame)[i] = 0xdeadbeef;
|
||||
}
|
||||
|
||||
frame->ra = (rt_ubase_t)texit;
|
||||
frame->a0 = (rt_ubase_t)parameter;
|
||||
frame->epc = (rt_ubase_t)tentry;
|
||||
|
||||
/* force to machine mode(MPP=11) and set MPIE to 1 */
|
||||
frame->mstatus = 0x00007880;
|
||||
|
||||
return stk;
|
||||
}
|
||||
|
||||
void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
|
||||
{
|
||||
if (rt_thread_switch_interrupt_flag == 0)
|
||||
rt_interrupt_from_thread = from;
|
||||
|
||||
rt_interrupt_to_thread = to;
|
||||
rt_thread_switch_interrupt_flag = 1;
|
||||
|
||||
return ;
|
||||
}
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-03 Bernard The first version
|
||||
*/
|
||||
|
||||
#ifndef CPUPORT_H__
|
||||
#define CPUPORT_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* bytes of register width */
|
||||
#ifdef ARCH_CPU_64BIT
|
||||
#define STORE sd
|
||||
#define LOAD ld
|
||||
#define REGBYTES 8
|
||||
#else
|
||||
#define STORE sw
|
||||
#define LOAD lw
|
||||
#define REGBYTES 4
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-03 Bernard The first version
|
||||
*/
|
||||
|
||||
#ifndef RISCV_OPS_H__
|
||||
#define RISCV_OPS_H__
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ASSEMBLER__)
|
||||
|
||||
#define read_csr(reg) ({ unsigned long __tmp; \
|
||||
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
|
||||
#define write_csr(reg, val) ({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
|
||||
|
||||
#define set_csr(reg, bit) ({ unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
|
||||
#define clear_csr(reg, bit) ({ unsigned long __tmp; \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
|
||||
__tmp; })
|
||||
#endif /* end of __GNUC__ */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-03 Bernard The first version
|
||||
*/
|
||||
|
||||
#ifndef RISCV_PLIC_H__
|
||||
#define RISCV_PLIC_H__
|
||||
|
||||
#ifndef PLIC_BASE_ADDR
|
||||
#define PLIC_BASE_ADDR 0x0
|
||||
#endif
|
||||
|
||||
/* Priority Register - 32 bits per source */
|
||||
#define PLIC_PRIORITY_OFFSET (0x00000000UL)
|
||||
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
|
||||
|
||||
/* Pending Register - 1 bit per soirce */
|
||||
#define PLIC_PENDING_OFFSET (0x00001000UL)
|
||||
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
|
||||
|
||||
/* Enable Register - 0x80 per target */
|
||||
#define PLIC_ENABLE_OFFSET (0x00002000UL)
|
||||
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
|
||||
|
||||
/* Priority Threshold Register - 0x1000 per target */
|
||||
#define PLIC_THRESHOLD_OFFSET (0x00200000UL)
|
||||
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
|
||||
|
||||
/* Claim Register - 0x1000 per target */
|
||||
#define PLIC_CLAIM_OFFSET (0x00200004UL)
|
||||
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
|
||||
|
||||
#if defined(__GNUC__) && !defined(__ASSEMBLER__)
|
||||
__attribute__((always_inline)) static inline void __plic_set_feature(unsigned int feature)
|
||||
{
|
||||
volatile unsigned int *feature_ptr = (volatile unsigned int *)PLIC_BASE_ADDR;
|
||||
*feature_ptr = feature;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_set_threshold(unsigned int threshold)
|
||||
{
|
||||
unsigned int hart_id = read_csr(mhartid);
|
||||
volatile unsigned int *threshold_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_THRESHOLD_OFFSET +
|
||||
(hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
|
||||
*threshold_ptr = threshold;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_set_priority(unsigned int source, unsigned int priority)
|
||||
{
|
||||
volatile unsigned int *priority_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_PRIORITY_OFFSET +
|
||||
(source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
|
||||
*priority_ptr = priority;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_set_pending(unsigned int source)
|
||||
{
|
||||
volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_PENDING_OFFSET +
|
||||
((source >> 5) << 2));
|
||||
*current_ptr = (1 << (source & 0x1F));
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_irq_enable(unsigned int source)
|
||||
{
|
||||
unsigned int hart_id = read_csr(mhartid);
|
||||
volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_ENABLE_OFFSET +
|
||||
(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
|
||||
((source >> 5) << 2));
|
||||
unsigned int current = *current_ptr;
|
||||
current = current | (1 << (source & 0x1F));
|
||||
*current_ptr = current;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_irq_disable(unsigned int source)
|
||||
{
|
||||
unsigned int hart_id = read_csr(mhartid);
|
||||
volatile unsigned int *current_ptr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_ENABLE_OFFSET +
|
||||
(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
|
||||
((source >> 5) << 2));
|
||||
unsigned int current = *current_ptr;
|
||||
current = current & ~((1 << (source & 0x1F)));
|
||||
*current_ptr = current;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline unsigned int __plic_irq_claim(void)
|
||||
{
|
||||
unsigned int hart_id = read_csr(mhartid);
|
||||
volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_CLAIM_OFFSET +
|
||||
(hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
|
||||
return *claim_addr;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void __plic_irq_complete(unsigned int source)
|
||||
{
|
||||
unsigned int hart_id = read_csr(mhartid);
|
||||
volatile unsigned int *claim_addr = (volatile unsigned int *)(PLIC_BASE_ADDR +
|
||||
PLIC_CLAIM_OFFSET +
|
||||
(hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
|
||||
*claim_addr = source;
|
||||
}
|
||||
#endif /* end of __GNUC__ */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue