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Merge pull request #5426 from Rbb666/master 

Refresh using dma2d,screen refresh average 25fps
This commit is contained in:
Bernard Xiong 2022-01-14 22:51:21 +08:00 committed by GitHub
parent 5decbb5170 eaf54ca571
commit 2949ced0f4
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 78 additions and 136 deletions
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14
bsp/stm32/libraries/HAL_Drivers/drv_lcd_mipi.c
View File

@ -23,7 +23,7 @@ struct stm32_lcd
struct rt_device parent;
struct rt_device_graphic_info info;
};
static struct stm32_lcd lcd;
struct stm32_lcd lcd;
extern void stm32_mipi_lcd_init(void);
extern void stm32_mipi_lcd_config(rt_uint32_t pixel_format);
@ -76,7 +76,7 @@ rt_err_t ltdc_init(void)
HAL_DSI_Init(&hdsi, &dsi_pll);
hdsi_video.VirtualChannelID = 0;
hdsi_video.ColorCoding = DSI_RGB888;
hdsi_video.ColorCoding = DSI_RGB565;
hdsi_video.VSPolarity = DSI_VSYNC_ACTIVE_HIGH;
hdsi_video.HSPolarity = DSI_HSYNC_ACTIVE_HIGH;
hdsi_video.DEPolarity = DSI_DATA_ENABLE_ACTIVE_HIGH;
@ -130,7 +130,7 @@ rt_err_t ltdc_init(void)
HAL_DSI_Start(&(hdsi));
stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_ARGB888);
stm32_mipi_lcd_config(RTGRAPHIC_PIXEL_FORMAT_RGB565);
return RT_EOK;
}
@ -143,7 +143,7 @@ void ltdc_layer_init(uint16_t index, uint32_t framebuffer)
layer_cfg.WindowX1 = LCD_WIDTH;
layer_cfg.WindowY0 = 0;
layer_cfg.WindowY1 = LCD_HEIGHT;
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
layer_cfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
layer_cfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
layer_cfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
layer_cfg.Alpha = 255;
@ -169,9 +169,9 @@ static rt_err_t stm32_lcd_init(rt_device_t device)
{
lcd.info.width = LCD_WIDTH;
lcd.info.height = LCD_HEIGHT;
lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_ARGB888;
lcd.info.bits_per_pixel = 32;
lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);
lcd.info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd.info.bits_per_pixel = 16;
lcd.info.framebuffer = (void *)rt_malloc_align(LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8), 32);;
memset(lcd.info.framebuffer, 0, LCD_WIDTH * LCD_HEIGHT * (lcd.info.bits_per_pixel / 8));
ltdc_init();
ltdc_layer_init(0, (uint32_t)lcd.info.framebuffer);

2
bsp/stm32/stm32f469-st-disco/applications/lvgl/lv_conf.h
View File

@ -12,7 +12,7 @@
#define LV_CONF_H
#define LV_USE_PERF_MONITOR 1
#define LV_COLOR_DEPTH 32
#define LV_COLOR_DEPTH 16
#define LV_USE_GPU_STM32_DMA2D 1
#define LV_GPU_DMA2D_CMSIS_INCLUDE "stm32f469xx.h"

26
bsp/stm32/stm32f469-st-disco/applications/lvgl/lv_demo.c
View File

@ -15,14 +15,17 @@
#include <rtdbg.h>
#ifndef LV_THREAD_STACK_SIZE
#define LV_THREAD_STACK_SIZE 4096
#define LV_THREAD_STACK_SIZE 4096
#endif
#ifndef LV_THREAD_PRIO
#define LV_THREAD_PRIO (RT_THREAD_PRIORITY_MAX*2/3)
#define LV_THREAD_PRIO (RT_THREAD_PRIORITY_MAX * 2 / 8)
#endif
static void lvgl_thread(void *parameter)
static struct rt_thread lvgl_thread;
static rt_uint8_t lvgl_thread_stack[LV_THREAD_STACK_SIZE];
static void lvgl_entry(void *parameter)
{
extern void lv_demo_music(void);
lv_demo_music();
@ -30,7 +33,7 @@ static void lvgl_thread(void *parameter)
while(1)
{
lv_task_handler();
rt_thread_mdelay(1);
rt_thread_mdelay(5);
}
}
@ -38,12 +41,15 @@ static int lvgl_demo_init(void)
{
rt_thread_t tid;
tid = rt_thread_create("LVGL", lvgl_thread, RT_NULL, LV_THREAD_STACK_SIZE, LV_THREAD_PRIO, 10);
if(tid == RT_NULL)
{
LOG_E("Fail to create 'LVGL' thread");
}
rt_thread_startup(tid);
rt_thread_init(&lvgl_thread,
"LVGL",
lvgl_entry,
RT_NULL,
&lvgl_thread_stack[0],
sizeof(lvgl_thread_stack),
LV_THREAD_PRIO,
10);
rt_thread_startup(&lvgl_thread);
return 0;
}

172
bsp/stm32/stm32f469-st-disco/applications/lvgl/lv_port_disp.c
View File

@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-10-18 Meco Man The first version
* 2021-12-24 Rb Refresh using dma2d
*/
#include <lvgl.h>
#include <lcd_port.h>
@ -22,133 +23,79 @@ static struct rt_device_graphic_info info;
static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
static DMA_HandleTypeDef DmaHandle;
#define DMA_STREAM DMA2_Stream0
#define DMA_CHANNEL DMA_CHANNEL_0
#define DMA_STREAM_IRQ DMA2_Stream0_IRQn
#define DMA_STREAM_IRQHANDLER DMA2_Stream0_IRQHandler
#define DISP_BUF_SIZE (LV_HOR_RES_MAX * LV_VER_RES_MAX / 4)
static int32_t x1_flush;
static int32_t y1_flush;
static int32_t x2_flush;
static int32_t y2_fill;
static int32_t y_fill_act;
static const lv_color_t * buf_to_flush;
static void DMA_TransferComplete(DMA_HandleTypeDef *han)
{
y_fill_act ++;
if(y_fill_act > y2_fill)
{
lv_disp_flush_ready(&disp_drv);
}
else
{
buf_to_flush += (x2_flush - x1_flush + 1);
if (HAL_DMA_Start_IT(han,(uint32_t)buf_to_flush,
(uint32_t)&((uint32_t *)info.framebuffer)[y_fill_act * info.width + x1_flush],
(x2_flush - x1_flush + 1)) != HAL_OK)
{
LOG_E("HAL_DMA_Start_IT error");
RT_ASSERT(0);
}
}
}
static void DMA_TransferError(DMA_HandleTypeDef *han)
{
LOG_E("DMA_TransferError");
RT_ASSERT(0);
}
void DMA_STREAM_IRQHANDLER(void)
{
rt_interrupt_enter();
HAL_DMA_IRQHandler(&DmaHandle);
rt_interrupt_leave();
}
static lv_disp_drv_t g_disp_drv;
extern LTDC_HandleTypeDef hltdc;
volatile rt_bool_t g_gpu_state = RT_FALSE;
static void lvgl_dma_config(void)
{
/*## -1- Enable DMA2 clock #################################################*/
__HAL_RCC_DMA2_CLK_ENABLE();
/*##-2- Select the DMA functional Parameters ###############################*/
DmaHandle.Init.Channel = DMA_CHANNEL; /* DMA_CHANNEL_0 */
DmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY; /* M2M transfer mode */
DmaHandle.Init.PeriphInc = DMA_PINC_ENABLE; /* Peripheral increment mode Enable */
DmaHandle.Init.MemInc = DMA_MINC_ENABLE; /* Memory increment mode Enable */
DmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; /* Peripheral data alignment : 32bit */
DmaHandle.Init.MemDataAlignment = DMA_PDATAALIGN_WORD; /* memory data alignment : 32bit */
DmaHandle.Init.Mode = DMA_NORMAL; /* Normal DMA mode */
DmaHandle.Init.Priority = DMA_PRIORITY_HIGH; /* priority level : high */
DmaHandle.Init.FIFOMode = DMA_FIFOMODE_ENABLE; /* FIFO mode enabled */
DmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL; /* FIFO threshold: 1/4 full */
DmaHandle.Init.MemBurst = DMA_MBURST_SINGLE; /* Memory burst */
DmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; /* Peripheral burst */
DmaHandle.Instance = DMA_STREAM;
if (HAL_DMA_Init(&DmaHandle) != HAL_OK)
{
LOG_E("HAL_DMA_Init error");
RT_ASSERT(0);
}
HAL_DMA_RegisterCallback(&DmaHandle, HAL_DMA_XFER_CPLT_CB_ID, DMA_TransferComplete);
HAL_DMA_RegisterCallback(&DmaHandle, HAL_DMA_XFER_ERROR_CB_ID, DMA_TransferError);
HAL_NVIC_SetPriority(DMA_STREAM_IRQ, 0, 0);
HAL_NVIC_EnableIRQ(DMA_STREAM_IRQ);
HAL_NVIC_SetPriority(DMA2D_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
__HAL_RCC_DMA2D_CLK_ENABLE();
}
static void lcd_fb_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
{
/*Return if the area is out the screen*/
if (area->x2 < 0) return;
if (area->y2 < 0) return;
if (area->x1 > info.width - 1) return;
if (area->y1 > info.height - 1) return;
uint32_t OffLineSrc = LV_HOR_RES_MAX - (area->x2 - area->x1 + 1);
uint32_t addr = (uint32_t) hltdc.LayerCfg[0].FBStartAdress + 2 * (LV_HOR_RES_MAX * area->y1 + area->x1);
/*Truncate the area to the screen*/
int32_t act_x1 = area->x1 < 0 ? 0 : area->x1;
int32_t act_y1 = area->y1 < 0 ? 0 : area->y1;
int32_t act_x2 = area->x2 > info.width - 1 ? info.width - 1 : area->x2;
int32_t act_y2 = area->y2 > info.height - 1 ? info.height - 1 : area->y2;
DMA2D->CR = 0x00000000UL | (1 << 9);
DMA2D->FGMAR = (uint32_t) (uint16_t*) (color_p);
DMA2D->OMAR = (uint32_t) addr;
x1_flush = act_x1;
y1_flush = act_y1;
x2_flush = act_x2;
y2_fill = act_y2;
y_fill_act = act_y1;
buf_to_flush = color_p;
DMA2D->FGOR = 0;
DMA2D->OOR = OffLineSrc;
if (HAL_DMA_Start_IT(&DmaHandle,(uint32_t)buf_to_flush,
(uint32_t)&((uint32_t *)info.framebuffer)[y_fill_act * info.width + x1_flush],
(x2_flush - x1_flush + 1)) != HAL_OK)
DMA2D->FGPFCCR = DMA2D_OUTPUT_RGB565;
DMA2D->OPFCCR = DMA2D_OUTPUT_RGB565;
DMA2D->NLR = (area->y2 - area->y1 + 1) | ((area->x2 - area->x1 + 1) << 16);
DMA2D->CR |= DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE;
DMA2D->CR |= DMA2D_CR_START;
g_gpu_state = RT_TRUE;
}
void DMA2D_IRQHandler(void)
{
rt_interrupt_enter();
if ((DMA2D->ISR & DMA2D_FLAG_TC) != 0U)
{
LOG_E("HAL_DMA_Start_IT error");
RT_ASSERT(0);
if ((DMA2D->CR & DMA2D_IT_TC) != 0U)
{
DMA2D->CR &= ~DMA2D_IT_TC;
DMA2D->IFCR = DMA2D_FLAG_TC;
if (g_gpu_state == RT_TRUE)
{
g_gpu_state = RT_FALSE;
lv_disp_flush_ready(&g_disp_drv);
}
}
}
rt_interrupt_leave();
}
void lv_port_disp_init(void)
{
rt_err_t result;
void* buf_1 = RT_NULL;
void* buf_2 = RT_NULL;
static lv_color_t lv_disp_buf1[DISP_BUF_SIZE] = {0};
lcd_device = rt_device_find("lcd");
if (lcd_device == 0)
{
LOG_E("error!");
LOG_E("lcd_device error!");
return;
}
result = rt_device_open(lcd_device, 0);
if (result != RT_EOK)
{
LOG_E("error!");
@ -157,6 +104,7 @@ void lv_port_disp_init(void)
/* get framebuffer address */
result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
if (result != RT_EOK)
{
LOG_E("error!");
@ -165,26 +113,12 @@ void lv_port_disp_init(void)
}
RT_ASSERT (info.bits_per_pixel == 8 || info.bits_per_pixel == 16 ||
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
info.bits_per_pixel == 24 || info.bits_per_pixel == 32);
lvgl_dma_config();
buf_1 = rt_malloc(info.width * info.height * sizeof(lv_color_t));
if (buf_1 == RT_NULL)
{
LOG_E("malloc memory failed");
return;
}
buf_2 = rt_malloc(info.width * info.height * sizeof(lv_color_t));
if (buf_2 == RT_NULL)
{
LOG_E("malloc memory failed");
return;
}
/*Initialize `disp_buf` with the buffer(s).*/
lv_disp_draw_buf_init(&disp_buf, buf_1, buf_2, info.width * info.height);
lv_disp_draw_buf_init(&disp_buf, lv_disp_buf1, RT_NULL, DISP_BUF_SIZE);
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
@ -200,4 +134,6 @@ void lv_port_disp_init(void)
/*Finally register the driver*/
lv_disp_drv_register(&disp_drv);
g_disp_drv = disp_drv;
}