mirror of
https://github.com/RT-Thread/rt-thread.git
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port lpc176x for IAR
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1215 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
848a08f62e
commit
27ad56b8d2
168
libcpu/arm/lpc17xx/context_iar.S
Normal file
168
libcpu/arm/lpc17xx/context_iar.S
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@ -0,0 +1,168 @@
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;/*
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; * File : context_iar.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2009, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2010-02-04 Magicoe Edit for LPC17xx Series
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; * 2010-12-20 aozima edit for IAR
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; */
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;/**
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; * @addtogroup LPC17
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; */
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;/*@{*/
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_thread_switch_interrput_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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EXPORT rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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CPSID I
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BX LR
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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EXPORT rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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BX LR
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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EXPORT rt_hw_context_switch_interrupt
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EXPORT rt_hw_context_switch
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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; set rt_thread_switch_interrput_flag to 1
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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BX LR
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; r0 --> swith from thread stack
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; r1 --> swith to thread stack
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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EXPORT rt_hw_pend_sv
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rt_hw_pend_sv:
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; disable interrupt to protect context switch
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MRS r2, PRIMASK
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CPSID I
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; get rt_thread_switch_interrupt_flag
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LDR r0, =rt_thread_switch_interrput_flag
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LDR r1, [r0]
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CBZ r1, pendsv_exit ; pendsv already handled
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; clear rt_thread_switch_interrput_flag to 0
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MOV r1, #0x00
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STR r1, [r0]
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LDR r0, =rt_interrupt_from_thread
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LDR r1, [r0]
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CBZ r1, swtich_to_thread ; skip register save at the first time
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MRS r1, psp ; get from thread stack pointer
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STMFD r1!, {r4 - r11} ; push r4 - r11 register
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LDR r0, [r0]
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STR r1, [r0] ; update from thread stack pointer
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swtich_to_thread
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LDR r1, =rt_interrupt_to_thread
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LDR r1, [r1]
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LDR r1, [r1] ; load thread stack pointer
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LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
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MSR psp, r1 ; update stack pointer
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pendsv_exit
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; restore interrupt
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MSR PRIMASK, r2
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ORR lr, lr, #0x04
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BX lr
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; * this fucntion is used to perform the first thread switch
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; */
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EXPORT rt_hw_context_switch_to
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rt_hw_context_switch_to:
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; set to thread
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LDR r1, =rt_interrupt_to_thread
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STR r0, [r1]
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; set from thread to 0
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LDR r1, =rt_interrupt_from_thread
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MOV r0, #0x0
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STR r0, [r1]
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; set interrupt flag to 1
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LDR r1, =rt_thread_switch_interrput_flag
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MOV r0, #1
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STR r0, [r1]
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; set the PendSV exception priority
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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STR r1, [r0]
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; trigger the PendSV exception (causes context switch)
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LDR r0, =NVIC_INT_CTRL
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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; enable interrupts at processor level
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CPSIE I
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; never reach here!
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; compatible with old version
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EXPORT rt_hw_interrupt_thread_switch
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rt_hw_interrupt_thread_switch:
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BX lr
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END
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35
libcpu/arm/lpc17xx/fault_iar.S
Normal file
35
libcpu/arm/lpc17xx/fault_iar.S
Normal file
@ -0,0 +1,35 @@
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;/*
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; * File : fault_iar.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2010-12-20 aozima edit for IAR
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; */
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_hw_hard_fault_exception
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EXPORT rt_hw_hard_fault
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rt_hw_hard_fault:
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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END
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345
libcpu/arm/lpc17xx/start_iar.S
Normal file
345
libcpu/arm/lpc17xx/start_iar.S
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@ -0,0 +1,345 @@
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;/*****************************************************************************
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; * @file: start_iar.S
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC17xx Device Series
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; * @version: V1.02
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; * @date: 31. July 2009
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; *
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; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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IMPORT rt_hw_hard_fault
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IMPORT rt_hw_pend_sv
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IMPORT rt_hw_timer_handler
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD rt_hw_hard_fault
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DCD MemManage_Handler
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DCD BusFault_Handler
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DCD UsageFault_Handler
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD DebugMon_Handler
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DCD 0
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DCD rt_hw_pend_sv
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DCD rt_hw_timer_handler
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; External Interrupts
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DCD WDT_IRQHandler ; 16: Watchdog Timer
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DCD TIMER0_IRQHandler ; 17: Timer0
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DCD TIMER1_IRQHandler ; 18: Timer1
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DCD TIMER2_IRQHandler ; 19: Timer2
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DCD TIMER3_IRQHandler ; 20: Timer3
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DCD UART0_IRQHandler ; 21: UART0
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DCD UART1_IRQHandler ; 22: UART1
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DCD UART2_IRQHandler ; 23: UART2
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DCD UART3_IRQHandler ; 24: UART3
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DCD PWM1_IRQHandler ; 25: PWM1
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DCD I2C0_IRQHandler ; 26: I2C0
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DCD I2C1_IRQHandler ; 27: I2C1
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DCD I2C2_IRQHandler ; 28: I2C2
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DCD SPI_IRQHandler ; 29: SPI
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DCD SSP0_IRQHandler ; 30: SSP0
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DCD SSP1_IRQHandler ; 31: SSP1
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DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
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DCD RTC_IRQHandler ; 33: Real Time Clock
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DCD EINT0_IRQHandler ; 34: External Interrupt 0
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DCD EINT1_IRQHandler ; 35: External Interrupt 1
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DCD EINT2_IRQHandler ; 36: External Interrupt 2
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DCD EINT3_IRQHandler ; 37: External Interrupt 3
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DCD ADC_IRQHandler ; 38: A/D Converter
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DCD BOD_IRQHandler ; 39: Brown-Out Detect
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DCD USB_IRQHandler ; 40: USB
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DCD CAN_IRQHandler ; 41: CAN
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DCD DMA_IRQHandler ; 42: General Purpose DMA
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DCD I2S_IRQHandler ; 43: I2S
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DCD ENET_IRQHandler ; 44: Ethernet
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DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
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DCD MCPWM_IRQHandler ; 46: Motor Control PWM
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DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
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DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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|
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER(1)
|
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SysTick_Handler
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B SysTick_Handler
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|
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PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
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WDT_IRQHandler
|
||||
B WDT_IRQHandler
|
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|
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PUBWEAK TIMER0_IRQHandler
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||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER0_IRQHandler
|
||||
B TIMER0_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART0_IRQHandler
|
||||
B UART0_IRQHandler
|
||||
|
||||
PUBWEAK UART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART1_IRQHandler
|
||||
B UART1_IRQHandler
|
||||
|
||||
PUBWEAK UART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART2_IRQHandler
|
||||
B UART2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK PWM1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PWM1_IRQHandler
|
||||
B PWM1_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C0_IRQHandler
|
||||
B I2C0_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C1_IRQHandler
|
||||
B I2C1_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2C2_IRQHandler
|
||||
B I2C2_IRQHandler
|
||||
|
||||
PUBWEAK SPI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SPI_IRQHandler
|
||||
B SPI_IRQHandler
|
||||
|
||||
PUBWEAK SSP0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP0_IRQHandler
|
||||
B SSP0_IRQHandler
|
||||
|
||||
PUBWEAK SSP1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
SSP1_IRQHandler
|
||||
B SSP1_IRQHandler
|
||||
|
||||
PUBWEAK PLL0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL0_IRQHandler
|
||||
B PLL0_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK EINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT0_IRQHandler
|
||||
B EINT0_IRQHandler
|
||||
|
||||
PUBWEAK EINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT1_IRQHandler
|
||||
B EINT1_IRQHandler
|
||||
|
||||
PUBWEAK EINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT2_IRQHandler
|
||||
B EINT2_IRQHandler
|
||||
|
||||
PUBWEAK EINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
EINT3_IRQHandler
|
||||
B EINT3_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK BOD_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
BOD_IRQHandler
|
||||
B BOD_IRQHandler
|
||||
|
||||
PUBWEAK USB_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
USB_IRQHandler
|
||||
B USB_IRQHandler
|
||||
|
||||
PUBWEAK CAN_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
CAN_IRQHandler
|
||||
B CAN_IRQHandler
|
||||
|
||||
PUBWEAK DMA_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
DMA_IRQHandler
|
||||
B DMA_IRQHandler
|
||||
|
||||
PUBWEAK I2S_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
I2S_IRQHandler
|
||||
B I2S_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK RIT_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
RIT_IRQHandler
|
||||
B RIT_IRQHandler
|
||||
|
||||
PUBWEAK MCPWM_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
MCPWM_IRQHandler
|
||||
B MCPWM_IRQHandler
|
||||
|
||||
PUBWEAK QEI_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
QEI_IRQHandler
|
||||
B QEI_IRQHandler
|
||||
|
||||
PUBWEAK PLL1_IRQHandler
|
||||
SECTION .text:CODE:REORDER(1)
|
||||
PLL1_IRQHandler
|
||||
B PLL1_IRQHandler
|
||||
|
||||
END
|
||||
Loading…
x
Reference in New Issue
Block a user