From 58297059ec7c91d2833d6ef1394351db696c7a82 Mon Sep 17 00:00:00 2001 From: yangjie Date: Tue, 25 May 2021 21:09:27 +0800 Subject: [PATCH] [lts-3.1.x][bsp] imx6ul bsp sync from master --- bsp/imx6ul/.config | 202 +++- bsp/imx6ul/SConstruct | 3 +- bsp/imx6ul/drivers/Kconfig | 3 + bsp/imx6ul/drivers/iomux/uart_iomux_config.c | 21 +- bsp/imx6ul/drivers/serial.c | 27 +- bsp/imx6ul/drivers/serial.h | 3 +- bsp/imx6ul/{imx6.lds => link.lds} | 0 .../platform/include/mx6ul/imx6ul-pinfunc.h | 915 ------------------ .../platform/include/mx6ul/iomux_register.h | 3 +- bsp/imx6ul/rtconfig.h | 216 +---- bsp/imx6ul/rtconfig.py | 14 +- 11 files changed, 240 insertions(+), 1167 deletions(-) rename bsp/imx6ul/{imx6.lds => link.lds} (100%) delete mode 100644 bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h diff --git a/bsp/imx6ul/.config b/bsp/imx6ul/.config index 0068adc43f..4fa2072fb4 100644 --- a/bsp/imx6ul/.config +++ b/bsp/imx6ul/.config @@ -22,6 +22,12 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 # CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set # CONFIG_RT_DEBUG_INIT_CONFIG is not set @@ -53,6 +59,7 @@ CONFIG_RT_USING_MEMPOOL=y # CONFIG_RT_USING_NOHEAP is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set CONFIG_RT_USING_HEAP=y @@ -64,11 +71,15 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40002 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40004 CONFIG_ARCH_ARM=y # CONFIG_RT_USING_CPU_FFS is not set CONFIG_ARCH_ARM_CORTEX_A=y +# CONFIG_RT_SMP_AUTO_BOOT is not set +CONFIG_RT_USING_GIC_V2=y +# CONFIG_RT_USING_GIC_V3 is not set +# CONFIG_RT_NO_USING_GIC is not set CONFIG_ARCH_ARM_CORTEX_A7=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set @@ -115,8 +126,6 @@ CONFIG_DFS_FD_MAX=16 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set # # Device Drivers @@ -131,8 +140,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set # CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_PWM is not set # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set @@ -163,8 +174,10 @@ CONFIG_RT_USING_LIBC=y CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_POSIX_MMAP is not set # CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set # CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_FIXED_TIMEZONE=8 # # Network @@ -201,8 +214,14 @@ CONFIG_RT_USING_POSIX=y # CONFIG_RT_USING_RYM is not set # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_LWP is not set +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + # # RT-Thread online packages # @@ -210,10 +229,15 @@ CONFIG_RT_USING_POSIX=y # # IoT - internet of things # +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set # CONFIG_PKG_USING_WEBCLIENT is not set # CONFIG_PKG_USING_WEBNET is not set # CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set # CONFIG_PKG_USING_CJSON is not set # CONFIG_PKG_USING_JSMN is not set @@ -240,6 +264,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set # CONFIG_PKG_USING_ATSRV_SOCKET is not set # CONFIG_PKG_USING_WIZNET is not set @@ -251,8 +277,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_GAGENT_CLOUD is not set # CONFIG_PKG_USING_ALI_IOTKIT is not set # CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOTHUB is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set # CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set # CONFIG_PKG_USING_IPMSG is not set @@ -261,8 +289,26 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_LIBRWS is not set # CONFIG_PKG_USING_TCPSERVER is not set # CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set # # security packages @@ -270,6 +316,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_MBEDTLS is not set # CONFIG_PKG_USING_libsodium is not set # CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set # # language packages @@ -286,6 +334,10 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_STEMWIN is not set # CONFIG_PKG_USING_WAVPLAYER is not set # CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set # # tools packages @@ -297,7 +349,35 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set # # system packages @@ -306,17 +386,47 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_PERSIMMON is not set # CONFIG_PKG_USING_CAIRO is not set # CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_PARTITION is not set # CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set # CONFIG_PKG_USING_SQLITE is not set # CONFIG_PKG_USING_RTI is not set # CONFIG_PKG_USING_LITTLEVGL2RTT is not set # CONFIG_PKG_USING_CMSIS is not set # CONFIG_PKG_USING_DFS_YAFFS is not set # CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set # CONFIG_PKG_USING_THREAD_POOL is not set # CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set # # peripheral libraries and drivers @@ -324,6 +434,8 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SENSORS_DRIVERS is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AS7341 is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_U8G2 is not set @@ -332,10 +444,16 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_SX12XX is not set # CONFIG_PKG_USING_SIGNAL_LED is not set # CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_WM_LIBRARIES is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set # CONFIG_PKG_USING_INFRARED is not set # CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set # CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_AD7746 is not set @@ -343,8 +461,52 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_I2C_TOOLS is not set # CONFIG_PKG_USING_NRF24L01 is not set # CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_LCD_DRIVERS is not set # CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set # # miscellaneous packages @@ -354,6 +516,7 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_MINILZO is not set # CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set # CONFIG_PKG_USING_MULTIBUTTON is not set # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set # CONFIG_PKG_USING_CANFESTIVAL is not set @@ -374,9 +537,24 @@ CONFIG_RT_USING_POSIX=y # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set # CONFIG_PKG_USING_HELLO is not set # CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_KI is not set # CONFIG_PKG_USING_ARMv7M_DWT is not set # CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_COWSAY is not set +CONFIG_RT_USING_UART1=y CONFIG_SOC_MCIMX6X4=y diff --git a/bsp/imx6ul/SConstruct b/bsp/imx6ul/SConstruct index 9483ea927d..de15998d09 100644 --- a/bsp/imx6ul/SConstruct +++ b/bsp/imx6ul/SConstruct @@ -10,7 +10,7 @@ else: sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] from building import * -TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT +TARGET = 'rtthread.' + rtconfig.TARGET_EXT DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], @@ -20,6 +20,7 @@ env = Environment(tools = ['mingw'], AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] Export('RTT_ROOT') Export('rtconfig') diff --git a/bsp/imx6ul/drivers/Kconfig b/bsp/imx6ul/drivers/Kconfig index e69de29bb2..95c536178d 100644 --- a/bsp/imx6ul/drivers/Kconfig +++ b/bsp/imx6ul/drivers/Kconfig @@ -0,0 +1,3 @@ +config RT_USING_UART1 + bool "Enable UART1" + default y diff --git a/bsp/imx6ul/drivers/iomux/uart_iomux_config.c b/bsp/imx6ul/drivers/iomux/uart_iomux_config.c index bad8e945c3..4da7598986 100644 --- a/bsp/imx6ul/drivers/iomux/uart_iomux_config.c +++ b/bsp/imx6ul/drivers/iomux/uart_iomux_config.c @@ -33,10 +33,21 @@ #include "io.h" #include -#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084) -#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088) +#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084) +#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088) #define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624) +#define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \ + do {\ + writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\ + if (select_input_offset != 0)\ + writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\ + writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\ + } while(0); + +#define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p) PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p) +#define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p) PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p) + void uart1_iomux_config(void) { /* UART1 TXD */ @@ -97,11 +108,11 @@ void uart_iomux_config(int instance) return uart5_iomux_config(); case HW_UART7: - return uart5_iomux_config(); + return uart5_iomux_config(); case HW_UART8: - return uart5_iomux_config(); - + return uart5_iomux_config(); + default: assert(false); } diff --git a/bsp/imx6ul/drivers/serial.c b/bsp/imx6ul/drivers/serial.c index 0f6943cfbd..5764d088de 100644 --- a/bsp/imx6ul/drivers/serial.c +++ b/bsp/imx6ul/drivers/serial.c @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion @@ -10,9 +11,7 @@ #include #include #include - #include - #include "serial.h" struct hw_uart_device @@ -122,16 +121,6 @@ static const struct rt_uart_ops _uart_ops = uart_getc, }; -#ifdef RT_USING_UART0 -/* UART device driver structure */ -static struct hw_uart_device _uart0_device = -{ - HW_UART0, - IMX_INT_UART0 -}; -static struct rt_serial_device _serial0; -#endif - #ifdef RT_USING_UART1 /* UART1 device driver structure */ static struct hw_uart_device _uart1_device = @@ -155,18 +144,6 @@ int rt_hw_uart_init(void) config.invert = NRZ_NORMAL; config.bufsz = RT_SERIAL_RB_BUFSZ; -#ifdef RT_USING_UART0 - uart = &_uart0_device; - - _serial0.ops = &_uart_ops; - _serial0.config = config; - - /* register UART1 device */ - rt_hw_serial_register(&_serial0, "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); -#endif - #ifdef RT_USING_UART1 uart = &_uart1_device; _serial1.ops = &_uart_ops; diff --git a/bsp/imx6ul/drivers/serial.h b/bsp/imx6ul/drivers/serial.h index 00d464bde0..862ba65ef7 100644 --- a/bsp/imx6ul/drivers/serial.h +++ b/bsp/imx6ul/drivers/serial.h @@ -1,7 +1,8 @@ /* * COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd - * + * * SPDX-License-Identifier: Apache-2.0 + * * Change Logs: * Date Author Notes * 2013-03-30 Bernard the first verion diff --git a/bsp/imx6ul/imx6.lds b/bsp/imx6ul/link.lds similarity index 100% rename from bsp/imx6ul/imx6.lds rename to bsp/imx6ul/link.lds diff --git a/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h b/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h deleted file mode 100644 index dc66fe20ed..0000000000 --- a/bsp/imx6ul/platform/include/mx6ul/imx6ul-pinfunc.h +++ /dev/null @@ -1,915 +0,0 @@ -/* - * Copyright 2014 - 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX6UL_PINFUNC_H -#define __DTS_IMX6UL_PINFUNC_H - -#define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \ - do {\ - writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\ - if (select_input_offset != 0)\ - writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\ - writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\ - } while(0); - -/* - * The pin function ID is a tuple of - * - */ -#define MX6UL_PAD_JTAG_MOD__SJC_MOD(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__GPT2_CLK(p) PIN_CFG(0x0044, 0x02D0, 0x05A0, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY(p) PIN_CFG(0x0044, 0x02D0, 0x04C0, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00(p) PIN_CFG(0x0044, 0x02D0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__SJC_TMS(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1(p) PIN_CFG(0x0048, 0x02D4, 0x0598, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__CCM_WAIT(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT(p) PIN_CFG(0x0048, 0x02D4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__SJC_TDO(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2(p) PIN_CFG(0x004C, 0x02D8, 0x059C, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC(p) PIN_CFG(0x004C, 0x02D8, 0x05FC, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__CCM_STOP(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT(p) PIN_CFG(0x004C, 0x02D8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__SJC_TDI(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK(p) PIN_CFG(0x0050, 0x02DC, 0x05F8, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__PWM6_OUT(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__MQS_LEFT(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL(p) PIN_CFG(0x0050, 0x02DC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__SJC_TCK(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__PWM7_OUT(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL(p) PIN_CFG(0x0054, 0x02E0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS(p) PIN_CFG(0x0058, 0x02E4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL(p) PIN_CFG(0x005C, 0x02E8, 0x05AC, 0x0, 0x1, p) -#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1(p) PIN_CFG(0x005C, 0x02E8, 0x058C, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID(p) PIN_CFG(0x005C, 0x02E8, 0x04B8, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1(p) PIN_CFG(0x005C, 0x02E8, 0x0574, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B(p) PIN_CFG(0x005C, 0x02E8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA(p) PIN_CFG(0x0060, 0x02EC, 0x05B0, 0x0, 0x1, p) -#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC(p) PIN_CFG(0x0060, 0x02EC, 0x0664, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2(p) PIN_CFG(0x0060, 0x02EC, 0x057C, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B(p) PIN_CFG(0x0060, 0x02EC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL(p) PIN_CFG(0x0064, 0x02F0, 0x05A4, 0x0, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP(p) PIN_CFG(0x0064, 0x02F0, 0x066C, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_GPIO1_IO02__UART1_TX(p) PIN_CFG(0x0064, 0x02F0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA(p) PIN_CFG(0x0068, 0x02F4, 0x05A8, 0x0, 0x1, p) -#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC(p) PIN_CFG(0x0068, 0x02F4, 0x0660, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B(p) PIN_CFG(0x0068, 0x02F4, 0x0668, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_GPIO1_IO03__UART1_RX(p) PIN_CFG(0x0068, 0x02F4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1(p) PIN_CFG(0x006C, 0x02F8, 0x0574, 0x0, 0x1, p) -#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO04__UART5_TX(p) PIN_CFG(0x006C, 0x02F8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2(p) PIN_CFG(0x0070, 0x02FC, 0x057C, 0x0, 0x1, p) -#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID(p) PIN_CFG(0x0070, 0x02FC, 0x04BC, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD(p) PIN_CFG(0x0070, 0x02FC, 0x0530, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO05__UART5_RX(p) PIN_CFG(0x0070, 0x02FC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO(p) PIN_CFG(0x0074, 0x0300, 0x0578, 0x0, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO(p) PIN_CFG(0x0074, 0x0300, 0x0580, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP(p) PIN_CFG(0x0074, 0x0300, 0x069C, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS(p) PIN_CFG(0x0074, 0x0300, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK(p) PIN_CFG(0x0078, 0x0304, 0x0528, 0x3, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B(p) PIN_CFG(0x0078, 0x0304, 0x0674, 0x4, 0x1, p) -#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__CCM_STOP(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS(p) PIN_CFG(0x0078, 0x0304, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC(p) PIN_CFG(0x007C, 0x0308, 0x052C, 0x3, 0x1, p) -#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY(p) PIN_CFG(0x007C, 0x0308, 0x04C0, 0x6, 0x1, p) -#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS(p) PIN_CFG(0x007C, 0x0308, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN(p) PIN_CFG(0x0080, 0x030C, 0x0618, 0x2, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC(p) PIN_CFG(0x0080, 0x030C, 0x0524, 0x3, 0x1, p) -#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS(p) PIN_CFG(0x0080, 0x030C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p) PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p) -#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL(p) PIN_CFG(0x0084, 0x0310, 0x05B4, 0x2, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT(p) PIN_CFG(0x0084, 0x0310, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p) PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p) -#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA(p) PIN_CFG(0x0088, 0x0314, 0x05B8, 0x2, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK(p) PIN_CFG(0x0088, 0x0314, 0x0594, 0x4, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN(p) PIN_CFG(0x0088, 0x0314, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS(p) PIN_CFG(0x008C, 0x0318, 0x0620, 0x0, 0x2, p) -#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP(p) PIN_CFG(0x008C, 0x0318, 0x066C, 0x2, 0x1, p) -#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP(p) PIN_CFG(0x008C, 0x0318, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS(p) PIN_CFG(0x0090, 0x031C, 0x0620, 0x0, 0x3, p) -#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B(p) PIN_CFG(0x0090, 0x031C, 0x0668, 0x2, 0x1, p) -#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B(p) PIN_CFG(0x0090, 0x031C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__UART2_TX(p) PIN_CFG(0x0094, 0x0320, 0x062C, 0x0, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL(p) PIN_CFG(0x0094, 0x0320, 0x05BC, 0x2, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1(p) PIN_CFG(0x0094, 0x0320, 0x058C, 0x4, 0x1, p) -#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0(p) PIN_CFG(0x0094, 0x0320, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__UART2_RX(p) PIN_CFG(0x0098, 0x0324, 0x062C, 0x0, 0x1, p) -#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA(p) PIN_CFG(0x0098, 0x0324, 0x05C0, 0x2, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2(p) PIN_CFG(0x0098, 0x0324, 0x0590, 0x4, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK(p) PIN_CFG(0x0098, 0x0324, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS(p) PIN_CFG(0x009C, 0x0328, 0x0628, 0x0, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x12, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI(p) PIN_CFG(0x009C, 0x0328, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS(p) PIN_CFG(0x00A0, 0x032C, 0x0628, 0x0, 0x1, p) -#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__ENET1_COL(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX(p) PIN_CFG(0x00A0, 0x032C, 0x0588, 0x12, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO(p) PIN_CFG(0x00A0, 0x032C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__UART3_TX(p) PIN_CFG(0x00A4, 0x0330, 0x0634, 0x0, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS(p) PIN_CFG(0x00A4, 0x0330, 0x0628, 0x4, 0x2, p) -#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x7, 0x0, p) -#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID(p) PIN_CFG(0x00A4, 0x0330, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__UART3_RX(p) PIN_CFG(0x00A8, 0x0334, 0x0634, 0x0, 0x1, p) -#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS(p) PIN_CFG(0x00A8, 0x0334, 0x0628, 0x4, 0x3, p) -#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT(p) PIN_CFG(0x00A8, 0x0334, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS(p) PIN_CFG(0x00AC, 0x0338, 0x0630, 0x0, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x12, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT(p) PIN_CFG(0x00AC, 0x0338, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS(p) PIN_CFG(0x00B0, 0x033C, 0x0630, 0x0, 0x1, p) -#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX(p) PIN_CFG(0x00B0, 0x033C, 0x0584, 0x12, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B(p) PIN_CFG(0x00B0, 0x033C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__UART4_TX(p) PIN_CFG(0x00B4, 0x0340, 0x063C, 0x0, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL(p) PIN_CFG(0x00B4, 0x0340, 0x05A4, 0x12, 0x1, p) -#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK(p) PIN_CFG(0x00B4, 0x0340, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART4_RX_DATA__UART4_RX(p) PIN_CFG(0x00B8, 0x0344, 0x063C, 0x0, 0x1, p) -#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA(p) PIN_CFG(0x00B8, 0x0344, 0x05A8, 0x12, 0x2, p) -#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0(p) PIN_CFG(0x00B8, 0x0344, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_UART5_TX_DATA__UART5_TX(p) PIN_CFG(0x00BC, 0x0348, 0x0644, 0x0, 0x4, p) -#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL(p) PIN_CFG(0x00BC, 0x0348, 0x05AC, 0x12, 0x2, p) -#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00(p) PIN_CFG(0x00BC, 0x0348, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART5_RX_DATA__UART5_RX(p) PIN_CFG(0x00C0, 0x034C, 0x0644, 0x0, 0x5, p) -#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA(p) PIN_CFG(0x00C0, 0x034C, 0x05B0, 0x12, 0x2, p) -#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO(p) PIN_CFG(0x00C0, 0x034C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS(p) PIN_CFG(0x00C4, 0x0350, 0x0638, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL(p) PIN_CFG(0x00C4, 0x0350, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS(p) PIN_CFG(0x00C8, 0x0354, 0x0638, 0x1, 0x1, p) -#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX(p) PIN_CFG(0x00C8, 0x0354, 0x0584, 0x4, 0x1, p) -#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL(p) PIN_CFG(0x00C8, 0x0354, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS(p) PIN_CFG(0x00CC, 0x0358, 0x0640, 0x1, 0x3, p) -#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT(p) PIN_CFG(0x00CC, 0x0358, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS(p) PIN_CFG(0x00D0, 0x035C, 0x0640, 0x1, 0x4, p) -#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX(p) PIN_CFG(0x00D0, 0x035C, 0x0588, 0x4, 0x1, p) -#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT(p) PIN_CFG(0x00D0, 0x035C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS(p) PIN_CFG(0x00D4, 0x0360, 0x0648, 0x1, 0x2, p) -#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO(p) PIN_CFG(0x00D4, 0x0360, 0x0580, 0x4, 0x1, p) -#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB(p) PIN_CFG(0x00D4, 0x0360, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS(p) PIN_CFG(0x00D8, 0x0364, 0x0648, 0x1, 0x3, p) -#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB(p) PIN_CFG(0x00D8, 0x0364, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS(p) PIN_CFG(0x00DC, 0x0368, 0x0650, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1(p) PIN_CFG(0x00DC, 0x0368, 0x0574, 0x14, 0x2, p) -#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK(p) PIN_CFG(0x00DC, 0x0368, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS(p) PIN_CFG(0x00E0, 0x036C, 0x0650, 0x1, 0x1, p) -#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2(p) PIN_CFG(0x00E0, 0x036C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA0__UART6_TX(p) PIN_CFG(0x00E4, 0x0370, 0x064C, 0x1, 0x1, p) -#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL(p) PIN_CFG(0x00E4, 0x0370, 0x05B4, 0x3, 0x1, p) -#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO(p) PIN_CFG(0x00E4, 0x0370, 0x0578, 0x4, 0x1, p) -#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR(p) PIN_CFG(0x00E4, 0x0370, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__UART6_RX(p) PIN_CFG(0x00E8, 0x0374, 0x064C, 0x1, 0x2, p) -#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA(p) PIN_CFG(0x00E8, 0x0374, 0x05B8, 0x3, 0x1, p) -#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC(p) PIN_CFG(0x00E8, 0x0374, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__UART7_TX(p) PIN_CFG(0x00EC, 0x0378, 0x0654, 0x1, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL(p) PIN_CFG(0x00EC, 0x0378, 0x05BC, 0x3, 0x1, p) -#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M(p) PIN_CFG(0x00EC, 0x0378, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA0__UART7_RX(p) PIN_CFG(0x00F0, 0x037C, 0x0654, 0x1, 0x1, p) -#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA(p) PIN_CFG(0x00F0, 0x037C, 0x05C0, 0x3, 0x1, p) -#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05(p) PIN_CFG(0x00F0, 0x037C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__UART8_TX(p) PIN_CFG(0x00F4, 0x0380, 0x065C, 0x1, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK(p) PIN_CFG(0x00F4, 0x0380, 0x0564, 0x3, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR(p) PIN_CFG(0x00F4, 0x0380, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__UART8_RX(p) PIN_CFG(0x00F8, 0x0384, 0x065C, 0x1, 0x1, p) -#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI(p) PIN_CFG(0x00F8, 0x0384, 0x056C, 0x3, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC(p) PIN_CFG(0x00F8, 0x0384, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS(p) PIN_CFG(0x00FC, 0x0388, 0x0658, 0x1, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO(p) PIN_CFG(0x00FC, 0x0388, 0x0568, 0x3, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2(p) PIN_CFG(0x00FC, 0x0388, 0x057C, 0x14, 0x2, p) -#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID(p) PIN_CFG(0x00FC, 0x0388, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS(p) PIN_CFG(0x0100, 0x038C, 0x0658, 0x1, 0x1, p) -#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY(p) PIN_CFG(0x0100, 0x038C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_CLK__LCDIF_CLK(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_CLK__UART4_TX(p) PIN_CFG(0x0104, 0x0390, 0x063C, 0x2, 0x2, p) -#define MX6UL_PAD_LCD_CLK__SAI3_MCLK(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_CLK__EIM_CS2_B(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_CLK__GPIO3_IO00(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB(p) PIN_CFG(0x0104, 0x0390, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__UART4_RX(p) PIN_CFG(0x0108, 0x0394, 0x063C, 0x2, 0x3, p) -#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC(p) PIN_CFG(0x0108, 0x0394, 0x060C, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY(p) PIN_CFG(0x0108, 0x0394, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC(p) PIN_CFG(0x010C, 0x0398, 0x05DC, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS(p) PIN_CFG(0x010C, 0x0398, 0x0638, 0x2, 0x2, p) -#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK(p) PIN_CFG(0x010C, 0x0398, 0x0608, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1(p) PIN_CFG(0x010C, 0x0398, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY(p) PIN_CFG(0x0110, 0x039C, 0x05DC, 0x1, 0x1, p) -#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS(p) PIN_CFG(0x0110, 0x039C, 0x0638, 0x2, 0x3, p) -#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2(p) PIN_CFG(0x0110, 0x039C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_RESET__LCDIF_RESET(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_RESET__LCDIF_CS(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_RESET__GPIO3_IO04(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3(p) PIN_CFG(0x0114, 0x03A0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__PWM1_OUT(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__I2C3_SDA(p) PIN_CFG(0x0118, 0x03A4, 0x05B8, 0x4, 0x2, p) -#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK(p) PIN_CFG(0x0118, 0x03A4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__PWM2_OUT(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__I2C3_SCL(p) PIN_CFG(0x011C, 0x03A8, 0x05B4, 0x4, 0x2, p) -#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC(p) PIN_CFG(0x011C, 0x03A8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__PWM3_OUT(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__I2C4_SDA(p) PIN_CFG(0x0120, 0x03AC, 0x05C0, 0x4, 0x2, p) -#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK(p) PIN_CFG(0x0120, 0x03AC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__PWM4_OUT(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__I2C4_SCL(p) PIN_CFG(0x0124, 0x03B0, 0x05BC, 0x4, 0x2, p) -#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA(p) PIN_CFG(0x0124, 0x03B0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS(p) PIN_CFG(0x0128, 0x03B4, 0x0658, 0x1, 0x2, p) -#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA(p) PIN_CFG(0x0128, 0x03B4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS(p) PIN_CFG(0x012C, 0x03B8, 0x0658, 0x1, 0x3, p) -#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1(p) PIN_CFG(0x012C, 0x03B8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS(p) PIN_CFG(0x0130, 0x03BC, 0x0650, 0x1, 0x2, p) -#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2(p) PIN_CFG(0x0130, 0x03BC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS(p) PIN_CFG(0x0134, 0x03C0, 0x0650, 0x1, 0x3, p) -#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK(p) PIN_CFG(0x0134, 0x03C0, 0x061C, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3(p) PIN_CFG(0x0134, 0x03C0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__SPDIF_IN(p) PIN_CFG(0x0138, 0x03C4, 0x0618, 0x1, 0x2, p) -#define MX6UL_PAD_LCD_DATA08__CSI_DATA16(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__EIM_DATA00(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX(p) PIN_CFG(0x0138, 0x03C4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__CSI_DATA17(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__EIM_DATA01(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX(p) PIN_CFG(0x013C, 0x03C8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__CSI_DATA18(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__EIM_DATA02(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX(p) PIN_CFG(0x0140, 0x03CC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__CSI_DATA19(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__EIM_DATA03(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX(p) PIN_CFG(0x0144, 0x03D0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC(p) PIN_CFG(0x0148, 0x03D4, 0x060C, 0x1, 0x1, p) -#define MX6UL_PAD_LCD_DATA12__CSI_DATA20(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__EIM_DATA04(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY(p) PIN_CFG(0x0148, 0x03D4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK(p) PIN_CFG(0x014C, 0x03D8, 0x0608, 0x1, 0x1, p) -#define MX6UL_PAD_LCD_DATA13__CSI_DATA21(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__EIM_DATA05(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B(p) PIN_CFG(0x014C, 0x03D8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__CSI_DATA22(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__EIM_DATA06(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4(p) PIN_CFG(0x0150, 0x03DC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__CSI_DATA23(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__EIM_DATA07(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5(p) PIN_CFG(0x0154, 0x03E0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__UART7_TX(p) PIN_CFG(0x0158, 0x03E4, 0x0654, 0x1, 0x2, p) -#define MX6UL_PAD_LCD_DATA16__CSI_DATA01(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__EIM_DATA08(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6(p) PIN_CFG(0x0158, 0x03E4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__UART7_RX(p) PIN_CFG(0x015C, 0x03E8, 0x0654, 0x1, 0x3, p) -#define MX6UL_PAD_LCD_DATA17__CSI_DATA00(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__EIM_DATA09(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7(p) PIN_CFG(0x015C, 0x03E8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__PWM5_OUT(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__CSI_DATA10(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__EIM_DATA10(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD(p) PIN_CFG(0x0160, 0x03EC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__EIM_DATA11(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__PWM6_OUT(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA19__CSI_DATA11(p) PIN_CFG(0x0164, 0x03F0, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__EIM_DATA12(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__UART8_TX(p) PIN_CFG(0x0168, 0x03F4, 0x065C, 0x1, 0x2, p) -#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK(p) PIN_CFG(0x0168, 0x03F4, 0x0534, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA20__CSI_DATA12(p) PIN_CFG(0x0168, 0x03F4, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__UART8_RX(p) PIN_CFG(0x016C, 0x03F8, 0x065C, 0x1, 0x3, p) -#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__CSI_DATA13(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__EIM_DATA13(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1(p) PIN_CFG(0x016C, 0x03F8, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI(p) PIN_CFG(0x0170, 0x03FC, 0x053C, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__CSI_DATA14(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__EIM_DATA14(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2(p) PIN_CFG(0x0170, 0x03FC, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__MQS_LEFT(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO(p) PIN_CFG(0x0174, 0x0400, 0x0538, 0x2, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__CSI_DATA15(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__EIM_DATA15(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3(p) PIN_CFG(0x0174, 0x0400, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK(p) PIN_CFG(0x0178, 0x0404, 0x0670, 0x1, 0x2, p) -#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__KPP_ROW00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2(p) PIN_CFG(0x0178, 0x0404, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD(p) PIN_CFG(0x017C, 0x0408, 0x0678, 0x1, 0x2, p) -#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__KPP_COL00(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3(p) PIN_CFG(0x017C, 0x0408, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0(p) PIN_CFG(0x0180, 0x040C, 0x067C, 0x1, 0x2, p) -#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__KPP_ROW01(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__EIM_AD08(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY(p) PIN_CFG(0x0180, 0x040C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1(p) PIN_CFG(0x0184, 0x0410, 0x0680, 0x1, 0x2, p) -#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__KPP_COL01(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__EIM_AD09(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1(p) PIN_CFG(0x0184, 0x0410, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2(p) PIN_CFG(0x0188, 0x0414, 0x0684, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__KPP_ROW02(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__EIM_AD10(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2(p) PIN_CFG(0x0188, 0x0414, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3(p) PIN_CFG(0x018C, 0x0418, 0x0688, 0x1, 0x2, p) -#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__KPP_COL02(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__EIM_AD11(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3(p) PIN_CFG(0x018C, 0x0418, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4(p) PIN_CFG(0x0190, 0x041C, 0x068C, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK(p) PIN_CFG(0x0190, 0x041C, 0x0564, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_DATA04__EIM_AD12(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA04__UART2_TX(p) PIN_CFG(0x0190, 0x041C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5(p) PIN_CFG(0x0194, 0x0420, 0x0690, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI(p) PIN_CFG(0x0194, 0x0420, 0x056C, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_DATA05__EIM_AD13(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA05__UART2_RX(p) PIN_CFG(0x0194, 0x0420, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6(p) PIN_CFG(0x0198, 0x0424, 0x0694, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO(p) PIN_CFG(0x0198, 0x0424, 0x0568, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_DATA06__EIM_AD14(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS(p) PIN_CFG(0x0198, 0x0424, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7(p) PIN_CFG(0x019C, 0x0428, 0x0698, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__EIM_AD15(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS(p) PIN_CFG(0x019C, 0x0428, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_ALE__PWM3_OUT(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_ALE__EIM_ADDR17(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_ALE__GPIO4_IO10(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1(p) PIN_CFG(0x01A0, 0x042C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__PWM4_OUT(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__EIM_BCLK(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY(p) PIN_CFG(0x01A4, 0x0430, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_READY_B__UART3_TX(p) PIN_CFG(0x01A8, 0x0434, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK(p) PIN_CFG(0x01AC, 0x0438, 0x0554, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_CE0_B__UART3_RX(p) PIN_CFG(0x01AC, 0x0438, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI(p) PIN_CFG(0x01B0, 0x043C, 0x055C, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS(p) PIN_CFG(0x01B0, 0x043C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO(p) PIN_CFG(0x01B4, 0x0440, 0x0558, 0x3, 0x1, p) -#define MX6UL_PAD_NAND_CLE__EIM_ADDR16(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_CLE__GPIO4_IO15(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS(p) PIN_CFG(0x01B4, 0x0440, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_NAND_DQS__CSI_FIELD(p) PIN_CFG(0x01B8, 0x0444, 0x0530, 0x1, 0x1, p) -#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_NAND_DQS__PWM5_OUT(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_NAND_DQS__EIM_WAIT(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_NAND_DQS__GPIO4_IO16(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK(p) PIN_CFG(0x01B8, 0x0444, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_CMD__USDHC1_CMD(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_SD1_CMD__SPDIF_OUT(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_SD1_CMD__EIM_ADDR19(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_CMD__GPIO2_IO16(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR(p) PIN_CFG(0x01BC, 0x0448, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_CLK__USDHC1_CLK(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_SD1_CLK__SAI2_MCLK(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_SD1_CLK__SPDIF_IN(p) PIN_CFG(0x01C0, 0x044C, 0x0618, 0x3, 0x3, p) -#define MX6UL_PAD_SD1_CLK__EIM_ADDR20(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_CLK__GPIO2_IO17(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC(p) PIN_CFG(0x01C0, 0x044C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x1, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC(p) PIN_CFG(0x01C4, 0x0450, 0x05FC, 0x2, 0x1, p) -#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID(p) PIN_CFG(0x01C4, 0x0450, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_DATA1__GPT2_CLK(p) PIN_CFG(0x01C8, 0x0454, 0x05A0, 0x1, 0x1, p) -#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK(p) PIN_CFG(0x01C8, 0x0454, 0x05F8, 0x2, 0x1, p) -#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX(p) PIN_CFG(0x01C8, 0x0454, 0x0584, 0x3, 0x3, p) -#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR(p) PIN_CFG(0x01C8, 0x0454, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1(p) PIN_CFG(0x01CC, 0x0458, 0x0598, 0x1, 0x1, p) -#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC(p) PIN_CFG(0x01CC, 0x0458, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2(p) PIN_CFG(0x01D0, 0x045C, 0x059C, 0x1, 0x1, p) -#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX(p) PIN_CFG(0x01D0, 0x045C, 0x0588, 0x3, 0x3, p) -#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID(p) PIN_CFG(0x01D0, 0x045C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__CSI_MCLK(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B(p) PIN_CFG(0x01D4, 0x0460, 0x0674, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__I2C1_SDA(p) PIN_CFG(0x01D4, 0x0460, 0x05A8, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_MCLK__UART6_TX(p) PIN_CFG(0x01D4, 0x0460, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK(p) PIN_CFG(0x01D8, 0x0464, 0x0528, 0x0, 0x1, p) -#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP(p) PIN_CFG(0x01D8, 0x0464, 0x069C, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL(p) PIN_CFG(0x01D8, 0x0464, 0x05A4, 0x3, 0x2, p) -#define MX6UL_PAD_CSI_PIXCLK__EIM_OE(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_PIXCLK__UART6_RX(p) PIN_CFG(0x01D8, 0x0464, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC(p) PIN_CFG(0x01DC, 0x0468, 0x052C, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK(p) PIN_CFG(0x01DC, 0x0468, 0x0670, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA(p) PIN_CFG(0x01DC, 0x0468, 0x05B0, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__EIM_RW(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS(p) PIN_CFG(0x01DC, 0x0468, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC(p) PIN_CFG(0x01E0, 0x046C, 0x0524, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD(p) PIN_CFG(0x01E0, 0x046C, 0x0678, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL(p) PIN_CFG(0x01E0, 0x046C, 0x05AC, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS(p) PIN_CFG(0x01E0, 0x046C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__CSI_DATA02(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0(p) PIN_CFG(0x01E4, 0x0470, 0x067C, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK(p) PIN_CFG(0x01E4, 0x0470, 0x0544, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__EIM_AD00(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA00__UART5_TX(p) PIN_CFG(0x01E4, 0x0470, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__CSI_DATA03(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1(p) PIN_CFG(0x01E8, 0x0474, 0x0680, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__EIM_AD01(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA01__UART5_RX(p) PIN_CFG(0x01E8, 0x0474, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__CSI_DATA04(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2(p) PIN_CFG(0x01EC, 0x0478, 0x0684, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI(p) PIN_CFG(0x01EC, 0x0478, 0x054C, 0x3, 0x1, p) -#define MX6UL_PAD_CSI_DATA02__EIM_AD02(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS(p) PIN_CFG(0x01EC, 0x0478, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__CSI_DATA05(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3(p) PIN_CFG(0x01F0, 0x047C, 0x0688, 0x1, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO(p) PIN_CFG(0x01F0, 0x047C, 0x0548, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__EIM_AD03(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS(p) PIN_CFG(0x01F0, 0x047C, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA04__CSI_DATA06(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4(p) PIN_CFG(0x01F4, 0x0480, 0x068C, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK(p) PIN_CFG(0x01F4, 0x0480, 0x0534, 0x3, 0x1, p) -#define MX6UL_PAD_CSI_DATA04__EIM_AD04(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC(p) PIN_CFG(0x01F4, 0x0480, 0x05EC, 0x6, 0x1, p) -#define MX6UL_PAD_CSI_DATA04__USDHC1_WP(p) PIN_CFG(0x01F4, 0x0480, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__CSI_DATA07(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5(p) PIN_CFG(0x01F8, 0x0484, 0x0690, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x3, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__EIM_AD05(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK(p) PIN_CFG(0x01F8, 0x0484, 0x05E8, 0x6, 0x1, p) -#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B(p) PIN_CFG(0x01F8, 0x0484, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__CSI_DATA08(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6(p) PIN_CFG(0x01FC, 0x0488, 0x0694, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI(p) PIN_CFG(0x01FC, 0x0488, 0x053C, 0x3, 0x1, p) -#define MX6UL_PAD_CSI_DATA06__EIM_AD06(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B(p) PIN_CFG(0x01FC, 0x0488, 0x0000, 0x8, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__CSI_DATA09(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x0, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7(p) PIN_CFG(0x0200, 0x048C, 0x0698, 0x1, 0x2, p) -#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x2, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO(p) PIN_CFG(0x0200, 0x048C, 0x0538, 0x3, 0x1, p) -#define MX6UL_PAD_CSI_DATA07__EIM_AD07(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x4, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x6, 0x0, p) -#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT(p) PIN_CFG(0x0200, 0x048C, 0x0000, 0x8, 0x0, p) - -/* - * The TAMPER Pin can be used for GPIO, which depends on - * TAMPER_PIN_DISABLE[1:0] settings. - */ -#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00(p) PIN_CFG(0x001C, 0x02A8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01(p) PIN_CFG(0x0020, 0x02AC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02(p) PIN_CFG(0x0024, 0x02B0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03(p) PIN_CFG(0x0028, 0x02B4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04(p) PIN_CFG(0x002C, 0x02B8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05(p) PIN_CFG(0x0030, 0x02BC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06(p) PIN_CFG(0x0034, 0x02C0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07(p) PIN_CFG(0x0038, 0x02C4, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08(p) PIN_CFG(0x003C, 0x02C8, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09(p) PIN_CFG(0x0040, 0x02CC, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10(p) PIN_CFG(0x0014, 0x02A0, 0x0000, 0x5, 0x0, p) -#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11(p) PIN_CFG(0x0018, 0x02A4, 0x0000, 0x5, 0x0, p) - -#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/bsp/imx6ul/platform/include/mx6ul/iomux_register.h b/bsp/imx6ul/platform/include/mx6ul/iomux_register.h index c75a6617c9..fe92524cfb 100644 --- a/bsp/imx6ul/platform/include/mx6ul/iomux_register.h +++ b/bsp/imx6ul/platform/include/mx6ul/iomux_register.h @@ -1,5 +1,4 @@ #ifndef _IOMUX_REGISTER_H_ #define _IOMUX_REGISTER_H_ -#include "imx6ul-pinfunc.h" -#endif +#endif diff --git a/bsp/imx6ul/rtconfig.h b/bsp/imx6ul/rtconfig.h index 0d7aa807d2..4cc1b24df0 100644 --- a/bsp/imx6ul/rtconfig.h +++ b/bsp/imx6ul/rtconfig.h @@ -9,12 +9,8 @@ /* RT-Thread Kernel */ #define RT_NAME_MAX 8 -/* RT_USING_ARCH_DATA_TYPE is not set */ -/* RT_USING_SMP is not set */ #define RT_ALIGN_SIZE 4 -/* RT_THREAD_PRIORITY_8 is not set */ #define RT_THREAD_PRIORITY_32 -/* RT_THREAD_PRIORITY_256 is not set */ #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK @@ -22,19 +18,10 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 -/* RT_USING_TIMER_SOFT is not set */ + +/* kservice optimization */ + #define RT_DEBUG -/* RT_DEBUG_COLOR is not set */ -/* RT_DEBUG_INIT_CONFIG is not set */ -/* RT_DEBUG_THREAD_CONFIG is not set */ -/* RT_DEBUG_SCHEDULER_CONFIG is not set */ -/* RT_DEBUG_IPC_CONFIG is not set */ -/* RT_DEBUG_TIMER_CONFIG is not set */ -/* RT_DEBUG_IRQ_CONFIG is not set */ -/* RT_DEBUG_MEM_CONFIG is not set */ -/* RT_DEBUG_SLAB_CONFIG is not set */ -/* RT_DEBUG_MEMHEAP_CONFIG is not set */ -/* RT_DEBUG_MODULE_CONFIG is not set */ /* Inter-Thread communication */ @@ -43,41 +30,31 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE -/* RT_USING_SIGNALS is not set */ /* Memory Management */ #define RT_USING_MEMPOOL -/* RT_USING_MEMHEAP is not set */ -/* RT_USING_NOHEAP is not set */ #define RT_USING_SMALL_MEM -/* RT_USING_SLAB is not set */ -/* RT_USING_MEMTRACE is not set */ #define RT_USING_HEAP /* Kernel Device Object */ #define RT_USING_DEVICE -/* RT_USING_DEVICE_OPS is not set */ -/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x30105 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40004 #define ARCH_ARM -/* RT_USING_CPU_FFS is not set */ #define ARCH_ARM_CORTEX_A +#define RT_USING_GIC_V2 #define ARCH_ARM_CORTEX_A7 -/* ARCH_CPU_STACK_GROWS_UPWARD is not set */ /* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT -/* RT_USING_USER_MAIN is not set */ /* C++ features */ -/* RT_USING_CPLUSPLUS is not set */ /* Command shell */ @@ -87,14 +64,11 @@ #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB #define FINSH_USING_DESCRIPTION -/* FINSH_ECHO_DISABLE_DEFAULT is not set */ #define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_CMD_SIZE 80 -/* FINSH_USING_AUTH is not set */ #define FINSH_USING_MSH #define FINSH_USING_MSH_DEFAULT -/* FINSH_USING_MSH_ONLY is not set */ #define FINSH_ARG_MAX 10 /* Device virtual file system */ @@ -104,248 +78,98 @@ #define DFS_FILESYSTEMS_MAX 2 #define DFS_FILESYSTEM_TYPES_MAX 2 #define DFS_FD_MAX 16 -/* RT_USING_DFS_MNTTABLE is not set */ -/* RT_USING_DFS_ELMFAT is not set */ #define RT_USING_DFS_DEVFS -/* RT_USING_DFS_ROMFS is not set */ -/* RT_USING_DFS_RAMFS is not set */ -/* RT_USING_DFS_UFFS is not set */ -/* RT_USING_DFS_JFFS2 is not set */ /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 -/* RT_USING_SYSTEM_WORKQUEUE is not set */ #define RT_USING_SERIAL #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -/* RT_USING_CAN is not set */ -/* RT_USING_HWTIMER is not set */ -/* RT_USING_CPUTIME is not set */ -/* RT_USING_I2C is not set */ #define RT_USING_PIN -/* RT_USING_ADC is not set */ -/* RT_USING_PWM is not set */ -/* RT_USING_MTD_NOR is not set */ -/* RT_USING_MTD_NAND is not set */ -/* RT_USING_PM is not set */ -/* RT_USING_RTC is not set */ -/* RT_USING_SDIO is not set */ -/* RT_USING_SPI is not set */ -/* RT_USING_WDT is not set */ -/* RT_USING_AUDIO is not set */ -/* RT_USING_SENSOR is not set */ -/* RT_USING_TOUCH is not set */ -/* RT_USING_HWCRYPTO is not set */ -/* RT_USING_PULSE_ENCODER is not set */ -/* RT_USING_INPUT_CAPTURE is not set */ -/* RT_USING_WIFI is not set */ /* Using USB */ -/* RT_USING_USB_HOST is not set */ -/* RT_USING_USB_DEVICE is not set */ /* POSIX layer and C standard library */ #define RT_USING_LIBC -/* RT_USING_PTHREADS is not set */ #define RT_USING_POSIX -/* RT_USING_POSIX_MMAP is not set */ -/* RT_USING_POSIX_TERMIOS is not set */ -/* RT_USING_POSIX_AIO is not set */ -/* RT_USING_MODULE is not set */ +#define RT_LIBC_FIXED_TIMEZONE 8 /* Network */ /* Socket abstraction layer */ -/* RT_USING_SAL is not set */ /* Network interface device */ -/* RT_USING_NETDEV is not set */ /* light weight TCP/IP stack */ -/* RT_USING_LWIP is not set */ /* AT commands */ -/* RT_USING_AT is not set */ /* VBUS(Virtual Software BUS) */ -/* RT_USING_VBUS is not set */ /* Utilities */ -/* RT_USING_RYM is not set */ -/* RT_USING_ULOG is not set */ -/* RT_USING_UTEST is not set */ -/* RT_USING_LWP is not set */ + +/* RT-Thread Utestcases */ + /* RT-Thread online packages */ /* IoT - internet of things */ -/* PKG_USING_PAHOMQTT is not set */ -/* PKG_USING_WEBCLIENT is not set */ -/* PKG_USING_WEBNET is not set */ -/* PKG_USING_MONGOOSE is not set */ -/* PKG_USING_WEBTERMINAL is not set */ -/* PKG_USING_CJSON is not set */ -/* PKG_USING_JSMN is not set */ -/* PKG_USING_LIBMODBUS is not set */ -/* PKG_USING_FREEMODBUS is not set */ -/* PKG_USING_LJSON is not set */ -/* PKG_USING_EZXML is not set */ -/* PKG_USING_NANOPB is not set */ /* Wi-Fi */ /* Marvell WiFi */ -/* PKG_USING_WLANMARVELL is not set */ /* Wiced WiFi */ -/* PKG_USING_WLAN_WICED is not set */ -/* PKG_USING_RW007 is not set */ -/* PKG_USING_COAP is not set */ -/* PKG_USING_NOPOLL is not set */ -/* PKG_USING_NETUTILS is not set */ -/* PKG_USING_AT_DEVICE is not set */ -/* PKG_USING_ATSRV_SOCKET is not set */ -/* PKG_USING_WIZNET is not set */ /* IoT Cloud */ -/* PKG_USING_ONENET is not set */ -/* PKG_USING_GAGENT_CLOUD is not set */ -/* PKG_USING_ALI_IOTKIT is not set */ -/* PKG_USING_AZURE is not set */ -/* PKG_USING_TENCENT_IOTHUB is not set */ -/* PKG_USING_JIOT-C-SDK is not set */ -/* PKG_USING_NIMBLE is not set */ -/* PKG_USING_OTA_DOWNLOADER is not set */ -/* PKG_USING_IPMSG is not set */ -/* PKG_USING_LSSDP is not set */ -/* PKG_USING_AIRKISS_OPEN is not set */ -/* PKG_USING_LIBRWS is not set */ -/* PKG_USING_TCPSERVER is not set */ -/* PKG_USING_PROTOBUF_C is not set */ -/* PKG_USING_ONNX_PARSER is not set */ -/* PKG_USING_ONNX_BACKEND is not set */ /* security packages */ -/* PKG_USING_MBEDTLS is not set */ -/* PKG_USING_libsodium is not set */ -/* PKG_USING_TINYCRYPT is not set */ /* language packages */ -/* PKG_USING_LUA is not set */ -/* PKG_USING_JERRYSCRIPT is not set */ -/* PKG_USING_MICROPYTHON is not set */ /* multimedia packages */ -/* PKG_USING_OPENMV is not set */ -/* PKG_USING_MUPDF is not set */ -/* PKG_USING_STEMWIN is not set */ -/* PKG_USING_WAVPLAYER is not set */ -/* PKG_USING_TJPGD is not set */ /* tools packages */ -/* PKG_USING_CMBACKTRACE is not set */ -/* PKG_USING_EASYFLASH is not set */ -/* PKG_USING_EASYLOGGER is not set */ -/* PKG_USING_SYSTEMVIEW is not set */ -/* PKG_USING_RDB is not set */ -/* PKG_USING_QRCODE is not set */ -/* PKG_USING_ULOG_EASYFLASH is not set */ -/* PKG_USING_ADBD is not set */ /* system packages */ -/* PKG_USING_GUIENGINE is not set */ -/* PKG_USING_PERSIMMON is not set */ -/* PKG_USING_CAIRO is not set */ -/* PKG_USING_PIXMAN is not set */ -/* PKG_USING_LWEXT4 is not set */ -/* PKG_USING_PARTITION is not set */ -/* PKG_USING_FAL is not set */ -/* PKG_USING_SQLITE is not set */ -/* PKG_USING_RTI is not set */ -/* PKG_USING_LITTLEVGL2RTT is not set */ -/* PKG_USING_CMSIS is not set */ -/* PKG_USING_DFS_YAFFS is not set */ -/* PKG_USING_LITTLEFS is not set */ -/* PKG_USING_THREAD_POOL is not set */ -/* PKG_USING_ROBOTS is not set */ + +/* Micrium: Micrium software products porting for RT-Thread */ + /* peripheral libraries and drivers */ -/* PKG_USING_SENSORS_DRIVERS is not set */ -/* PKG_USING_REALTEK_AMEBA is not set */ -/* PKG_USING_SHT2X is not set */ -/* PKG_USING_STM32_SDIO is not set */ -/* PKG_USING_ICM20608 is not set */ -/* PKG_USING_U8G2 is not set */ -/* PKG_USING_BUTTON is not set */ -/* PKG_USING_PCF8574 is not set */ -/* PKG_USING_SX12XX is not set */ -/* PKG_USING_SIGNAL_LED is not set */ -/* PKG_USING_LEDBLINK is not set */ -/* PKG_USING_WM_LIBRARIES is not set */ -/* PKG_USING_KENDRYTE_SDK is not set */ -/* PKG_USING_INFRARED is not set */ -/* PKG_USING_ROSSERIAL is not set */ -/* PKG_USING_AT24CXX is not set */ -/* PKG_USING_MOTIONDRIVER2RTT is not set */ -/* PKG_USING_AD7746 is not set */ -/* PKG_USING_PCA9685 is not set */ -/* PKG_USING_I2C_TOOLS is not set */ -/* PKG_USING_NRF24L01 is not set */ -/* PKG_USING_TOUCH_DRIVERS is not set */ -/* PKG_USING_LCD_DRIVERS is not set */ -/* PKG_USING_MAX17048 is not set */ + +/* AI packages */ + /* miscellaneous packages */ -/* PKG_USING_LIBCSV is not set */ -/* PKG_USING_OPTPARSE is not set */ -/* PKG_USING_FASTLZ is not set */ -/* PKG_USING_MINILZO is not set */ -/* PKG_USING_QUICKLZ is not set */ -/* PKG_USING_MULTIBUTTON is not set */ -/* PKG_USING_FLEXIBLE_BUTTON is not set */ -/* PKG_USING_CANFESTIVAL is not set */ -/* PKG_USING_ZLIB is not set */ -/* PKG_USING_DSTR is not set */ -/* PKG_USING_TINYFRAME is not set */ -/* PKG_USING_KENDRYTE_DEMO is not set */ -/* PKG_USING_DIGITALCTRL is not set */ -/* PKG_USING_UPACKER is not set */ -/* PKG_USING_UPARAM is not set */ /* samples: kernel and components samples */ -/* PKG_USING_KERNEL_SAMPLES is not set */ -/* PKG_USING_FILESYSTEM_SAMPLES is not set */ -/* PKG_USING_NETWORK_SAMPLES is not set */ -/* PKG_USING_PERIPHERAL_SAMPLES is not set */ -/* PKG_USING_HELLO is not set */ -/* PKG_USING_VI is not set */ -/* PKG_USING_NNOM is not set */ -/* PKG_USING_LIBANN is not set */ -/* PKG_USING_ELAPACK is not set */ -/* PKG_USING_ARMv7M_DWT is not set */ -/* PKG_USING_VT100 is not set */ + +/* entertainment: terminal games and other interesting software packages */ + +#define RT_USING_UART1 #define SOC_MCIMX6X4 #endif diff --git a/bsp/imx6ul/rtconfig.py b/bsp/imx6ul/rtconfig.py index 0a9ea3dce3..258e035e5a 100644 --- a/bsp/imx6ul/rtconfig.py +++ b/bsp/imx6ul/rtconfig.py @@ -3,17 +3,11 @@ import os # toolchains options ARCH='arm' CPU='cortex-a' -CROSS_TOOL='gcc' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') +CROSS_TOOL=os.getenv('RTT_CC') or 'gcc' # only support GNU GCC compiler. PLATFORM = 'gcc' -EXEC_PATH = '/usr/bin' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') +EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin' BUILD = 'debug' @@ -33,8 +27,8 @@ if PLATFORM == 'gcc': DEVICE = ' -march=armv7-a -mtune=cortex-a9 -mfpu=vfpv3-d16 -ftree-vectorize -ffast-math -mfloat-abi=softfp' CFLAGS = DEVICE + ' -Wall' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' - LINK_SCRIPT = 'imx6.lds' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-imx6.map,-cref,-u,system_vectors'+\ + LINK_SCRIPT = 'link.lds' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors'+\ ' -T %s' % LINK_SCRIPT CPATH = ''