diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_can.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_can.c index 2b02447d86..1847d584c2 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_can.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_can.c @@ -28,12 +28,12 @@ struct ch32v307x_can_baud_info { - uint32_t baud_rate; - uint16_t prescaler; - uint8_t tsjw; //CAN synchronisation jump width. - uint8_t tbs1; //CAN time quantum in bit segment 1. - uint8_t tbs2; //CAN time quantum in bit segment 2. - uint8_t notused; + rt_uint32_t baud_rate; + rt_uint16_t prescaler; + rt_uint8_t tsjw; //CAN synchronisation jump width. + rt_uint8_t tbs1; //CAN time quantum in bit segment 1. + rt_uint8_t tbs2; //CAN time quantum in bit segment 2. + rt_uint8_t notused; }; #define CH32V307X_CAN_BAUD_DEF(xrate, xsjw, xbs1, xbs2, xprescale) \ @@ -165,7 +165,7 @@ rt_weak void ch32v307x_can_gpio_init(CAN_TypeDef *can_base) static uint32_t get_can_baud_index(rt_uint32_t baud) { - uint32_t len, index; + rt_uint32_t len, index; len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]); for (index = 0; index < len; index++) @@ -176,9 +176,9 @@ static uint32_t get_can_baud_index(rt_uint32_t baud) return 0; /* default baud is CAN1MBaud */ } -static uint8_t get_can_mode_rtt2n32(uint8_t rtt_can_mode) +static rt_uint8_t get_can_mode_rtt2n32(rt_uint8_t rtt_can_mode) { - uint8_t mode = CAN_Mode_Normal; + rt_uint8_t mode = CAN_Mode_Normal; switch (rtt_can_mode) { case RT_CAN_MODE_NORMAL: @@ -558,9 +558,9 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) } /* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) +#define TMIDxR_TXRQ ((rt_uint32_t)0x00000001) -static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint32_t mailbox_index) +static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t mailbox_index) { CanTxMsg CAN_TxMessage = {0}; CanTxMsg *TxMessage = &CAN_TxMessage; @@ -629,20 +629,20 @@ static int _can_send_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint3 /* Set DLC */ TxMessage->DLC = pmsg->len & 0x0FU; - can_base->sTxMailBox[mailbox_index].TXMDTR &= (uint32_t)0xFFFFFFF0; + can_base->sTxMailBox[mailbox_index].TXMDTR &= (rt_uint32_t)0xFFFFFFF0; can_base->sTxMailBox[mailbox_index].TXMDTR |= TxMessage->DLC; /* Set data */ can_base->sTxMailBox[mailbox_index].TXMDHR = - (((uint32_t)pmsg->data[7] << 24) | - ((uint32_t)pmsg->data[6] << 16) | - ((uint32_t)pmsg->data[5] << 8) | - ((uint32_t)pmsg->data[4])); + (((rt_uint32_t)pmsg->data[7] << 24) | + ((rt_uint32_t)pmsg->data[6] << 16) | + ((rt_uint32_t)pmsg->data[5] << 8) | + ((rt_uint32_t)pmsg->data[4])); can_base->sTxMailBox[mailbox_index].TXMDLR = - (((uint32_t)pmsg->data[3] << 24) | - ((uint32_t)pmsg->data[2] << 16) | - ((uint32_t)pmsg->data[1] << 8) | - ((uint32_t)pmsg->data[0])); + (((rt_uint32_t)pmsg->data[3] << 24) | + ((rt_uint32_t)pmsg->data[2] << 16) | + ((rt_uint32_t)pmsg->data[1] << 8) | + ((rt_uint32_t)pmsg->data[0])); /* Request transmission */ can_base->sTxMailBox[mailbox_index].TXMIR |= TMIDxR_TXRQ; @@ -665,7 +665,7 @@ static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t return _can_send_rtmsg(drv_can_obj->can_base, ((struct rt_can_msg *)buf), box_num); } -static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint32_t FIFONum) +static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, rt_uint32_t FIFONum) { CanRxMsg CAN_RxMessage = {0}; CanRxMsg *RxMessage = &CAN_RxMessage; @@ -676,30 +676,30 @@ static int _can_recv_rtmsg(CAN_TypeDef *can_base, struct rt_can_msg *pmsg, uint3 return -RT_ERROR; } /* Get the Id */ - RxMessage->IDE = (uint8_t)(0x04 & can_base->sFIFOMailBox[FIFONum].RXMIR); + RxMessage->IDE = (rt_uint8_t)(0x04 & can_base->sFIFOMailBox[FIFONum].RXMIR); if (RxMessage->IDE == CAN_Id_Standard) { - RxMessage->StdId = (uint32_t)0x000007FF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 21); + RxMessage->StdId = (rt_uint32_t)0x000007FF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 21); } else { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 3); + RxMessage->ExtId = (rt_uint32_t)0x1FFFFFFF & (can_base->sFIFOMailBox[FIFONum].RXMIR >> 3); } - RxMessage->RTR = (uint8_t)0x02 & can_base->sFIFOMailBox[FIFONum].RXMIR; + RxMessage->RTR = (rt_uint8_t)0x02 & can_base->sFIFOMailBox[FIFONum].RXMIR; /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & can_base->sFIFOMailBox[FIFONum].RXMDTR; + RxMessage->DLC = (rt_uint8_t)0x0F & can_base->sFIFOMailBox[FIFONum].RXMDTR; /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDTR >> 8); + RxMessage->FMI = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDTR >> 8); /* Get the data field */ - pmsg->data[0] = (uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR; - pmsg->data[1] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 8); - pmsg->data[2] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 16); - pmsg->data[3] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 24); - pmsg->data[4] = (uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR; - pmsg->data[5] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 8); - pmsg->data[6] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 16); - pmsg->data[7] = (uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 24); + pmsg->data[0] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDLR; + pmsg->data[1] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 8); + pmsg->data[2] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 16); + pmsg->data[3] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDLR >> 24); + pmsg->data[4] = (rt_uint8_t)0xFF & can_base->sFIFOMailBox[FIFONum].RXMDHR; + pmsg->data[5] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 8); + pmsg->data[6] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 16); + pmsg->data[7] = (rt_uint8_t)0xFF & (can_base->sFIFOMailBox[FIFONum].RXMDHR >> 24); /* get len */ pmsg->len = RxMessage->DLC; diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_dac.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_dac.c index 80fdacf14d..877c16bfe2 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_dac.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_dac.c @@ -106,7 +106,7 @@ static rt_uint32_t ch32_dac_get_channel(rt_uint32_t channel) static rt_err_t ch32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value) { - uint32_t dac_channel; + rt_uint32_t dac_channel; DAC_HandleTypeDef *ch32_dac_handler; RT_ASSERT(device != RT_NULL); diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c index 32b37fd506..59f30f023a 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c @@ -13,11 +13,11 @@ #ifdef BSP_USING_GPIO #define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) -#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) -#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) +#define PIN_PORT(pin) ((rt_uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((rt_uint8_t)((pin) & 0xFu)) #define PIN_STPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) -#define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) +#define PIN_STPIN(pin) ((rt_uint16_t)(1u << PIN_NO(pin))) #if defined(GPIOZ) #define __CH32_PORT_MAX 12u @@ -89,7 +89,7 @@ static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, }; -static uint32_t pin_irq_enable_mask = 0; +static rt_uint32_t pin_irq_enable_mask = 0; #define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0])) @@ -133,7 +133,7 @@ static rt_base_t ch32_pin_get(const char *name) static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) { GPIO_TypeDef *gpio_port; - uint16_t gpio_pin; + rt_uint16_t gpio_pin; if (PIN_PORT(pin) < PIN_STPORT_MAX) { @@ -146,7 +146,7 @@ static void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) static int ch32_pin_read(rt_device_t dev, rt_base_t pin) { GPIO_TypeDef *gpio_port; - uint16_t gpio_pin; + rt_uint16_t gpio_pin; int value = PIN_LOW; if (PIN_PORT(pin) < PIN_STPORT_MAX) @@ -215,7 +215,7 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) return -1; } -rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint32_t pinbit) { rt_int32_t mapindex = bit2bitno(pinbit); if (mapindex < 0 || mapindex >= (rt_int32_t)ITEM_NUM(pin_irq_map)) @@ -426,7 +426,7 @@ rt_inline void pin_irq_hdr(int irqno) } } -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +void HAL_GPIO_EXTI_Callback(rt_uint16_t GPIO_Pin) { pin_irq_hdr(bit2bitno(GPIO_Pin)); } diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c index 38432c1083..c4f227156b 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c @@ -210,12 +210,12 @@ static rt_err_t ch32_hwtimer_start(struct rt_hwtimer_device *timer, rt_uint32_t if (mode == HWTIMER_MODE_ONESHOT) { /* set timer to single mode */ - tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); tim->instance->CTLR1 |= TIM_OPMode_Single; } else { - tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); tim->instance->CTLR1 |= TIM_OPMode_Repetitive; } @@ -302,12 +302,12 @@ static rt_err_t ch32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_ if (*(rt_hwtimer_mode_t *)args == HWTIMER_MODE_ONESHOT) { /* set timer to single mode */ - tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); tim->instance->CTLR1 |= TIM_OPMode_Single; } else { - tim->instance->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + tim->instance->CTLR1 &= (rt_uint16_t) ~((rt_uint16_t)TIM_OPM); tim->instance->CTLR1 |= TIM_OPMode_Repetitive; } break; diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.c b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.c index d2a48983a2..89d11a0878 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.c +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.c @@ -66,9 +66,9 @@ static struct ch32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = static rt_uint32_t ch32_spi_clock_get(SPI_TypeDef *spix); static void ch32_spi_clock_and_io_init(SPI_TypeDef *spix); static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData); -static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, uint8_t *recv_buf, uint16_t send_length); -static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t send_length); -static rt_err_t spi_receive(SPI_TypeDef *Instance, uint8_t *recv_buf,uint16_t send_length); +static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint8_t *recv_buf, rt_uint16_t send_length); +static rt_err_t spi_transmit(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint16_t send_length); +static rt_err_t spi_receive(SPI_TypeDef *Instance, rt_uint8_t *recv_buf,rt_uint16_t send_length); static void ch32_spi_clock_and_io_init(SPI_TypeDef *spix) { @@ -168,7 +168,7 @@ static rt_uint32_t ch32_spi_clock_get(SPI_TypeDef *spix) * */ static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData) { - uint8_t i=0; + rt_uint8_t i=0; while (SPI_I2S_GetFlagStatus(Instance, SPI_I2S_FLAG_TXE) == RESET) { i++; @@ -188,9 +188,9 @@ static rt_uint8_t spix_readwritebyte(SPI_TypeDef *Instance, rt_uint8_t TxData) /* *spi transmit and receive * */ -static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, uint8_t *recv_buf, uint16_t send_length) +static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint8_t *recv_buf, rt_uint16_t send_length) { - uint16_t i=0; + rt_uint16_t i=0; for(i = 0; i < send_length; i++) { recv_buf[i] = spix_readwritebyte(Instance, send_buf[i]); @@ -201,9 +201,9 @@ static rt_err_t spi_transmitreceive(SPI_TypeDef *Instance, uint8_t *send_buf, ui /* *spi transmit * */ -static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t send_length) +static rt_err_t spi_transmit(SPI_TypeDef *Instance, rt_uint8_t *send_buf, rt_uint16_t send_length) { - uint16_t i=0; + rt_uint16_t i=0; for(i = 0; i < send_length; i++) { spix_readwritebyte(Instance, send_buf[i]); @@ -214,9 +214,9 @@ static rt_err_t spi_transmit(SPI_TypeDef *Instance, uint8_t *send_buf, uint16_t /* *spi receive * */ -static rt_err_t spi_receive(SPI_TypeDef *Instance, uint8_t *recv_buf,uint16_t send_length) +static rt_err_t spi_receive(SPI_TypeDef *Instance, rt_uint8_t *recv_buf,rt_uint16_t send_length) { - uint16_t i=0; + rt_uint16_t i=0; for(i = 0; i < send_length; i++) { recv_buf[i] = spix_readwritebyte(Instance, 0xFF); /*发送数据为0xff 此时显示为不发送*/ @@ -285,7 +285,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat spi_handle->Init.SPI_NSS = SPI_NSS_Soft; //device is not RT_NULL, so spi_bus not need check - uint32_t SPI_APB_CLOCK; + rt_uint32_t SPI_APB_CLOCK; ch32_spi_clock_and_io_init(spi_handle->Instance); SPI_APB_CLOCK = ch32_spi_clock_get(spi_handle->Instance); @@ -311,7 +311,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat } else if (cfg->max_hz >= SPI_APB_CLOCK / 64) { - spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; + spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; } else if (cfg->max_hz >= SPI_APB_CLOCK / 128) { @@ -322,11 +322,11 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat /* min prescaler 256 */ spi_handle->Init.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; } - LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d", - HAL_RCC_GetSysClockFreq(), - SPI_APB_CLOCK, - cfg->max_hz, - spi_handle->Init.SPI_BaudRatePrescaler); + LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d", + HAL_RCC_GetSysClockFreq(), + SPI_APB_CLOCK, + cfg->max_hz, + spi_handle->Init.SPI_BaudRatePrescaler); if (cfg->mode & RT_SPI_MSB) { @@ -342,7 +342,7 @@ static rt_err_t ch32_spi_init(struct ch32_spi *spi_drv, struct rt_spi_configurat SPI_Cmd(spi_handle->Instance, ENABLE); - LOG_D("%s init done", spi_drv->config->bus_name); + LOG_D("%s init done", spi_drv->config->bus_name); return RT_EOK; } @@ -358,9 +358,9 @@ static rt_err_t spi_configure(struct rt_spi_device *device, return ch32_spi_init(spi_drv, configuration); } -static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +static rt_ssize_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) { - rt_err_t state; + rt_err_t state = RT_EOK; rt_size_t message_length, already_send_length; rt_uint16_t send_length; rt_uint8_t *recv_buf; @@ -384,11 +384,11 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_RESET); } - LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); - LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", - spi_drv->config->bus_name, - (uint32_t)message->send_buf, - (uint32_t)message->recv_buf, message->length); + LOG_D("%s transfer prepare and start", spi_drv->config->bus_name); + LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", + spi_drv->config->bus_name, + (rt_uint32_t)message->send_buf, + (rt_uint32_t)message->recv_buf, message->length); message_length = message->length; recv_buf = message->recv_buf; @@ -416,12 +416,12 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message /* start once data exchange */ if (message->send_buf && message->recv_buf) { - state = spi_transmitreceive(spi_handle->Instance, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length); + state = spi_transmitreceive(spi_handle->Instance, (rt_uint8_t *)send_buf, (rt_uint8_t *)recv_buf, send_length); } else if (message->send_buf) { - state = spi_transmit(spi_handle->Instance, (uint8_t *)send_buf, send_length); + state = spi_transmit(spi_handle->Instance, (rt_uint8_t *)send_buf, send_length); if (message->cs_release && (device->config.mode & RT_SPI_3WIRE)) { /* release the CS by disable SPI when using 3 wires SPI */ @@ -430,20 +430,20 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message } else { - memset((uint8_t *)recv_buf, 0xff, send_length); + rt_memset((rt_uint8_t *)recv_buf, 0xff, send_length); /* clear the old error flag */ SPI_I2S_ClearFlag(spi_handle->Instance, SPI_I2S_FLAG_OVR); - state = spi_receive(spi_handle->Instance, (uint8_t *)recv_buf, send_length); + state = spi_receive(spi_handle->Instance, (rt_uint8_t *)recv_buf, send_length); } if (state != RT_EOK) { - LOG_I("spi transfer error : %d", state); + LOG_I("spi transfer error : %d", state); message->length = 0; } else { - LOG_D("%s transfer done", spi_drv->config->bus_name); + LOG_D("%s transfer done", spi_drv->config->bus_name); } } @@ -456,6 +456,11 @@ static rt_uint32_t spi_xfer(struct rt_spi_device *device, struct rt_spi_message GPIO_WriteBit(cs->GPIOx, cs->GPIO_Pin, Bit_SET); } + if(state != RT_EOK) + { + return -RT_ERROR; + } + return message->length; } @@ -478,7 +483,7 @@ static int rt_hw_spi_bus_init(void) result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &ch32_spi_ops); RT_ASSERT(result == RT_EOK); - LOG_D("%s bus init done", spi_config[i].bus_name); + LOG_D("%s bus init done", spi_config[i].bus_name); } return result; @@ -487,7 +492,7 @@ static int rt_hw_spi_bus_init(void) /** * Attach the spi device to SPI bus, this function must be used after initialization. */ -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin) +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, rt_uint16_t cs_gpio_pin) { RT_ASSERT(bus_name != RT_NULL); RT_ASSERT(device_name != RT_NULL); diff --git a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.h b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.h index 42ab229e61..7a6458d7e9 100644 --- a/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.h +++ b/bsp/wch/risc-v/Libraries/ch32_drivers/drv_spi.h @@ -22,16 +22,10 @@ extern "C" { #endif /* ifdef __cplusplus */ -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin); - -#ifdef __cplusplus -} -#endif /* ifdef __cplusplus */ - struct ch32_hw_spi_cs { GPIO_TypeDef* GPIOx; - uint16_t GPIO_Pin; + rt_uint16_t GPIO_Pin; }; struct ch32_spi_config @@ -56,17 +50,17 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + rt_uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + rt_uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - volatile uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + volatile rt_uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + rt_uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + rt_uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - volatile uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + volatile rt_uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ } SPI_HandleTypeDef; @@ -82,6 +76,11 @@ struct ch32_spi }; -rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin); + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, rt_uint16_t cs_gpio_pin); + +#ifdef __cplusplus +} +#endif /* ifdef __cplusplus */ #endif /*__DRV_SPI_H__ */