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[bsp] Remove none-released porting

This commit is contained in:
Bernard Xiong 2014-07-12 11:08:38 +08:00
parent 23686587ff
commit 2604440ceb
50 changed files with 0 additions and 4919 deletions
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13
bsp/dev3210/SConscript
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@ -1,13 +0,0 @@
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
if GetDepend('RT_USING_NEWLIB'):
src_bsp = src_bsp + ['newlib_stub.c']
src_drv = ['uart.c', 'lnn800x480.c']
src = File(src_bsp + src_drv)
CPPPATH = [GetCurrentDir()]
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

29
bsp/dev3210/SConstruct
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@ -1,29 +0,0 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)

119
bsp/dev3210/application.c
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rtthread.h>
#include <soc3210.h>
#ifdef RT_USING_DFS
#include <dfs.h>
#include <dfs_elm.h>
#ifdef RT_USING_DFS_ROMFS
#include <dfs_romfs.h>
#endif
#ifdef RT_USING_DFS_DEVFS
#include <devfs.h>
#endif
#endif
#ifdef RT_USING_RTGUI
#include <rtgui/rtgui.h>
#include <rtgui/event.h>
#include <rtgui/rtgui_server.h>
#endif
void rt_init_thread_entry(void *parameter)
{
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
/* init the device filesystem */
dfs_init();
#if defined(RT_USING_DFS_ROMFS)
dfs_romfs_init();
if (dfs_mount(RT_NULL, "/", "rom", 0, &romfs_root) == 0)
{
rt_kprintf("ROM File System initialized!\n");
}
else
rt_kprintf("ROM File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_ELMFAT)
/* init the elm chan FatFs filesystam*/
elm_init();
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/sd", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
rt_kprintf("File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_DEVFS)
devfs_init();
if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
rt_kprintf("Device File System initialized!\n");
else
rt_kprintf("Device File System initialzation failed!\n");
#ifdef RT_USING_NEWLIB
/* init libc */
libc_system_init("uart");
rt_kprintf("libc init done\n");
#endif
#endif
}
#endif
#ifdef RT_USING_RTGUI
{
rtgui_rect_t rect;
rtgui_system_server_init();
/* register dock panel */
rect.x1 = 0;
rect.y1 = 0;
rect.x2 = 400;
rect.y2 = 480;
// rtgui_panel_register("panel", &rect);
/* register main panel */
rect.x1 = 400;
rect.y1 = 0;
rect.x2 = 800;
rect.y2 = 480;
// rtgui_panel_register("main", &rect);
// rtgui_panel_set_default_focused("main");
rt_hw_lcd_init();
}
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
/* create initialization thread */
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
4096, 8, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}

103
bsp/dev3210/board.c
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@ -1,103 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init(void)
{
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart");
#endif
/* init operating system timer */
rt_hw_timer_init();
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
/*@}*/
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_console_output(const char *ptr)
{
/* stream mode */
while (*ptr)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(UART0_BASE) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(UART0_BASE) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(UART0_BASE) = *ptr;
ptr ++;
}
}

24
bsp/dev3210/board.h
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@ -1,24 +0,0 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2010, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
/* 32M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
#define CPU_HZ (250 * 1000000)
#endif

119
bsp/dev3210/dev3210_ram.lds
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@ -1,119 +0,0 @@
/*
* File : jz47xx_ram.lds
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard move the beginning entry to 0x80200000
*/
OUTPUT_ARCH(mips)
GROUP(-lgcc -lc)
ENTRY(_start)
SECTIONS
{
. = 0x80200000 ;
.start :
{
*(.start);
}
. = ALIGN(4);
.text :
{
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.rodata1)
*(.rodata1.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
}
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

11
bsp/dev3210/dw.txt
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# download script for boot loader
ifaddr dmfe0 192.168.1.100
load tftp://192.168.1.5/boot_3210 0x80200000
# download script for RT-Thread
ifaddr dmfe0 192.168.1.100
load tftp://192.168.1.5/rtthread.elf
# burn script for RT-Thread
ifaddr dmfe0 192.168.1.100
devcp tftp://192.168.1.5/rtthread.elf /dev/mtd0

102
bsp/dev3210/lnn800x480.c
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@ -1,102 +0,0 @@
/*
* File : lnn800x480.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-01-01 bernard first version from QiuYi's driver
*/
#include <rtthread.h>
#include <soc3210.h>
/* LCD driver for 800x480 16bit */
#define RT_HW_LCD_WIDTH 800
#define RT_HW_LCD_HEIGHT 480
#define K1BASE 0xA0000000
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * RT_HW_LCD_WIDTH * 2) + x * 2)
ALIGN(4)
volatile rt_uint16_t _rt_framebuffer[RT_HW_LCD_HEIGHT][RT_HW_LCD_WIDTH];
static struct rt_device_graphic_info _lcd_info;
static rt_err_t rt_lcd_init (rt_device_t dev)
{
/* disable LCD controller */
LCD_CTRL = LCD_CTRL & 0xfffe;
/* set LCD clock */
HSB_MISC_REG = (HSB_MISC_REG & 0xFFFD01FF) |
(0x01 << 17) | /* enable LCD */
(0x05 << 9); /* clock */
LCD_VBARA = (rt_uint32_t)_rt_framebuffer - 0x80000000;
LCD_VBARB = (rt_uint32_t)_rt_framebuffer - 0x80000000;
LCD_HTIM = 0x12c031f;
LCD_VTIM = 0x11501df;
LCD_HVLEN = 0x41e0279;
LCD_CTRL = 0x8709;
rt_kprintf("VBARA 0x%08x\n", LCD_VBARA);
rt_kprintf("CTRL 0x%08x\n", LCD_CTRL);
rt_kprintf("HTIM 0x%08x\n", LCD_HTIM);
rt_kprintf("VTIM 0x%08x\n", LCD_VTIM);
rt_kprintf("HVLEN 0x%08x\n", LCD_HVLEN);
rt_kprintf("HSB_MISC 0x%08x\n", HSB_MISC_REG);
return RT_EOK;
}
static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
}
void rt_hw_lcd_init(void)
{
rt_device_t lcd = rt_malloc(sizeof(struct rt_device));
if (lcd == RT_NULL)
return; /* no memory yet */
_lcd_info.bits_per_pixel = 16;
_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_lcd_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
_lcd_info.width = RT_HW_LCD_WIDTH;
_lcd_info.height = RT_HW_LCD_HEIGHT;
/* init device structure */
lcd->type = RT_Device_Class_Graphic;
lcd->init = rt_lcd_init;
lcd->open = RT_NULL;
lcd->close = RT_NULL;
lcd->control = rt_lcd_control;
lcd->user_data = (void*)&_lcd_info;
/* register lcd device to RT-Thread */
rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR);
}

43
bsp/dev3210/newlib_stub.c
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/*
* File : newlib_stub.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
/* some newlib leaked function in CodeSourcery G++ Lite for MIPS version */
int getpid(void)
{
return 0;
}
int gettimeofday(struct timeval *__tp, void *__tzp)
{
struct timespec tp;
if (libc_get_time(&tp) == 0)
{
if (__tp != RT_NULL)
{
__tp->tv_sec = tp.tv_sec;
__tp->tv_usec = tp.tv_nsec * 1000UL;
}
return tp.tv_sec;
}
return 0;
}

169
bsp/dev3210/rtconfig.h
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@ -1,169 +0,0 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 10
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 256
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_INTERRUPT_INFO
/* Using Hook */
#define RT_USING_HOOK
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore */
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
/* Using SLAB MM */
#define RT_USING_SLAB
/* #define RT_USING_SMALL_MEM */
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_UART
#define RT_USING_UART1
#define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */
/* the buffer size of console */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: the runtime libc library */
/* the runtime libc library */
/* #define RT_USING_NEWLIB */
/* #define RT_USING_PTHREADS */
/* SECTION: finsh, a C-Express shell */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_DEVICE_NAME "uart"
/* SECTION: device filesystem support */
#define RT_USING_DFS
/* #define RT_USING_DFS_ELMFAT */
#define RT_USING_DFS_ROMFS
/* #define RT_USING_DFS_DEVFS */
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 4
/* Using working directory */
#define DFS_USING_WORKDIR
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable DNS */
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* SECTION: RT-Thread/GUI */
// #define RT_USING_RTGUI
#ifdef RT_USING_RTGUI
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support 12 weight font */
#define RTGUI_USING_FONT12
/* support Chinese font */
#define RTGUI_USING_FONTHZ
/* use DFS as file interface */
#define RTGUI_USING_DFS_FILERW
/* use bmp font as Chinese font */
#define RTGUI_USING_HZ_BMP
/* use small size in RTGUI */
#define RTGUI_USING_SMALL_SIZE
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
#endif // RT_USING_RTGUI
#endif

59
bsp/dev3210/rtconfig.py
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@ -1,59 +0,0 @@
import os
# CPU options
ARCH='mips'
CPU ='loongson'
# toolchains options
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_MIPS_ELF/bin'
elif CROSS_TOOL == 'keil':
print '================ERROR============================'
print 'Not support keil yet!'
print '================================================='
exit(0)
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support iar yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
PREFIX = 'mips-sde-elf-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips2'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread-3210.map,-cref,-u,Reset_Handler -T dev3210_ram.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

92
bsp/dev3210/startup.c
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@ -1,92 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <cache.h>
#include "board.h"
#define A_K0BASE 0x80000000
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern unsigned char __bss_start;
extern unsigned char __bss_end;
extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init cache */
rt_hw_cache_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* copy vector */
memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
/* init board */
rt_hw_board_init();
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device(FINSH_DEVICE_NAME);
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
/*@}*/

295
bsp/dev3210/uart.c
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@ -1,295 +0,0 @@
/*
* File : uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
struct rt_uart_soc3210
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
rt_ubase_t level;
rt_uint8_t isr;
struct rt_uart_soc3210* uart = &uart_device;
/* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3;
if (isr & 0x02) /* receive data available */
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if (uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init (rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
#if 0
/* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
/* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x3;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
/* Enable UART unit, enable and clear FIFO */
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
#endif
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_uint8_t *ptr;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_soc3210 *uart = (struct rt_uart_soc3210 *)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size != 0)
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_soc3210 *uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART1)
uart->hw_base = UART0_BASE;
uart->irq = IRQ_UART0;
#elif defined(RT_USING_UART2)
uart->hw_base = UART1_BASE;
uart->irq = IRQ_UART1;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/

19
bsp/dev3210/uart.h
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@ -1,19 +0,0 @@
/*
* File : uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009 - 2012, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
*/
#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif

12
bsp/jz47xx/SConscript
View File

@ -1,12 +0,0 @@
import rtconfig
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
src_drv = ['uart.c']
src = File(src_bsp + src_drv)
CPPPATH = str(Dir('#'))
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

29
bsp/jz47xx/SConstruct
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@ -1,29 +0,0 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-jz47xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)

50
bsp/jz47xx/application.c
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@ -1,50 +0,0 @@
/*
* File : app.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
/**
* @addtogroup JZ47xx
*/
/*@{*/
#include <rtthread.h>
#include <jz4755.h>
static struct rt_thread thread1;
static rt_uint8_t thread1_stack[1024];
void thread_entry(void* parameter)
{
while (1)
{
rt_kprintf("IPR: 0x%08x, SR : 0x%08x, CAUSE: 0x%08x\n", INTC_IPR, read_c0_status(), read_c0_cause());
rt_thread_delay(100);
}
}
int rt_application_init()
{
rt_err_t result;
result = rt_thread_init(&thread1, "t1",
thread_entry, RT_NULL,
&thread1_stack[0], sizeof(thread1_stack),
200, 10);
if (result == RT_EOK)
rt_thread_startup(&thread1);
return 0;
}
/*@}*/

87
bsp/jz47xx/board.c
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@ -1,87 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include <jz4755.h>
/**
* @addtogroup JZ47xx
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(int vector, void* param)
{
/* increase a OS tick */
rt_tick_increase();
/* clear flag */
TCU_TFCR = TCU_TFCR_OSTFLAG;
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
rt_uint32_t val;
/* disable TCU clock */
CPM_CLKGR &= ~CPM_CLKGR_TCU;
TCU_TECR = TCU_TECR_OSTCL;
/* set */
OST_DR = RT_TICK_PER_SECOND * 0xcffff;
/* clear counter */
OST_CNT = 0;
#ifdef RTC_SRC_EXTAL
OST_CSR = (val | OST_TCSR_EXT_EN);
#else
OST_CSR = (val | OST_TCSR_PCLK_EN);
#endif
TCU_TFCR = TCU_TFCR_OSTFLAG;
TCU_TMCR = TCU_TMCR_OSTMCL;
TCU_TESR = TCU_TESR_OSTST;
rt_hw_interrupt_install(IRQ_TCU0, rt_hw_timer_handler, RT_NULL, "tick");
rt_hw_interrupt_umask (IRQ_TCU0);
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init()
{
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart");
#endif
/* init operating system timer */
rt_hw_timer_init();
}
/*@}*/

23
bsp/jz47xx/board.h
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@ -1,23 +0,0 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
/* 32M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
#endif

154
bsp/jz47xx/jz47xx_ram.lds
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@ -1,154 +0,0 @@
/*
* File : jz47xx_ram.lds
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-08-23 bernard change to jz47xx
* 2010-09-04 bernard move the beginning entry to 0x80100000
*/
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
OUTPUT_ARCH(mips)
MEMORY
{
/* 16M SDRAM */
DRAM : ORIGIN = 0x80100000, LENGTH = 0x01000000
/* 16K SRAM */
IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000
}
ENTRY(_start)
SECTIONS
{
. = 0x80100000 ;
.start :
{
*(.start);
} > DRAM
. = ALIGN(4);
.text :
{
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.rodata1)
*(.rodata1.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
} > DRAM
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
} > DRAM
. = ALIGN(4);
_iramat = .;
.iram : AT(_iramat)
{
_iramstart = .;
*(.vectors.1);
. = 0x100;
*(.vectors.2);
. = 0x180;
*(.vectors.3);
. = 0x200;
*(.vectors.4);
*(.vectors);
*(.icode);
*(.irodata);
*(.idata);
KEEP(*(.vectors*))
_iramend = .;
} > IRAM
_iramcopy = LOADADDR(.iram);
.sbss :
{
__bss_start = .;
*(.sbss)
*(.sbss.*)
*(.dynsbss)
*(.scommon)
} > DRAM
.bss :
{
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
__bss_end = .;
} > DRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

153
bsp/jz47xx/rtconfig.h
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@ -1,153 +0,0 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 10
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 256
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_INTERRUPT_INFO
/* Using Hook */
#define RT_USING_HOOK
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 10
/* SECTION: IPC */
/* Using Semaphore */
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_UART
#define RT_USING_UART1
#define RT_UART_RX_BUFFER_SIZE 64
/* SECTION: Console options */
/* the buffer size of console */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
/* SECTION: finsh, a C-Express shell */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_DEVICE_NAME "uart"
/* SECTION: device filesystem support */
/* #define RT_USING_DFS */
#define RT_USING_DFS_ELMFAT
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 4
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
/* #define RT_USING_LWIP */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable DNS */
#define RT_LWIP_DNS
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* SECTION: RT-Thread/GUI */
/* #define RT_USING_RTGUI */
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 12
/* support 16 weight font */
#define RTGUI_USING_FONT16
/* support Chinese font */
#define RTGUI_USING_FONTHZ
/* use DFS as file interface */
#define RTGUI_USING_DFS_FILERW
/* use font file as Chinese font */
#define RTGUI_USING_HZ_FILE
/* use small size in RTGUI */
#define RTGUI_USING_SMALL_SIZE
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* default font size in RTGUI */
#define RTGUI_DEFAULT_FONT_SIZE 16
#endif

59
bsp/jz47xx/rtconfig.py
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@ -1,59 +0,0 @@
import os
# toolchains options
ARCH = 'mips'
CPU = 'jz47xx'
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = '/home/bernard/workspace/jz/mips-2011.09/bin'
elif CROSS_TOOL == 'keil':
print '================ERROR============================'
print 'Not support keil yet!'
print '================================================='
exit(0)
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support iar yet!'
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
# toolchains
PREFIX = 'mips-sde-elf-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mips32 -msoft-float'
CFLAGS = DEVICE + ' -EL -G0 -DRT_USING_MINILIBC -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -x assembler-with-cpp'
LFLAGS = DEVICE + ' -EL -Wl,--gc-sections,-Map=rtthread-jz47xx.map,-cref,-u,Reset_Handler -T jz47xx_ram.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
RT_USING_MINILIBC = True
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
COPY_ACTION = 'copy rtthread.bin usbboot\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

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bsp/jz47xx/startup.c
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@ -1,82 +0,0 @@
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <cache.h>
#include "board.h"
/**
* @addtogroup jz47xx
*/
/*@{*/
extern unsigned char __bss_start;
extern unsigned char __bss_end;
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* init cache */
rt_hw_cache_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* init board */
rt_hw_board_init();
rt_show_version();
/* init tick */
rt_system_tick_init();
/* init timer system */
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
#ifdef RT_USING_DEVICE
/* init all device */
rt_device_init_all();
#endif
/* init application */
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
finsh_set_device(FINSH_DEVICE_NAME);
#endif
/* init idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
/*@}*/

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bsp/jz47xx/uart.c
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#include <rthw.h>
#include <rtthread.h>
#include <jz4755.h>
/**
* @addtogroup Jz47xx
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
#define UART_BAUDRATE 57600
#define DEV_CLK 12000000
/*
* Define macros for UARTIER
* UART Interrupt Enable Register
*/
#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
/*
* Define macros for UARTISR
* UART Interrupt Status Register
*/
#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
#define UARTISR_IID (7 << 1) /* Source of Interrupt */
#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
#define UARTISR_FFMS_NO_FIFO (0 << 6)
#define UARTISR_FFMS_FIFO_MODE (3 << 6)
/*
* Define macros for UARTFCR
* UART FIFO Control Register
*/
#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
#define UARTFCR_RTRG_1 (0 << 6)
#define UARTFCR_RTRG_4 (1 << 6)
#define UARTFCR_RTRG_8 (2 << 6)
#define UARTFCR_RTRG_15 (3 << 6)
/*
* Define macros for UARTLCR
* UART Line Control Register
*/
#define UARTLCR_WLEN (3 << 0) /* word length */
#define UARTLCR_WLEN_5 (0 << 0)
#define UARTLCR_WLEN_6 (1 << 0)
#define UARTLCR_WLEN_7 (2 << 0)
#define UARTLCR_WLEN_8 (3 << 0)
#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
#define UARTLCR_PE (1 << 3) /* 0: parity disable */
#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
/*
* Define macros for UARTLSR
* UART Line Status Register
*/
#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
#define UARTLSR_PER (1 << 2) /* 0: no parity error */
#define UARTLSR_FER (1 << 3) /* 0; no framing error */
#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
/*
* Define macros for UARTMCR
* UART Modem Control Register
*/
#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */
#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */
#define UARTMCR_OUT1 (1 << 2) /* 0: UARTMSR.RI is set to 0 and RI_ input high */
#define UARTMCR_OUT2 (1 << 3) /* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
/*
* Define macros for UARTMSR
* UART Modem Status Register
*/
#define UARTMSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UARTMSR */
#define UARTMSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UARTMSR */
#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */
#define UARTMSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UARTMSR */
#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */
#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */
#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */
/*
* Define macros for SIRCR
* Slow IrDA Control Register
*/
#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1: 0 pulse width is 1.6us for 115.2Kbps */
#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
struct rt_uart_jz
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int vector, void* param)
{
rt_ubase_t level, isr;
struct rt_uart_jz* uart = param;
/* read interrupt status and clear it */
isr = UART_ISR(uart->hw_base);
if (isr & UARTISR_IID_RDI) /* Receive Data Available */
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_RDR(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if(uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init (rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
RT_ASSERT(uart != RT_NULL);
/* Init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = ~UARTFCR_UUE; /* disable UART unite */
/* Enable UART clock */
/* Set both receiver and transmitter in UART mode (not SIR) */
UART_SIRCR(uart->hw_base) = ~(SIRCR_RSIRE | SIRCR_TSIRE);
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = UARTLCR_WLEN_8;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
UART_DLHR(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_DLLR(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
/* Enable UART unit, enable and clear FIFO */
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, uart, "uart");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_RIE | UARTIER_RTIE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_uint8_t* ptr;
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t*) buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char*)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
/* write data */
UART_TDR(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
/* write data */
UART_TDR(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while ( size != 0 )
{
/* FIFO status, contain valid data */
while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
/* write data */
UART_TDR(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t) ptr - (rt_size_t) buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_jz* uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0)
uart->hw_base = UART0_BASE;
uart->irq = IRQ_UART0;
#elif defined(RT_USING_UART1)
uart->hw_base = UART1_BASE;
uart->irq = IRQ_UART1;
#elif defined(RT_USING_UART2)
uart->hw_base = UART2_BASE;
uart->irq = IRQ_UART2;
#elif defined(RT_USING_UART3)
uart->hw_base = UART3_BASE;
uart->irq = IRQ_UART3;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent,
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/

6
bsp/jz47xx/uart.h
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@ -1,6 +0,0 @@
#ifndef __UART_H__
#define __UART_H__
void rt_hw_uart_init(void);
#endif

93
libcpu/mips/jz47xx/cache.c
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@ -1,93 +0,0 @@
#include "jz47xx.h"
#include "cache.h"
#define CACHE_SIZE 16*1024
#define CACHE_LINE_SIZE 32
#define KSEG0 0x80000000
#define K0_TO_K1() \
do { \
unsigned long __k0_addr; \
\
__asm__ __volatile__( \
"la %0, 1f\n\t" \
"or %0, %0, %1\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r"(__k0_addr) \
: "r" (0x20000000) ); \
} while(0)
#define K1_TO_K0() \
do { \
unsigned long __k0_addr; \
__asm__ __volatile__( \
"nop;nop;nop;nop;nop;nop;nop\n\t" \
"la %0, 1f\n\t" \
"jr %0\n\t" \
"nop\n\t" \
"1: nop\n" \
: "=&r" (__k0_addr)); \
} while (0)
#define INVALIDATE_BTB() \
do { \
unsigned long tmp; \
__asm__ __volatile__( \
".set mips32\n\t" \
"mfc0 %0, $16, 7\n\t" \
"nop\n\t" \
"ori %0, 2\n\t" \
"mtc0 %0, $16, 7\n\t" \
"nop\n\t" \
".set mips2\n\t" \
: "=&r" (tmp)); \
} while (0)
#define SYNC_WB() __asm__ __volatile__ ("sync")
#define cache_op(op,addr) \
__asm__ __volatile__( \
" .set noreorder \n" \
" .set mips32\n\t \n" \
" cache %0, %1 \n" \
" .set mips0 \n" \
" .set reorder" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
void __icache_invalidate_all(void)
{
unsigned int i;
K0_TO_K1();
asm volatile (".set noreorder\n"
".set mips32\n\t"
"mtc0\t$0,$28\n\t"
"mtc0\t$0,$29\n"
".set mips0\n"
".set reorder\n");
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Store_Tag_I, i);
K1_TO_K0();
INVALIDATE_BTB();
}
void __dcache_writeback_all(void)
{
unsigned int i;
for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
cache_op(Index_Writeback_Inv_D, i);
SYNC_WB();
}
void rt_hw_cache_init(void)
{
__dcache_writeback_all();
__icache_invalidate_all();
}

40
libcpu/mips/jz47xx/cache.h
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@ -1,40 +0,0 @@
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
void rt_hw_cache_init(void);
#endif

42
libcpu/mips/jz47xx/cache_gcc.S
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@ -1,42 +0,0 @@
/*
* File : cache_init.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include "../common/mips.inc"
#include "../common/mipsregs.h"
#include "../common/stackframe.h"
.text
.set noreorder
.globl cache_init
.ent cache_init
cache_init:
.set noreorder
mtc0 zero, CP0_TAGLO
move t0, a0 // cache total size
move t1, a1 // cache line size
li t2, 0x80000000
addu t3, t0, t2
_cache_init_loop:
cache 8, 0(t2) // icache_index_store_tag
cache 9, 0(t2) // dcache_index_store_tag
addu t2, t1
bne t2, t3, _cache_init_loop
nop
mfc0 t0, CP0_CONFIG
li t1, 0x7
not t1
and t0, t0, t1
or t0, 0x3 // cacheable, noncoherent, write-back, write allocate
mtc0 t0, CP0_CONFIG
jr ra
nop
.set reorder
.end cache_init

146
libcpu/mips/jz47xx/context_gcc.S
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@ -1,146 +0,0 @@
/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Jz4755
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
.globl system_dump
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
mfc0 t1, CP0_STATUS
and t0, t1
andi t0, 0xff00
beqz t0, spurious_interrupt
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder

68
libcpu/mips/jz47xx/cpu.c
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/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <jz4755.h>
/* Watchdog definitions */
#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3)
#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3)
#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3)
#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3)
#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3)
#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3)
#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3)
#define WDT_CLK_EXTAL ( 0x1 << 2)
#define WDT_CLK_RTC ( 0x1 << 1)
#define WDT_CLK_PCLK ( 0x1 << 0)
#define WDT_CLK_MASK ( 7 )
#define WDT_ENABLE ( 1 << 0 )
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset()
{
/* open the watch-dog */
WDT_TCSR = WDT_CLK_EXTAL;
WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
WDT_TDR = 0x03;
WDT_TCNT = 0x00;
WDT_TCER |= WDT_ENABLE;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/

65
libcpu/mips/jz47xx/exception.c
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/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Jz47xx
*/
/*@{*/
/**
* exception handle table
*/
exception_func_t sys_exception_handlers[33];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > 32) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<33; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
/*@}*/

133
libcpu/mips/jz47xx/interrupt.c
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/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
*/
#include <rthw.h>
#include "jz47xx.h"
#define JZ47XX_MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static struct rt_irq_desc irq_handle_table[JZ47XX_MAX_INTR];
/**
* @addtogroup Jz47xx
*/
/*@{*/
void rt_hw_interrupt_handler(int vector)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init()
{
rt_int32_t index;
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (index = 0; index < JZ47XX_MAX_INTR; index ++)
{
irq_handle_table[index].handler = (rt_isr_handler_t)rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INTC_IMSR = (1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INTC_IMCR = (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param handler the interrupt service routine to be installed
* @param param the interrupt service function parameter
* @param name the interrupt name
* @return old handler
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector,
rt_isr_handler_t handler,
void *param,
char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < JZ47XX_MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
void rt_interrupt_dispatch(void *ptreg)
{
int i;
rt_isr_handler_t irq_func;
static rt_uint32_t pending = 0;
/* the hardware interrupt */
pending |= INTC_IPR;
if (!pending) return;
for (i = JZ47XX_MAX_INTR; i > 0; --i)
{
if ((pending & (1<<i)))
{
pending &= ~(1<<i);
irq_func = irq_handle_table[i].handler;
/* do interrupt */
(*irq_func)(i, irq_handle_table[i].param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[i].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
/* ack interrupt */
INTC_IPR = (1 << i);
}
}
}
/*@}*/

55
libcpu/mips/jz47xx/jz4740.h
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@ -1,55 +0,0 @@
#ifndef __JZ4740_H__
#define __JZ4740_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* Clock Gate Register Definitions */
#define CPM_CLKGR_UART1 (1 << 15)
#define CPM_CLKGR_UHC (1 << 14)
#define CPM_CLKGR_IPU (1 << 13)
#define CPM_CLKGR_DMAC (1 << 12)
#define CPM_CLKGR_UDC (1 << 11)
#define CPM_CLKGR_LCD (1 << 10)
#define CPM_CLKGR_CIM (1 << 9)
#define CPM_CLKGR_SADC (1 << 8)
#define CPM_CLKGR_MSC (1 << 7)
#define CPM_CLKGR_AIC1 (1 << 6)
#define CPM_CLKGR_AIC2 (1 << 5)
#define CPM_CLKGR_SSI (1 << 4)
#define CPM_CLKGR_I2C (1 << 3)
#define CPM_CLKGR_RTC (1 << 2)
#define CPM_CLKGR_TCU (1 << 1)
#define CPM_CLKGR_UART0 (1 << 0)
/* Interrupt Definitions */
#define IRQ_I2C 1
#define IRQ_UHC 3
#define IRQ_UART0 9
#define IRQ_SADC 12
#define IRQ_MSC 14
#define IRQ_RTC 15
#define IRQ_SSI 16
#define IRQ_CIM 17
#define IRQ_AIC 18
#define IRQ_ETH 19
#define IRQ_DMAC 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_UDC 24
#define IRQ_GPIO3 25
#define IRQ_GPIO2 26
#define IRQ_GPIO1 27
#define IRQ_GPIO0 28
#define IRQ_IPU 29
#define IRQ_LCD 30
#endif

83
libcpu/mips/jz47xx/jz4755.h
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#ifndef __JZ4755_H__
#define __JZ4755_H__
#include "jz47xx.h"
#define WDT_BASE 0xB0002000
#define OST_BASE 0xB00020e0
/* Watchdog */
#define WDT_TDR __REG16(WDT_BASE + 0x00) /* Watchdog Timer Data Register */
#define WDT_TCER __REG8(WDT_BASE + 0x04) /* Watchdog Counter Enable Register */
#define WDT_TCNT __REG16(WDT_BASE + 0x08) /* Watchdog Timer Counter Register */
#define WDT_TCSR __REG16(WDT_BASE + 0x0C) /* Watchdog Timer Control Register */
/* OS Timer */
#define OST_DR __REG32(OST_BASE + 0x00) /* OS Timer Data Register */
#define OST_CNT __REG32(OST_BASE + 0x08) /* OS Timer Counter Register */
#define OST_CSR __REG16(OST_BASE + 0x0C) /* OS Timer Control Register */
/* OST Register Definitions */
#define OST_TCSR_EXT_EN ( 0x1 << 2)
#define OST_TCSR_RTC_EN ( 0x1 << 1)
#define OST_TCSR_PCLK_EN ( 0x1 << 0)
/* Clock Gate Register Definitions */
#define CPM_CLKGR_AUX_CPU ( 1 << 24 )
#define CPM_CLKGR_AHB1 ( 1 << 23 )
#define CPM_CLKGR_IDCT ( 1 << 22 )
#define CPM_CLKGR_DB ( 1 << 21 )
#define CPM_CLKGR_ME ( 1 << 20 )
#define CPM_CLKGR_MC ( 1 << 19 )
#define CPM_CLKGR_TVE ( 1 << 18 )
#define CPM_CLKGR_TSSI ( 1 << 17 )
#define CPM_CLKGR_MSC1 ( 1 << 16 )
#define CPM_CLKGR_UART2 ( 1 << 15 )
#define CPM_CLKGR_UART1 ( 1 << 14 )
#define CPM_CLKGR_IPU ( 1 << 13 )
#define CPM_CLKGR_DMAC ( 1 << 12 )
#define CPM_CLKGR_BCH ( 1 << 11 )
#define CPM_CLKGR_UDC ( 1 << 10 )
#define CPM_CLKGR_LCD ( 1 << 9 )
#define CPM_CLKGR_CIM ( 1 << 8 )
#define CPM_CLKGR_SADC ( 1 << 7 )
#define CPM_CLKGR_MSC0 ( 1 << 6 )
#define CPM_CLKGR_AIC ( 1 << 5 )
#define CPM_CLKGR_SSI1 ( 1 << 4 )
#define CPM_CLKGR_I2C ( 1 << 3 )
#define CPM_CLKGR_RTC ( 1 << 2 )
#define CPM_CLKGR_TCU ( 1 << 1 )
#define CPM_CLKGR_UART0 ( 1 << 0 )
/* Interrupt Definitions */
#define IRQ_ETH 0
#define IRQ_SFT 4
#define IRQ_I2C 5
#define IRQ_RTC 6
#define IRQ_UART2 7
#define IRQ_UART1 8
#define IRQ_UART0 9
#define IRQ_AIC 10
#define IRQ_GPIO5 11
#define IRQ_GPIO4 12
#define IRQ_GPIO3 13
#define IRQ_GPIO2 14
#define IRQ_GPIO1 15
#define IRQ_GPIO0 16
#define IRQ_BCH 17
#define IRQ_SADC 18
#define IRQ_CIM 19
#define IRQ_TSSI 20
#define IRQ_TCU2 21
#define IRQ_TCU1 22
#define IRQ_TCU0 23
#define IRQ_MSC1 24
#define IRQ_MSC0 25
#define IRQ_SSI 26
#define IRQ_UDC 27
#define IRQ_DMA1 28 /* Used for DMA channel 4-7 */
#define IRQ_DMA0 29 /* Used for DMA channel 0-3 */
#define IRQ_IPU 30
#define IRQ_LCD 31
#endif

263
libcpu/mips/jz47xx/jz47xx.h
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#ifndef __JZ47XX_H__
#define __JZ47XX_H__
#include "../common/mipsregs.h"
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define HARB_BASE 0xB3000000
#define EMC_BASE 0xB3010000
#define DMAC_BASE 0xB3020000
#define UHC_BASE 0xB3030000
#define UDC_BASE 0xB3040000
#define LCD_BASE 0xB3050000
#define CIM_BASE 0xB3060000
#define ETH_BASE 0xB3100000
#define NBM_BASE 0xB3F00000
#define CPM_BASE 0xB0000000
#define INTC_BASE 0xB0001000
#define TCU_BASE 0xB0002000
#define RTC_BASE 0xB0003000
#define GPIO_BASE 0xB0010000
#define AIC_BASE 0xB0020000
#define MSC_BASE 0xB0021000
#define UART0_BASE 0xB0030000
#define UART1_BASE 0xB0031000
#define UART2_BASE 0xB0032000
#define UART3_BASE 0xB0033000
#define FIR_BASE 0xB0040000
#define SCC_BASE 0xB0041000
#define SCC0_BASE 0xB0041000
#define I2C_BASE 0xB0042000
#define SSI_BASE 0xB0043000
#define SCC1_BASE 0xB0044000
#define PWM0_BASE 0xB0050000
#define PWM1_BASE 0xB0051000
#define DES_BASE 0xB0060000
#define UPRT_BASE 0xB0061000
#define KBC_BASE 0xB0062000
/* CPM Register */
#define CPM_CPCCR __REG32(CPM_BASE + 0x00) /* Clock Control Register */
#define CPM_LCR __REG32(CPM_BASE + 0x04) /* Low Power Control Register */
#define CPM_RSR __REG32(CPM_BASE + 0x08) /* Reset Status Register */
#define CPM_CPPCR __REG32(CPM_BASE + 0x10) /* PLL Control Register */
#define CPM_CPPSR __REG32(CPM_BASE + 0x14) /* PLL Switch and Status Register */
#define CPM_CLKGR __REG32(CPM_BASE + 0x20) /* Clock Gate Register */
#define CPM_OPCR __REG32(CPM_BASE + 0x24) /* Osillator and Power Control Register */
#define CPM_I2SCDR __REG32(CPM_BASE + 0x60) /* I2S Device Clock Divider Register */
#define CPM_LPCDR __REG32(CPM_BASE + 0x64) /* LCD Pixel Clock Divider Register */
#define CPM_MSCCDR __REG32(CPM_BASE + 0x68) /* MSC Clock Divider Register */
#define CPM_SSICDR __REG32(CPM_BASE + 0x74) /* SSI Clock Divider Register */
#define CPM_CIMCDR __REG32(CPM_BASE + 0x7C) /* CIM MCLK Clock Divider Register */
/* Interrupt Controller Regester */
#define INTC_ISR __REG32(INTC_BASE + 0x00)
#define INTC_IMR __REG32(INTC_BASE + 0x04)
#define INTC_IMSR __REG32(INTC_BASE + 0x08)
#define INTC_IMCR __REG32(INTC_BASE + 0x0c)
#define INTC_IPR __REG32(INTC_BASE + 0x10)
/* TCU Register */
#define TCU_TSTR __REG32(TCU_BASE + 0xF0)
#define TCU_TSTSR __REG32(TCU_BASE + 0xF4)
#define TCU_TSTCR __REG32(TCU_BASE + 0xF8)
#define TCU_TSR __REG32(TCU_BASE + 0x1C)
#define TCU_TSSR __REG32(TCU_BASE + 0x2C)
#define TCU_TSCR __REG32(TCU_BASE + 0x3C)
#define TCU_TER __REG32(TCU_BASE + 0x10)
#define TCU_TESR __REG32(TCU_BASE + 0x14)
#define TCU_TECR __REG32(TCU_BASE + 0x18)
#define TCU_TFR __REG32(TCU_BASE + 0x20)
#define TCU_TFSR __REG32(TCU_BASE + 0x24)
#define TCU_TFCR __REG32(TCU_BASE + 0x28)
#define TCU_TMR __REG32(TCU_BASE + 0x30)
#define TCU_TMSR __REG32(TCU_BASE + 0x34)
#define TCU_TMCR __REG32(TCU_BASE + 0x38)
#define TCU_TDFR0_OFFSET 0x40
#define TCU_TDFR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
#define TCU_TDHR0_OFFSET 0x44
#define TCU_TDHR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
#define TCU_TCNT0_OFFSET 0x48
#define TCU_TCNT(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
#define TCU_TCSR0_OFFSET 0x4C
#define TCU_TCSR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
/* TCU Register Definitions */
#define TCU_TCSR_PWM_SD (1 << 9)
#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
#define TCU_TCSR_PWM_EN (1 << 7)
#define TCU_TCSR_PRESCALE_BIT 3
#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
#define TCU_TCSR_EXT_EN (1 << 2)
#define TCU_TCSR_RTC_EN (1 << 1)
#define TCU_TCSR_PCK_EN (1 << 0)
#define TCU_TER_OSTEN (1 << 15)
#define TCU_TER_TCEN5 (1 << 5)
#define TCU_TER_TCEN4 (1 << 4)
#define TCU_TER_TCEN3 (1 << 3)
#define TCU_TER_TCEN2 (1 << 2)
#define TCU_TER_TCEN1 (1 << 1)
#define TCU_TER_TCEN0 (1 << 0)
#define TCU_TESR_OSTST (1 << 15)
#define TCU_TESR_TCST5 (1 << 5)
#define TCU_TESR_TCST4 (1 << 4)
#define TCU_TESR_TCST3 (1 << 3)
#define TCU_TESR_TCST2 (1 << 2)
#define TCU_TESR_TCST1 (1 << 1)
#define TCU_TESR_TCST0 (1 << 0)
#define TCU_TECR_OSTCL (1 << 15)
#define TCU_TECR_TCCL5 (1 << 5)
#define TCU_TECR_TCCL4 (1 << 4)
#define TCU_TECR_TCCL3 (1 << 3)
#define TCU_TECR_TCCL2 (1 << 2)
#define TCU_TECR_TCCL1 (1 << 1)
#define TCU_TECR_TCCL0 (1 << 0)
#define TCU_TFR_HFLAG5 (1 << 21)
#define TCU_TFR_HFLAG4 (1 << 20)
#define TCU_TFR_HFLAG3 (1 << 19)
#define TCU_TFR_HFLAG2 (1 << 18)
#define TCU_TFR_HFLAG1 (1 << 17)
#define TCU_TFR_HFLAG0 (1 << 16)
#define TCU_TFR_FFLAG5 (1 << 5)
#define TCU_TFR_FFLAG4 (1 << 4)
#define TCU_TFR_FFLAG3 (1 << 3)
#define TCU_TFR_FFLAG2 (1 << 2)
#define TCU_TFR_FFLAG1 (1 << 1)
#define TCU_TFR_FFLAG0 (1 << 0)
#define TCU_TFSR_HFLAG5 (1 << 21)
#define TCU_TFSR_HFLAG4 (1 << 20)
#define TCU_TFSR_HFLAG3 (1 << 19)
#define TCU_TFSR_HFLAG2 (1 << 18)
#define TCU_TFSR_HFLAG1 (1 << 17)
#define TCU_TFSR_HFLAG0 (1 << 16)
#define TCU_TFSR_OSTFLAG (1 << 15)
#define TCU_TFSR_FFLAG5 (1 << 5)
#define TCU_TFSR_FFLAG4 (1 << 4)
#define TCU_TFSR_FFLAG3 (1 << 3)
#define TCU_TFSR_FFLAG2 (1 << 2)
#define TCU_TFSR_FFLAG1 (1 << 1)
#define TCU_TFSR_FFLAG0 (1 << 0)
#define TCU_TFCR_HFLAG5 (1 << 21)
#define TCU_TFCR_HFLAG4 (1 << 20)
#define TCU_TFCR_HFLAG3 (1 << 19)
#define TCU_TFCR_HFLAG2 (1 << 18)
#define TCU_TFCR_HFLAG1 (1 << 17)
#define TCU_TFCR_HFLAG0 (1 << 16)
#define TCU_TFCR_OSTFLAG (1 << 15)
#define TCU_TFCR_FFLAG5 (1 << 5)
#define TCU_TFCR_FFLAG4 (1 << 4)
#define TCU_TFCR_FFLAG3 (1 << 3)
#define TCU_TFCR_FFLAG2 (1 << 2)
#define TCU_TFCR_FFLAG1 (1 << 1)
#define TCU_TFCR_FFLAG0 (1 << 0)
#define TCU_TMR_HMASK5 (1 << 21)
#define TCU_TMR_HMASK4 (1 << 20)
#define TCU_TMR_HMASK3 (1 << 19)
#define TCU_TMR_HMASK2 (1 << 18)
#define TCU_TMR_HMASK1 (1 << 17)
#define TCU_TMR_HMASK0 (1 << 16)
#define TCU_TMR_OSTMASK (1 << 15)
#define TCU_TMR_FMASK5 (1 << 5)
#define TCU_TMR_FMASK4 (1 << 4)
#define TCU_TMR_FMASK3 (1 << 3)
#define TCU_TMR_FMASK2 (1 << 2)
#define TCU_TMR_FMASK1 (1 << 1)
#define TCU_TMR_FMASK0 (1 << 0)
#define TCU_TMSR_HMST5 (1 << 21)
#define TCU_TMSR_HMST4 (1 << 20)
#define TCU_TMSR_HMST3 (1 << 19)
#define TCU_TMSR_HMST2 (1 << 18)
#define TCU_TMSR_HMST1 (1 << 17)
#define TCU_TMSR_HMST0 (1 << 16)
#define TCU_TMSR_OSTMST (1 << 15)
#define TCU_TMSR_FMST5 (1 << 5)
#define TCU_TMSR_FMST4 (1 << 4)
#define TCU_TMSR_FMST3 (1 << 3)
#define TCU_TMSR_FMST2 (1 << 2)
#define TCU_TMSR_FMST1 (1 << 1)
#define TCU_TMSR_FMST0 (1 << 0)
#define TCU_TMCR_HMCL5 (1 << 21)
#define TCU_TMCR_HMCL4 (1 << 20)
#define TCU_TMCR_HMCL3 (1 << 19)
#define TCU_TMCR_HMCL2 (1 << 18)
#define TCU_TMCR_HMCL1 (1 << 17)
#define TCU_TMCR_HMCL0 (1 << 16)
#define TCU_TMCR_OSTMCL (1 << 15)
#define TCU_TMCR_FMCL5 (1 << 5)
#define TCU_TMCR_FMCL4 (1 << 4)
#define TCU_TMCR_FMCL3 (1 << 3)
#define TCU_TMCR_FMCL2 (1 << 2)
#define TCU_TMCR_FMCL1 (1 << 1)
#define TCU_TMCR_FMCL0 (1 << 0)
#define TCU_TSR_WDTS (1 << 16)
#define TCU_TSR_STOP5 (1 << 5)
#define TCU_TSR_STOP4 (1 << 4)
#define TCU_TSR_STOP3 (1 << 3)
#define TCU_TSR_STOP2 (1 << 2)
#define TCU_TSR_STOP1 (1 << 1)
#define TCU_TSR_STOP0 (1 << 0)
#define TCU_TSSR_WDTSS (1 << 16)
#define TCU_TSSR_STPS5 (1 << 5)
#define TCU_TSSR_STPS4 (1 << 4)
#define TCU_TSSR_STPS3 (1 << 3)
#define TCU_TSSR_STPS2 (1 << 2)
#define TCU_TSSR_STPS1 (1 << 1)
#define TCU_TSSR_STPS0 (1 << 0)
#define TCU_TSSR_WDTSC (1 << 16)
#define TCU_TSSR_STPC5 (1 << 5)
#define TCU_TSSR_STPC4 (1 << 4)
#define TCU_TSSR_STPC3 (1 << 3)
#define TCU_TSSR_STPC2 (1 << 2)
#define TCU_TSSR_STPC1 (1 << 1)
#define TCU_TSSR_STPC0 (1 << 0)
#define OST_TCSR_CNT_MD ( 1 << 15 )
#define OST_TCSR_PWM_SHUT_ABRUPT ( 1 << 9 )
#define OST_TCSR_PRESCALE1 ( 0x0 << 3)
#define OST_TCSR_PRESCALE4 ( 0x1 << 3)
#define OST_TCSR_PRESCALE16 ( 0x2 << 3)
#define OST_TCSR_PRESCALE64 ( 0x3 << 3)
#define OST_TCSR_PRESCALE256 ( 0x4 << 3)
#define OST_TCSR_PRESCALE1024 ( 0x5 << 3)
/* Uart Register */
#define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */
#define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */
#define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */
#define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */
#define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */
#define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */
#define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */
#define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */
#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
#define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */
#define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */
#define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */
#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
#define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
#endif

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libcpu/mips/jz47xx/mipscfg.c
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/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

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libcpu/mips/jz47xx/stack.c
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/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Jz47xx
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x0403;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

151
libcpu/mips/jz47xx/start_gcc.S
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/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "jz47xx.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* init cp0 registers. */
li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
mtc0 t0, CP0_STATUS
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* init caches, assumes a 4way * 128set * 32byte I/D cache */
mtc0 zero, CP0_TAGLO /* TAGLO reg */
mtc0 zero, CP0_TAGHI /* TAGHI reg */
li t0, 3 /* enable cache for kseg0 accesses */
mtc0 t0, CP0_CONFIG /* CONFIG reg */
la t0, 0x80000000 /* an idx op should use an unmappable address */
ori t1, t0, 0x4000 /* 16kB cache */
_cache_loop:
cache 0x8, 0(t0) /* index store icache tag */
cache 0x9, 0(t0) /* index store dcache tag */
bne t0, t1, _cache_loop
addiu t0, t0, 0x20 /* 32 bytes per cache line */
nop
/* invalidate BTB */
mfc0 t0, CP0_CONFIG
nop
ori t0, 2
mtc0 t0, CP0_CONFIG
nop
/* copy IRAM section */
la t0, _iramcopy
la t1, _iramstart
la t2, _iramend
_iram_loop:
lw t3, 0(t0)
sw t3, 0(t1)
addiu t1, 4
bne t1, t2, _iram_loop
addiu t0, 4
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
srl k1, k1, 2
lw k0, sys_exception_handlers(k1)
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder

188
libcpu/mips/loongson/cache.c
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#include "../common/mipsregs.h"
#include "cache.h"
#define K0BASE 0x80000000
#define PRID_3210I 0x4200
typedef struct cacheinfo_t {
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t {
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu (void)
{
unsigned int cpu_id;
void invalidate_cache (void);
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_3210I:
rt_kprintf ("CPU:SoC3210\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
break;
default:
rt_kprintf ("Unknown CPU type, system halted!\n");
while (1) {}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config = read_c0_config ();
unsigned int icache_size, ic_lsize;
unsigned int dcache_size, dc_lsize;
icache_size = 1 << (12 + ((config >> 9) & 7));
dcache_size = 1 << (12 + ((config >> 6) & 7));
ic_lsize = 16 << ((config >> 5) & 1);
dc_lsize = 16 << ((config >> 4) & 1);
rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
dcache_size >> 10, dc_lsize);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
icache_size >> 10, ic_lsize);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = ic_lsize;
pcacheinfo->dcacheline_size = dc_lsize;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
start = K0BASE;
while(start < end) {
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while(start <end){
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while(start < end) {
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all()
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start <end){
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while(start < end){
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while(start < end) {
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end) {
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}

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libcpu/mips/loongson/cache.h
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#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Gc3210I (unsigned int);
extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
void rt_hw_cache_init(void);
#endif

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libcpu/mips/loongson/cache.inc
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#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif

202
libcpu/mips/loongson/cache_gcc.S
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#include "../common/mipsregs.h"
#include "../common/mips.inc"
#include "../common/asm.h"
#include "cache.inc"
.ent cache_init
.global cache_init
.set noreorder
cache_init:
move t1,ra
####part 2####
cache_detect_4way:
mfc0 t4, CP0_CONFIG
andi t5, t4, 0x0e00
srl t5, t5, 9 #ic
andi t6, t4, 0x01c0
srl t6, t6, 6 #dc
addiu t8, $0, 1
addiu t9, $0, 2
#set dcache way
beq t6, $0, cache_d1way
addiu t7, $0, 1 #1 way
beq t6, t8, cache_d2way
addiu t7, $0, 2 #2 way
beq $0, $0, cache_d4way
addiu t7, $0, 4 #4 way
cache_d1way:
beq $0, $0, 1f
addiu t6, t6, 12 #1 way
cache_d2way:
beq $0, $0, 1f
addiu t6, t6, 11 #2 way
cache_d4way:
addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
1: #set icache way
beq t5, $0, cache_i1way
addiu t3, $0, 1 #1 way
beq t5, t8, cache_i2way
addiu t3, $0, 2 #2 way
beq $0, $0, cache_i4way
addiu t3, $0, 4 #4 way
cache_i1way:
beq $0, $0, 1f
addiu t5, t5, 12
cache_i2way:
beq $0, $0, 1f
addiu t5, t5, 11
cache_i4way:
addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
1: addiu t4, $0, 1
sllv t6, t4, t6
sllv t5, t4, t5
#if 0
la t0, memvar
sw t7, 0x0(t0) #ways
sw t5, 0x4(t0) #icache size
sw t6, 0x8(t0) #dcache size
#endif
####part 3####
.set mips3
lui a0, 0x8000
addu a1, $0, t5
addu a2, $0, t6
cache_init_d2way:
#a0=0x80000000, a1=icache_size, a2=dcache_size
#a3, v0 and v1 used as local registers
mtc0 $0, CP0_TAGHI
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
mtc0 $0, CP0_TAGLO
beq t7, 1, 4f
cache Index_Store_Tag_D, 0x0(v0) # 1 way
beq t7, 2 ,4f
cache Index_Store_Tag_D, 0x1(v0) # 2 way
cache Index_Store_Tag_D, 0x2(v0) # 4 way
cache Index_Store_Tag_D, 0x3(v0)
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_i2way:
addu v0, $0, a0
addu v1, a0, a1
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t3, 1, 4f
cache Index_Invalidate_I, 0x0(v0) # 1 way
beq t3, 2, 4f
cache Index_Invalidate_I, 0x1(v0) # 2 way
cache Index_Invalidate_I, 0x2(v0)
cache Index_Invalidate_I, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_d2way:
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t7, 1, 4f
cache Index_Writeback_Inv_D, 0x0(v0) #1 way
beq t7, 2, 4f
cache Index_Writeback_Inv_D, 0x1(v0) # 2 way
cache Index_Writeback_Inv_D, 0x2(v0)
cache Index_Writeback_Inv_D, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_init_finish:
jr t1
nop
.set reorder
.end cache_init
###########################
# Enable CPU cache #
###########################
LEAF(enable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x03
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (enable_cpu_cache)
###########################
# disable CPU cache #
###########################
LEAF(disable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x2
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (disable_cpu_cache)
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Clear_TagLo)
.set noreorder
mtc0 zero, CP0_TAGLO
nop
.set reorder
j ra
END(Clear_TagLo)
.set mips3
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Invalidate_Icache_Gc3210I)
.set noreorder
cache Index_Invalidate_I,0(a0)
cache Index_Invalidate_I,1(a0)
cache Index_Invalidate_I,2(a0)
cache Index_Invalidate_I,3(a0)
.set reorder
j ra
END(Invalidate_Icache_Gc3210I)
/**********************************/
/* Invalidate Data Cache */
/**********************************/
LEAF(Invalidate_Dcache_ClearTag_Gc3210I)
.set noreorder
cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag
cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_ClearTag_Gc3210I)
LEAF(Invalidate_Dcache_Fill_Gc3210I)
.set noreorder
cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag
cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_Fill_Gc3210I)
LEAF(Writeback_Invalidate_Dcache)
.set noreorder
cache Hit_Writeback_Inv_D, (a0)
.set reorder
j ra
END(Writeback_Invalidate_Dcache)
.set mips0

141
libcpu/mips/loongson/context_gcc.S
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/*
* File : context_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder

50
libcpu/mips/loongson/cpu.c
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@ -1,50 +0,0 @@
/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
*/
#include <rtthread.h>
#include <soc3210.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WD_CTRL |= 0x01;
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
/*@}*/

83
libcpu/mips/loongson/exception.c
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@ -1,83 +0,0 @@
/*
* File : exception.c
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup SoC3210
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/

152
libcpu/mips/loongson/interrupt.c
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@ -1,152 +0,0 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2013-03-29 aozima Modify the interrupt interface implementations.
*/
#include <rtthread.h>
#include <rthw.h>
#include "soc3210.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static struct rt_irq_desc irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t idx;
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
INT_EN &= ~(1 << vector);
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
INT_EN |= (1 << vector);
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if(vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
}
return old_handler;
}
void rt_interrupt_dispatch(void *ptreg)
{
int irq;
void *param;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
/* check os timer */
c0_status = read_c0_status();
if (c0_status & 0x8000)
{
rt_hw_timer_handler();
}
if (c0_status & 0x0400)
{
/* the hardware interrupt */
status |= INT_ISR;
if (!status) return;
for (irq = MAX_INTR; irq > 0; --irq)
{
if ((status & (1 << irq)))
{
status &= ~(1 << irq);
irq_func = irq_handle_table[irq].handler;
param = irq_handle_table[irq].param;
/* do interrupt */
(*irq_func)(irq, param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
/* ack interrupt */
INT_CLR = (1 << irq);
}
}
}
}
/*@}*/

82
libcpu/mips/loongson/mipscfg.c
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/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2010, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

172
libcpu/mips/loongson/soc3210.h
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#ifndef __SOC3210_H__
#define __SOC3210_H__
#include "../common/mipsregs.h"
/* registers */
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define EMI_BASE 0xBF000000
#define NN_BASE 0xBF000040
#define LCD_BASE 0xBF001000
#define HSB_MISC_BASE 0xBF003200
#define SPI_BASE 0xBF004000
#define PS2_BASE 0xBF004040
#define UART0_BASE 0xBF004080
#define UART1_BASE 0xBF004090
#define I2C_BASE 0xBF0040D0
#define LPB_MISC_BASE 0xBF004100
#define AC97_BASE 0xBF004200
#define AC97_DMA_BASE 0xBF004280
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
#define MAC0_BASE 0xBF005200
#define MAC1_BASE 0xBF005300
/* LCD registers */
#define LCD_CTRL __REG32(LCD_BASE + 0x000)
#define LCD_STAT __REG32(LCD_BASE + 0x004)
#define LCD_HTIM __REG32(LCD_BASE + 0x008)
#define LCD_VTIM __REG32(LCD_BASE + 0x00C)
#define LCD_HVLEN __REG32(LCD_BASE + 0x010)
#define LCD_VBARA __REG32(LCD_BASE + 0x014)
#define LCD_VBARB __REG32(LCD_BASE + 0x018)
#define LCD_PCLT __REG32(LCD_BASE + 0x800)
/* HSB misc registers */
#define HSB_MISC_REG __REG32(HSB_MISC_BASE + 0x00)
#define INT_EDGE __REG32(HSB_MISC_BASE + 0x04)
#define INT_STEER __REG32(HSB_MISC_BASE + 0x08)
#define INT_POL __REG32(HSB_MISC_BASE + 0x0C)
#define INT_SET __REG32(HSB_MISC_BASE + 0x10)
#define INT_CLR __REG32(HSB_MISC_BASE + 0x14)
#define INT_EN __REG32(HSB_MISC_BASE + 0x18)
#define INT_ISR __REG32(HSB_MISC_BASE + 0x1C)
#define GPIO_OE_60_29 __REG32(HSB_MISC_BASE + 0x20)
#define GPIO_I_60_29 __REG32(HSB_MISC_BASE + 0x24)
#define GPIO_O_60_29 __REG32(HSB_MISC_BASE + 0x28)
#define HSB_ARB_CFG __REG32(HSB_MISC_BASE + 0x2C)
#define WD_TIMER __REG32(HSB_MISC_BASE + 0x30)
#define WD_CTRL __REG32(HSB_MISC_BASE + 0x34)
/* SPI registers */
#define SPI_SPCR __REG8(SPI_BASE + 0x00)
#define SPI_SPSR __REG8(SPI_BASE + 0x01)
#define SPI_TX_FIFO __REG8(SPI_BASE + 0x02)
#define SPI_SPER __REG8(SPI_BASE + 0x03)
/* PS/2 registers */
#define PS2_RIBUF __REG8(PS2_BASE + 0x00)
#define PS2_WOBUF __REG8(PS2_BASE + 0x00)
#define PS2_RSR __REG8(PS2_BASE + 0x04)
#define PS2_WSC __REG8(PS2_BASE + 0x04)
#define PS2_DLL __REG8(PS2_BASE + 0x08)
#define PS2_DLH __REG8(PS2_BASE + 0x09)
#define PS2_DL_KBD __REG8(PS2_BASE + 0x0A)
#define PS2_DL_AUX __REG8(PS2_BASE + 0x0B)
/* UART registers */
#define UART_DAT(base) __REG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01)
/* LPB misc registers */
#define GPIO_OE_7_0 __REG8(LPB_MISC_BASE + 0x00)
#define GPIO_OE_15_8 __REG8(LPB_MISC_BASE + 0x01)
#define GPIO_OE_23_16 __REG8(LPB_MISC_BASE + 0x02)
#define GPIO_OE_28_24 __REG8(LPB_MISC_BASE + 0x03)
#define GPIO_I_7_0 __REG8(LPB_MISC_BASE + 0x10)
#define GPIO_I_15_8 __REG8(LPB_MISC_BASE + 0x11)
#define GPIO_I_23_16 __REG8(LPB_MISC_BASE + 0x12)
#define GPIO_I_28_24 __REG8(LPB_MISC_BASE + 0x13)
#define GPIO_O_7_0 __REG8(LPB_MISC_BASE + 0x20)
#define GPIO_O_15_8 __REG8(LPB_MISC_BASE + 0x21)
#define GPIO_O_23_16 __REG8(LPB_MISC_BASE + 0x22)
#define GPIO_O_28_24 __REG8(LPB_MISC_BASE + 0x23)
#define LPB_MISC_CFG __REG8(LPB_MISC_BASE + 0x40)
/* MAC0 registers */
#define MAC0_BUS_MODE __REG32(MAC0_BASE + 0x00)
#define MAC0_TX_POLL_REQ __REG32(MAC0_BASE + 0x08)
#define MAC0_RX_POLL_REQ __REG32(MAC0_BASE + 0x10)
#define MAC0_RX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x18)
#define MAC0_TX_LIST_BASE_ADDR __REG32(MAC0_BASE + 0x20)
#define MAC0_STATUS __REG32(MAC0_BASE + 0x28)
#define MAC0_OP_MODE __REG32(MAC0_BASE + 0x30)
#define MAC0_INTERRUPT_EN __REG32(MAC0_BASE + 0x38)
#define MAC0_MISSED_FRAME_STATISTIC __REG32(MAC0_BASE + 0x40)
#define MAC0_SMI_EEPROM_CTL __REG32(MAC0_BASE + 0x48)
#define MAC0_BYTE_ALIGN __REG32(MAC0_BASE + 0x50)
#define MAC0_GPT_IM_CTL __REG32(MAC0_BASE + 0x58)
/* MAC1 registers */
#define MAC1_BUS_MODE __REG32(MAC1_BASE + 0x00)
#define MAC1_TX_POLL_REQ __REG32(MAC1_BASE + 0x08)
#define MAC1_RX_POLL_REQ __REG32(MAC1_BASE + 0x10)
#define MAC1_RX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x18)
#define MAC1_TX_LIST_BASE_ADDR __REG32(MAC1_BASE + 0x20)
#define MAC1_STATUS __REG32(MAC1_BASE + 0x28)
#define MAC1_OP_MODE __REG32(MAC1_BASE + 0x30)
#define MAC1_INTERRUPT_EN __REG32(MAC1_BASE + 0x38)
#define MAC1_MISSED_FRAME_STATISTIC __REG32(MAC1_BASE + 0x40)
#define MAC1_SMI_EEPROM_CTL __REG32(MAC1_BASE + 0x48)
#define MAC1_BYTE_ALIGN __REG32(MAC1_BASE + 0x50)
#define MAC1_GPT_IM_CTL __REG32(MAC1_BASE + 0x58)
/* Peripheral Interrupt Number */
#define IRQ_LCD 0
#define IRQ_MAC1 1
#define IRQ_MAC2 2
#define IRQ_AC97 3
#define IRQ_SPI 8
#define IRQ_KEY 9
#define IRQ_MOUSE 10
#define IRQ_UART0 11
#define IRQ_UART1 12
#define IRQ_I2C 13
#define IRQ_CAN0 14
#define IRQ_CAN1 15
#define IRQ_GPIO15 20
#define IRQ_GPIO14 21
#define IRQ_GPIO13 22
#define IRQ_GPIO12 23
#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
#endif

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libcpu/mips/loongson/stack.c
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/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-07-07 Bernard porting to Jz47xx
*/
#include <rtthread.h>
/**
* @addtogroup Loongson SoC3210
*/
/*@{*/
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

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libcpu/mips/loongson/start_gcc.S
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/*
* File : start_gcc.S
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
#include "soc3210.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder