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[bsp/n32] 修复每次上电都初始化RTC导致上电时间被重置的问题

This commit is contained in:
liangzohar 2024-09-10 16:54:03 +08:00 committed by Meco Man
parent 9de975fa93
commit 240172609c
1 changed files with 60 additions and 53 deletions
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113
bsp/n32/libraries/n32_drivers/drv_rtc.c
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@ -14,6 +14,8 @@
#ifdef BSP_USING_RTC #ifdef BSP_USING_RTC
#define USER_WRITE_BKP_DAT1_DATA 0xA5A5
uint32_t SynchPrediv, AsynchPrediv; uint32_t SynchPrediv, AsynchPrediv;
static rt_err_t n32_rtc_get_timeval(struct timeval *tv) static rt_err_t n32_rtc_get_timeval(struct timeval *tv)
@ -105,93 +107,98 @@ static rt_err_t n32_rtc_init(void)
/* Allow access to RTC */ /* Allow access to RTC */
PWR_BackupAccessEnable(ENABLE); PWR_BackupAccessEnable(ENABLE);
if (USER_WRITE_BKP_DAT1_DATA != BKP_ReadBkpData(BKP_DAT1) )
{
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) #if defined(SOC_N32G45X) || defined(SOC_N32WB452)
/* Reset Backup */ /* Reset Backup */
BKP_DeInit(); BKP_DeInit();
#endif #endif
/* Disable RTC clock */ /* Disable RTC clock */
RCC_EnableRtcClk(DISABLE); RCC_EnableRtcClk(DISABLE);
#ifdef BSP_RTC_USING_HSE #ifdef BSP_RTC_USING_HSE
/* Enable the HSE OSC */ /* Enable the HSE OSC */
RCC_EnableLsi(DISABLE); RCC_EnableLsi(DISABLE);
RCC_ConfigHse(RCC_HSE_ENABLE); RCC_ConfigHse(RCC_HSE_ENABLE);
while (RCC_WaitHseStable() == ERROR) while (RCC_WaitHseStable() == ERROR)
{ {
} }
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
rt_kprintf("rtc clock source is set hse/128!\n"); rt_kprintf("rtc clock source is set hse/128!\n");
RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128); RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128);
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
rt_kprintf("rtc clock source is set hse/32!\n"); rt_kprintf("rtc clock source is set hse/32!\n");
RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV32); RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV32);
#endif #endif
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
SynchPrediv = 0x1E8; // 8M/128 = 62.5KHz SynchPrediv = 0x1E8; // 8M/128 = 62.5KHz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
SynchPrediv = 0x7A0; // 8M/32 = 250KHz SynchPrediv = 0x7A0; // 8M/32 = 250KHz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#endif #endif
#endif /* BSP_RTC_USING_HSE */ #endif /* BSP_RTC_USING_HSE */
#ifdef BSP_RTC_USING_LSE #ifdef BSP_RTC_USING_LSE
rt_kprintf("rtc clock source is set lse!\n"); rt_kprintf("rtc clock source is set lse!\n");
/* Enable the LSE OSC32_IN PC14 */ /* Enable the LSE OSC32_IN PC14 */
RCC_EnableLsi(DISABLE); // LSI is turned off here to ensure that only one clock is turned on RCC_EnableLsi(DISABLE); // LSI is turned off here to ensure that only one clock is turned on
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
RCC_ConfigLse(RCC_LSE_ENABLE); RCC_ConfigLse(RCC_LSE_ENABLE);
while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET) while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET)
{ {
} }
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
RCC_ConfigLse(RCC_LSE_ENABLE,0x28); RCC_ConfigLse(RCC_LSE_ENABLE,0x28);
while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET)
{ {
} }
#endif #endif
RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE); RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE);
SynchPrediv = 0xFF; // 32.768KHz SynchPrediv = 0xFF; // 32.768KHz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#endif /* BSP_RTC_USING_LSE */ #endif /* BSP_RTC_USING_LSE */
#ifdef BSP_RTC_USING_LSI #ifdef BSP_RTC_USING_LSI
rt_kprintf("rtc clock source is set lsi!\n"); rt_kprintf("rtc clock source is set lsi!\n");
/* Enable the LSI OSC */ /* Enable the LSI OSC */
RCC_EnableLsi(ENABLE); RCC_EnableLsi(ENABLE);
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET) while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET)
{ {
} }
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET)
{ {
} }
#endif #endif
RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI); RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI);
#if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR)
SynchPrediv = 0x136; // 39.64928KHz SynchPrediv = 0x136; // 39.64928KHz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
SynchPrediv = 0x14A; // 41828Hz SynchPrediv = 0x14A; // 41828Hz
AsynchPrediv = 0x7F; // value range: 0-7F AsynchPrediv = 0x7F; // value range: 0-7F
#endif #endif
#endif /* BSP_RTC_USING_LSI */ #endif /* BSP_RTC_USING_LSI */
/* Enable the RTC Clock */ /* Enable the RTC Clock */
RCC_EnableRtcClk(ENABLE); RCC_EnableRtcClk(ENABLE);
RTC_WaitForSynchro(); RTC_WaitForSynchro();
if (rt_rtc_config() != RT_EOK) if (rt_rtc_config() != RT_EOK)
{ {
rt_kprintf("rtc init failed.\n"); rt_kprintf("rtc init failed.\n");
return -RT_ERROR; return -RT_ERROR;
}
BKP_WriteBkpData(BKP_DAT1, USER_WRITE_BKP_DAT1_DATA);
} }
return RT_EOK; return RT_EOK;