From 240172609cddc50806c984593541a215e8899a74 Mon Sep 17 00:00:00 2001 From: liangzohar Date: Tue, 10 Sep 2024 16:54:03 +0800 Subject: [PATCH] =?UTF-8?q?[bsp/n32]=20=E4=BF=AE=E5=A4=8D=E6=AF=8F?= =?UTF-8?q?=E6=AC=A1=E4=B8=8A=E7=94=B5=E9=83=BD=E5=88=9D=E5=A7=8B=E5=8C=96?= =?UTF-8?q?RTC=E5=AF=BC=E8=87=B4=E4=B8=8A=E7=94=B5=E6=97=B6=E9=97=B4?= =?UTF-8?q?=E8=A2=AB=E9=87=8D=E7=BD=AE=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/n32/libraries/n32_drivers/drv_rtc.c | 113 +++++++++++++----------- 1 file changed, 60 insertions(+), 53 deletions(-) diff --git a/bsp/n32/libraries/n32_drivers/drv_rtc.c b/bsp/n32/libraries/n32_drivers/drv_rtc.c index 1bf01cec19..58291629a9 100644 --- a/bsp/n32/libraries/n32_drivers/drv_rtc.c +++ b/bsp/n32/libraries/n32_drivers/drv_rtc.c @@ -14,6 +14,8 @@ #ifdef BSP_USING_RTC +#define USER_WRITE_BKP_DAT1_DATA 0xA5A5 + uint32_t SynchPrediv, AsynchPrediv; static rt_err_t n32_rtc_get_timeval(struct timeval *tv) @@ -105,93 +107,98 @@ static rt_err_t n32_rtc_init(void) /* Allow access to RTC */ PWR_BackupAccessEnable(ENABLE); + if (USER_WRITE_BKP_DAT1_DATA != BKP_ReadBkpData(BKP_DAT1) ) + { #if defined(SOC_N32G45X) || defined(SOC_N32WB452) - /* Reset Backup */ - BKP_DeInit(); + /* Reset Backup */ + BKP_DeInit(); #endif - /* Disable RTC clock */ - RCC_EnableRtcClk(DISABLE); + /* Disable RTC clock */ + RCC_EnableRtcClk(DISABLE); #ifdef BSP_RTC_USING_HSE - /* Enable the HSE OSC */ - RCC_EnableLsi(DISABLE); - RCC_ConfigHse(RCC_HSE_ENABLE); - while (RCC_WaitHseStable() == ERROR) - { - } + /* Enable the HSE OSC */ + RCC_EnableLsi(DISABLE); + RCC_ConfigHse(RCC_HSE_ENABLE); + while (RCC_WaitHseStable() == ERROR) + { + } #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - rt_kprintf("rtc clock source is set hse/128!\n"); - RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128); + rt_kprintf("rtc clock source is set hse/128!\n"); + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV128); #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - rt_kprintf("rtc clock source is set hse/32!\n"); - RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV32); + rt_kprintf("rtc clock source is set hse/32!\n"); + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_HSE_DIV32); #endif #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - SynchPrediv = 0x1E8; // 8M/128 = 62.5KHz - AsynchPrediv = 0x7F; // value range: 0-7F + SynchPrediv = 0x1E8; // 8M/128 = 62.5KHz + AsynchPrediv = 0x7F; // value range: 0-7F #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - SynchPrediv = 0x7A0; // 8M/32 = 250KHz - AsynchPrediv = 0x7F; // value range: 0-7F + SynchPrediv = 0x7A0; // 8M/32 = 250KHz + AsynchPrediv = 0x7F; // value range: 0-7F #endif #endif /* BSP_RTC_USING_HSE */ #ifdef BSP_RTC_USING_LSE - rt_kprintf("rtc clock source is set lse!\n"); - /* Enable the LSE OSC32_IN PC14 */ - RCC_EnableLsi(DISABLE); // LSI is turned off here to ensure that only one clock is turned on + rt_kprintf("rtc clock source is set lse!\n"); + /* Enable the LSE OSC32_IN PC14 */ + RCC_EnableLsi(DISABLE); // LSI is turned off here to ensure that only one clock is turned on #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - RCC_ConfigLse(RCC_LSE_ENABLE); - while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET) - { - } + RCC_ConfigLse(RCC_LSE_ENABLE); + while (RCC_GetFlagStatus(RCC_FLAG_LSERD) == RESET) + { + } #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - RCC_ConfigLse(RCC_LSE_ENABLE,0x28); - while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) - { - } + RCC_ConfigLse(RCC_LSE_ENABLE,0x28); + while (RCC_GetFlagStatus(RCC_LDCTRL_FLAG_LSERD) == RESET) + { + } #endif - RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE); + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSE); - SynchPrediv = 0xFF; // 32.768KHz - AsynchPrediv = 0x7F; // value range: 0-7F + SynchPrediv = 0xFF; // 32.768KHz + AsynchPrediv = 0x7F; // value range: 0-7F #endif /* BSP_RTC_USING_LSE */ #ifdef BSP_RTC_USING_LSI - rt_kprintf("rtc clock source is set lsi!\n"); - /* Enable the LSI OSC */ - RCC_EnableLsi(ENABLE); + rt_kprintf("rtc clock source is set lsi!\n"); + /* Enable the LSI OSC */ + RCC_EnableLsi(ENABLE); #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET) - { - } + while (RCC_GetFlagStatus(RCC_FLAG_LSIRD) == RESET) + { + } #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) - { - } + while (RCC_GetFlagStatus(RCC_CTRLSTS_FLAG_LSIRD) == RESET) + { + } #endif - RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI); + RCC_ConfigRtcClk(RCC_RTCCLK_SRC_LSI); #if defined(SOC_N32G45X) || defined(SOC_N32WB452) || defined(SOC_N32G4FR) - SynchPrediv = 0x136; // 39.64928KHz - AsynchPrediv = 0x7F; // value range: 0-7F + SynchPrediv = 0x136; // 39.64928KHz + AsynchPrediv = 0x7F; // value range: 0-7F #elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X) - SynchPrediv = 0x14A; // 41828Hz - AsynchPrediv = 0x7F; // value range: 0-7F + SynchPrediv = 0x14A; // 41828Hz + AsynchPrediv = 0x7F; // value range: 0-7F #endif #endif /* BSP_RTC_USING_LSI */ - /* Enable the RTC Clock */ - RCC_EnableRtcClk(ENABLE); - RTC_WaitForSynchro(); + /* Enable the RTC Clock */ + RCC_EnableRtcClk(ENABLE); + RTC_WaitForSynchro(); - if (rt_rtc_config() != RT_EOK) - { - rt_kprintf("rtc init failed.\n"); - return -RT_ERROR; + if (rt_rtc_config() != RT_EOK) + { + rt_kprintf("rtc init failed.\n"); + return -RT_ERROR; + } + + BKP_WriteBkpData(BKP_DAT1, USER_WRITE_BKP_DAT1_DATA); } return RT_EOK;