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[libcpu/risc-v] support noncached normal memory (#7051)

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* [libcpu/risc-v] support noncached normal memory

* [mm] check before dereference in _fetch_page

* [mm] add comments on ioremap

* [ioremap] report more info on failed
This commit is contained in:
Shell 2023-03-16 10:26:55 +08:00 committed by GitHub
parent 65301b9cdd
commit 2394e75265
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 35 additions and 16 deletions
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2
components/mm/ioremap.c
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@ -62,7 +62,7 @@ static void *_ioremap_type(void *paddr, size_t size, enum ioremap_type type)
if (err) if (err)
{ {
LOG_W("IOREMAP 0x%lx failed", paddr); LOG_W("IOREMAP 0x%lx failed %d\n", paddr, err);
v_addr = NULL; v_addr = NULL;
} }
else else

14
components/mm/ioremap.h
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@ -16,6 +16,20 @@
extern "C" { extern "C" {
#endif #endif
/**
* IOREMAP family
* `rt_ioremap` default to map physical memory in MMIO region as DEVICE memory
* to kernel space. And there are 3 variants currently supported.
*
* name | attribution
* ------------------ | -----------
* rt_ioremap_nocache | Device (MMU_MAP_K_DEVICE)
* rt_ioremap_cache | Normal memory (MMU_MAP_K_RWCB)
* rt_ioremap_wt | Normal memory but guarantee that
* | Each write access should go to system memory directly
* | Currently as non-cacheable
*/
void *rt_ioremap(void *paddr, size_t size); void *rt_ioremap(void *paddr, size_t size);
void *rt_ioremap_nocache(void *paddr, size_t size); void *rt_ioremap_nocache(void *paddr, size_t size);
void *rt_ioremap_cached (void *paddr, size_t size); void *rt_ioremap_cached (void *paddr, size_t size);

33
components/mm/mm_fault.c
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@ -29,23 +29,26 @@
static int _fetch_page(rt_varea_t varea, struct rt_mm_fault_msg *msg) static int _fetch_page(rt_varea_t varea, struct rt_mm_fault_msg *msg)
{ {
int err = UNRECOVERABLE; int err = UNRECOVERABLE;
varea->mem_obj->on_page_fault(varea, msg); if (varea->mem_obj && varea->mem_obj->on_page_fault)
if (msg->response.status == MM_FAULT_STATUS_OK)
{ {
void *store = msg->response.vaddr; varea->mem_obj->on_page_fault(varea, msg);
rt_size_t store_sz = msg->response.size; if (msg->response.status == MM_FAULT_STATUS_OK)
{
void *store = msg->response.vaddr;
rt_size_t store_sz = msg->response.size;
if (msg->vaddr + store_sz > varea->start + varea->size) if (msg->vaddr + store_sz > varea->start + varea->size)
{ {
LOG_W("%s more size of buffer is provided than varea", __func__); LOG_W("%s more size of buffer is provided than varea", __func__);
} }
else else
{ {
rt_hw_mmu_map(varea->aspace, msg->vaddr, store + PV_OFFSET, rt_hw_mmu_map(varea->aspace, msg->vaddr, store + PV_OFFSET,
store_sz, varea->attr); store_sz, varea->attr);
rt_hw_tlb_invalidate_range(varea->aspace, msg->vaddr, store_sz, rt_hw_tlb_invalidate_range(varea->aspace, msg->vaddr, store_sz,
ARCH_PAGE_SIZE); ARCH_PAGE_SIZE);
err = RECOVERABLE; err = RECOVERABLE;
}
} }
} }
return err; return err;

1
libcpu/risc-v/t-head/c906/riscv_mmu.h
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@ -88,6 +88,7 @@
#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V) #define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V) #define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_K_RW PTE_WRAP(PTE_G | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V) #define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V) #define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V)
#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V) #define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)

1
libcpu/risc-v/virt64/riscv_mmu.h
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@ -73,6 +73,7 @@
#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V) #define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V) #define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_K_RW (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) #define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V) #define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) #define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)