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Merge pull request #811 from aozima/update_cortex-m_port 

[libcpu] Update cortex m port
This commit is contained in:
Bernard Xiong 2017-08-18 11:30:28 +08:00 committed by GitHub
parent f975ef5146 959b97aa34
commit 2331ebdc8e
13 changed files with 28 additions and 9 deletions
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4
bsp/stm32f20x/stm32_rom.icf
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@ -28,8 +28,8 @@ do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly, block RTT_INIT_FUNC };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in RAM_region { readwrite, block CSTACK, last block HEAP};

4
libcpu/arm/cortex-m0/context_gcc.S
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@ -181,7 +181,9 @@ rt_hw_context_switch_to:
NOP
MSR MSP, R0
CPSIE I /* enable interrupts at processor level */
/* enable interrupts at processor level */
CPSIE F
CPSIE I
/* never reach here! */

1
libcpu/arm/cortex-m0/context_iar.S
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@ -188,6 +188,7 @@ rt_hw_context_switch_to:
MSR msp, r0
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

1
libcpu/arm/cortex-m0/context_rvds.S
View File

@ -191,6 +191,7 @@ rt_hw_context_switch_to PROC
MSR msp, r0
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

4
libcpu/arm/cortex-m3/context_gcc.S
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@ -162,7 +162,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I /* enable interrupts at processor level */
/* enable interrupts at processor level */
CPSIE F
CPSIE I
/* never reach here! */

4
libcpu/arm/cortex-m3/context_iar.S
View File

@ -161,7 +161,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I ; enable interrupts at processor level
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

1
libcpu/arm/cortex-m3/context_rvds.S
View File

@ -168,6 +168,7 @@ rt_hw_context_switch_to PROC
MSR msp, r0
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

4
libcpu/arm/cortex-m4/context_gcc.S
View File

@ -203,7 +203,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I /* enable interrupts at processor level */
/* enable interrupts at processor level */
CPSIE F
CPSIE I
/* never reach here! */

4
libcpu/arm/cortex-m4/context_iar.S
View File

@ -207,7 +207,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I ; enable interrupts at processor level
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

1
libcpu/arm/cortex-m4/context_rvds.S
View File

@ -208,6 +208,7 @@ rt_hw_context_switch_to PROC
MSR msp, r0
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

4
libcpu/arm/cortex-m7/context_gcc.S
View File

@ -203,7 +203,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I /* enable interrupts at processor level */
/* enable interrupts at processor level */
CPSIE F
CPSIE I
/* never reach here! */

4
libcpu/arm/cortex-m7/context_iar.S
View File

@ -207,7 +207,9 @@ rt_hw_context_switch_to:
NOP
MSR msp, r0
CPSIE I ; enable interrupts at processor level
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!

1
libcpu/arm/cortex-m7/context_rvds.S
View File

@ -208,6 +208,7 @@ rt_hw_context_switch_to PROC
MSR msp, r0
; enable interrupts at processor level
CPSIE F
CPSIE I
; never reach here!