Updated WM8978 I2S Master mode code. NOTICE: This mode is still unusable due to a suspecting hardware bug of STM32.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@474 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
kyle.hu.gz
parent
f73af11ea2
commit
2190f72040
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@ -3,6 +3,10 @@
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#include "stm32f10x.h"
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#include "codec.h"
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/*
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* IMPORTANT NOTICE:
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* CODEC_MASTER_MODE = 1 is still unusable due to a suspecting hardware bug of STM32.
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*/
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#define CODEC_MASTER_MODE 0
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/*
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@ -41,7 +45,6 @@ struct codec_device
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struct codec_device codec;
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static uint16_t r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8;
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static uint16_t zero = 0;
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static void NVIC_Configuration(void)
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{
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@ -78,19 +81,19 @@ static void GPIO_Configuration(void)
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#if CODEC_MASTER_MODE
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// WS, CK
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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// SD
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#else
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/* Configure SPI2 pins: CK, WS and SD */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#endif
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@ -120,13 +123,9 @@ static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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#if CODEC_MASTER_MODE
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while ((SPI2->SR & SPI_SR_CHSIDE) == 1);
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DMA_ClearFlag(DMA1_FLAG_TC5);
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#endif
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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@ -136,35 +135,6 @@ static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#if CODEC_MASTER_MODE
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static void DMA_ZeroFill_I2S()
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{
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DMA_InitTypeDef DMA_InitStructure;
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/* DMA1 Channel2 configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel5, DISABLE);
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DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI2->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) &zero;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = 1;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
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//DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#endif
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static void I2S_Configuration(void)
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{
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I2S_InitTypeDef I2S_InitStructure;
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@ -241,15 +211,21 @@ static rt_err_t codec_init(rt_device_t dev)
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codec_send(REG_AUDIO_INTERFACE | BCP_NORMAL | LRP_NORMAL | WL_16BITS | FMT_I2S);
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// PLL setup.
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// fs = 44.1KHz / 256fs = 11.2896MHz
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// fs = 44.1KHz * 256fs = 11.2896MHz
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// F_PLL = 11.2896MHz * 4 * 2 = 90.3168MHz
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// R = 90.3168MHz / 12.288MHz = 7.35
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// PLL_N = 7
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// PLL_K = 5872026 (5921370 for STM32's 44.117KHz fs generated from 72MHz clock)
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codec_send(REG_PLL_N | 7);
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#if CODEC_MASTER_MODE
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0xCC);
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codec_send(REG_PLL_K3 | 0x19A);
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#else
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0x12D);
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codec_send(REG_PLL_K3 | 0x5A);
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#endif
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN | PLLEN);
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codec_send(r06);
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@ -259,7 +235,7 @@ static rt_err_t codec_init(rt_device_t dev)
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// Set LOUT2/ROUT2 in BTL operation.
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codec_send(REG_BEEP | INVROUT2);
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// Set output volume to -22dB.
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// Set output volume.
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vol(20);
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return RT_EOK;
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@ -307,53 +283,67 @@ void eq3d(uint8_t depth)
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codec_send(REG_3D | ((depth & DEPTH3D_MASK) << DEPTH3D_POS));
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}
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void sample_rate(uint8_t sr)
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rt_err_t sample_rate(uint8_t sr)
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{
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if (sr == 44)
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uint16_t r07 = REG_ADDITIONAL;
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switch (sr)
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{
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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case 8:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_8KHZ;
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break;
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case 11:
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r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV8 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_12KHZ;
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break;
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#if CODEC_MASTER_MODE
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case 12:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_12KHZ;
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break;
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#endif
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case 16:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_16KHZ;
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break;
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case 22:
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r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_24KHZ;
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break;
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#if CODEC_MASTER_MODE
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case 24:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_24KHZ;
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break;
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#endif
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case 32:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_32KHZ;
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break;
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case 44:
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r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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codec_send(r06);
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}
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else
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{
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switch (sr)
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{
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case 8:
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codec_send(REG_ADDITIONAL | SR_8KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
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break;
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case 12:
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codec_send(REG_ADDITIONAL | SR_12KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
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break;
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case 16:
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codec_send(REG_ADDITIONAL | SR_16KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
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break;
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case 24:
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codec_send(REG_ADDITIONAL | SR_24KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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break;
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case 32:
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codec_send(REG_ADDITIONAL | SR_32KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
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break;
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case 48:
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
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break;
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default:
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return;
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}
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codec_send(r06);
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r07 |= SR_48KHZ;
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break;
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case 48:
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
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r07 |= SR_48KHZ;
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break;
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default:
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return RT_ERROR;
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}
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codec_send(r06);
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codec_send(r07);
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return RT_EOK;
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}
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FINSH_FUNCTION_EXPORT(vol, Set volume);
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@ -367,14 +357,9 @@ FINSH_FUNCTION_EXPORT(sample_rate, Set sample rate);
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static rt_err_t codec_open(rt_device_t dev, rt_uint16_t oflag)
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{
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#if !CODEC_MASTER_MODE
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/* enable I2S */
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I2S_Cmd(SPI2, ENABLE);
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#if CODEC_MASTER_MODE
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DMA_ZeroFill_I2S();
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r06 |= MS;
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codec_send(r06);
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#endif
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return RT_EOK;
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@ -385,13 +370,27 @@ static rt_err_t codec_close(rt_device_t dev)
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/* interrupt mode */
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if (dev->flag & RT_DEVICE_FLAG_INT_TX)
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{
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#if CODEC_MASTER_MODE
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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codec_send(r06);
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#else
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/* Disable the I2S2 */
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I2S_Cmd(SPI2, DISABLE);
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#endif
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}
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#if CODEC_MASTER_MODE
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else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
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{
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DMA_Cmd(DMA1_Channel5, DISABLE);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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@ -458,6 +457,16 @@ static rt_size_t codec_write(rt_device_t dev, rt_off_t pos,
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{
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DMA_Configuration((rt_uint32_t) node->data_ptr, node->data_size);
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}
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#if CODEC_MASTER_MODE
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if ((r06 & MS) == 0)
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{
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I2S_Cmd(SPI2, ENABLE);
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r06 |= MS;
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codec_send(r06);
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}
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#endif
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}
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rt_hw_interrupt_enable(level);
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@ -506,7 +515,22 @@ void codec_isr()
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if (SPI_I2S_GetITStatus(SPI2, SPI_I2S_IT_TXE) == SET)
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{
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#if CODEC_MASTER_MODE
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if ((r06 & MS) == 0)
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{
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I2S_Cmd(SPI2, ENABLE);
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SPI_I2S_SendData(SPI2, node->data_ptr[codec.offset++]);
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r06 |= MS;
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codec_send(r06);
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}
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else
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{
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SPI_I2S_SendData(SPI2, node->data_ptr[codec.offset++]);
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}
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#else
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SPI_I2S_SendData(SPI2, node->data_ptr[codec.offset++]);
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#endif
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}
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if (codec.offset == node->data_size)
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@ -533,6 +557,16 @@ void codec_isr()
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/* no data on the list, disable I2S interrupt */
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SPI_I2S_ITConfig(SPI2, SPI_I2S_IT_TXE, DISABLE);
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#if CODEC_MASTER_MODE
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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codec_send(r06);
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#endif
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rt_kprintf("*\n");
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}
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}
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@ -556,11 +590,29 @@ void codec_dma_isr()
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{
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/* enable next dma request */
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DMA_Configuration((rt_uint32_t) codec.data_list[codec.read_index].data_ptr, codec.data_list[codec.read_index].data_size);
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#if CODEC_MASTER_MODE
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if ((r06 & MS) == 0)
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{
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I2S_Cmd(SPI2, ENABLE);
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r06 |= MS;
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codec_send(r06);
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}
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#endif
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}
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else
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{
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#if CODEC_MASTER_MODE
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DMA_ZeroFill_I2S();
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DMA_Cmd(DMA1_Channel5, DISABLE);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET);
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_BSY) == SET);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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codec_send(r06);
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#endif
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rt_kprintf("*\n");
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