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rt-thread-official
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Code Issues Releases Wiki Activity

修复RTC问题，增加GCC工具链

This commit is contained in:
yanmowudi 2021-09-13 20:19:14 +08:00
parent 160d448660
commit 208eb0a385
36 changed files with 13865 additions and 10471 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

192
bsp/swm320/.config
View File

@ -21,6 +21,13 @@ CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
@ -54,6 +61,7 @@ CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
@ -64,8 +72,9 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
@ -89,19 +98,19 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
@ -116,6 +125,8 @@ CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
@ -154,6 +165,7 @@ CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
@ -190,8 +202,14 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
@ -239,6 +257,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
@ -259,8 +278,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
@ -275,6 +292,13 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
#
# security packages
@ -291,6 +315,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
@ -300,9 +325,13 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
@ -311,6 +340,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
@ -339,33 +369,23 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
@ -376,14 +396,39 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_WCWIDTH is not set
#
# peripheral libraries and drivers
@ -408,7 +453,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
@ -446,10 +490,55 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
@ -460,44 +549,25 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_TERMBOX is not set
#
# Hardware Drivers Config
@ -508,8 +578,8 @@ CONFIG_SOC_SWM320=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART0 is not set
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
CONFIG_BSP_USING_GPIO=y

3853
bsp/swm320/JLinkLog.txt Normal file
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File diff suppressed because it is too large Load Diff

40
bsp/swm320/JLinkSettings.ini Normal file
View File

@ -0,0 +1,40 @@
[BREAKPOINTS]
ForceImpTypeAny = 0
ShowInfoWin = 1
EnableFlashBP = 2
BPDuringExecution = 0
[CFI]
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
[FLASH]
EraseType = 0x00
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
MinNumBytesFlashDL = 0
SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 1
Device="Cortex-M4"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00
RAMUsageLimit = 0x00
[SWO]
SWOLogFile=""
[MEM]
RdOverrideOrMask = 0x00
RdOverrideAndMask = 0xFFFFFFFF
RdOverrideAddr = 0xFFFFFFFF
WrOverrideOrMask = 0x00
WrOverrideAndMask = 0xFFFFFFFF
WrOverrideAddr = 0xFFFFFFFF

2
bsp/swm320/README.md
View File

@ -119,7 +119,7 @@
- 使用 Jlink 连接开发板到 PC （需要 Jlink 驱动）
将串口 0 引脚为：`[PA2/PA3]`和 USB 转串口模块 P2 相连，串口配置方式为115200-N-8-1。
将串口 1 引脚为：`[PC2/PC3]`和 USB 转串口模块 J11 相连，串口配置方式为115200-N-8-1。
当使用 [env工具](https://www.rt-thread.org/page/download.html) 正确编译产生出rtthread.bin映像文件后，可以使用 ISP 的方式来烧写到设备中。

59
bsp/swm320/applications/main.c
View File

@ -10,7 +10,7 @@
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN 21
#define LED_PIN 32
int main(void)
{
@ -29,7 +29,7 @@ int main(void)
}
// #ifdef RT_USING_PIN
// #define KEY1_PIN 25
// #define KEY1_PIN 31
// void key1_cb(void *args)
// {
// rt_kprintf("key1 irq!\n");
@ -46,7 +46,7 @@ int main(void)
// #endif
#ifdef RT_USING_ADC
#define ADC_DEV_NAME "adc0"
#define ADC_DEV_NAME "adc1"
#define ADC_DEV_CHANNEL 0
#define REFER_VOLTAGE 330
#define CONVERT_BITS (1 << 12)
@ -64,16 +64,15 @@ static int adc_vol_sample(int argc, char *argv[])
return RT_ERROR;
}
while (1)
{
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d,", value);
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
rt_thread_mdelay(500);
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
}
ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
rt_kprintf("the value is :%d,", value);
vol = value * REFER_VOLTAGE / CONVERT_BITS;
rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
return ret;
}
@ -143,17 +142,17 @@ MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
#endif
#ifdef RT_USING_PWM
#define PWM_DEV_NAME "pwm0" /* PWM???? */
#define PWM_DEV_CHANNEL 0 /* PWM?? */
#define PWM_DEV_NAME "pwm0" /* PWM设备名称 */
#define PWM_DEV_CHANNEL 0 /* PWM通道 */
struct rt_device_pwm *pwm_dev; /* PWM???? */
struct rt_device_pwm *pwm_dev; /* PWM设备句柄 */
static int pwm_sample(int argc, char *argv[])
{
rt_uint32_t period, pulse;
period = 500000; /* ???0.5ms,?????ns */
pulse = 250000; /* PWM?????,?????ns */
period = 500000; /* 周期为0.5ms,单位为纳秒ns */
pulse = 250000; /* PWM脉冲宽度值,单位为纳秒ns */
pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
if (pwm_dev == RT_NULL)
@ -170,26 +169,27 @@ MSH_CMD_EXPORT(pwm_sample, pwm sample);
#endif
#ifdef RT_USING_RTC
#include <time.h>
static int rtc_sample(int argc, char *argv[])
{
rt_err_t ret = RT_EOK;
time_t now;
ret = set_date(2020, 6, 15);
ret = set_date(2020, 2, 28);
if (ret != RT_EOK)
{
rt_kprintf("set RTC date failed\n");
return ret;
}
ret = set_time(11, 15, 50);
ret = set_time(23, 59, 55);
if (ret != RT_EOK)
{
rt_kprintf("set RTC time failed\n");
return ret;
}
rt_thread_mdelay(3000);
//rt_thread_mdelay(3000);
now = time(RT_NULL);
rt_kprintf("%s\n", ctime(&now));
@ -205,7 +205,7 @@ static rt_device_t wdg_dev;
static void idle_hook(void)
{
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, NULL);
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
rt_kprintf("feed the dog!\n ");
}
@ -264,7 +264,7 @@ MSH_CMD_EXPORT(wdt_sample, wdt sample);
static int rt_hw_spi_flash_init(void)
{
rt_hw_spi_device_attach("spi0", "spi00", GPIOA, PIN12);
rt_hw_spi_device_attach("spi0", "spi00", GPIOP, PIN22);
if (RT_NULL == rt_sfud_flash_probe(W25Q_FLASH_NAME, W25Q_SPI_DEVICE_NAME))
{
@ -273,7 +273,6 @@ static int rt_hw_spi_flash_init(void)
return RT_EOK;
}
/* ???????? */
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
static void spi_w25q_sample(int argc, char *argv[])
@ -292,12 +291,12 @@ static void spi_w25q_sample(int argc, char *argv[])
rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX);
}
/* ?? spi ???????? */
/* 查找 spi 设备获取设备句柄 */
spi_dev_w25q = (struct rt_spi_device *)rt_device_find(name);
struct rt_spi_configuration cfg;
cfg.data_width = 8;
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
cfg.max_hz = 20 * 1000 * 1000; /* 20M */
cfg.max_hz = 30 * 1000 * 1000; /* 20M */
rt_spi_configure(spi_dev_w25q, &cfg);
if (!spi_dev_w25q)
@ -306,11 +305,11 @@ static void spi_w25q_sample(int argc, char *argv[])
}
else
{
/* ??1:?? rt_spi_send_then_recv()??????ID */
/* 方式1：使用 rt_spi_send_then_recv()发送命令读取ID */
rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5);
rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]);
/* ??2:?? rt_spi_transfer_message()??????ID */
/* 方式2：使用 rt_spi_transfer_message()发送命令读取ID */
struct rt_spi_message msg1, msg2;
msg1.send_buf = &w25x_read_id;
@ -352,7 +351,6 @@ static void spi_flash_elmfat_sample(void)
rt_kprintf("Write string '%s' to /user/test.txt.\n", str);
/* ????????????,??????????????*/
fd = open("/user/test.txt", O_WRONLY | O_CREAT);
if (fd >= 0)
{
@ -362,7 +360,6 @@ static void spi_flash_elmfat_sample(void)
close(fd);
}
/* ????????? */
fd = open("/user/test.txt", O_RDONLY);
if (fd >= 0)
{
@ -397,7 +394,7 @@ MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
//{
// int fd, size;
// struct statfs elm_stat;
// char str[] = "elmfat mount to sdcard.\r\n", buf[80];
// char str[] = "elmfat mount to sdcard.", buf[80];
// if (dfs_mkfs("elm", SDCARD_NAME) == 0)
// rt_kprintf("make elmfat filesystem success.\n");

4
bsp/swm320/drivers/Kconfig
View File

@ -245,11 +245,11 @@ menu "On-chip Peripheral Drivers"
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS(CS/A12,MISO/A11,MOSI/A10,CLK/A9)"
bool "Enable SPI0 BUS(CS/P22,MISO/P19,MOSI/P18,CLK/P23)"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS(CS/C4,MISO/C5,MOSI/C6,CLK/C7)"
bool "Enable SPI1 BUS(CS/B6,MISO/B3,MOSI/B2,CLK/B1)"
default n
endif

36
bsp/swm320/drivers/board.c
View File

@ -17,6 +17,7 @@ static void bsp_clock_config(void)
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
SysTick->CTRL |= 0x00000004UL;
}
void SysTick_Handler(void)
{
/* enter interrupt */
@ -28,6 +29,41 @@ void SysTick_Handler(void)
rt_interrupt_leave();
}
/**
* This function will delay for some us.
*
* @param us the delay time of us
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void rt_hw_board_init()
{
bsp_clock_config();

12
bsp/swm320/drivers/drv_crypto.c
View File

@ -21,11 +21,6 @@ struct swm_hwcrypto_device
#ifdef BSP_USING_CRC
struct hash_ctx_des
{
struct swm_crc_cfg contex;
};
static struct hwcrypto_crc_cfg crc_backup_cfg;
static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
@ -108,6 +103,7 @@ static const struct hwcrypto_crc_ops crc_ops =
{
.update = _crc_update,
};
#endif /* BSP_USING_CRC */
static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
{
@ -170,7 +166,7 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
case HWCRYPTO_TYPE_CRC:
if (des->contex && src->contex)
{
rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
rt_memcpy(des->contex, src->contex, sizeof(struct swm_crc_cfg));
}
break;
#endif /* BSP_USING_CRC */
@ -226,5 +222,5 @@ int rt_hw_crypto_init(void)
}
INIT_BOARD_EXPORT(rt_hw_crypto_init);
#endif /* BSP_USING_WDT */
#endif /* RT_USING_WDT */
#endif /* RT_USING_HWCRYPTO */

1
bsp/swm320/drivers/drv_gpio.c
View File

@ -475,6 +475,7 @@ static void rt_hw_pin_isr(GPIO_TypeDef *GPIOx)
}
}
}
void GPIOA_Handler(void)
{
rt_interrupt_enter();

110
bsp/swm320/drivers/drv_rtc.c
View File

@ -10,6 +10,7 @@
*/
#include "drv_rtc.h"
#include <sys/time.h>
#ifdef RT_USING_RTC
#ifdef BSP_USING_RTC
@ -18,8 +19,6 @@
#define LOG_TAG "drv.rtc"
#include <drv_log.h>
static struct rt_device rtc_device;
static uint32_t calcWeekDay(uint32_t year, uint32_t month, uint32_t date)
{
uint32_t i, cnt = 0;
@ -55,8 +54,8 @@ static time_t swm_get_rtc_time_stamp(void)
tm_new.tm_min = get_datetime.Minute;
tm_new.tm_hour = get_datetime.Hour;
tm_new.tm_mday = get_datetime.Date;
tm_new.tm_mon = get_datetime.Month - 1;
tm_new.tm_year = get_datetime.Year - 1900;
tm_new.tm_mon = get_datetime.Month;
tm_new.tm_year = get_datetime.Year;
LOG_D("get rtc time.");
return mktime(&tm_new);
@ -72,9 +71,9 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
set_datetime.Minute = p_tm->tm_min;
set_datetime.Hour = p_tm->tm_hour;
set_datetime.Date = p_tm->tm_mday;
set_datetime.Month = p_tm->tm_mon + 1;
set_datetime.Year = p_tm->tm_year + 1900;
// datetime.Day = p_tm->tm_wday;
set_datetime.Month = p_tm->tm_mon;
set_datetime.Year = p_tm->tm_year;
// set_datetime.Day = p_tm->tm_wday;
RTC_Stop(RTC);
while (RTC->CFGABLE == 0)
@ -86,7 +85,7 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
RTC->MONDAY = (calcWeekDay(set_datetime.Year, set_datetime.Month, set_datetime.Date)
<< RTC_MONDAY_DAY_Pos) |
((set_datetime.Month) << RTC_MONDAY_MON_Pos);
RTC->YEAR = set_datetime.Year - 1901;
RTC->YEAR = set_datetime.Year;
RTC->LOAD = 1 << RTC_LOAD_TIME_Pos;
RTC_Start(RTC);
@ -94,43 +93,7 @@ static rt_err_t swm_set_rtc_time_stamp(time_t time_stamp)
return RT_EOK;
}
static rt_err_t swm_rtc_control(rt_device_t rtc_device, int cmd, void *args)
{
rt_err_t result = RT_EOK;
RT_ASSERT(rtc_device != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = swm_get_rtc_time_stamp();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
break;
default:
break;
}
return result;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops swm_rtc_ops =
{
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
swm_rtc_control};
#endif
static void swm_rtc_init(void)
static rt_err_t swm_rtc_init(void)
{
RTC_InitStructure rtc_initstruct;
@ -144,37 +107,50 @@ static void swm_rtc_init(void)
rtc_initstruct.MinuteIEn = 0;
RTC_Init(RTC, &rtc_initstruct);
RTC_Start(RTC);
return RT_EOK;
}
static rt_err_t rt_hw_rtc_register(rt_device_t rtc_device, const char *name, rt_uint32_t flag)
static rt_err_t swm_rtc_get_secs(void *args)
{
RT_ASSERT(rtc_device != RT_NULL);
*(rt_uint32_t *)args = swm_get_rtc_time_stamp();
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
swm_rtc_init();
#ifdef RT_USING_DEVICE_OPS
rtc_device->ops = &swm_rtc_ops;
#else
rtc_device->init = RT_NULL;
rtc_device->open = RT_NULL;
rtc_device->close = RT_NULL;
rtc_device->read = RT_NULL;
rtc_device->write = RT_NULL;
rtc_device->control = swm_rtc_control;
#endif
rtc_device->type = RT_Device_Class_RTC;
rtc_device->rx_indicate = RT_NULL;
rtc_device->tx_complete = RT_NULL;
rtc_device->user_data = RT_NULL;
/* register a character device */
return rt_device_register(rtc_device, name, flag);
return RT_EOK;
}
static rt_err_t swm_rtc_set_secs(void *args)
{
rt_err_t result = RT_EOK;
if (swm_set_rtc_time_stamp(*(rt_uint32_t *)args))
{
result = -RT_ERROR;
}
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
return result;
}
static const struct rt_rtc_ops swm_rtc_ops =
{
swm_rtc_init,
swm_rtc_get_secs,
swm_rtc_set_secs,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
static rt_rtc_dev_t swm_rtc_device;
int rt_hw_rtc_init(void)
{
rt_err_t result;
result = rt_hw_rtc_register(&rtc_device, "rtc", RT_DEVICE_FLAG_RDWR);
swm_rtc_device.ops = &swm_rtc_ops;
result = rt_hw_rtc_register(&swm_rtc_device, "rtc", RT_DEVICE_FLAG_RDWR,RT_NULL);
if (result != RT_EOK)
{
LOG_E("rtc register err code: %d", result);

2
bsp/swm320/drivers/drv_sdio.c
View File

@ -47,7 +47,7 @@ static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
SDIO_TypeDef *hw_sdio = sdio->sdio_des.hw_sdio;
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
rt_tick_from_millisecond(1000), &status) != RT_EOK)
{
LOG_E("wait completed timeout");
cmd->err = -RT_ETIMEOUT;

12
bsp/swm320/drivers/drv_spi.c
View File

@ -279,15 +279,15 @@ int rt_hw_spi_init(void)
rt_err_t result;
#ifdef BSP_USING_SPI0
PORT_Init(PORTA, PIN9, FUNMUX1_SPI0_SCLK, 0);
PORT_Init(PORTA, PIN10, FUNMUX0_SPI0_MOSI, 0);
PORT_Init(PORTA, PIN11, FUNMUX1_SPI0_MISO, 1);
PORT_Init(PORTP, PIN23, FUNMUX1_SPI0_SCLK, 0);
PORT_Init(PORTP, PIN18, FUNMUX0_SPI0_MOSI, 0);
PORT_Init(PORTP, PIN19, FUNMUX1_SPI0_MISO, 1);
#endif //BSP_USING_SPI0
#ifdef BSP_USING_SPI1
PORT_Init(PORTC, PIN7, FUNMUX1_SPI1_SCLK, 0);
PORT_Init(PORTC, PIN6, FUNMUX0_SPI1_MOSI, 0);
PORT_Init(PORTC, PIN5, FUNMUX1_SPI1_MISO, 1);
PORT_Init(PORTB, PIN1, FUNMUX1_SPI1_SCLK, 0);
PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0);
PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1);
#endif //BSP_USING_SPI1
for (int i = 0; i < sizeof(spi_cfg) / sizeof(spi_cfg[0]); i++)
{

160
bsp/swm320/drivers/linker_scripts/link.lds
View File

@ -1,71 +1,137 @@
/* Entry Point */
ENTRY(Reset_Handler)
/* Specify the memory areas */
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (arx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512k */
RAM (arw) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128k */
CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 1024KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
/* Define output sections */
SECTIONS
{
. = ORIGIN(ROM);
.text :
{
KEEP(*(.isr_vector))
*(.text)
*(.text*)
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
} > ROM
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
. = ALIGN(4);
__data_load__ = LOADADDR(.data);
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
.data :
{
__data_start__ = .;
*(.data)
*(.data*)
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
__data_end__ = .;
} > RAM AT> ROM
_etext = .;
} > CODE = 0
. = ALIGN(4);
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
__bss_start__ = .;
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss*)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
.heap :
{
end = .;
__HeapBase = .;
_end = .;
*(.heap)
} > RAM
/* .stack_dummy section doesn't contains any symbols.
* It is only used for linker to calculate size of stack sections */
.stack_dummy :
{
*(.stack)
} > RAM
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

27
bsp/swm320/libraries/CMSIS/CoreSupport/arm_common_tables.h
View File

@ -85,14 +85,13 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
@ -108,13 +107,13 @@ extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENG
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)

54
bsp/swm320/libraries/CMSIS/CoreSupport/arm_const_structs.h
View File

@ -46,34 +46,34 @@
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7349
bsp/swm320/libraries/CMSIS/CoreSupport/arm_math.h
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File diff suppressed because it is too large Load Diff

709
bsp/swm320/libraries/CMSIS/CoreSupport/core_cm0.h
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@ -1,4 +1,4 @@
/**************************************************************************//**
/**************************************************************************/ /**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.00
@ -34,16 +34,16 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#if defined(__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#ifdef __cplusplus
extern "C" {
extern "C"
{
#endif
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
@ -59,7 +59,6 @@
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
@ -68,85 +67,84 @@
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined(__TMS470__)
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#elif defined(__CSMC__)
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ ) /* Cosmic */
#if ( __CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#if defined(__CC_ARM)
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#elif defined(__GNUC__)
#if defined(__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ICCARM__)
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TMS470__)
#if defined __TI__VFP_SUPPORT____
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__TASKING__)
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__CSMC__) /* Cosmic */
#if (__CSMC__ & 0x400) // FPU present for parser
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#ifdef __cplusplus
}
@ -160,25 +158,26 @@
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
extern "C"
{
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
@ -190,18 +189,16 @@
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*@} end of group Cortex_M0 */
/*******************************************************************************
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
@ -209,275 +206,268 @@
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
typedef union
{
struct
{
uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */
uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */
uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */
uint32_t C : 1; /*!< bit: 29 Carry condition code flag */
uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */
uint32_t N : 1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
typedef union
{
struct
{
uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
@ -487,7 +477,6 @@ typedef struct
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@ -495,20 +484,17 @@ typedef struct
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
@ -519,8 +505,6 @@ typedef struct
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
@ -530,36 +514,33 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
#define _BIT_SHIFT(IRQn) ((((uint32_t)(IRQn)) & 0x03) * 8)
#define _SHP_IDX(IRQn) (((((uint32_t)(IRQn)&0x0F) - 8) >> 2))
#define _IP_IDX(IRQn) (((uint32_t)(IRQn) >> 2))
/** \brief Enable External Interrupt
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Disable External Interrupt
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Get Pending Interrupt
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
@ -569,37 +550,34 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return ((uint32_t)((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn)&0x1F))) ? 1 : 0));
}
/** \brief Set Pending Interrupt
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn)&0x1F));
}
/** \brief Clear Pending Interrupt
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
@ -608,18 +586,21 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if (IRQn < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
}
/** \brief Get Interrupt Priority
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
@ -630,36 +611,38 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
if (IRQn < 0)
{
return ((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for Cortex-M0 system interrupts */
else
{
return ((uint32_t)(((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for device specific interrupts */
}
/** \brief System Reset
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while (1)
; /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
@ -667,7 +650,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
@ -682,25 +665,23 @@ __STATIC_INLINE void NVIC_SystemReset(void)
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)
return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority(SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}

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@ -1,4 +1,4 @@
/**************************************************************************//**
/**************************************************************************/ /**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.00
@ -34,22 +34,20 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
@ -63,11 +61,10 @@
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
@ -76,11 +73,10 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
@ -89,11 +85,10 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
@ -102,11 +97,10 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
@ -115,11 +109,10 @@ __STATIC_INLINE uint32_t __get_APSR(void)
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
@ -128,11 +121,10 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
@ -141,11 +133,10 @@ __STATIC_INLINE uint32_t __get_PSP(void)
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
@ -154,11 +145,10 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
@ -167,11 +157,10 @@ __STATIC_INLINE uint32_t __get_MSP(void)
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
@ -180,11 +169,10 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
@ -193,28 +181,25 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
@ -222,13 +207,12 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
@ -237,11 +221,10 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void)
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@ -250,11 +233,10 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
@ -263,14 +245,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@ -281,14 +262,13 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return(0);
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
@ -298,15 +278,14 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
@ -314,257 +293,277 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
__ASM volatile("cpsie i"
:
:
: "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
__ASM volatile("cpsid i"
:
:
: "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, control"
: "=r"(result));
return (result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
__ASM volatile("MSR control, %0"
:
: "r"(control)
: "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, ipsr"
: "=r"(result));
return (result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, apsr"
: "=r"(result));
return (result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, xpsr"
: "=r"(result));
return (result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, psp\n"
: "=r"(result));
return (result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
__ASM volatile("MSR psp, %0\n"
:
: "r"(topOfProcStack)
: "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, msp\n"
: "=r"(result));
return (result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
__ASM volatile("MSR msp, %0\n"
:
: "r"(topOfMainStack)
: "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, primask"
: "=r"(result));
return (result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
__ASM volatile("MSR primask, %0"
:
: "r"(priMask)
: "memory");
}
#if (__CORTEX_M >= 0x03)
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
__ASM volatile("cpsie f"
:
:
: "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
__ASM volatile("cpsid f"
:
:
: "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, basepri_max"
: "=r"(result));
return (result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
__ASM volatile("MSR basepri, %0"
:
: "r"(value)
: "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
__ASM volatile("MRS %0, faultmask"
: "=r"(result));
return (result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
__ASM volatile("MSR faultmask, %0"
:
: "r"(faultMask)
: "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@ -572,52 +571,52 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
/* Empty asm statement works as a scheduling barrier */
__ASM volatile("");
__ASM volatile("VMRS %0, fpscr"
: "=r"(result));
__ASM volatile("");
return (result);
#else
return(0);
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
/* Empty asm statement works as a scheduling barrier */
__ASM volatile("");
__ASM volatile("VMSR fpscr, %0"
:
: "r"(fpscr)
: "vfpcc");
__ASM volatile("");
#endif
}
#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
@ -625,8 +624,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>

410
bsp/swm320/libraries/CMSIS/CoreSupport/core_cmInstr.h
View File

@ -1,4 +1,4 @@
/**************************************************************************//**
/**************************************************************************/ /**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.00
@ -34,54 +34,47 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
@ -89,24 +82,21 @@
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
@ -115,8 +105,7 @@
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
#define __REV __rev
/** \brief Reverse byte order (16 bit)
@ -128,8 +117,8 @@
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
rev16 r0, r0
bx lr
}
#endif
@ -143,12 +132,11 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@ -157,8 +145,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#define __ROR __ror
/** \brief Breakpoint
@ -168,10 +155,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
@ -180,8 +166,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
@ -190,8 +175,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
@ -200,8 +184,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
@ -210,8 +193,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr))
/** \brief STR Exclusive (8 bit)
@ -222,8 +204,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
@ -234,8 +215,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
@ -246,16 +226,14 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
#define __CLREX __clrex
/** \brief Signed Saturate
@ -265,8 +243,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
#define __SSAT __ssat
/** \brief Unsigned Saturate
@ -276,8 +253,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
#define __USAT __usat
/** \brief Count leading zeros
@ -286,8 +262,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#define __CLZ __clz
/** \brief Rotate Right with Extend (32 bit)
@ -299,12 +274,11 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
rrx r0, r0
bx lr
}
#endif
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
@ -312,8 +286,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
#define __LDRBT(ptr) ((uint8_t)__ldrt(ptr))
/** \brief LDRT Unprivileged (16 bit)
@ -322,8 +295,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
#define __LDRHT(ptr) ((uint16_t)__ldrt(ptr))
/** \brief LDRT Unprivileged (32 bit)
@ -332,8 +304,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
#define __LDRT(ptr) ((uint32_t)__ldrt(ptr))
/** \brief STRT Unprivileged (8 bit)
@ -342,8 +313,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
#define __STRBT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (16 bit)
@ -352,8 +322,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
#define __STRHT(value, ptr) __strt(value, ptr)
/** \brief STRT Unprivileged (32 bit)
@ -362,101 +331,93 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#if defined(__thumb__) && !defined(__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l"(r)
#define __CMSIS_GCC_USE_REG(r) "l"(r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#define __CMSIS_GCC_OUT_REG(r) "=r"(r)
#define __CMSIS_GCC_USE_REG(r) "r"(r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
__ASM volatile("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
__ASM volatile("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
__ASM volatile("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
__ASM volatile("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
__ASM volatile("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
__ASM volatile("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
__ASM volatile("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
@ -464,19 +425,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
return __builtin_bswap32(value);
#else
uint32_t result;
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
__ASM volatile("rev %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
@ -484,15 +446,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
__ASM volatile("rev16 %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
@ -500,19 +463,20 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
return (short)__builtin_bswap16(value);
#else
uint32_t result;
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
__ASM volatile("revsh %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
@ -521,12 +485,11 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
@ -535,10 +498,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#define __BKPT(value) __ASM volatile("bkpt " #value)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Reverse bit order of value
@ -547,15 +509,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
__ASM volatile("rbit %0, %1"
: "=r"(result)
: "r"(value));
return (result);
}
/** \brief LDR Exclusive (8 bit)
This function executes a exclusive LDR instruction for 8 bit value.
@ -563,22 +526,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
__ASM volatile("ldrexb %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
__ASM volatile("ldrexb %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint8_t) result); /* Add explicit type cast here */
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
This function executes a exclusive LDR instruction for 16 bit values.
@ -586,22 +553,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
__ASM volatile("ldrexh %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
__ASM volatile("ldrexh %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint16_t) result); /* Add explicit type cast here */
return ((uint16_t)result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
This function executes a exclusive LDR instruction for 32 bit values.
@ -609,15 +580,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
__ASM volatile("ldrex %0, %1"
: "=r"(result)
: "Q"(*addr));
return (result);
}
/** \brief STR Exclusive (8 bit)
This function executes a exclusive STR instruction for 8 bit values.
@ -627,15 +599,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
__ASM volatile("strexb %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"((uint32_t)value));
return (result);
}
/** \brief STR Exclusive (16 bit)
This function executes a exclusive STR instruction for 16 bit values.
@ -645,15 +618,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
__ASM volatile("strexh %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"((uint32_t)value));
return (result);
}
/** \brief STR Exclusive (32 bit)
This function executes a exclusive STR instruction for 32 bit values.
@ -663,26 +637,27 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
__ASM volatile("strex %0, %2, %1"
: "=&r"(result), "=Q"(*addr)
: "r"(value));
return (result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
__ASM volatile("clrex" ::
: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
@ -691,13 +666,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __SSAT(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("ssat %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
/** \brief Unsigned Saturate
@ -707,13 +684,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
#define __USAT(ARG1, ARG2) \
( \
{ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM("usat %0, %1, %2" \
: "=r"(__RES) \
: "I"(ARG2), "r"(__ARG1)); \
__RES; \
})
/** \brief Count leading zeros
@ -722,15 +701,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return ((uint8_t) result); /* Add explicit type cast here */
__ASM volatile("clz %0, %1"
: "=r"(result)
: "r"(value));
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief Rotate Right with Extend (32 bit)
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
@ -738,15 +718,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
\param [in] value Value to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
uint32_t result;
uint32_t result;
__ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
__ASM volatile("rrx %0, %1"
: __CMSIS_GCC_OUT_REG(result)
: __CMSIS_GCC_USE_REG(value));
return (result);
}
/** \brief LDRT Unprivileged (8 bit)
This function executes a Unprivileged LDRT instruction for 8 bit value.
@ -754,22 +735,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
__ASM volatile("ldrbt %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
__ASM volatile("ldrbt %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint8_t) result); /* Add explicit type cast here */
return ((uint8_t)result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (16 bit)
This function executes a Unprivileged LDRT instruction for 16 bit values.
@ -777,22 +762,26 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
__ASM volatile("ldrht %0, %1"
: "=r"(result)
: "Q"(*addr));
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
__ASM volatile("ldrht %0, [%1]"
: "=r"(result)
: "r"(addr)
: "memory");
#endif
return ((uint16_t) result); /* Add explicit type cast here */
return ((uint16_t)result); /* Add explicit type cast here */
}
/** \brief LDRT Unprivileged (32 bit)
This function executes a Unprivileged LDRT instruction for 32 bit values.
@ -800,15 +789,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
__ASM volatile("ldrt %0, %1"
: "=r"(result)
: "Q"(*addr));
return (result);
}
/** \brief STRT Unprivileged (8 bit)
This function executes a Unprivileged STRT instruction for 8 bit values.
@ -816,12 +806,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
__ASM volatile("strbt %1, %0"
: "=Q"(*addr)
: "r"((uint32_t)value));
}
/** \brief STRT Unprivileged (16 bit)
This function executes a Unprivileged STRT instruction for 16 bit values.
@ -829,12 +820,13 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
__ASM volatile("strht %1, %0"
: "=Q"(*addr)
: "r"((uint32_t)value));
}
/** \brief STRT Unprivileged (32 bit)
This function executes a Unprivileged STRT instruction for 32 bit values.
@ -842,25 +834,24 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value,
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
__ASM volatile("strt %1, %0"
: "=Q"(*addr)
: "r"(value));
}
#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
@ -868,8 +859,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, v
* Including the CMSIS ones.
*/
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
#elif defined(__CSMC__) /*------------------ COSMIC Compiler -------------------*/
/* Cosmic specific functions */
#include <cmsis_csm.h>

887
bsp/swm320/libraries/CMSIS/CoreSupport/core_cmSimd.h
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File diff suppressed because it is too large Load Diff

487
bsp/swm320/libraries/CMSIS/DeviceSupport/SWM320.h
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@ -327,9 +327,9 @@ typedef struct
#define SYS_PLLCR_OFF_Pos 2
#define SYS_PLLCR_OFF_Msk (0x01 << SYS_PLLCR_OFF_Pos)
#define SYS_PLLDIV_FBDIV_Pos 0 //PLL FeedBack分频寄存器 \
//VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \
//PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
#define SYS_PLLDIV_FBDIV_Pos 0 /* PLL FeedBack分频寄存器 \
VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV \
PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV */
#define SYS_PLLDIV_FBDIV_Msk (0x1FF << SYS_PLLDIV_FBDIV_Pos)
#define SYS_PLLDIV_ADDIV_Pos 9 //ADC时钟基（即VCO输出分频后的时钟）经ADDIV分频后作为ADC的转换时钟
#define SYS_PLLDIV_ADDIV_Msk (0x1F << SYS_PLLDIV_ADDIV_Pos)
@ -364,8 +364,8 @@ typedef struct
typedef struct
{
__IO uint32_t PORTA_SEL; //给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
//当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设
__IO uint32_t PORTA_SEL; /*给PORTA_SEL[2n+2:2n]赋相应的值，将PORTA.PINn引脚配置成GPIO、模拟、数字等功能
当赋值为PORTA_PINn_FUNMUX时，PORTA.PINn引脚可通过PORTA_MUX寄存器连接到各种数字外设 */
__IO uint32_t PORTB_SEL;
__IO uint32_t PORTC_SEL;
@ -1182,447 +1182,6 @@ typedef struct
__IO uint32_t INTCLR; //写1清除中断标志，只对边沿触发中断有用
} GPIO_TypeDef;
#define GPIO_DATA_PIN0_Pos 0
#define GPIO_DATA_PIN0_Msk (0x01 << GPIO_DATA_PIN0_Pos)
#define GPIO_DATA_PIN1_Pos 1
#define GPIO_DATA_PIN1_Msk (0x01 << GPIO_DATA_PIN1_Pos)
#define GPIO_DATA_PIN2_Pos 2
#define GPIO_DATA_PIN2_Msk (0x01 << GPIO_DATA_PIN2_Pos)
#define GPIO_DATA_PIN3_Pos 3
#define GPIO_DATA_PIN3_Msk (0x01 << GPIO_DATA_PIN3_Pos)
#define GPIO_DATA_PIN4_Pos 4
#define GPIO_DATA_PIN4_Msk (0x01 << GPIO_DATA_PIN4_Pos)
#define GPIO_DATA_PIN5_Pos 5
#define GPIO_DATA_PIN5_Msk (0x01 << GPIO_DATA_PIN5_Pos)
#define GPIO_DATA_PIN6_Pos 6
#define GPIO_DATA_PIN6_Msk (0x01 << GPIO_DATA_PIN6_Pos)
#define GPIO_DATA_PIN7_Pos 7
#define GPIO_DATA_PIN7_Msk (0x01 << GPIO_DATA_PIN7_Pos)
#define GPIO_DATA_PIN8_Pos 8
#define GPIO_DATA_PIN8_Msk (0x01 << GPIO_DATA_PIN8_Pos)
#define GPIO_DATA_PIN9_Pos 9
#define GPIO_DATA_PIN9_Msk (0x01 << GPIO_DATA_PIN9_Pos)
#define GPIO_DATA_PIN10_Pos 10
#define GPIO_DATA_PIN10_Msk (0x01 << GPIO_DATA_PIN10_Pos)
#define GPIO_DATA_PIN11_Pos 11
#define GPIO_DATA_PIN11_Msk (0x01 << GPIO_DATA_PIN11_Pos)
#define GPIO_DATA_PIN12_Pos 12
#define GPIO_DATA_PIN12_Msk (0x01 << GPIO_DATA_PIN12_Pos)
#define GPIO_DATA_PIN13_Pos 13
#define GPIO_DATA_PIN13_Msk (0x01 << GPIO_DATA_PIN13_Pos)
#define GPIO_DATA_PIN14_Pos 14
#define GPIO_DATA_PIN14_Msk (0x01 << GPIO_DATA_PIN14_Pos)
#define GPIO_DATA_PIN15_Pos 15
#define GPIO_DATA_PIN15_Msk (0x01 << GPIO_DATA_PIN15_Pos)
#define GPIO_DATA_PIN16_Pos 16
#define GPIO_DATA_PIN16_Msk (0x01 << GPIO_DATA_PIN16_Pos)
#define GPIO_DATA_PIN17_Pos 17
#define GPIO_DATA_PIN17_Msk (0x01 << GPIO_DATA_PIN17_Pos)
#define GPIO_DATA_PIN18_Pos 18
#define GPIO_DATA_PIN18_Msk (0x01 << GPIO_DATA_PIN18_Pos)
#define GPIO_DATA_PIN19_Pos 19
#define GPIO_DATA_PIN19_Msk (0x01 << GPIO_DATA_PIN19_Pos)
#define GPIO_DATA_PIN20_Pos 20
#define GPIO_DATA_PIN20_Msk (0x01 << GPIO_DATA_PIN20_Pos)
#define GPIO_DATA_PIN21_Pos 21
#define GPIO_DATA_PIN21_Msk (0x01 << GPIO_DATA_PIN21_Pos)
#define GPIO_DATA_PIN22_Pos 22
#define GPIO_DATA_PIN22_Msk (0x01 << GPIO_DATA_PIN22_Pos)
#define GPIO_DATA_PIN23_Pos 23
#define GPIO_DATA_PIN23_Msk (0x01 << GPIO_DATA_PIN23_Pos)
#define GPIO_DIR_PIN0_Pos 0
#define GPIO_DIR_PIN0_Msk (0x01 << GPIO_DIR_PIN0_Pos)
#define GPIO_DIR_PIN1_Pos 1
#define GPIO_DIR_PIN1_Msk (0x01 << GPIO_DIR_PIN1_Pos)
#define GPIO_DIR_PIN2_Pos 2
#define GPIO_DIR_PIN2_Msk (0x01 << GPIO_DIR_PIN2_Pos)
#define GPIO_DIR_PIN3_Pos 3
#define GPIO_DIR_PIN3_Msk (0x01 << GPIO_DIR_PIN3_Pos)
#define GPIO_DIR_PIN4_Pos 4
#define GPIO_DIR_PIN4_Msk (0x01 << GPIO_DIR_PIN4_Pos)
#define GPIO_DIR_PIN5_Pos 5
#define GPIO_DIR_PIN5_Msk (0x01 << GPIO_DIR_PIN5_Pos)
#define GPIO_DIR_PIN6_Pos 6
#define GPIO_DIR_PIN6_Msk (0x01 << GPIO_DIR_PIN6_Pos)
#define GPIO_DIR_PIN7_Pos 7
#define GPIO_DIR_PIN7_Msk (0x01 << GPIO_DIR_PIN7_Pos)
#define GPIO_DIR_PIN8_Pos 8
#define GPIO_DIR_PIN8_Msk (0x01 << GPIO_DIR_PIN8_Pos)
#define GPIO_DIR_PIN9_Pos 9
#define GPIO_DIR_PIN9_Msk (0x01 << GPIO_DIR_PIN9_Pos)
#define GPIO_DIR_PIN10_Pos 10
#define GPIO_DIR_PIN10_Msk (0x01 << GPIO_DIR_PIN10_Pos)
#define GPIO_DIR_PIN11_Pos 11
#define GPIO_DIR_PIN11_Msk (0x01 << GPIO_DIR_PIN11_Pos)
#define GPIO_DIR_PIN12_Pos 12
#define GPIO_DIR_PIN12_Msk (0x01 << GPIO_DIR_PIN12_Pos)
#define GPIO_DIR_PIN13_Pos 13
#define GPIO_DIR_PIN13_Msk (0x01 << GPIO_DIR_PIN13_Pos)
#define GPIO_DIR_PIN14_Pos 14
#define GPIO_DIR_PIN14_Msk (0x01 << GPIO_DIR_PIN14_Pos)
#define GPIO_DIR_PIN15_Pos 15
#define GPIO_DIR_PIN15_Msk (0x01 << GPIO_DIR_PIN15_Pos)
#define GPIO_DIR_PIN16_Pos 16
#define GPIO_DIR_PIN16_Msk (0x01 << GPIO_DIR_PIN16_Pos)
#define GPIO_DIR_PIN17_Pos 17
#define GPIO_DIR_PIN17_Msk (0x01 << GPIO_DIR_PIN17_Pos)
#define GPIO_DIR_PIN18_Pos 18
#define GPIO_DIR_PIN18_Msk (0x01 << GPIO_DIR_PIN18_Pos)
#define GPIO_DIR_PIN19_Pos 19
#define GPIO_DIR_PIN19_Msk (0x01 << GPIO_DIR_PIN19_Pos)
#define GPIO_DIR_PIN20_Pos 20
#define GPIO_DIR_PIN20_Msk (0x01 << GPIO_DIR_PIN20_Pos)
#define GPIO_DIR_PIN21_Pos 21
#define GPIO_DIR_PIN21_Msk (0x01 << GPIO_DIR_PIN21_Pos)
#define GPIO_DIR_PIN22_Pos 22
#define GPIO_DIR_PIN22_Msk (0x01 << GPIO_DIR_PIN22_Pos)
#define GPIO_DIR_PIN23_Pos 23
#define GPIO_DIR_PIN23_Msk (0x01 << GPIO_DIR_PIN23_Pos)
#define GPIO_INTLVLTRG_PIN0_Pos 0
#define GPIO_INTLVLTRG_PIN0_Msk (0x01 << GPIO_INTLVLTRG_PIN0_Pos)
#define GPIO_INTLVLTRG_PIN1_Pos 1
#define GPIO_INTLVLTRG_PIN1_Msk (0x01 << GPIO_INTLVLTRG_PIN1_Pos)
#define GPIO_INTLVLTRG_PIN2_Pos 2
#define GPIO_INTLVLTRG_PIN2_Msk (0x01 << GPIO_INTLVLTRG_PIN2_Pos)
#define GPIO_INTLVLTRG_PIN3_Pos 3
#define GPIO_INTLVLTRG_PIN3_Msk (0x01 << GPIO_INTLVLTRG_PIN3_Pos)
#define GPIO_INTLVLTRG_PIN4_Pos 4
#define GPIO_INTLVLTRG_PIN4_Msk (0x01 << GPIO_INTLVLTRG_PIN4_Pos)
#define GPIO_INTLVLTRG_PIN5_Pos 5
#define GPIO_INTLVLTRG_PIN5_Msk (0x01 << GPIO_INTLVLTRG_PIN5_Pos)
#define GPIO_INTLVLTRG_PIN6_Pos 6
#define GPIO_INTLVLTRG_PIN6_Msk (0x01 << GPIO_INTLVLTRG_PIN6_Pos)
#define GPIO_INTLVLTRG_PIN7_Pos 7
#define GPIO_INTLVLTRG_PIN7_Msk (0x01 << GPIO_INTLVLTRG_PIN7_Pos)
#define GPIO_INTLVLTRG_PIN8_Pos 8
#define GPIO_INTLVLTRG_PIN8_Msk (0x01 << GPIO_INTLVLTRG_PIN8_Pos)
#define GPIO_INTLVLTRG_PIN9_Pos 9
#define GPIO_INTLVLTRG_PIN9_Msk (0x01 << GPIO_INTLVLTRG_PIN9_Pos)
#define GPIO_INTLVLTRG_PIN10_Pos 10
#define GPIO_INTLVLTRG_PIN10_Msk (0x01 << GPIO_INTLVLTRG_PIN10_Pos)
#define GPIO_INTLVLTRG_PIN11_Pos 11
#define GPIO_INTLVLTRG_PIN11_Msk (0x01 << GPIO_INTLVLTRG_PIN11_Pos)
#define GPIO_INTLVLTRG_PIN12_Pos 12
#define GPIO_INTLVLTRG_PIN12_Msk (0x01 << GPIO_INTLVLTRG_PIN12_Pos)
#define GPIO_INTLVLTRG_PIN13_Pos 13
#define GPIO_INTLVLTRG_PIN13_Msk (0x01 << GPIO_INTLVLTRG_PIN13_Pos)
#define GPIO_INTLVLTRG_PIN14_Pos 14
#define GPIO_INTLVLTRG_PIN14_Msk (0x01 << GPIO_INTLVLTRG_PIN14_Pos)
#define GPIO_INTLVLTRG_PIN15_Pos 15
#define GPIO_INTLVLTRG_PIN15_Msk (0x01 << GPIO_INTLVLTRG_PIN15_Pos)
#define GPIO_INTLVLTRG_PIN16_Pos 16
#define GPIO_INTLVLTRG_PIN16_Msk (0x01 << GPIO_INTLVLTRG_PIN16_Pos)
#define GPIO_INTLVLTRG_PIN17_Pos 17
#define GPIO_INTLVLTRG_PIN17_Msk (0x01 << GPIO_INTLVLTRG_PIN17_Pos)
#define GPIO_INTLVLTRG_PIN18_Pos 18
#define GPIO_INTLVLTRG_PIN18_Msk (0x01 << GPIO_INTLVLTRG_PIN18_Pos)
#define GPIO_INTLVLTRG_PIN19_Pos 19
#define GPIO_INTLVLTRG_PIN19_Msk (0x01 << GPIO_INTLVLTRG_PIN19_Pos)
#define GPIO_INTLVLTRG_PIN20_Pos 20
#define GPIO_INTLVLTRG_PIN20_Msk (0x01 << GPIO_INTLVLTRG_PIN20_Pos)
#define GPIO_INTLVLTRG_PIN21_Pos 21
#define GPIO_INTLVLTRG_PIN21_Msk (0x01 << GPIO_INTLVLTRG_PIN21_Pos)
#define GPIO_INTLVLTRG_PIN22_Pos 22
#define GPIO_INTLVLTRG_PIN22_Msk (0x01 << GPIO_INTLVLTRG_PIN22_Pos)
#define GPIO_INTLVLTRG_PIN23_Pos 23
#define GPIO_INTLVLTRG_PIN23_Msk (0x01 << GPIO_INTLVLTRG_PIN23_Pos)
#define GPIO_INTBE_PIN0_Pos 0
#define GPIO_INTBE_PIN0_Msk (0x01 << GPIO_INTBE_PIN0_Pos)
#define GPIO_INTBE_PIN1_Pos 1
#define GPIO_INTBE_PIN1_Msk (0x01 << GPIO_INTBE_PIN1_Pos)
#define GPIO_INTBE_PIN2_Pos 2
#define GPIO_INTBE_PIN2_Msk (0x01 << GPIO_INTBE_PIN2_Pos)
#define GPIO_INTBE_PIN3_Pos 3
#define GPIO_INTBE_PIN3_Msk (0x01 << GPIO_INTBE_PIN3_Pos)
#define GPIO_INTBE_PIN4_Pos 4
#define GPIO_INTBE_PIN4_Msk (0x01 << GPIO_INTBE_PIN4_Pos)
#define GPIO_INTBE_PIN5_Pos 5
#define GPIO_INTBE_PIN5_Msk (0x01 << GPIO_INTBE_PIN5_Pos)
#define GPIO_INTBE_PIN6_Pos 6
#define GPIO_INTBE_PIN6_Msk (0x01 << GPIO_INTBE_PIN6_Pos)
#define GPIO_INTBE_PIN7_Pos 7
#define GPIO_INTBE_PIN7_Msk (0x01 << GPIO_INTBE_PIN7_Pos)
#define GPIO_INTBE_PIN8_Pos 8
#define GPIO_INTBE_PIN8_Msk (0x01 << GPIO_INTBE_PIN8_Pos)
#define GPIO_INTBE_PIN9_Pos 9
#define GPIO_INTBE_PIN9_Msk (0x01 << GPIO_INTBE_PIN9_Pos)
#define GPIO_INTBE_PIN10_Pos 10
#define GPIO_INTBE_PIN10_Msk (0x01 << GPIO_INTBE_PIN10_Pos)
#define GPIO_INTBE_PIN11_Pos 11
#define GPIO_INTBE_PIN11_Msk (0x01 << GPIO_INTBE_PIN11_Pos)
#define GPIO_INTBE_PIN12_Pos 12
#define GPIO_INTBE_PIN12_Msk (0x01 << GPIO_INTBE_PIN12_Pos)
#define GPIO_INTBE_PIN13_Pos 13
#define GPIO_INTBE_PIN13_Msk (0x01 << GPIO_INTBE_PIN13_Pos)
#define GPIO_INTBE_PIN14_Pos 14
#define GPIO_INTBE_PIN14_Msk (0x01 << GPIO_INTBE_PIN14_Pos)
#define GPIO_INTBE_PIN15_Pos 15
#define GPIO_INTBE_PIN15_Msk (0x01 << GPIO_INTBE_PIN15_Pos)
#define GPIO_INTBE_PIN16_Pos 16
#define GPIO_INTBE_PIN16_Msk (0x01 << GPIO_INTBE_PIN16_Pos)
#define GPIO_INTBE_PIN17_Pos 17
#define GPIO_INTBE_PIN17_Msk (0x01 << GPIO_INTBE_PIN17_Pos)
#define GPIO_INTBE_PIN18_Pos 18
#define GPIO_INTBE_PIN18_Msk (0x01 << GPIO_INTBE_PIN18_Pos)
#define GPIO_INTBE_PIN19_Pos 19
#define GPIO_INTBE_PIN19_Msk (0x01 << GPIO_INTBE_PIN19_Pos)
#define GPIO_INTBE_PIN20_Pos 20
#define GPIO_INTBE_PIN20_Msk (0x01 << GPIO_INTBE_PIN20_Pos)
#define GPIO_INTBE_PIN21_Pos 21
#define GPIO_INTBE_PIN21_Msk (0x01 << GPIO_INTBE_PIN21_Pos)
#define GPIO_INTBE_PIN22_Pos 22
#define GPIO_INTBE_PIN22_Msk (0x01 << GPIO_INTBE_PIN22_Pos)
#define GPIO_INTBE_PIN23_Pos 23
#define GPIO_INTBE_PIN23_Msk (0x01 << GPIO_INTBE_PIN23_Pos)
#define GPIO_INTRISEEN_PIN0_Pos 0
#define GPIO_INTRISEEN_PIN0_Msk (0x01 << GPIO_INTRISEEN_PIN0_Pos)
#define GPIO_INTRISEEN_PIN1_Pos 1
#define GPIO_INTRISEEN_PIN1_Msk (0x01 << GPIO_INTRISEEN_PIN1_Pos)
#define GPIO_INTRISEEN_PIN2_Pos 2
#define GPIO_INTRISEEN_PIN2_Msk (0x01 << GPIO_INTRISEEN_PIN2_Pos)
#define GPIO_INTRISEEN_PIN3_Pos 3
#define GPIO_INTRISEEN_PIN3_Msk (0x01 << GPIO_INTRISEEN_PIN3_Pos)
#define GPIO_INTRISEEN_PIN4_Pos 4
#define GPIO_INTRISEEN_PIN4_Msk (0x01 << GPIO_INTRISEEN_PIN4_Pos)
#define GPIO_INTRISEEN_PIN5_Pos 5
#define GPIO_INTRISEEN_PIN5_Msk (0x01 << GPIO_INTRISEEN_PIN5_Pos)
#define GPIO_INTRISEEN_PIN6_Pos 6
#define GPIO_INTRISEEN_PIN6_Msk (0x01 << GPIO_INTRISEEN_PIN6_Pos)
#define GPIO_INTRISEEN_PIN7_Pos 7
#define GPIO_INTRISEEN_PIN7_Msk (0x01 << GPIO_INTRISEEN_PIN7_Pos)
#define GPIO_INTRISEEN_PIN8_Pos 8
#define GPIO_INTRISEEN_PIN8_Msk (0x01 << GPIO_INTRISEEN_PIN8_Pos)
#define GPIO_INTRISEEN_PIN9_Pos 9
#define GPIO_INTRISEEN_PIN9_Msk (0x01 << GPIO_INTRISEEN_PIN9_Pos)
#define GPIO_INTRISEEN_PIN10_Pos 10
#define GPIO_INTRISEEN_PIN10_Msk (0x01 << GPIO_INTRISEEN_PIN10_Pos)
#define GPIO_INTRISEEN_PIN11_Pos 11
#define GPIO_INTRISEEN_PIN11_Msk (0x01 << GPIO_INTRISEEN_PIN11_Pos)
#define GPIO_INTRISEEN_PIN12_Pos 12
#define GPIO_INTRISEEN_PIN12_Msk (0x01 << GPIO_INTRISEEN_PIN12_Pos)
#define GPIO_INTRISEEN_PIN13_Pos 13
#define GPIO_INTRISEEN_PIN13_Msk (0x01 << GPIO_INTRISEEN_PIN13_Pos)
#define GPIO_INTRISEEN_PIN14_Pos 14
#define GPIO_INTRISEEN_PIN14_Msk (0x01 << GPIO_INTRISEEN_PIN14_Pos)
#define GPIO_INTRISEEN_PIN15_Pos 15
#define GPIO_INTRISEEN_PIN15_Msk (0x01 << GPIO_INTRISEEN_PIN15_Pos)
#define GPIO_INTRISEEN_PIN16_Pos 16
#define GPIO_INTRISEEN_PIN16_Msk (0x01 << GPIO_INTRISEEN_PIN16_Pos)
#define GPIO_INTRISEEN_PIN17_Pos 17
#define GPIO_INTRISEEN_PIN17_Msk (0x01 << GPIO_INTRISEEN_PIN17_Pos)
#define GPIO_INTRISEEN_PIN18_Pos 18
#define GPIO_INTRISEEN_PIN18_Msk (0x01 << GPIO_INTRISEEN_PIN18_Pos)
#define GPIO_INTRISEEN_PIN19_Pos 19
#define GPIO_INTRISEEN_PIN19_Msk (0x01 << GPIO_INTRISEEN_PIN19_Pos)
#define GPIO_INTRISEEN_PIN20_Pos 20
#define GPIO_INTRISEEN_PIN20_Msk (0x01 << GPIO_INTRISEEN_PIN20_Pos)
#define GPIO_INTRISEEN_PIN21_Pos 21
#define GPIO_INTRISEEN_PIN21_Msk (0x01 << GPIO_INTRISEEN_PIN21_Pos)
#define GPIO_INTRISEEN_PIN22_Pos 22
#define GPIO_INTRISEEN_PIN22_Msk (0x01 << GPIO_INTRISEEN_PIN22_Pos)
#define GPIO_INTRISEEN_PIN23_Pos 23
#define GPIO_INTRISEEN_PIN23_Msk (0x01 << GPIO_INTRISEEN_PIN23_Pos)
#define GPIO_INTEN_PIN0_Pos 0
#define GPIO_INTEN_PIN0_Msk (0x01 << GPIO_INTEN_PIN0_Pos)
#define GPIO_INTEN_PIN1_Pos 1
#define GPIO_INTEN_PIN1_Msk (0x01 << GPIO_INTEN_PIN1_Pos)
#define GPIO_INTEN_PIN2_Pos 2
#define GPIO_INTEN_PIN2_Msk (0x01 << GPIO_INTEN_PIN2_Pos)
#define GPIO_INTEN_PIN3_Pos 3
#define GPIO_INTEN_PIN3_Msk (0x01 << GPIO_INTEN_PIN3_Pos)
#define GPIO_INTEN_PIN4_Pos 4
#define GPIO_INTEN_PIN4_Msk (0x01 << GPIO_INTEN_PIN4_Pos)
#define GPIO_INTEN_PIN5_Pos 5
#define GPIO_INTEN_PIN5_Msk (0x01 << GPIO_INTEN_PIN5_Pos)
#define GPIO_INTEN_PIN6_Pos 6
#define GPIO_INTEN_PIN6_Msk (0x01 << GPIO_INTEN_PIN6_Pos)
#define GPIO_INTEN_PIN7_Pos 7
#define GPIO_INTEN_PIN7_Msk (0x01 << GPIO_INTEN_PIN7_Pos)
#define GPIO_INTEN_PIN8_Pos 8
#define GPIO_INTEN_PIN8_Msk (0x01 << GPIO_INTEN_PIN8_Pos)
#define GPIO_INTEN_PIN9_Pos 9
#define GPIO_INTEN_PIN9_Msk (0x01 << GPIO_INTEN_PIN9_Pos)
#define GPIO_INTEN_PIN10_Pos 10
#define GPIO_INTEN_PIN10_Msk (0x01 << GPIO_INTEN_PIN10_Pos)
#define GPIO_INTEN_PIN11_Pos 11
#define GPIO_INTEN_PIN11_Msk (0x01 << GPIO_INTEN_PIN11_Pos)
#define GPIO_INTEN_PIN12_Pos 12
#define GPIO_INTEN_PIN12_Msk (0x01 << GPIO_INTEN_PIN12_Pos)
#define GPIO_INTEN_PIN13_Pos 13
#define GPIO_INTEN_PIN13_Msk (0x01 << GPIO_INTEN_PIN13_Pos)
#define GPIO_INTEN_PIN14_Pos 14
#define GPIO_INTEN_PIN14_Msk (0x01 << GPIO_INTEN_PIN14_Pos)
#define GPIO_INTEN_PIN15_Pos 15
#define GPIO_INTEN_PIN15_Msk (0x01 << GPIO_INTEN_PIN15_Pos)
#define GPIO_INTEN_PIN16_Pos 16
#define GPIO_INTEN_PIN16_Msk (0x01 << GPIO_INTEN_PIN16_Pos)
#define GPIO_INTEN_PIN17_Pos 17
#define GPIO_INTEN_PIN17_Msk (0x01 << GPIO_INTEN_PIN17_Pos)
#define GPIO_INTEN_PIN18_Pos 18
#define GPIO_INTEN_PIN18_Msk (0x01 << GPIO_INTEN_PIN18_Pos)
#define GPIO_INTEN_PIN19_Pos 19
#define GPIO_INTEN_PIN19_Msk (0x01 << GPIO_INTEN_PIN19_Pos)
#define GPIO_INTEN_PIN20_Pos 20
#define GPIO_INTEN_PIN20_Msk (0x01 << GPIO_INTEN_PIN20_Pos)
#define GPIO_INTEN_PIN21_Pos 21
#define GPIO_INTEN_PIN21_Msk (0x01 << GPIO_INTEN_PIN21_Pos)
#define GPIO_INTEN_PIN22_Pos 22
#define GPIO_INTEN_PIN22_Msk (0x01 << GPIO_INTEN_PIN22_Pos)
#define GPIO_INTEN_PIN23_Pos 23
#define GPIO_INTEN_PIN23_Msk (0x01 << GPIO_INTEN_PIN23_Pos)
#define GPIO_INTRAWSTAT_PIN0_Pos 0
#define GPIO_INTRAWSTAT_PIN0_Msk (0x01 << GPIO_INTRAWSTAT_PIN0_Pos)
#define GPIO_INTRAWSTAT_PIN1_Pos 1
#define GPIO_INTRAWSTAT_PIN1_Msk (0x01 << GPIO_INTRAWSTAT_PIN1_Pos)
#define GPIO_INTRAWSTAT_PIN2_Pos 2
#define GPIO_INTRAWSTAT_PIN2_Msk (0x01 << GPIO_INTRAWSTAT_PIN2_Pos)
#define GPIO_INTRAWSTAT_PIN3_Pos 3
#define GPIO_INTRAWSTAT_PIN3_Msk (0x01 << GPIO_INTRAWSTAT_PIN3_Pos)
#define GPIO_INTRAWSTAT_PIN4_Pos 4
#define GPIO_INTRAWSTAT_PIN4_Msk (0x01 << GPIO_INTRAWSTAT_PIN4_Pos)
#define GPIO_INTRAWSTAT_PIN5_Pos 5
#define GPIO_INTRAWSTAT_PIN5_Msk (0x01 << GPIO_INTRAWSTAT_PIN5_Pos)
#define GPIO_INTRAWSTAT_PIN6_Pos 6
#define GPIO_INTRAWSTAT_PIN6_Msk (0x01 << GPIO_INTRAWSTAT_PIN6_Pos)
#define GPIO_INTRAWSTAT_PIN7_Pos 7
#define GPIO_INTRAWSTAT_PIN7_Msk (0x01 << GPIO_INTRAWSTAT_PIN7_Pos)
#define GPIO_INTRAWSTAT_PIN8_Pos 8
#define GPIO_INTRAWSTAT_PIN8_Msk (0x01 << GPIO_INTRAWSTAT_PIN8_Pos)
#define GPIO_INTRAWSTAT_PIN9_Pos 9
#define GPIO_INTRAWSTAT_PIN9_Msk (0x01 << GPIO_INTRAWSTAT_PIN9_Pos)
#define GPIO_INTRAWSTAT_PIN10_Pos 10
#define GPIO_INTRAWSTAT_PIN10_Msk (0x01 << GPIO_INTRAWSTAT_PIN10_Pos)
#define GPIO_INTRAWSTAT_PIN11_Pos 11
#define GPIO_INTRAWSTAT_PIN11_Msk (0x01 << GPIO_INTRAWSTAT_PIN11_Pos)
#define GPIO_INTRAWSTAT_PIN12_Pos 12
#define GPIO_INTRAWSTAT_PIN12_Msk (0x01 << GPIO_INTRAWSTAT_PIN12_Pos)
#define GPIO_INTRAWSTAT_PIN13_Pos 13
#define GPIO_INTRAWSTAT_PIN13_Msk (0x01 << GPIO_INTRAWSTAT_PIN13_Pos)
#define GPIO_INTRAWSTAT_PIN14_Pos 14
#define GPIO_INTRAWSTAT_PIN14_Msk (0x01 << GPIO_INTRAWSTAT_PIN14_Pos)
#define GPIO_INTRAWSTAT_PIN15_Pos 15
#define GPIO_INTRAWSTAT_PIN15_Msk (0x01 << GPIO_INTRAWSTAT_PIN15_Pos)
#define GPIO_INTRAWSTAT_PIN16_Pos 16
#define GPIO_INTRAWSTAT_PIN16_Msk (0x01 << GPIO_INTRAWSTAT_PIN16_Pos)
#define GPIO_INTRAWSTAT_PIN17_Pos 17
#define GPIO_INTRAWSTAT_PIN17_Msk (0x01 << GPIO_INTRAWSTAT_PIN17_Pos)
#define GPIO_INTRAWSTAT_PIN18_Pos 18
#define GPIO_INTRAWSTAT_PIN18_Msk (0x01 << GPIO_INTRAWSTAT_PIN18_Pos)
#define GPIO_INTRAWSTAT_PIN19_Pos 19
#define GPIO_INTRAWSTAT_PIN19_Msk (0x01 << GPIO_INTRAWSTAT_PIN19_Pos)
#define GPIO_INTRAWSTAT_PIN20_Pos 20
#define GPIO_INTRAWSTAT_PIN20_Msk (0x01 << GPIO_INTRAWSTAT_PIN20_Pos)
#define GPIO_INTRAWSTAT_PIN21_Pos 21
#define GPIO_INTRAWSTAT_PIN21_Msk (0x01 << GPIO_INTRAWSTAT_PIN21_Pos)
#define GPIO_INTRAWSTAT_PIN22_Pos 22
#define GPIO_INTRAWSTAT_PIN22_Msk (0x01 << GPIO_INTRAWSTAT_PIN22_Pos)
#define GPIO_INTRAWSTAT_PIN23_Pos 23
#define GPIO_INTRAWSTAT_PIN23_Msk (0x01 << GPIO_INTRAWSTAT_PIN23_Pos)
#define GPIO_INTSTAT_PIN0_Pos 0
#define GPIO_INTSTAT_PIN0_Msk (0x01 << GPIO_INTSTAT_PIN0_Pos)
#define GPIO_INTSTAT_PIN1_Pos 1
#define GPIO_INTSTAT_PIN1_Msk (0x01 << GPIO_INTSTAT_PIN1_Pos)
#define GPIO_INTSTAT_PIN2_Pos 2
#define GPIO_INTSTAT_PIN2_Msk (0x01 << GPIO_INTSTAT_PIN2_Pos)
#define GPIO_INTSTAT_PIN3_Pos 3
#define GPIO_INTSTAT_PIN3_Msk (0x01 << GPIO_INTSTAT_PIN3_Pos)
#define GPIO_INTSTAT_PIN4_Pos 4
#define GPIO_INTSTAT_PIN4_Msk (0x01 << GPIO_INTSTAT_PIN4_Pos)
#define GPIO_INTSTAT_PIN5_Pos 5
#define GPIO_INTSTAT_PIN5_Msk (0x01 << GPIO_INTSTAT_PIN5_Pos)
#define GPIO_INTSTAT_PIN6_Pos 6
#define GPIO_INTSTAT_PIN6_Msk (0x01 << GPIO_INTSTAT_PIN6_Pos)
#define GPIO_INTSTAT_PIN7_Pos 7
#define GPIO_INTSTAT_PIN7_Msk (0x01 << GPIO_INTSTAT_PIN7_Pos)
#define GPIO_INTSTAT_PIN8_Pos 8
#define GPIO_INTSTAT_PIN8_Msk (0x01 << GPIO_INTSTAT_PIN8_Pos)
#define GPIO_INTSTAT_PIN9_Pos 9
#define GPIO_INTSTAT_PIN9_Msk (0x01 << GPIO_INTSTAT_PIN9_Pos)
#define GPIO_INTSTAT_PIN10_Pos 10
#define GPIO_INTSTAT_PIN10_Msk (0x01 << GPIO_INTSTAT_PIN10_Pos)
#define GPIO_INTSTAT_PIN11_Pos 11
#define GPIO_INTSTAT_PIN11_Msk (0x01 << GPIO_INTSTAT_PIN11_Pos)
#define GPIO_INTSTAT_PIN12_Pos 12
#define GPIO_INTSTAT_PIN12_Msk (0x01 << GPIO_INTSTAT_PIN12_Pos)
#define GPIO_INTSTAT_PIN13_Pos 13
#define GPIO_INTSTAT_PIN13_Msk (0x01 << GPIO_INTSTAT_PIN13_Pos)
#define GPIO_INTSTAT_PIN14_Pos 14
#define GPIO_INTSTAT_PIN14_Msk (0x01 << GPIO_INTSTAT_PIN14_Pos)
#define GPIO_INTSTAT_PIN15_Pos 15
#define GPIO_INTSTAT_PIN15_Msk (0x01 << GPIO_INTSTAT_PIN15_Pos)
#define GPIO_INTSTAT_PIN16_Pos 16
#define GPIO_INTSTAT_PIN16_Msk (0x01 << GPIO_INTSTAT_PIN16_Pos)
#define GPIO_INTSTAT_PIN17_Pos 17
#define GPIO_INTSTAT_PIN17_Msk (0x01 << GPIO_INTSTAT_PIN17_Pos)
#define GPIO_INTSTAT_PIN18_Pos 18
#define GPIO_INTSTAT_PIN18_Msk (0x01 << GPIO_INTSTAT_PIN18_Pos)
#define GPIO_INTSTAT_PIN19_Pos 19
#define GPIO_INTSTAT_PIN19_Msk (0x01 << GPIO_INTSTAT_PIN19_Pos)
#define GPIO_INTSTAT_PIN20_Pos 20
#define GPIO_INTSTAT_PIN20_Msk (0x01 << GPIO_INTSTAT_PIN20_Pos)
#define GPIO_INTSTAT_PIN21_Pos 21
#define GPIO_INTSTAT_PIN21_Msk (0x01 << GPIO_INTSTAT_PIN21_Pos)
#define GPIO_INTSTAT_PIN22_Pos 22
#define GPIO_INTSTAT_PIN22_Msk (0x01 << GPIO_INTSTAT_PIN22_Pos)
#define GPIO_INTSTAT_PIN23_Pos 23
#define GPIO_INTSTAT_PIN23_Msk (0x01 << GPIO_INTSTAT_PIN23_Pos)
#define GPIO_INTCLR_PIN0_Pos 0
#define GPIO_INTCLR_PIN0_Msk (0x01 << GPIO_INTCLR_PIN0_Pos)
#define GPIO_INTCLR_PIN1_Pos 1
#define GPIO_INTCLR_PIN1_Msk (0x01 << GPIO_INTCLR_PIN1_Pos)
#define GPIO_INTCLR_PIN2_Pos 2
#define GPIO_INTCLR_PIN2_Msk (0x01 << GPIO_INTCLR_PIN2_Pos)
#define GPIO_INTCLR_PIN3_Pos 3
#define GPIO_INTCLR_PIN3_Msk (0x01 << GPIO_INTCLR_PIN3_Pos)
#define GPIO_INTCLR_PIN4_Pos 4
#define GPIO_INTCLR_PIN4_Msk (0x01 << GPIO_INTCLR_PIN4_Pos)
#define GPIO_INTCLR_PIN5_Pos 5
#define GPIO_INTCLR_PIN5_Msk (0x01 << GPIO_INTCLR_PIN5_Pos)
#define GPIO_INTCLR_PIN6_Pos 6
#define GPIO_INTCLR_PIN6_Msk (0x01 << GPIO_INTCLR_PIN6_Pos)
#define GPIO_INTCLR_PIN7_Pos 7
#define GPIO_INTCLR_PIN7_Msk (0x01 << GPIO_INTCLR_PIN7_Pos)
#define GPIO_INTCLR_PIN8_Pos 8
#define GPIO_INTCLR_PIN8_Msk (0x01 << GPIO_INTCLR_PIN8_Pos)
#define GPIO_INTCLR_PIN9_Pos 9
#define GPIO_INTCLR_PIN9_Msk (0x01 << GPIO_INTCLR_PIN9_Pos)
#define GPIO_INTCLR_PIN10_Pos 10
#define GPIO_INTCLR_PIN10_Msk (0x01 << GPIO_INTCLR_PIN10_Pos)
#define GPIO_INTCLR_PIN11_Pos 11
#define GPIO_INTCLR_PIN11_Msk (0x01 << GPIO_INTCLR_PIN11_Pos)
#define GPIO_INTCLR_PIN12_Pos 12
#define GPIO_INTCLR_PIN12_Msk (0x01 << GPIO_INTCLR_PIN12_Pos)
#define GPIO_INTCLR_PIN13_Pos 13
#define GPIO_INTCLR_PIN13_Msk (0x01 << GPIO_INTCLR_PIN13_Pos)
#define GPIO_INTCLR_PIN14_Pos 14
#define GPIO_INTCLR_PIN14_Msk (0x01 << GPIO_INTCLR_PIN14_Pos)
#define GPIO_INTCLR_PIN15_Pos 15
#define GPIO_INTCLR_PIN15_Msk (0x01 << GPIO_INTCLR_PIN15_Pos)
#define GPIO_INTCLR_PIN16_Pos 16
#define GPIO_INTCLR_PIN16_Msk (0x01 << GPIO_INTCLR_PIN16_Pos)
#define GPIO_INTCLR_PIN17_Pos 17
#define GPIO_INTCLR_PIN17_Msk (0x01 << GPIO_INTCLR_PIN17_Pos)
#define GPIO_INTCLR_PIN18_Pos 18
#define GPIO_INTCLR_PIN18_Msk (0x01 << GPIO_INTCLR_PIN18_Pos)
#define GPIO_INTCLR_PIN19_Pos 19
#define GPIO_INTCLR_PIN19_Msk (0x01 << GPIO_INTCLR_PIN19_Pos)
#define GPIO_INTCLR_PIN20_Pos 20
#define GPIO_INTCLR_PIN20_Msk (0x01 << GPIO_INTCLR_PIN20_Pos)
#define GPIO_INTCLR_PIN21_Pos 21
#define GPIO_INTCLR_PIN21_Msk (0x01 << GPIO_INTCLR_PIN21_Pos)
#define GPIO_INTCLR_PIN22_Pos 22
#define GPIO_INTCLR_PIN22_Msk (0x01 << GPIO_INTCLR_PIN22_Pos)
#define GPIO_INTCLR_PIN23_Pos 23
#define GPIO_INTCLR_PIN23_Msk (0x01 << GPIO_INTCLR_PIN23_Pos)
typedef struct
{
__IO uint32_t LDVAL; //定时器加载值，使能后定时器从此数值开始向下递减计数
@ -1790,10 +1349,10 @@ typedef struct
#define UART_BAUD_RXIF_Msk (0x01 << UART_BAUD_RXIF_Pos)
#define UART_BAUD_ABREN_Pos 23 //Auto Baudrate Enable，写1启动自动波特率校准，完成后自动清零
#define UART_BAUD_ABREN_Msk (0x01 << UART_BAUD_ABREN_Pos)
#define UART_BAUD_ABRBIT_Pos 24 //Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF \
#define UART_BAUD_ABRBIT_Pos 24 /*Auto Baudrate Bit，用于计算波特率的检测位长，0 1位，通过测起始位 脉宽计算波特率，要求发送端发送0xFF \
// 1 2位，通过测起始位加1位数据位脉宽计算波特率，要求发送端发送0xFE \
// 1 4位，通过测起始位加3位数据位脉宽计算波特率，要求发送端发送0xF8 \
// 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80
// 1 8位，通过测起始位加7位数据位脉宽计算波特率，要求发送端发送0x80 */
#define UART_BAUD_ABRBIT_Msk (0x03 << UART_BAUD_ABRBIT_Pos)
#define UART_BAUD_ABRERR_Pos 26 //Auto Baudrate Error，0 自动波特率校准成功 1 自动波特率校准失败
#define UART_BAUD_ABRERR_Msk (0x01 << UART_BAUD_ABRERR_Pos)
@ -2724,22 +2283,12 @@ typedef struct
uint32_t RESERVED[5];
} FILTER;
union
struct
{ //在正常工作模式下可读写，复位时不可访问
struct
{
__O uint32_t INFO;
__IO uint32_t INFO;
__O uint32_t DATA[12];
} TXFRAME;
struct
{
__I uint32_t INFO;
__I uint32_t DATA[12];
} RXFRAME;
};
__IO uint32_t DATA[12];
} FRAME;
};
__I uint32_t RMCNT; //Receive Message Count
@ -2877,11 +2426,11 @@ typedef struct
#define LCD_START_BURST_Pos 2
#define LCD_START_BURST_Msk (0x01 << LCD_START_BURST_Pos)
#define LCD_CR0_VPIX_Pos 0 //当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \
//当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767
#define LCD_CR0_VPIX_Pos 0 /*当portrait为0时，表示垂直方向的像素个数，0表示1个，最大为767 \
//当portrait为1时，表示水平方向的像素个数，0表示1个，最大为767 */
#define LCD_CR0_VPIX_Msk (0x3FF << LCD_CR0_VPIX_Pos)
#define LCD_CR0_HPIX_Pos 10 //当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \
//当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023
#define LCD_CR0_HPIX_Pos 10 /*当portrait为0时，表示水平方向的像素个数，0表示1个，最大为1023 \
//当portrait为1时，表示垂直方向的像素个数，0表示1个，最大为1023 */
#define LCD_CR0_HPIX_Msk (0x3FF << LCD_CR0_HPIX_Pos)
#define LCD_CR0_DCLK_Pos 20 //0 DOTCLK一直翻转 1 DOTCLK在空闲时停在1
#define LCD_CR0_DCLK_Msk (0x01 << LCD_CR0_DCLK_Pos)
@ -3121,7 +2670,7 @@ typedef struct
{
__IO uint32_t DATA;
__IO uint32_t ADDR;
__IO uint32_t ERASE;
__IO uint32_t SWM_ERASE;
__IO uint32_t CACHE;
__IO uint32_t CFG0;
__IO uint32_t CFG1;
@ -3376,8 +2925,8 @@ typedef struct
#define RTC_TRIM_DEC_Pos 8
#define RTC_TRIM_DEC_Msk (0x01 << RTC_TRIM_DEC_Pos)
#define RTC_TRIMM_CYCLE_Pos 0 //用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \
//cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推
#define RTC_TRIMM_CYCLE_Pos 0 /* 用于计数周期微调，如果INC为1，则第n个计数周期调整为(32768±ADJ)+1,否则调整为(32768±ADJ)-1 \
//cycles=0时，不进行微调整；cycles=1，则n为2；cycles=7，则n为8；以此类推 */
#define RTC_TRIMM_CYCLE_Msk (0x07 << RTC_TRIMM_CYCLE_Pos)
#define RTC_TRIMM_INC_Pos 3
#define RTC_TRIMM_INC_Msk (0x01 << RTC_TRIMM_INC_Pos)

124
bsp/swm320/libraries/CMSIS/DeviceSupport/startup/arm/startup_SWM320.s
View File

@ -79,7 +79,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD GPIOA5_Handler
DCD GPIOA6_Handler
DCD GPIOA7_Handler
DCD GPIOB0_Handler
DCD GPIOB0_Handler
DCD GPIOB1_Handler
DCD GPIOB2_Handler
DCD GPIOB3_Handler
@ -157,262 +157,262 @@ Reset_Handler PROC
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler PROC
EXPORT MemManage_Handler [WEAK]
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler PROC
EXPORT BusFault_Handler [WEAK]
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler PROC
EXPORT UsageFault_Handler [WEAK]
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler PROC
EXPORT DebugMon_Handler [WEAK]
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
B .
ENDP
GPIOA0_Handler PROC
EXPORT GPIOA0_Handler [WEAK]
EXPORT GPIOA0_Handler [WEAK]
B .
ENDP
GPIOA1_Handler PROC
EXPORT GPIOA1_Handler [WEAK]
EXPORT GPIOA1_Handler [WEAK]
B .
ENDP
GPIOA2_Handler PROC
EXPORT GPIOA2_Handler [WEAK]
EXPORT GPIOA2_Handler [WEAK]
B .
ENDP
GPIOA3_Handler PROC
EXPORT GPIOA3_Handler [WEAK]
EXPORT GPIOA3_Handler [WEAK]
B .
ENDP
GPIOA4_Handler PROC
EXPORT GPIOA4_Handler [WEAK]
EXPORT GPIOA4_Handler [WEAK]
B .
ENDP
GPIOA5_Handler PROC
EXPORT GPIOA5_Handler [WEAK]
EXPORT GPIOA5_Handler [WEAK]
B .
ENDP
GPIOA6_Handler PROC
EXPORT GPIOA6_Handler [WEAK]
EXPORT GPIOA6_Handler [WEAK]
B .
ENDP
GPIOA7_Handler PROC
EXPORT GPIOA7_Handler [WEAK]
EXPORT GPIOA7_Handler [WEAK]
B .
ENDP
GPIOB0_Handler PROC
EXPORT GPIOB0_Handler [WEAK]
EXPORT GPIOB0_Handler [WEAK]
B .
ENDP
GPIOB1_Handler PROC
EXPORT GPIOB1_Handler [WEAK]
EXPORT GPIOB1_Handler [WEAK]
B .
ENDP
GPIOB2_Handler PROC
EXPORT GPIOB2_Handler [WEAK]
EXPORT GPIOB2_Handler [WEAK]
B .
ENDP
GPIOB3_Handler PROC
EXPORT GPIOB3_Handler [WEAK]
EXPORT GPIOB3_Handler [WEAK]
B .
ENDP
GPIOB4_Handler PROC
EXPORT GPIOB4_Handler [WEAK]
EXPORT GPIOB4_Handler [WEAK]
B .
ENDP
GPIOB5_Handler PROC
EXPORT GPIOB5_Handler [WEAK]
EXPORT GPIOB5_Handler [WEAK]
B .
ENDP
GPIOB6_Handler PROC
EXPORT GPIOB6_Handler [WEAK]
EXPORT GPIOB6_Handler [WEAK]
B .
ENDP
GPIOB7_Handler PROC
EXPORT GPIOB7_Handler [WEAK]
EXPORT GPIOB7_Handler [WEAK]
B .
ENDP
GPIOC0_Handler PROC
EXPORT GPIOC0_Handler [WEAK]
EXPORT GPIOC0_Handler [WEAK]
B .
ENDP
GPIOC1_Handler PROC
EXPORT GPIOC1_Handler [WEAK]
EXPORT GPIOC1_Handler [WEAK]
B .
ENDP
GPIOC2_Handler PROC
EXPORT GPIOC2_Handler [WEAK]
EXPORT GPIOC2_Handler [WEAK]
B .
ENDP
GPIOC3_Handler PROC
EXPORT GPIOC3_Handler [WEAK]
EXPORT GPIOC3_Handler [WEAK]
B .
ENDP
GPIOC4_Handler PROC
EXPORT GPIOC4_Handler [WEAK]
EXPORT GPIOC4_Handler [WEAK]
B .
ENDP
GPIOC5_Handler PROC
EXPORT GPIOC5_Handler [WEAK]
EXPORT GPIOC5_Handler [WEAK]
B .
ENDP
GPIOC6_Handler PROC
EXPORT GPIOC6_Handler [WEAK]
EXPORT GPIOC6_Handler [WEAK]
B .
ENDP
GPIOC7_Handler PROC
EXPORT GPIOC7_Handler [WEAK]
EXPORT GPIOC7_Handler [WEAK]
B .
ENDP
GPIOM0_Handler PROC
EXPORT GPIOM0_Handler [WEAK]
EXPORT GPIOM0_Handler [WEAK]
B .
ENDP
GPIOM1_Handler PROC
EXPORT GPIOM1_Handler [WEAK]
EXPORT GPIOM1_Handler [WEAK]
B .
ENDP
GPIOM2_Handler PROC
EXPORT GPIOM2_Handler [WEAK]
EXPORT GPIOM2_Handler [WEAK]
B .
ENDP
GPIOM3_Handler PROC
EXPORT GPIOM3_Handler [WEAK]
EXPORT GPIOM3_Handler [WEAK]
B .
ENDP
GPIOM4_Handler PROC
EXPORT GPIOM4_Handler [WEAK]
EXPORT GPIOM4_Handler [WEAK]
B .
ENDP
GPIOM5_Handler PROC
EXPORT GPIOM5_Handler [WEAK]
EXPORT GPIOM5_Handler [WEAK]
B .
ENDP
GPIOM6_Handler PROC
EXPORT GPIOM6_Handler [WEAK]
EXPORT GPIOM6_Handler [WEAK]
B .
ENDP
GPIOM7_Handler PROC
EXPORT GPIOM7_Handler [WEAK]
EXPORT GPIOM7_Handler [WEAK]
B .
ENDP
DMA_Handler PROC
EXPORT DMA_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
B .
ENDP
LCD_Handler PROC
EXPORT LCD_Handler [WEAK]
EXPORT LCD_Handler [WEAK]
B .
ENDP
NORFLC_Handler PROC
EXPORT NORFLC_Handler [WEAK]
EXPORT NORFLC_Handler [WEAK]
B .
ENDP
CAN_Handler PROC
EXPORT CAN_Handler [WEAK]
EXPORT CAN_Handler [WEAK]
B .
ENDP
PULSE_Handler PROC
EXPORT PULSE_Handler [WEAK]
EXPORT PULSE_Handler [WEAK]
B .
ENDP
WDT_Handler PROC
EXPORT WDT_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
B .
ENDP
PWM_Handler PROC
EXPORT PWM_Handler [WEAK]
EXPORT PWM_Handler [WEAK]
B .
ENDP
UART0_Handler PROC
EXPORT UART0_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
B .
ENDP
UART1_Handler PROC
EXPORT UART1_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
B .
ENDP
UART2_Handler PROC
EXPORT UART2_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
B .
ENDP
UART3_Handler PROC
EXPORT UART3_Handler [WEAK]
EXPORT UART3_Handler [WEAK]
B .
ENDP
@ -437,12 +437,12 @@ ADC0_Handler PROC
ENDP
RTC_Handler PROC
EXPORT RTC_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
B .
ENDP
BOD_Handler PROC
EXPORT BOD_Handler [WEAK]
EXPORT BOD_Handler [WEAK]
B .
ENDP
@ -452,32 +452,32 @@ SDIO_Handler PROC
ENDP
GPIOA_Handler PROC
EXPORT GPIOA_Handler [WEAK]
EXPORT GPIOA_Handler [WEAK]
B .
ENDP
GPIOB_Handler PROC
EXPORT GPIOB_Handler [WEAK]
EXPORT GPIOB_Handler [WEAK]
B .
ENDP
GPIOC_Handler PROC
EXPORT GPIOC_Handler [WEAK]
EXPORT GPIOC_Handler [WEAK]
B .
ENDP
GPIOM_Handler PROC
EXPORT GPIOM_Handler [WEAK]
EXPORT GPIOM_Handler [WEAK]
B .
ENDP
GPION_Handler PROC
EXPORT GPION_Handler [WEAK]
EXPORT GPION_Handler [WEAK]
B .
ENDP
GPIOP_Handler PROC
EXPORT GPIOP_Handler [WEAK]
EXPORT GPIOP_Handler [WEAK]
B .
ENDP
@ -487,7 +487,7 @@ ADC1_Handler PROC
ENDP
FPU_Handler PROC
EXPORT FPU_Handler [WEAK]
EXPORT FPU_Handler [WEAK]
B .
ENDP

610
bsp/swm320/libraries/CMSIS/DeviceSupport/startup/gcc/startup_SWM320.s
View File

@ -1,242 +1,406 @@
.syntax unified
.arch armv7-m
.thumb
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward */
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space 0x4000
__StackTop:
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space 0x4000
__HeapLimit:
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop
.long Reset_Handler
.long NMI_Handler
.long HardFault_Handler
.long MemManage_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long DebugMon_Handler
.long 0
.long PendSV_Handler
.long SysTick_Handler
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* External interrupts */
.long GPIOA0_Handler
.long GPIOA1_Handler
.long GPIOA2_Handler
.long GPIOA3_Handler
.long GPIOA4_Handler
.long GPIOA5_Handler
.long GPIOA6_Handler
.long GPIOA7_Handler
.long GPIOB0_Handler
.long GPIOB1_Handler
.long GPIOB2_Handler
.long GPIOB3_Handler
.long GPIOB4_Handler
.long GPIOB5_Handler
.long GPIOB6_Handler
.long GPIOB7_Handler
.long GPIOC0_Handler
.long GPIOC1_Handler
.long GPIOC2_Handler
.long GPIOC3_Handler
.long GPIOC4_Handler
.long GPIOC5_Handler
.long GPIOC6_Handler
.long GPIOC7_Handler
.long GPIOM0_Handler
.long GPIOM1_Handler
.long GPIOM2_Handler
.long GPIOM3_Handler
.long GPIOM4_Handler
.long GPIOM5_Handler
.long GPIOM6_Handler
.long GPIOM7_Handler
.long DMA_Handler
.long LCD_Handler
.long NORFLC_Handler
.long CAN_Handler
.long PULSE_Handler
.long WDT_Handler
.long PWM_Handler
.long UART0_Handler
.long UART1_Handler
.long UART2_Handler
.long UART3_Handler
.long Default_Handler
.long I2C0_Handler
.long I2C1_Handler
.long SPI0_Handler
.long ADC0_Handler
.long RTC_Handler
.long BOD_Handler
.long SDIO_Handler
.long GPIOA_Handler
.long GPIOB_Handler
.long GPIOC_Handler
.long GPIOM_Handler
.long GPION_Handler
.long GPIOP_Handler
.long ADC1_Handler
.long FPU_Handler
.long SPI1_Handler
.long TIMR0_Handler
.long TIMR1_Handler
.long TIMR2_Handler
.long TIMR3_Handler
.long TIMR4_Handler
.long TIMR5_Handler
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
.section .text.Reset_Handler
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by symbols evaluated in linker script. */
ldr sp, =__StackTop /* set stack pointer */
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
ldr r1, =__data_load__
ldr r2, =__data_start__
ldr r3, =__data_end__
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word GPIOA0_Handler
.word GPIOA1_Handler
.word GPIOA2_Handler
.word GPIOA3_Handler
.word GPIOA4_Handler
.word GPIOA5_Handler
.word GPIOA6_Handler
.word GPIOA7_Handler
.word GPIOB0_Handler
.word GPIOB1_Handler
.word GPIOB2_Handler
.word GPIOB3_Handler
.word GPIOB4_Handler
.word GPIOB5_Handler
.word GPIOB6_Handler
.word GPIOB7_Handler
.word GPIOC0_Handler
.word GPIOC1_Handler
.word GPIOC2_Handler
.word GPIOC3_Handler
.word GPIOC4_Handler
.word GPIOC5_Handler
.word GPIOC6_Handler
.word GPIOC7_Handler
.word GPIOM0_Handler
.word GPIOM1_Handler
.word GPIOM2_Handler
.word GPIOM3_Handler
.word GPIOM4_Handler
.word GPIOM5_Handler
.word GPIOM6_Handler
.word GPIOM7_Handler
.word DMA_Handler
.word LCD_Handler
.word NORFLC_Handler
.word CAN_Handler
.word PULSE_Handler
.word WDT_Handler
.word PWM_Handler
.word UART0_Handler
.word UART1_Handler
.word UART2_Handler
.word UART3_Handler
.word 0
.word I2C0_Handler
.word I2C1_Handler
.word SPI0_Handler
.word ADC0_Handler
.word RTC_Handler
.word ANAC_Handler
.word SDIO_Handler
.word GPIOA_Handler
.word GPIOB_Handler
.word GPIOC_Handler
.word GPIOM_Handler
.word GPION_Handler
.word GPIOP_Handler
.word ADC1_Handler
.word FPU_Handler
.word SPI1_Handler
.word TIMR0_Handler
.word TIMR1_Handler
.word TIMR2_Handler
.word TIMR3_Handler
.word TIMR4_Handler
.word TIMR5_Handler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.Lflash_to_ram_loop:
cmp r2, r3
ittt lo
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo .Lflash_to_ram_loop
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
ldr r2, =__bss_start__
ldr r3, =__bss_end__
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.Lbss_to_ram_loop:
cmp r2, r3
ittt lo
movlo r0, #0
strlo r0, [r2], #4
blo .Lbss_to_ram_loop
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
ldr r0, =main
bx r0
.pool
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.text
/* Macro to define default handlers.
Default handler will be weak symbol and just dead loops. */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.endm
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
def_default_handler GPIOA0_Handler
def_default_handler GPIOA1_Handler
def_default_handler GPIOA2_Handler
def_default_handler GPIOA3_Handler
def_default_handler GPIOA4_Handler
def_default_handler GPIOA5_Handler
def_default_handler GPIOA6_Handler
def_default_handler GPIOA7_Handler
def_default_handler GPIOB0_Handler
def_default_handler GPIOB1_Handler
def_default_handler GPIOB2_Handler
def_default_handler GPIOB3_Handler
def_default_handler GPIOB4_Handler
def_default_handler GPIOB5_Handler
def_default_handler GPIOB6_Handler
def_default_handler GPIOB7_Handler
def_default_handler GPIOC0_Handler
def_default_handler GPIOC1_Handler
def_default_handler GPIOC2_Handler
def_default_handler GPIOC3_Handler
def_default_handler GPIOC4_Handler
def_default_handler GPIOC5_Handler
def_default_handler GPIOC6_Handler
def_default_handler GPIOC7_Handler
def_default_handler GPIOM0_Handler
def_default_handler GPIOM1_Handler
def_default_handler GPIOM2_Handler
def_default_handler GPIOM3_Handler
def_default_handler GPIOM4_Handler
def_default_handler GPIOM5_Handler
def_default_handler GPIOM6_Handler
def_default_handler GPIOM7_Handler
def_default_handler DMA_Handler
def_default_handler LCD_Handler
def_default_handler NORFLC_Handler
def_default_handler CAN_Handler
def_default_handler PULSE_Handler
def_default_handler WDT_Handler
def_default_handler PWM_Handler
def_default_handler UART0_Handler
def_default_handler UART1_Handler
def_default_handler UART2_Handler
def_default_handler UART3_Handler
def_default_handler I2C0_Handler
def_default_handler I2C1_Handler
def_default_handler SPI0_Handler
def_default_handler ADC0_Handler
def_default_handler RTC_Handler
def_default_handler BOD_Handler
def_default_handler SDIO_Handler
def_default_handler GPIOA_Handler
def_default_handler GPIOB_Handler
def_default_handler GPIOC_Handler
def_default_handler GPIOM_Handler
def_default_handler GPION_Handler
def_default_handler GPIOP_Handler
def_default_handler ADC1_Handler
def_default_handler FPU_Handler
def_default_handler SPI1_Handler
def_default_handler TIMR0_Handler
def_default_handler TIMR1_Handler
def_default_handler TIMR2_Handler
def_default_handler TIMR3_Handler
def_default_handler TIMR4_Handler
def_default_handler TIMR5_Handler
.weak GPIOA0_Handler
.thumb_set GPIOA0_Handler,Default_Handler
def_default_handler Default_Handler
.weak GPIOA1_Handler
.thumb_set GPIOA1_Handler,Default_Handler
.weak GPIOA2_Handler
.thumb_set GPIOA2_Handler,Default_Handler
.weak GPIOA3_Handler
.thumb_set GPIOA3_Handler,Default_Handler
.weak GPIOA4_Handler
.thumb_set GPIOA4_Handler,Default_Handler
.weak GPIOA5_Handler
.thumb_set GPIOA5_Handler,Default_Handler
.weak GPIOA6_Handler
.thumb_set GPIOA6_Handler,Default_Handler
.weak GPIOA7_Handler
.thumb_set GPIOA7_Handler,Default_Handler
.weak GPIOB0_Handler
.thumb_set GPIOB0_Handler,Default_Handler
.weak GPIOB1_Handler
.thumb_set GPIOB1_Handler,Default_Handler
.weak GPIOB2_Handler
.thumb_set GPIOB2_Handler,Default_Handler
.weak GPIOB3_Handler
.thumb_set GPIOB3_Handler,Default_Handler
.weak GPIOB4_Handler
.thumb_set GPIOB4_Handler,Default_Handler
.weak GPIOB5_Handler
.thumb_set GPIOB5_Handler,Default_Handler
.weak GPIOB6_Handler
.thumb_set GPIOB6_Handler,Default_Handler
.weak GPIOB7_Handler
.thumb_set GPIOB7_Handler,Default_Handler
.weak GPIOC0_Handler
.thumb_set GPIOC0_Handler,Default_Handler
.weak GPIOC1_Handler
.thumb_set GPIOC1_Handler,Default_Handler
.weak GPIOC2_Handler
.thumb_set GPIOC2_Handler,Default_Handler
.weak GPIOC3_Handler
.thumb_set GPIOC3_Handler,Default_Handler
.weak GPIOC4_Handler
.thumb_set GPIOC4_Handler,Default_Handler
.weak GPIOC5_Handler
.thumb_set GPIOC5_Handler,Default_Handler
.weak GPIOC6_Handler
.thumb_set GPIOC6_Handler,Default_Handler
.weak GPIOC7_Handler
.thumb_set GPIOC7_Handler,Default_Handler
.weak GPIOM0_Handler
.thumb_set GPIOM0_Handler,Default_Handler
.weak GPIOM1_Handler
.thumb_set GPIOM1_Handler,Default_Handler
.weak GPIOM2_Handler
.thumb_set GPIOM2_Handler,Default_Handler
.weak GPIOM3_Handler
.thumb_set GPIOM3_Handler,Default_Handler
.weak GPIOM4_Handler
.thumb_set GPIOM4_Handler,Default_Handler
.weak GPIOM5_Handler
.thumb_set GPIOM5_Handler,Default_Handler
.weak GPIOM6_Handler
.thumb_set GPIOM6_Handler,Default_Handler
.weak GPIOM7_Handler
.thumb_set GPIOM7_Handler,Default_Handler
.weak DMA_Handler
.thumb_set DMA_Handler,Default_Handler
.weak LCD_Handler
.thumb_set LCD_Handler,Default_Handler
.weak NORFLC_Handler
.thumb_set NORFLC_Handler,Default_Handler
.weak CAN_Handler
.thumb_set CAN_Handler,Default_Handler
.weak PULSE_Handler
.thumb_set PULSE_Handler,Default_Handler
.weak WDT_Handler
.thumb_set WDT_Handler,Default_Handler
.weak PWM_Handler
.thumb_set PWM_Handler,Default_Handler
.weak UART0_Handler
.thumb_set UART0_Handler,Default_Handler
.weak UART1_Handler
.thumb_set UART1_Handler,Default_Handler
.weak UART2_Handler
.thumb_set UART2_Handler,Default_Handler
.weak UART3_Handler
.thumb_set UART3_Handler,Default_Handler
.weak I2C0_Handler
.thumb_set I2C0_Handler,Default_Handler
.weak I2C1_Handler
.thumb_set I2C1_Handler,Default_Handler
.weak SPI0_Handler
.thumb_set SPI0_Handler,Default_Handler
.weak ADC0_Handler
.thumb_set ADC0_Handler,Default_Handler
.weak RTC_Handler
.thumb_set RTC_Handler,Default_Handler
.weak ANAC_Handler
.thumb_set ANAC_Handler,Default_Handler
.weak SDIO_Handler
.thumb_set SDIO_Handler,Default_Handler
.weak GPIOA_Handler
.thumb_set GPIOA_Handler,Default_Handler
.weak GPIOB_Handler
.thumb_set GPIOB_Handler,Default_Handler
.weak GPIOC_Handler
.thumb_set GPIOC_Handler,Default_Handler
.weak GPIOM_Handler
.thumb_set GPIOM_Handler,Default_Handler
.weak GPION_Handler
.thumb_set GPION_Handler,Default_Handler
.weak GPIOP_Handler
.thumb_set GPIOP_Handler,Default_Handler
.weak ADC1_Handler
.thumb_set ADC1_Handler,Default_Handler
.weak FPU_Handler
.thumb_set FPU_Handler,Default_Handler
.weak SPI1_Handler
.thumb_set SPI1_Handler,Default_Handler
.weak TIMR0_Handler
.thumb_set TIMR0_Handler,Default_Handler
.weak TIMR1_Handler
.thumb_set TIMR1_Handler,Default_Handler
.weak TIMR2_Handler
.thumb_set TIMR2_Handler,Default_Handler
.weak TIMR3_Handler
.thumb_set TIMR3_Handler,Default_Handler
.weak TIMR4_Handler
.thumb_set TIMR4_Handler,Default_Handler
.weak TIMR5_Handler
.thumb_set TIMR5_Handler,Default_Handler
.end

54
bsp/swm320/libraries/CMSIS/DeviceSupport/system_SWM320.c
View File

@ -43,7 +43,8 @@
/********************************** PLL 设定 **********************************************
* VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
* PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
* PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
* 注意：VCO输出频率需要在 [600MHz, 1200MHz] 之间
*****************************************************************************************/
#define SYS_PLL_SRC SYS_CLK_20MHz //可取值SYS_CLK_20MHz、SYS_CLK_XTAL
@ -173,15 +174,29 @@ void SystemInit(void)
}
}
void switchCLK_20MHz(void)
static void delay_3ms(void)
{
uint32_t i;
if (((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) &&
((SYS->CLKSEL & SYS_CLKSEL_LFCK_Msk) == 0)) //32KHz
{
for (i = 0; i < 20; i++)
__NOP();
}
else
{
for (i = 0; i < 20000; i++)
__NOP();
}
}
void switchCLK_20MHz(void)
{
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
for (i = 0; i < 1000; i++)
__NOP();
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
@ -189,13 +204,10 @@ void switchCLK_20MHz(void)
void switchCLK_40MHz(void)
{
uint32_t i;
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz
for (i = 0; i < 1000; i++)
__NOP();
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_HFCK_Msk; //HFCK <= HRC
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
@ -203,14 +215,11 @@ void switchCLK_40MHz(void)
void switchCLK_32KHz(void)
{
uint32_t i;
SYS->CLKEN |= (1 << SYS_CLKEN_RTCBKP_Pos);
SYS->LRCCR &= ~(1 << SYS_LRCCR_OFF_Pos);
for (i = 0; i < 100; i++)
__NOP();
delay_3ms();
SYS->CLKSEL &= ~SYS_CLKSEL_LFCK_Msk; //LFCK <= LRC
SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
@ -218,12 +227,10 @@ void switchCLK_32KHz(void)
void switchCLK_XTAL(void)
{
uint32_t i;
SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
for (i = 0; i < 1000; i++)
__NOP();
delay_3ms();
delay_3ms();
SYS->CLKSEL |= (1 << SYS_CLKSEL_HFCK_Pos); //HFCK <= XTAL
SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS_CLK <= HFCK
@ -231,13 +238,9 @@ void switchCLK_XTAL(void)
void switchCLK_PLL(void)
{
uint32_t i;
PLLInit();
SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
for (i = 0; i < 10000; i++)
__NOP();
SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
SYS->CLKSEL |= (1 << SYS_CLKSEL_LFCK_Pos); //LFCK <= PLL
SYS->CLKSEL &= ~SYS_CLKSEL_SYS_Msk; //SYS_CLK <= LFCK
@ -245,15 +248,12 @@ void switchCLK_PLL(void)
void PLLInit(void)
{
uint32_t i;
if (SYS_PLL_SRC == SYS_CLK_20MHz)
{
SYS->HRCCR = (0 << SYS_HRCCR_OFF_Pos) |
(0 << SYS_HRCCR_DBL_Pos); //HRC = 20MHz
for (i = 0; i < 1000; i++)
__NOP();
delay_3ms();
SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC
}
@ -261,8 +261,8 @@ void PLLInit(void)
{
SYS->XTALCR = (1 << SYS_XTALCR_EN_Pos);
for (i = 0; i < 20000; i++)
;
delay_3ms();
delay_3ms();
SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL
}

66
bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_can.c
View File

@ -126,32 +126,32 @@ void CAN_Transmit(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint8_t data[
if (format == CAN_FRAME_STD)
{
CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->TXFRAME.DATA[0] = id >> 3;
CANx->TXFRAME.DATA[1] = id << 5;
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
for (i = 0; i < size; i++)
{
CANx->TXFRAME.DATA[i + 2] = data[i];
CANx->FRAME.DATA[i + 2] = data[i];
}
}
else //if(format == CAN_FRAME_EXT)
{
CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(0 << CAN_INFO_RTR_Pos) |
(size << CAN_INFO_DLC_Pos);
CANx->TXFRAME.DATA[0] = id >> 21;
CANx->TXFRAME.DATA[1] = id >> 13;
CANx->TXFRAME.DATA[2] = id >> 5;
CANx->TXFRAME.DATA[3] = id << 3;
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
for (i = 0; i < size; i++)
{
CANx->TXFRAME.DATA[i + 4] = data[i];
CANx->FRAME.DATA[i + 4] = data[i];
}
}
@ -186,23 +186,23 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32
{
if (format == CAN_FRAME_STD)
{
CANx->TXFRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.INFO = (0 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->TXFRAME.DATA[0] = id >> 3;
CANx->TXFRAME.DATA[1] = id << 5;
CANx->FRAME.DATA[0] = id >> 3;
CANx->FRAME.DATA[1] = id << 5;
}
else //if(format == CAN_FRAME_EXT)
{
CANx->TXFRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->FRAME.INFO = (1 << CAN_INFO_FF_Pos) |
(1 << CAN_INFO_RTR_Pos) |
(0 << CAN_INFO_DLC_Pos);
CANx->TXFRAME.DATA[0] = id >> 21;
CANx->TXFRAME.DATA[1] = id >> 13;
CANx->TXFRAME.DATA[2] = id >> 5;
CANx->TXFRAME.DATA[3] = id << 3;
CANx->FRAME.DATA[0] = id >> 21;
CANx->FRAME.DATA[1] = id >> 13;
CANx->FRAME.DATA[2] = id >> 5;
CANx->FRAME.DATA[3] = id << 3;
}
if (once == 0)
@ -226,27 +226,27 @@ void CAN_TransmitRequest(CAN_TypeDef *CANx, uint32_t format, uint32_t id, uint32
void CAN_Receive(CAN_TypeDef *CANx, CAN_RXMessage *msg)
{
uint32_t i;
msg->format = (CANx->RXFRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
msg->format = (CANx->FRAME.INFO & CAN_INFO_FF_Msk) >> CAN_INFO_FF_Pos;
msg->remote = (CANx->RXFRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
msg->size = (CANx->RXFRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
msg->remote = (CANx->FRAME.INFO & CAN_INFO_RTR_Msk) >> CAN_INFO_RTR_Pos;
msg->size = (CANx->FRAME.INFO & CAN_INFO_DLC_Msk) >> CAN_INFO_DLC_Pos;
if (msg->format == CAN_FRAME_STD)
{
msg->id = (CANx->RXFRAME.DATA[0] << 3) | (CANx->RXFRAME.DATA[1] >> 5);
msg->id = (CANx->FRAME.DATA[0] << 3) | (CANx->FRAME.DATA[1] >> 5);
for (i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->RXFRAME.DATA[i + 2];
msg->data[i] = CANx->FRAME.DATA[i + 2];
}
}
else //if(msg->format == CAN_FRAME_EXT)
{
msg->id = (CANx->RXFRAME.DATA[0] << 21) | (CANx->RXFRAME.DATA[1] << 13) | (CANx->RXFRAME.DATA[2] << 5) | (CANx->RXFRAME.DATA[3] >> 3);
msg->id = (CANx->FRAME.DATA[0] << 21) | (CANx->FRAME.DATA[1] << 13) | (CANx->FRAME.DATA[2] << 5) | (CANx->FRAME.DATA[3] >> 3);
for (i = 0; i < msg->size; i++)
{
msg->data[i] = CANx->RXFRAME.DATA[i + 4];
msg->data[i] = CANx->FRAME.DATA[i + 4];
}
}

4
bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_gpio.c
View File

@ -23,8 +23,8 @@
/******************************************************************************************************************************************
* 函数名称: GPIO_Init()
* 功能说明: 引脚初始化，包含引脚方向、上拉电阻、下拉电阻、开漏输出
* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP
* 功能说明: 引脚初始化，包含引脚方向、上拉电阻、下拉电阻
* 输 入: GPIO_TypeDef * GPIOx 指定GPIO端口，有效值包括GPIOA、GPIOB、GPIOC、GPIOM、GPION、GPIOP
* uint32_t n 指定GPIO引脚，有效值包括PIN0、PIN1、PIN2、... ... PIN22、PIN23
* uint32_t dir 引脚方向，0 输入 1 输出
* uint32_t pull_up 上拉电阻，0 关闭上拉 1 开启上拉

4
bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_norflash.h
View File

@ -20,8 +20,8 @@ uint32_t NORFL_Read(uint32_t addr);
uint16_t NORFL_ReadID(uint32_t id_addr);
/* 当前版本总线读只支持字读
#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr))
#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */
#define NORFL_Read8(addr) *((volatile uint8_t *)(NORFLM_BASE + addr))
#define NORFL_Read16(addr) *((volatile uint16_t *)(NORFLM_BASE + addr)) */
#define NORFL_Read32(addr) *((volatile uint32_t *)(NORFLM_BASE + addr))
#define NORFL_CMD_READ 0

4
bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_rtc.c
View File

@ -53,7 +53,7 @@ void RTC_Init(RTC_TypeDef *RTCx, RTC_InitStructure *initStruct)
RTCx->MONDAY = (calcWeekDay(initStruct->Year, initStruct->Month, initStruct->Date) << RTC_MONDAY_DAY_Pos) |
(initStruct->Month << RTC_MONDAY_MON_Pos);
RTCx->YEAR = initStruct->Year - 1901;
RTCx->YEAR = initStruct->Year;
RTCx->LOAD = 1 << RTC_LOAD_TIME_Pos;
@ -105,7 +105,7 @@ void RTC_Stop(RTC_TypeDef *RTCx)
******************************************************************************************************************************************/
void RTC_GetDateTime(RTC_TypeDef *RTCx, RTC_DateTime *dateTime)
{
dateTime->Year = RTCx->YEAR + 1901;
dateTime->Year = RTCx->YEAR;
dateTime->Month = (RTCx->MONDAY & RTC_MONDAY_MON_Msk) >> RTC_MONDAY_MON_Pos;
dateTime->Date = (RTCx->DATHUR & RTC_DATHUR_DATE_Msk) >> RTC_DATHUR_DATE_Pos;
dateTime->Day = 1 << ((RTCx->MONDAY & RTC_MONDAY_DAY_Msk) >> RTC_MONDAY_DAY_Pos);

8
bsp/swm320/libraries/SWM320_StdPeriph_Driver/SWM320_wdt.c
View File

@ -28,7 +28,7 @@
* uint32_t peroid 取值0--4294967295，单位为单片机系统时钟周期
* uint32_t mode WDT_MODE_RESET 超时产生复位 WDT_MODE_INTERRUPT 超时产生中断
* 输 出: 无
* 注意事项: 复位使能时中断不起作用，因为计数周期结束时芯片直接复位了，无法响应中断
* 注意事项: 无
******************************************************************************************************************************************/
void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode)
{
@ -36,16 +36,18 @@ void WDT_Init(WDT_TypeDef *WDTx, uint32_t peroid, uint32_t mode)
WDT_Stop(WDTx); //设置前先关闭
WDTx->LOAD = peroid;
if (mode == WDT_MODE_RESET)
{
WDTx->LOAD = peroid / 2; //第一个计数周期置位中断标志、第二个计数周期将芯片复位
NVIC_DisableIRQ(WDT_IRQn);
WDTx->CR |= (1 << WDT_CR_RSTEN_Pos);
}
else //mode == WDT_MODE_INTERRUPT
{
WDTx->LOAD = peroid;
NVIC_EnableIRQ(WDT_IRQn);
WDTx->CR &= ~(1 << WDT_CR_RSTEN_Pos);

826
bsp/swm320/project.uvoptx
View File

File diff suppressed because it is too large Load Diff

324
bsp/swm320/project.uvprojx
View File

@ -10,13 +10,13 @@
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>SWM320xE</Device>
<Vendor>Synwit</Vendor>
<PackID>Synwit.SWM32_DFP.1.11.3</PackID>
<PackID>Synwit.SWM32_DFP.1.16.6</PackID>
<PackURL>http://www.synwit.com/pack</PackURL>
<Cpu>IRAM(0x20000000,0x20000) IROM(0x00000000,0x80000) CPUTYPE("Cortex-M4") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
@ -339,7 +339,7 @@
<MiscControls></MiscControls>
<Define>RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
<Undefine></Undefine>
<IncludePath>applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver</IncludePath>
<IncludePath>applications;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\none-gcc;libraries\CMSIS\CoreSupport;libraries\CMSIS\DeviceSupport;libraries\SWM320_StdPeriph_Driver;..\..\examples\utest\testcases\kernel</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -394,9 +394,9 @@
<GroupName>CPU</GroupName>
<Files>
<File>
<FileName>backtrace.c</FileName>
<FileName>showmem.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
<FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
</File>
<File>
<FileName>div0.c</FileName>
@ -404,9 +404,9 @@
<FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
</File>
<File>
<FileName>showmem.c</FileName>
<FileName>backtrace.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
<FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
</File>
<File>
<FileName>cpuport.c</FileName>
@ -439,14 +439,9 @@
<FilePath>..\..\components\drivers\src\completion.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileName>ringbuffer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
<File>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\pipe.c</FilePath>
<FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
</File>
<File>
<FileName>ringblk_buf.c</FileName>
@ -454,15 +449,20 @@
<FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
</File>
<File>
<FileName>ringbuffer.c</FileName>
<FileName>pipe.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
<FilePath>..\..\components\drivers\src\pipe.c</FilePath>
</File>
<File>
<FileName>waitqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
</File>
<File>
<FileName>dataqueue.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
</File>
<File>
<FileName>workqueue.c</FileName>
<FileType>1</FileType>
@ -474,9 +474,9 @@
<GroupName>Drivers</GroupName>
<Files>
<File>
<FileName>board.c</FileName>
<FileName>drv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\board.c</FilePath>
<FilePath>drivers\drv_gpio.c</FilePath>
</File>
<File>
<FileName>drv_uart.c</FileName>
@ -484,79 +484,29 @@
<FilePath>drivers\drv_uart.c</FilePath>
</File>
<File>
<FileName>drv_gpio.c</FileName>
<FileName>board.c</FileName>
<FileType>1</FileType>
<FilePath>drivers\drv_gpio.c</FilePath>
<FilePath>drivers\board.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>finsh</GroupName>
<GroupName>Finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\cmd.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\msh.c</FilePath>
</File>
<File>
<FileName>finsh_compiler.c</FileName>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_compiler.c</FilePath>
</File>
<File>
<FileName>finsh_error.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_error.c</FilePath>
</File>
<File>
<FileName>finsh_heap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_heap.c</FilePath>
</File>
<File>
<FileName>finsh_init.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_init.c</FilePath>
</File>
<File>
<FileName>finsh_node.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_node.c</FilePath>
</File>
<File>
<FileName>finsh_ops.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_ops.c</FilePath>
</File>
<File>
<FileName>finsh_parser.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_parser.c</FilePath>
</File>
<File>
<FileName>finsh_var.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_var.c</FilePath>
</File>
<File>
<FileName>finsh_vm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_vm.c</FilePath>
</File>
<File>
<FileName>finsh_token.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\finsh\finsh_token.c</FilePath>
<FilePath>..\..\components\finsh\cmd.c</FilePath>
</File>
</Files>
</Group>
@ -564,19 +514,14 @@
<GroupName>Kernel</GroupName>
<Files>
<File>
<FileName>clock.c</FileName>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
<FilePath>..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>components.c</FileName>
<FileName>thread.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\components.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
<FilePath>..\..\src\thread.c</FilePath>
</File>
<File>
<FileName>idle.c</FileName>
@ -593,25 +538,25 @@
<FileType>1</FileType>
<FilePath>..\..\src\irq.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
</File>
<File>
<FileName>device.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\device.c</FilePath>
</File>
<File>
<FileName>kservice.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\kservice.c</FilePath>
</File>
<File>
<FileName>memheap.c</FileName>
<FileName>components.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\memheap.c</FilePath>
</File>
<File>
<FileName>mempool.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\mempool.c</FilePath>
</File>
<File>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\object.c</FilePath>
<FilePath>..\..\src\components.c</FilePath>
</File>
<File>
<FileName>scheduler.c</FileName>
@ -619,25 +564,25 @@
<FilePath>..\..\src\scheduler.c</FilePath>
</File>
<File>
<FileName>thread.c</FileName>
<FileName>object.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\thread.c</FilePath>
<FilePath>..\..\src\object.c</FilePath>
</File>
<File>
<FileName>timer.c</FileName>
<FileName>memheap.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\timer.c</FilePath>
<FilePath>..\..\src\memheap.c</FilePath>
</File>
<File>
<FileName>clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\src\clock.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<Files>
<File>
<FileName>libc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
</File>
<File>
<FileName>mem_std.c</FileName>
<FileType>1</FileType>
@ -649,130 +594,135 @@
<FilePath>..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
</File>
<File>
<FileName>stdlib.c</FileName>
<FileName>libc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath>
<FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
</File>
<File>
<FileName>time.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\libc\compilers\common\time.c</FilePath>
</File>
<File>
<FileName>stdlib.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>SWM320_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath>
</File>
<File>
<FileName>system_SWM320.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\CMSIS\DeviceSupport\system_SWM320.c</FilePath>
</File>
<File>
<FileName>SWM320_adc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath>
</File>
<File>
<FileName>SWM320_can.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath>
</File>
<File>
<FileName>SWM320_crc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath>
</File>
<File>
<FileName>SWM320_dma.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath>
</File>
<File>
<FileName>SWM320_exti.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath>
</File>
<File>
<FileName>SWM320_flash.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath>
</File>
<File>
<FileName>SWM320_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</FilePath>
</File>
<File>
<FileName>SWM320_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath>
</File>
<File>
<FileName>SWM320_lcd.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath>
</File>
<File>
<FileName>SWM320_norflash.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</FilePath>
</File>
<File>
<FileName>SWM320_port.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath>
</File>
<File>
<FileName>SWM320_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath>
</File>
<File>
<FileName>SWM320_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath>
</File>
<File>
<FileName>SWM320_sdio.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath>
</File>
<File>
<FileName>SWM320_sdram.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath>
</File>
<File>
<FileName>SWM320_spi.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_spi.c</FilePath>
</File>
<File>
<FileName>SWM320_flash.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_flash.c</FilePath>
</File>
<File>
<FileName>SWM320_sdram.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdram.c</FilePath>
</File>
<File>
<FileName>SWM320_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_pwm.c</FilePath>
</File>
<File>
<FileName>SWM320_sram.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sram.c</FilePath>
</File>
<File>
<FileName>SWM320_lcd.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_lcd.c</FilePath>
</File>
<File>
<FileName>SWM320_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_gpio.c</FilePath>
</File>
<File>
<FileName>SWM320_timr.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_timr.c</FilePath>
</File>
<File>
<FileName>SWM320_uart.c</FileName>
<FileName>SWM320_norflash.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath>
</File>
<File>
<FileName>SWM320_wdt.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_wdt.c</FilePath>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_norflash.c</FilePath>
</File>
<File>
<FileName>startup_SWM320.s</FileName>
<FileType>2</FileType>
<FilePath>libraries\CMSIS\DeviceSupport\startup\arm\startup_SWM320.s</FilePath>
</File>
<File>
<FileName>SWM320_can.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_can.c</FilePath>
</File>
<File>
<FileName>SWM320_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_i2c.c</FilePath>
</File>
<File>
<FileName>SWM320_port.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_port.c</FilePath>
</File>
<File>
<FileName>SWM320_uart.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_uart.c</FilePath>
</File>
<File>
<FileName>SWM320_dma.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_dma.c</FilePath>
</File>
<File>
<FileName>SWM320_crc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_crc.c</FilePath>
</File>
<File>
<FileName>SWM320_sdio.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_sdio.c</FilePath>
</File>
<File>
<FileName>SWM320_rtc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_rtc.c</FilePath>
</File>
<File>
<FileName>SWM320_exti.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_exti.c</FilePath>
</File>
<File>
<FileName>SWM320_adc.c</FileName>
<FileType>1</FileType>
<FilePath>libraries\SWM320_StdPeriph_Driver\SWM320_adc.c</FilePath>
</File>
</Files>
</Group>
</Groups>

33
bsp/swm320/rtconfig.h
View File

@ -16,6 +16,9 @@
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
@ -39,8 +42,8 @@
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40003
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40004
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
@ -59,16 +62,17 @@
/* Command shell */
#define RT_USING_FINSH
#define RT_USING_MSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
/* Device virtual file system */
@ -79,6 +83,7 @@
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
@ -88,6 +93,7 @@
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* Network */
@ -109,6 +115,9 @@
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
@ -139,6 +148,8 @@
/* system packages */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* Micrium: Micrium software products porting for RT-Thread */
@ -146,13 +157,15 @@
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* AI packages */
/* miscellaneous packages */
/* samples: kernel and components samples */
/* games: games run on RT-Thread console */
/* entertainment: terminal games and other interesting software packages */
/* Hardware Drivers Config */
@ -162,7 +175,7 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_UART1
#define BSP_USING_GPIO
/* Onboard Peripheral Drivers */