[cpu_cache] fix function replaced by macro

libcpu/arm/cortex-m7/cpu_cache.c

@@ -17,6 +17,8 @@
 /* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
 #define L1CACHE_LINESIZE_BYTE       (32)
 
+#ifdef RT_USING_CACHE
+
 void rt_hw_cpu_icache_enable(void)
 {
     SCB_EnableICache();
@@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
         RT_ASSERT(0);
     }
 }
+
+#endif /* RT_USING_CACHE */
+