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Merge pull request #4871 from wormsX/master 

Support T-HEAD Xuantie-E9xx Series CPU on Smart-EVB
This commit is contained in:
Bernard Xiong 2021-08-09 08:53:42 +08:00 committed by GitHub
parent 0880b43498 f60514cd71
commit 1e26128735
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
28 changed files with 459 additions and 202 deletions
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2
bsp/thead-smart/applications/main.c
View File

@ -12,7 +12,7 @@
int main(void)
{
return 0;
}

4
bsp/thead-smart/drivers/board.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -26,7 +26,7 @@ extern void ioreuse_initial(void);
/**
* This function will initial smartl-evb(e906) board.
* This function will initial smart-evb board.
*/
void rt_hw_board_init(void)
{

12
bsp/thead-smart/drivers/board_uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@ -35,7 +35,7 @@ struct
uint32_t base;
uint32_t irq;
void *handler;
}
}
const sg_usart_config[CONFIG_USART_NUM] =
{
{CSKY_UART_BASE, UART_IRQn, ck_usart0_irqhandler},
@ -44,22 +44,22 @@ const sg_usart_config[CONFIG_USART_NUM] =
int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler)
{
if (idx >= CONFIG_USART_NUM)
if (idx >= CONFIG_USART_NUM)
{
return -1;
}
if (base != NULL)
if (base != NULL)
{
*base = sg_usart_config[idx].base;
}
if (irq != NULL)
if (irq != NULL)
{
*irq = sg_usart_config[idx].irq;
}
if (handler != NULL)
if (handler != NULL)
{
*handler = sg_usart_config[idx].handler;
}

16
bsp/thead-smart/drivers/ck_irq.c
View File

@ -25,7 +25,7 @@ extern void (*g_nmivector)(void);
*/
void drv_irq_enable(uint32_t irq_num)
{
if (NMI_EXPn != irq_num)
if (NMI_EXPn != irq_num)
{
#ifdef CONFIG_SYSTEM_SECURE
csi_vic_enable_sirq(irq_num);
@ -42,7 +42,7 @@ void drv_irq_enable(uint32_t irq_num)
*/
void drv_irq_disable(uint32_t irq_num)
{
if (NMI_EXPn != irq_num)
if (NMI_EXPn != irq_num)
{
#ifdef CONFIG_SYSTEM_SECURE
csi_vic_disable_sirq(irq_num);
@ -60,11 +60,11 @@ void drv_irq_disable(uint32_t irq_num)
*/
void drv_irq_register(uint32_t irq_num, void *irq_handler)
{
if (NMI_EXPn != irq_num)
if (NMI_EXPn != irq_num)
{
g_irqvector[irq_num] = irq_handler;
}
else
}
else
{
g_nmivector = irq_handler;
}
@ -77,11 +77,11 @@ void drv_irq_register(uint32_t irq_num, void *irq_handler)
*/
void drv_irq_unregister(uint32_t irq_num)
{
if (NMI_EXPn != irq_num)
if (NMI_EXPn != irq_num)
{
g_irqvector[irq_num] = (void *)Default_Handler;
}
else
}
else
{
g_nmivector = (void *)Default_Handler;
}

132
bsp/thead-smart/drivers/ck_usart.c
View File

@ -37,7 +37,7 @@
#define USART_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_USART(DRV_ERROR_PARAMETER))
typedef struct
typedef struct
{
uint32_t base;
uint32_t irq;
@ -59,7 +59,7 @@ extern int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, voi
static ck_usart_priv_t usart_instance[CONFIG_USART_NUM];
static const usart_capabilities_t usart_capabilities =
static const usart_capabilities_t usart_capabilities =
{
.asynchronous = 1, /* supports USART (Asynchronous) mode */
.synchronous_master = 0, /* supports Synchronous Master mode */
@ -86,10 +86,10 @@ int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud)
/* baudrate=(seriak clock freq)/(16*divisor); algorithm :rounding*/
uint32_t divisor = ((drv_get_usart_freq(usart_priv->idx) * 10) / baud) >> 4;
if ((divisor % 10) >= 5)
if ((divisor % 10) >= 5)
{
divisor = (divisor / 10) + 1;
} else
} else
{
divisor = divisor / 10;
}
@ -117,7 +117,7 @@ int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode)
{
USART_NULL_PARAM_CHK(handle);
if (mode == USART_MODE_ASYNCHRONOUS)
if (mode == USART_MODE_ASYNCHRONOUS)
{
return 0;
}
@ -139,7 +139,7 @@ int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity)
WAIT_USART_IDLE(addr);
switch (parity)
switch (parity)
{
case USART_PARITY_NONE:
/*CLear the PEN bit(LCR[3]) to disable parity.*/
@ -179,7 +179,7 @@ int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopb
WAIT_USART_IDLE(addr);
switch (stopbit)
switch (stopbit)
{
case USART_STOP_BITS_1:
/* Clear the STOP bit to set 1 stop bit*/
@ -223,7 +223,7 @@ int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e datab
* 11 -- 8 bits
*/
switch (databits)
switch (databits)
{
case USART_DATA_BITS_5:
addr->LCR &= LCR_WORD_SIZE_5;
@ -312,7 +312,7 @@ int csi_uart_getchar(usart_handle_t handle)
if (addr->LSR & LSR_DATA_READY)
{
ch = addr->RBR & 0xff;
ch = addr->RBR & 0xff;
}
return ch;
@ -332,11 +332,11 @@ int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch)
ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
uint32_t timecount = 0;
while ((!(addr->LSR & DW_LSR_TRANS_EMPTY)))
while ((!(addr->LSR & DW_LSR_TRANS_EMPTY)))
{
timecount++;
if (timecount >= UART_BUSY_TIMEOUT)
if (timecount >= UART_BUSY_TIMEOUT)
{
return ERR_USART(DRV_ERROR_TIMEOUT);
}
@ -354,7 +354,7 @@ int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch)
*/
void ck_usart_intr_threshold_empty(int32_t idx, ck_usart_priv_t *usart_priv)
{
if (usart_priv->tx_total_num == 0)
if (usart_priv->tx_total_num == 0)
{
return;
}
@ -362,7 +362,7 @@ void ck_usart_intr_threshold_empty(int32_t idx, ck_usart_priv_t *usart_priv)
volatile int i = 500;
ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
if (usart_priv->tx_cnt >= usart_priv->tx_total_num)
if (usart_priv->tx_cnt >= usart_priv->tx_total_num)
{
addr->IER &= (~IER_THRE_INT_ENABLE);
usart_priv->last_tx_num = usart_priv->tx_total_num;
@ -379,11 +379,11 @@ void ck_usart_intr_threshold_empty(int32_t idx, ck_usart_priv_t *usart_priv)
usart_priv->tx_buf = NULL;
usart_priv->tx_total_num = 0;
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_SEND_COMPLETE);
}
} else
} else
{
/* fix hardware bug */
while (addr->USR & USR_UART_BUSY);
@ -411,7 +411,7 @@ static void ck_usart_intr_recv_data(int32_t idx, ck_usart_priv_t *usart_priv)
usart_priv->rx_cnt++;
usart_priv->rx_buf++;
if (usart_priv->rx_cnt >= usart_priv->rx_total_num)
if (usart_priv->rx_cnt >= usart_priv->rx_total_num)
{
usart_priv->last_rx_num = usart_priv->rx_total_num;
usart_priv->rx_cnt = 0;
@ -419,7 +419,7 @@ static void ck_usart_intr_recv_data(int32_t idx, ck_usart_priv_t *usart_priv)
usart_priv->rx_busy = 0;
usart_priv->rx_total_num = 0;
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RECEIVE_COMPLETE);
}
@ -440,14 +440,14 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
uint32_t timecount = 0;
while (addr->LSR & 0x1)
while (addr->LSR & 0x1)
{
addr->RBR;
timecount++;
if (timecount >= UART_BUSY_TIMEOUT)
if (timecount >= UART_BUSY_TIMEOUT)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT);
}
@ -459,9 +459,9 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
/** Break Interrupt bit. This is used to indicate the detection of a
* break sequence on the serial input data.
*/
if (lsr_stat & DW_LSR_BI)
if (lsr_stat & DW_LSR_BI)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_BREAK);
}
@ -473,9 +473,9 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
* framing error in the receiver. A framing error occurs when the receiver
* does not detect a valid STOP bit in the received data.
*/
if (lsr_stat & DW_LSR_FE)
if (lsr_stat & DW_LSR_FE)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_FRAMING_ERROR);
}
@ -487,9 +487,9 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
* framing error in the receiver. A framing error occurs when the
* receiver does not detect a valid STOP bit in the received data.
*/
if (lsr_stat & DW_LSR_PE)
if (lsr_stat & DW_LSR_PE)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_PARITY_ERROR);
}
@ -500,9 +500,9 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
/** Overrun error bit. This is used to indicate the occurrence of an overrun error.
* This occurs if a new data character was received before the previous data was read.
*/
if (lsr_stat & DW_LSR_OE)
if (lsr_stat & DW_LSR_OE)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_OVERFLOW);
}
@ -516,29 +516,29 @@ static void ck_usart_intr_recv_line(int32_t idx, ck_usart_priv_t *usart_priv)
*/
static void ck_usart_intr_char_timeout(int32_t idx, ck_usart_priv_t *usart_priv)
{
if ((usart_priv->rx_total_num != 0) && (usart_priv->rx_buf != NULL))
if ((usart_priv->rx_total_num != 0) && (usart_priv->rx_buf != NULL))
{
ck_usart_intr_recv_data(idx, usart_priv);
return;
}
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RECEIVED);
} else
} else
{
ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
uint32_t timecount = 0;
while (addr->LSR & 0x1)
while (addr->LSR & 0x1)
{
addr->RBR;
timecount++;
if (timecount >= UART_BUSY_TIMEOUT)
if (timecount >= UART_BUSY_TIMEOUT)
{
if (usart_priv->cb_event)
if (usart_priv->cb_event)
{
usart_priv->cb_event(idx, USART_EVENT_RX_TIMEOUT);
}
@ -560,7 +560,7 @@ void ck_usart_irqhandler(int32_t idx)
uint8_t intr_state = addr->IIR & 0xf;
switch (intr_state)
switch (intr_state)
{
case DW_IIR_THR_EMPTY: /* interrupt source:transmitter holding register empty */
ck_usart_intr_threshold_empty(idx, usart_priv);
@ -591,7 +591,7 @@ void ck_usart_irqhandler(int32_t idx)
*/
usart_capabilities_t csi_usart_get_capabilities(int32_t idx)
{
if (idx < 0 || idx >= CONFIG_USART_NUM)
if (idx < 0 || idx >= CONFIG_USART_NUM)
{
usart_capabilities_t ret;
memset(&ret, 0, sizeof(usart_capabilities_t));
@ -615,7 +615,7 @@ usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event)
int32_t ret = target_usart_init(idx, &base, &irq, &handler);
if (ret < 0 || ret >= CONFIG_USART_NUM)
if (ret < 0 || ret >= CONFIG_USART_NUM)
{
return NULL;
}
@ -675,7 +675,7 @@ int32_t csi_usart_config(usart_handle_t handle,
/* control the data_bit of the usart*/
ret = csi_usart_config_baudrate(handle, baud);
if (ret < 0)
if (ret < 0)
{
return ret;
}
@ -683,7 +683,7 @@ int32_t csi_usart_config(usart_handle_t handle,
/* control mode of the usart*/
ret = csi_usart_config_mode(handle, mode);
if (ret < 0)
if (ret < 0)
{
return ret;
}
@ -691,7 +691,7 @@ int32_t csi_usart_config(usart_handle_t handle,
/* control the parity of the usart*/
ret = csi_usart_config_parity(handle, parity);
if (ret < 0)
if (ret < 0)
{
return ret;
}
@ -699,14 +699,14 @@ int32_t csi_usart_config(usart_handle_t handle,
/* control the stopbit of the usart*/
ret = csi_usart_config_stopbits(handle, stopbits);
if (ret < 0)
if (ret < 0)
{
return ret;
}
ret = csi_usart_config_databits(handle, bits);
if (ret < 0)
if (ret < 0)
{
return ret;
}
@ -729,7 +729,7 @@ int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num)
USART_NULL_PARAM_CHK(handle);
USART_NULL_PARAM_CHK(data);
if (num == 0)
if (num == 0)
{
return ERR_USART(DRV_ERROR_PARAMETER);
}
@ -811,12 +811,12 @@ int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num)
int32_t recv_num = 0;
uint8_t *dest = (uint8_t *)data;
while (addr->LSR & 0x1)
while (addr->LSR & 0x1)
{
*dest++ = addr->RBR;
recv_num++;
if (recv_num >= num)
if (recv_num >= num)
{
break;
}
@ -876,7 +876,7 @@ usart_status_t csi_usart_get_status(usart_handle_t handle)
memset(&usart_status, 0, sizeof(usart_status_t));
if (handle == NULL)
if (handle == NULL)
{
return usart_status;
}
@ -888,17 +888,17 @@ usart_status_t csi_usart_get_status(usart_handle_t handle)
usart_status.tx_busy = usart_priv->tx_busy;
usart_status.rx_busy = usart_priv->rx_busy;
if (line_status_reg & DW_LSR_BI)
if (line_status_reg & DW_LSR_BI)
{
usart_status.rx_break = 1;
}
if (line_status_reg & DW_LSR_FE)
if (line_status_reg & DW_LSR_FE)
{
usart_status.rx_framing_error = 1;
}
if (line_status_reg & DW_LSR_PE)
if (line_status_reg & DW_LSR_PE)
{
usart_status.rx_parity_error = 1;
}
@ -961,26 +961,26 @@ int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type)
uint32_t timecount = 0;
if (type == USART_FLUSH_WRITE) {
while ((!(addr->LSR & DW_LSR_TEMT)))
while ((!(addr->LSR & DW_LSR_TEMT)))
{
timecount++;
if (timecount >= UART_BUSY_TIMEOUT)
if (timecount >= UART_BUSY_TIMEOUT)
{
return ERR_USART(DRV_ERROR_TIMEOUT);
}
}
} else if (type == USART_FLUSH_READ)
} else if (type == USART_FLUSH_READ)
{
while (addr->LSR & 0x1) {
timecount++;
if (timecount >= UART_BUSY_TIMEOUT)
if (timecount >= UART_BUSY_TIMEOUT)
{
return ERR_USART(DRV_ERROR_TIMEOUT);
}
}
} else
} else
{
return ERR_USART(DRV_ERROR_PARAMETER);
}
@ -1002,16 +1002,16 @@ int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, i
ck_usart_priv_t *usart_priv = handle;
ck_usart_reg_t *addr = (ck_usart_reg_t *)(usart_priv->base);
switch (type)
switch (type)
{
case USART_INTR_WRITE:
if (flag == 0)
if (flag == 0)
{
addr->IER &= ~IER_THRE_INT_ENABLE;
} else if (flag == 1)
} else if (flag == 1)
{
addr->IER |= IER_THRE_INT_ENABLE;
} else
} else
{
return ERR_USART(DRV_ERROR_PARAMETER);
}
@ -1019,13 +1019,13 @@ int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, i
break;
case USART_INTR_READ:
if (flag == 0)
if (flag == 0)
{
addr->IER &= ~IER_RDA_INT_ENABLE;
} else if (flag == 1)
} else if (flag == 1)
{
addr->IER |= IER_RDA_INT_ENABLE;
} else
} else
{
return ERR_USART(DRV_ERROR_PARAMETER);
}
@ -1051,10 +1051,10 @@ uint32_t csi_usart_get_tx_count(usart_handle_t handle)
ck_usart_priv_t *usart_priv = handle;
if (usart_priv->tx_busy)
if (usart_priv->tx_busy)
{
return usart_priv->tx_cnt;
} else
} else
{
return usart_priv->last_tx_num;
}
@ -1070,10 +1070,10 @@ uint32_t csi_usart_get_rx_count(usart_handle_t handle)
USART_NULL_PARAM_CHK(handle);
ck_usart_priv_t *usart_priv = handle;
if (usart_priv->rx_busy)
if (usart_priv->rx_busy)
{
return usart_priv->rx_cnt;
} else
} else
{
return usart_priv->last_rx_num;
}
@ -1102,7 +1102,7 @@ int32_t csi_usart_config_flowctrl(usart_handle_t handle,
{
USART_NULL_PARAM_CHK(handle);
switch (flowctrl_type)
switch (flowctrl_type)
{
case USART_FLOWCTRL_CTS:
return ERR_USART(DRV_ERROR_UNSUPPORTED);

8
bsp/thead-smart/drivers/ck_usart.h
View File

@ -19,11 +19,11 @@
extern "C" {
#endif
#define BAUDRATE_DEFAULT 19200
#define BAUDRATE_DEFAULT 19200
#define UART_BUSY_TIMEOUT 1000000
#define UART_RECEIVE_TIMEOUT 1000
#define UART_TRANSMIT_TIMEOUT 1000
#define UART_MAX_FIFO 0x10
#define UART_MAX_FIFO 0x10
/* UART register bit definitions */
#define USR_UART_BUSY 0x01
@ -64,13 +64,13 @@ extern "C" {
typedef struct
{
union
union
{
__IM uint32_t RBR; /* Offset: 0x000 (R/ ) Receive buffer register */
__OM uint32_t THR; /* Offset: 0x000 ( /W) Transmission hold register */
__IOM uint32_t DLL; /* Offset: 0x000 (R/W) Clock frequency division low section register */
};
union
union
{
__IOM uint32_t DLH; /* Offset: 0x004 (R/W) Clock frequency division high section register */
__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */

162
bsp/thead-smart/drivers/core_rv32.h
View File

@ -290,6 +290,42 @@ typedef struct
/*@} end of group CSI_CACHE */
#define SYSMAP_SYSMAPCFG_B_Pos 0U /*!< SYSMAP SYSMAPCFG: B Position */
#define SYSMAP_SYSMAPCFG_B_Msk (0x1UL << SYSMAP_SYSMAPCFG_B_Pos) /*!< SYSMAP SYSMAPCFG: B Mask */
#define SYSMAP_SYSMAPCFG_C_Pos 1U /*!< SYSMAP SYSMAPCFG: C Position */
#define SYSMAP_SYSMAPCFG_C_Msk (0x1UL << SYSMAP_SYSMAPCFG_C_Pos) /*!< SYSMAP SYSMAPCFG: C Mask */
#define SYSMAP_SYSMAPCFG_SO_Pos 2U /*!< SYSMAP SYSMAPCFG: SO Position */
#define SYSMAP_SYSMAPCFG_SO_Msk (0x1UL << SYSMAP_SYSMAPCFG_SO_Pos) /*!< SYSMAP SYSMAPCFG: SO Mask */
/**
\ingroup CSI_core_register
\defgroup CSI_SYSMAP system map (SYSMAP)
\brief Type definitions for the SYSMAP Registers
@{
*/
typedef struct
{
__IOM uint32_t SYSMAPADDR0; /*!< Offset: 0x000 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG0; /*!< Offset: 0x004 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR1; /*!< Offset: 0x008 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG1; /*!< Offset: 0x00c (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR2; /*!< Offset: 0x010 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG2; /*!< Offset: 0x014 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR3; /*!< Offset: 0x018 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG3; /*!< Offset: 0x01c (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR4; /*!< Offset: 0x020 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG4; /*!< Offset: 0x024 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR5; /*!< Offset: 0x028 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG5; /*!< Offset: 0x02c (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR6; /*!< Offset: 0x030 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG6; /*!< Offset: 0x034 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPADDR7; /*!< Offset: 0x038 (R/W) SYSMAP configure register */
__IOM uint32_t SYSMAPCFG7; /*!< Offset: 0x03c (R/W) SYSMAP configure register */
} SYSMAP_Type;
/*@} end of group CSI_SYSMAP */
/**
\ingroup CSI_core_register
\defgroup CSI_SysTick System Tick Timer (CORET)
@ -383,12 +419,14 @@ typedef struct
#define TCIP_BASE (0xE000E000UL) /*!< Titly Coupled IP Base Address */
#define CORET_BASE (0xE0004000UL) /*!< CORET Base Address */
#define CLIC_BASE (0xE0800000UL) /*!< CLIC Base Address */
#define SYSMAP_BASE (0xEFFFF000UL) /*!< SYSMAP Base Address */
#define DCC_BASE (0xE4010000UL) /*!< DCC Base Address */
#define CACHE_BASE (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
#define CORET ((CORET_Type *) CORET_BASE ) /*!< SysTick configuration struct */
#define CLIC ((CLIC_Type *) CLIC_BASE ) /*!< CLIC configuration struct */
#define DCC ((DCC_Type *) DCC_BASE ) /*!< DCC configuration struct */
#define SYSMAP ((SYSMAP_Type *) SYSMAP_BASE ) /*!< SYSMAP configuration struct */
#define CACHE ((CACHE_Type *) CACHE_BASE ) /*!< cache configuration struct */
/*@} */
@ -646,7 +684,7 @@ __STATIC_INLINE void csi_mpu_disable_region(uint32_t idx)
*/
__STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
{
if (CORET->MTIMECMP) {
if ((CORET->MTIMECMP != 0) && (CORET->MTIMECMP != 0xffffffffffffffff)) {
CORET->MTIMECMP = CORET->MTIMECMP + ticks;
} else {
CORET->MTIMECMP = CORET->MTIME + ticks;
@ -691,6 +729,126 @@ __STATIC_INLINE uint32_t csi_coret_get_valueh(void)
}
/*@} end of CSI_Core_SysTickFunctions */
/* ########################## SYSMAP functions #################################### */
/**
\ingroup CSI_Core_FunctionInterface
\defgroup CSI_Core_SYSMAPFunctions SYSMAP Functions
\brief Functions that manage system map attribute
@{
*/
/**
\brief Get SYSMAPCFGx Register by index
\details Returns the content of the SYSMAPxCFG Register.
\param [in] idx SYSMAP region index
\return SYSMAPxCFG Register value
*/
__STATIC_INLINE uint8_t __get_SYSMAPCFGx(uint32_t idx)
{
switch (idx)
{
case 0: return SYSMAP->SYSMAPCFG0;
case 1: return SYSMAP->SYSMAPCFG1;
case 2: return SYSMAP->SYSMAPCFG2;
case 3: return SYSMAP->SYSMAPCFG3;
case 4: return SYSMAP->SYSMAPCFG4;
case 5: return SYSMAP->SYSMAPCFG5;
case 6: return SYSMAP->SYSMAPCFG6;
case 7: return SYSMAP->SYSMAPCFG7;
default: return 0;
}
}
/**
\brief Set SYSMAPCFGx by index
\details Writes the given value to the SYSMAPxCFG Register.
\param [in] idx SYSMAPx region index
\param [in] sysmapxcfg SYSMAPxCFG Register value to set
*/
__STATIC_INLINE void __set_SYSMAPCFGx(uint32_t idx, uint32_t sysmapxcfg)
{
switch (idx)
{
case 0: SYSMAP->SYSMAPCFG0 = sysmapxcfg; break;
case 1: SYSMAP->SYSMAPCFG1 = sysmapxcfg; break;
case 2: SYSMAP->SYSMAPCFG2 = sysmapxcfg; break;
case 3: SYSMAP->SYSMAPCFG3 = sysmapxcfg; break;
case 4: SYSMAP->SYSMAPCFG4 = sysmapxcfg; break;
case 5: SYSMAP->SYSMAPCFG5 = sysmapxcfg; break;
case 6: SYSMAP->SYSMAPCFG6 = sysmapxcfg; break;
case 7: SYSMAP->SYSMAPCFG7 = sysmapxcfg; break;
default: return;
}
}
/**
\brief Get SYSMAPADDRx Register by index
\details Returns the content of the SYSMAPADDRx Register.
\param [in] idx SYSMAP region index
\return SYSMAPADDRx Register value
*/
__STATIC_INLINE uint32_t __get_SYSMAPADDRx(uint32_t idx)
{
switch(idx)
{
case 0: return SYSMAP->SYSMAPADDR0;
case 1: return SYSMAP->SYSMAPADDR1;
case 2: return SYSMAP->SYSMAPADDR2;
case 3: return SYSMAP->SYSMAPADDR3;
case 4: return SYSMAP->SYSMAPADDR4;
case 5: return SYSMAP->SYSMAPADDR5;
case 6: return SYSMAP->SYSMAPADDR6;
case 7: return SYSMAP->SYSMAPADDR7;
default: return 0;
}
}
/**
\brief Set SYSMAPADDRx by index
\details Writes the given value to the SYSMAPADDRx Register.
\param [in] idx SYSMAP region index
\param [in] sysmapaddr SYSMAPADDRx Register value to set
*/
__STATIC_INLINE void __set_SYSMAPADDRx(uint32_t idx, uint32_t sysmapxaddr)
{
switch (idx)
{
case 0: SYSMAP->SYSMAPADDR0 = sysmapxaddr; break;
case 1: SYSMAP->SYSMAPADDR1 = sysmapxaddr; break;
case 2: SYSMAP->SYSMAPADDR2 = sysmapxaddr; break;
case 3: SYSMAP->SYSMAPADDR3 = sysmapxaddr; break;
case 4: SYSMAP->SYSMAPADDR4 = sysmapxaddr; break;
case 5: SYSMAP->SYSMAPADDR5 = sysmapxaddr; break;
case 6: SYSMAP->SYSMAPADDR6 = sysmapxaddr; break;
case 7: SYSMAP->SYSMAPADDR7 = sysmapxaddr; break;
default: return;
}
}
/**
\brief configure system map attribute.
\details
\param [in] idx system map region (0, 1, 2, ..., 7).
\param [in] base_addr base address must be aligned with page size.
\param [in] enable enable or disable memory protected region.
*/
__STATIC_INLINE void csi_sysmap_config_region(uint32_t idx, uint32_t base_addr, uint32_t attr)
{
uint32_t addr = 0;
if (idx > 7) {
return;
}
addr = base_addr >> 12;
attr = attr << 2;
__set_SYSMAPADDRx(idx, addr);
__set_SYSMAPCFGx(idx, attr);
}
/*@} end of CSI_Core_SYSMAPFunctions */
/* ##################################### DCC function ########################################### */
/**
@ -986,7 +1144,7 @@ __STATIC_INLINE void csi_dcache_invalid_range (uint32_t *addr, int32_t dsize)
__STATIC_INLINE void csi_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
#if (__DCACHE_PRESENT == 1)
#if (__DCACHE_PRESENT == 1U)
int32_t op_size = dsize + (uint32_t)addr % 32;
uint32_t op_addr = (uint32_t) addr & CACHE_INV_ADDR_Msk;
int32_t linesize = 32;

23
bsp/thead-smart/drivers/csi_rv32_gcc.h
View File

@ -184,6 +184,29 @@ __ALWAYS_STATIC_INLINE void __set_MHCR(uint32_t mhcr)
__ASM volatile("csrw mhcr, %0" : : "r"(mhcr));
}
/**
\brief Get MHINT
\details Returns the content of the MHINT Register.
\return MHINT Register value
*/
__ALWAYS_STATIC_INLINE uint32_t __get_MHINT(void)
{
uint32_t result;
__ASM volatile("csrr %0, mhint" : "=r"(result));
return (result);
}
/**
\brief Set MHINT
\details Writes the given value to the MHINT Register.
\param [in] MHINT Register value to set
*/
__ALWAYS_STATIC_INLINE void __set_MHINT(uint32_t mhint)
{
__ASM volatile("csrw mhint, %0" : : "r"(mhint));
}
/**
\brief Get MISA Register
\details Returns the content of the MISA Register.

2
bsp/thead-smart/drivers/drv_common.h
View File

@ -43,7 +43,7 @@ typedef void *drv_handle_t;
/**
\brief General power states
*/
typedef enum
typedef enum
{
DRV_POWER_OFF, ///< Power off: no operation possible
DRV_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events

50
bsp/thead-smart/drivers/dw_gpio.c
View File

@ -31,7 +31,7 @@ extern int32_t drv_pin_config_mode(port_name_e port, uint8_t offset, gpio_mode_e
typedef void *gpio_port_handle_t;
typedef struct
typedef struct
{
#ifdef CONFIG_LPM
uint8_t gpio_power_status;
@ -46,7 +46,7 @@ typedef struct
uint32_t value; ///< gpio value
} dw_gpio_priv_t;
typedef struct
typedef struct
{
uint8_t portidx;
uint8_t idx;
@ -71,13 +71,13 @@ static int32_t gpio_set_direction(
dw_gpio_priv_t *gpio_priv = port;
dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
if (direction == GPIO_DIRECTION_INPUT)
if (direction == GPIO_DIRECTION_INPUT)
{
gpio_reg->SWPORT_DDR &= (~gpio_priv->mask);
} else if (direction == GPIO_DIRECTION_OUTPUT)
} else if (direction == GPIO_DIRECTION_OUTPUT)
{
gpio_reg->SWPORT_DDR |= gpio_priv->mask;
} else
} else
{
return ERR_GPIO(GPIO_ERROR_DIRECTION);
}
@ -139,7 +139,7 @@ static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode
uint32_t offset = gpio_pin_priv->idx;
uint32_t mask = 1 << offset;
switch (irq_mode)
switch (irq_mode)
{
/* rising edge interrupt mode */
case GPIO_IRQ_MODE_RISING_EDGE:
@ -240,7 +240,7 @@ static void gpio_irq_disable(gpio_pin_handle_t pin)
void dw_gpio_irqhandler(int idx)
{
if (idx >= CONFIG_GPIO_NUM)
if (idx >= CONFIG_GPIO_NUM)
{
return;
}
@ -251,24 +251,24 @@ void dw_gpio_irqhandler(int idx)
uint8_t i;
/* find the interrput pin */
for (i = 0; i < 32; i++)
for (i = 0; i < 32; i++)
{
if (value & (1U << i))
if (value & (1U << i))
{
uint32_t pin_idx = i;
#ifndef CONFIG_CHIP_DANICA
uint8_t j;
if (idx > 0)
if (idx > 0)
{
for (j = 0; j < idx; j++)
for (j = 0; j < idx; j++)
{
pin_idx += gpio_handle[j].pin_num;
}
}
if (pin_idx >= CONFIG_GPIO_PIN_NUM)
if (pin_idx >= CONFIG_GPIO_PIN_NUM)
{
return;
}
@ -279,7 +279,7 @@ void dw_gpio_irqhandler(int idx)
gpio_irq_clear(gpio_pin_priv, (1 << i)); //clear the gpio interrupt
/* execute the callback function */
if ((gpio_event_cb_t)(gpio_pin_priv->cb))
if ((gpio_event_cb_t)(gpio_pin_priv->cb))
{
((gpio_event_cb_t)(gpio_pin_priv->cb))(gpio_pin_priv->offset);
}
@ -304,7 +304,7 @@ gpio_port_handle_t csi_gpio_port_initialize(int32_t port)
void *handler;
int32_t idx = target_gpio_port_init(port, &base, &irq, &handler, &pin_num);
if (idx < 0 || idx >= CONFIG_GPIO_NUM)
if (idx < 0 || idx >= CONFIG_GPIO_NUM)
{
return NULL;
}
@ -384,14 +384,14 @@ static void do_wakeup_sleep_action(void *handle)
gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event)
{
if (gpio_pin < 0 || gpio_pin >= CONFIG_GPIO_PIN_NUM)
if (gpio_pin < 0 || gpio_pin >= CONFIG_GPIO_PIN_NUM)
{
return NULL;
}
uint32_t i;
for (i = 0; i < CONFIG_GPIO_NUM; i++)
for (i = 0; i < CONFIG_GPIO_NUM; i++)
{
csi_gpio_port_initialize(i);
}
@ -400,14 +400,14 @@ gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_e
uint32_t port_idx;
int32_t pin_idx = target_gpio_pin_init(gpio_pin, &port_idx);
if (pin_idx < 0)
if (pin_idx < 0)
{
return NULL;
}
int32_t idx = pin_idx;
for (i = 0; i < port_idx; i++)
for (i = 0; i < port_idx; i++)
{
idx += (gpio_handle[i].pin_num);
}
@ -430,7 +430,7 @@ gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_e
*/
int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle)
{
if (handle == NULL)
if (handle == NULL)
{
return ERR_GPIO(DRV_ERROR_PARAMETER);
}
@ -455,7 +455,7 @@ int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state)
#ifdef CONFIG_LPM
dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
power_cb_t callback =
power_cb_t callback =
{
.wakeup = do_wakeup_sleep_action,
.sleep = do_prepare_sleep_action,
@ -509,7 +509,7 @@ int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
uint32_t ret = gpio_set_direction(gpio_priv, dir);
if (ret)
if (ret)
{
return ret;
}
@ -542,7 +542,7 @@ int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
uint32_t ret = gpio_set_direction(gpio_priv, dir);
if (ret)
if (ret)
{
return ret;
}
@ -613,18 +613,18 @@ int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, boo
uint32_t ret = 0;
if (enable)
if (enable)
{
ret = gpio_set_irq_mode(handle, mode);
if (ret)
if (ret)
{
return ret;
}
gpio_irq_enable(handle);
} else
} else
{
gpio_irq_disable(handle);

2
bsp/thead-smart/drivers/dw_gpio.h
View File

@ -19,7 +19,7 @@ extern "C" {
#endif
typedef struct
typedef struct
{
__IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */
__IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */

34
bsp/thead-smart/drivers/dw_timer.c
View File

@ -20,7 +20,7 @@
#define TIMER_NULL_PARAM_CHK(para) HANDLE_PARAM_CHK(para, ERR_TIMER(DRV_ERROR_PARAMETER))
typedef struct
typedef struct
{
#ifdef CONFIG_LPM
uint8_t timer_power_status;
@ -59,7 +59,7 @@ void dw_timer_irqhandler(int idx)
addr->TxEOI;
if (timer_priv->cb_event)
if (timer_priv->cb_event)
{
return timer_priv->cb_event(idx, TIMER_EVENT_TIMEOUT);
}
@ -69,10 +69,10 @@ void dw_timer_irqhandler(int idx)
#ifdef CONFIG_LPM
static void manage_clock(timer_handle_t handle, uint8_t enable)
{
if (handle == &timer_instance[0] || handle == &timer_instance[1])
if (handle == &timer_instance[0] || handle == &timer_instance[1])
{
drv_clock_manager_config(CLOCK_MANAGER_TIM, enable);
} else if (handle == &timer_instance[3] || handle == &timer_instance[2])
} else if (handle == &timer_instance[3] || handle == &timer_instance[2])
{
drv_clock_manager_config(CLOCK_MANAGER_TIM1, enable);
}
@ -103,7 +103,7 @@ static void do_wakeup_sleep_action(timer_handle_t handle)
*/
timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event)
{
if (idx < 0 || idx >= CONFIG_TIMER_NUM)
if (idx < 0 || idx >= CONFIG_TIMER_NUM)
{
return NULL;
}
@ -114,7 +114,7 @@ timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event)
int32_t real_idx = target_get_timer(idx, &base, &irq, &handler);
if (real_idx != idx)
if (real_idx != idx)
{
return NULL;
}
@ -134,7 +134,7 @@ timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event)
timer_deactive_control(addr);
timer_priv->cb_event = cb_event;
if (cb_event != NULL)
if (cb_event != NULL)
{
drv_irq_register(timer_priv->irq, handler);
drv_irq_enable(timer_priv->irq);
@ -172,7 +172,7 @@ int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state)
{
TIMER_NULL_PARAM_CHK(handle);
#ifdef CONFIG_LPM
power_cb_t callback =
power_cb_t callback =
{
.wakeup = do_wakeup_sleep_action,
.sleep = do_prepare_sleep_action,
@ -197,7 +197,7 @@ int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode)
dw_timer_priv_t *timer_priv = handle;
dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
switch (mode)
switch (mode)
{
case TIMER_MODE_FREE_RUNNING:
addr->TxControl &= ~DW_TIMER_TXCONTROL_MODE;
@ -248,15 +248,15 @@ int32_t csi_timer_start(timer_handle_t handle)
uint32_t min_us = drv_get_timer_freq(timer_priv->idx) / 1000000;
uint32_t load;
if (((timer_priv->timeout * drv_get_timer_freq(timer_priv->idx)) / 1000000) > 0xffffffff)
if (((timer_priv->timeout * drv_get_timer_freq(timer_priv->idx)) / 1000000) > 0xffffffff)
{
return ERR_TIMER(DRV_ERROR_PARAMETER);
}
if (min_us)
if (min_us)
{
load = (uint32_t)(timer_priv->timeout * min_us);
} else
} else
{
load = (uint32_t)(((uint64_t)(timer_priv->timeout) * drv_get_timer_freq(timer_priv->idx)) / 1000000);
}
@ -265,11 +265,11 @@ int32_t csi_timer_start(timer_handle_t handle)
if (timer_priv->timeout == 0) {
addr->TxLoadCount = 0xffffffff; /* load time(us) */
} else
} else
{
if ((addr->TxControl | 0x2) == 0x2) {
addr->TxLoadCount = 0xffffffff; /* load time(us) */
} else
} else
{
addr->TxLoadCount = load; /* load time(us) */
}
@ -368,7 +368,7 @@ timer_status_t csi_timer_get_status(timer_handle_t handle)
{
timer_status_t timer_status = {0};
if (handle == NULL)
if (handle == NULL)
{
return timer_status;
}
@ -376,12 +376,12 @@ timer_status_t csi_timer_get_status(timer_handle_t handle)
dw_timer_priv_t *timer_priv = handle;
dw_timer_reg_t *addr = (dw_timer_reg_t *)(timer_priv->base);
if (addr->TxControl & DW_TIMER_TXCONTROL_ENABLE)
if (addr->TxControl & DW_TIMER_TXCONTROL_ENABLE)
{
timer_status.active = 1;
}
if (timer_priv->timeout_flag == 1)
if (timer_priv->timeout_flag == 1)
{
timer_status.timeout = 1;
}

6
bsp/thead-smart/drivers/dw_timer.h
View File

@ -33,11 +33,11 @@ typedef struct
__IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */
__IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */
__IOM uint8_t TxControl: 5; /* Offset: 0x008 (R/W) Clock frequency division low section register */
uint8_t RESERVED0[3];
uint8_t RESERVED0[3];
__IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */
uint8_t RESERVED1[3];
uint8_t RESERVED1[3];
__IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */
uint8_t RESERVED2[3];
uint8_t RESERVED2[3];
} dw_timer_reg_t;
#ifdef __cplusplus

6
bsp/thead-smart/drivers/isr.c
View File

@ -25,7 +25,7 @@ extern void systick_handler(void);
extern void xPortSysTickHandler(void);
extern void OSTimeTick(void);
#define ATTRIBUTE_ISR
#define ATTRIBUTE_ISR __attribute__ ((interrupt ("machine")))
#define readl(addr) \
({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
@ -37,14 +37,14 @@ extern void OSTimeTick(void);
#endif
void __attribute__((isr)) SysTick_Handler(void)
ATTRIBUTE_ISR void SysTick_Handler(void)
{
#if(CONFIG_KERNEL_RTTHREAD == 1)
CSI_INTRPT_ENTER();
#endif
csi_coret_config(drv_get_sys_freq() / CONFIG_SYSTICK_HZ, CORET_IRQn);
#if defined(CONFIG_KERNEL_RHINO)
systick_handler();
#elif defined(CONFIG_KERNEL_FREERTOS)

2
bsp/thead-smart/drivers/novic_irq_tbl.c
View File

@ -22,7 +22,7 @@ void irq_vectors_init(void)
{
int i;
for (i = 0; i < 48; i++)
for (i = 0; i < 48; i++)
{
g_irqvector[i] = Default_Handler;
}

67
bsp/thead-smart/drivers/startup_gcc.S
View File

@ -24,7 +24,7 @@ __Vectors:
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_IRQHandler
.long SysTick_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
@ -35,38 +35,39 @@ __Vectors:
.long Default_Handler
/* External interrupts */
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long Default_IRQHandler
.long USART_IRQHandler
.long Default_Handler
.long TIM0_IRQHandler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.long Default_Handler
.size __Vectors,.-__Vectors
.text
.align 2

24
bsp/thead-smart/drivers/system.c
View File

@ -39,6 +39,23 @@ static void _system_init_for_kernel(void)
drv_irq_enable(CORET_IRQn);
}
/**
* @brief initialize system map
* @param None
* @return None
*/
void systemmap_config(void)
{
csi_sysmap_config_region(0, 0x20000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
csi_sysmap_config_region(1, 0x40000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
csi_sysmap_config_region(2, 0x50000000, SYSMAP_SYSMAPCFG_SO_Msk);
csi_sysmap_config_region(3, 0x50700000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
csi_sysmap_config_region(4, 0x60000000, SYSMAP_SYSMAPCFG_SO_Msk);
csi_sysmap_config_region(5, 0x80000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
csi_sysmap_config_region(6, 0x90000000, SYSMAP_SYSMAPCFG_B_Msk | SYSMAP_SYSMAPCFG_C_Msk);
csi_sysmap_config_region(7, 0xf0000000, SYSMAP_SYSMAPCFG_SO_Msk);
}
/**
* @brief initialize the system
* Initialize the psr and vbr.
@ -48,8 +65,9 @@ static void _system_init_for_kernel(void)
void SystemInit(void)
{
int i;
systemmap_config();
/* enable mstatus FS */
#if ((CONFIG_CPU_E906F==1) || (CONFIG_CPU_E906FD==1))
#if (__riscv_flen)
uint32_t mstatus = __get_MSTATUS();
mstatus |= (1 << 13);
__set_MSTATUS(mstatus);
@ -68,7 +86,7 @@ void SystemInit(void)
/* get interrupt level from info */
CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
for (i = 0; i < 64; i++)
for (i = 0; i < 64; i++)
{
CLIC->CLICINT[i].IP = 0;
CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
@ -77,7 +95,9 @@ void SystemInit(void)
/* tspend use positive interrupt */
CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
#if ((CONFIG_CPU_E902 != 1) && (CONFIG_CPU_E902M != 1))
csi_dcache_enable();
#endif
csi_icache_enable();
drv_irq_enable(Machine_Software_IRQn);

14
bsp/thead-smart/drivers/trap_c.c
View File

@ -23,24 +23,24 @@ void trap_c(uint32_t *regs)
vec = __get_MCAUSE() & 0x3FF;
printf("CPU Exception: NO.%d", vec);
printf("CPU Exception: NO.%ld", vec);
printf("\n");
for (i = 0; i < 31; i++)
for (i = 0; i < 31; i++)
{
printf("x%d: %08x\t", i + 1, regs[i]);
printf("x%d: %08lx\t", i + 1, regs[i]);
if ((i % 4) == 3)
if ((i % 4) == 3)
{
printf("\n");
}
}
printf("\n");
printf("mepc : %08x\n", regs[31]);
printf("mstatus: %08x\n", regs[32]);
printf("mepc : %08lx\n", regs[31]);
printf("mstatus: %08lx\n", regs[32]);
if (trap_c_callback)
if (trap_c_callback)
{
trap_c_callback();
}

11
bsp/thead-smart/drivers/vectors.S
View File

@ -10,6 +10,8 @@
#include <csi_config.h>
#include <rtconfig.h>
#include <cpuport.h>
/* Enable interrupts when returning from the handler */
#define MSTATUS_PRV1 0x1880
@ -47,7 +49,7 @@ irq_mstatus_fs_flag:
Default_IRQHandler:
ipush
#ifdef ARCH_RISCV_FPU
#ifdef __riscv_flen
csrr t1, mstatus
srli t1, t1, 13
andi t1, t1, 0x3
@ -92,7 +94,7 @@ Default_IRQHandler:
li t0, MSTATUS_PRV1
csrs mstatus, t0
#ifdef ARCH_RISCV_FPU
#ifdef __riscv_flen
la t0, irq_mstatus_fs_flag
lw t1, (t0)
li t0, 0x3
@ -135,6 +137,7 @@ Default_IRQHandler:
.type trap, %function
trap:
/* Check for interrupt */
j .
addi sp, sp, -4
sw t0, 0x0(sp)
csrr t0, mcause
@ -235,7 +238,7 @@ Default_Handler:
sw t5, 56(sp)
sw t6, 60(sp)
#ifdef ARCH_RISCV_FPU
#ifdef __riscv_flen
addi sp, sp, -(20*FREGBYTES)
FSTORE ft0, 0 * FREGBYTES(sp)
FSTORE ft1, 1 * FREGBYTES(sp)
@ -263,7 +266,7 @@ Default_Handler:
lw t0, (t0)
jalr t0
#ifdef ARCH_RISCV_FPU
#ifdef __riscv_flen
FLOAD ft0, 0 * FREGBYTES(sp)
FLOAD ft1, 1 * FREGBYTES(sp)
FLOAD ft2, 2 * FREGBYTES(sp)

5
bsp/thead-smart/gcc_csky.ld
View File

@ -101,6 +101,7 @@ SECTIONS
*(.rodata1)
*(.rodata*)
*(.rodata.*)
*(.srodata*)
*(.rodata.str1.4)
. = ALIGN(0x4) ;
__ctor_start__ = .;
@ -116,10 +117,10 @@ SECTIONS
} > REGION_RODATA
.data : {
. = ALIGN(0x4) ;
__sdata = . ;
__data_start__ = . ;
__sdata = . ;
data_start = . ;
KEEP(*startup.o(*.vectors*))
KEEP(*startup_gcc.o(*.vectors*))
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)

11
bsp/thead-smart/gdbinit Normal file
View File

@ -0,0 +1,11 @@
target remote 172.16.201.64:1025
set *(int *)0x0=0x6f
si
reset
set *(int *)0x40011008=0x0
set *(int *)0x4001101c=0x0
set disassemble-next-line on
show disassemble-next-line
lo

12
bsp/thead-smart/rtconfig.h
View File

@ -39,9 +39,19 @@
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40003
#define ARCH_RISCV
#define ARCH_RISCV32
#if(__riscv_flen == 64)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_D
#elif(__riscv_flen == 32)
#define ARCH_RISCV_FPU
#define ARCH_RISCV_FPU_S
#define ARCH_RISCV32
#else
#endif
#ifdef __riscv_zp64
#define ARCH_RISCV_DSP
#endif
/* RT-Thread Components */

31
bsp/thead-smart/rtconfig.py
View File

@ -1,9 +1,11 @@
import os
# toolchains options
# CPUNAME = e906/e906f/e906fd/e906p/e906fp/e906fdp
# CPUNAME = e907/e907f/e907fd/e907p/e907fp/e907fdp
ARCH ='risc-v'
CPU ='e906'
CPUNAME ='e906f'
CPU ='e9xx'
CPUNAME ='e906fdp'
VENDOR ='t-head'
CROSS_TOOL ='gcc'
@ -12,9 +14,9 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'/home/xinge/tools/riscv64-elf-x86_64-20200616-1.9.6/bin'
EXEC_PATH = r'/home/chenzx/.thead/riscv64-elf-x86_64-2.0.1/bin/'
else:
print 'Please make sure your toolchains is GNU GCC!'
print ('Please make sure your toolchains is GNU GCC!')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
@ -37,16 +39,23 @@ if PLATFORM == 'gcc':
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
if CPUNAME == 'e906fd':
DEVICE = ' -march=rv32imafdcxthead -mabi=ilp32d'
if CPUNAME == 'e906f':
DEVICE = ' -march=rv32imafcxthead -mabi=ilp32f'
if CPUNAME == 'e906':
DEVICE = ' -march=rv32imacxthead -mabi=ilp32'
if CPUNAME == 'e906fdp' or CPUNAME == 'e907fdp':
DEVICE = ' -march=rv32imafdcpzp64_xtheade -mabi=ilp32d'
if CPUNAME == 'e906fp' or CPUNAME == 'e907fp':
DEVICE = ' -march=rv32imafcpzp64_xtheade -mabi=ilp32f'
if CPUNAME == 'e906p' or CPUNAME == 'e907p':
DEVICE = ' -march=rv32imacpzp64_xtheade -mabi=ilp32'
if CPUNAME == 'e906fd' or CPUNAME == 'e907fd':
DEVICE = ' -march=rv32imafdc_xtheade -mabi=ilp32d'
if CPUNAME == 'e906f' or CPUNAME == 'e907f':
DEVICE = ' -march=rv32imafc_xtheade -mabi=ilp32f'
if CPUNAME == 'e906' or CPUNAME == 'e907':
DEVICE = ' -march=rv32imac_xtheade -mabi=ilp32'
CFLAGS = DEVICE + ' -c -g -ffunction-sections -fdata-sections -Wall -mcmodel=medlow'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-whole-archive -T gcc_csky.ld -lm -lc -lgcc -Wl,-gc-sections -Wl,-zmax-page-size=1024'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--no-whole-archive -T gcc_csky.ld -lm -lc -lgcc -Wl,-gc-sections -Wl,-zmax-page-size=1024 -Wl,-Map=rtt.map'
CPATH = ''
LPATH = ''

4
libcpu/risc-v/SConscript
View File

@ -10,7 +10,7 @@ group = []
list = os.listdir(cwd)
# add common code files
if rtconfig.CPU == "e906" :
if rtconfig.CPU == "e9xx" :
group = group
elif rtconfig.CPU == "nuclei" :
group = group
@ -20,7 +20,7 @@ else :
group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
# cpu porting code files
if rtconfig.CPU == "e906" :
if rtconfig.CPU == "e9xx" :
group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
else :
group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))

0
libcpu/risc-v/t-head/e906/SConscript → libcpu/risc-v/t-head/e9xx/SConscript
View File

18
libcpu/risc-v/t-head/e906/context_gcc.S → libcpu/risc-v/t-head/e9xx/context_gcc.S
View File

@ -181,7 +181,11 @@ PendSV_Handler:
FSTORE f31, 31 * FREGBYTES(sp)
#endif
#ifdef ARCH_RISCV_DSP
addi sp, sp, -33 * REGBYTES
#else
addi sp, sp, -32 * REGBYTES
#endif
STORE x1, 1 * REGBYTES(sp)
csrr x1, mepc
@ -221,6 +225,10 @@ PendSV_Handler:
STORE x29, 29 * REGBYTES(sp)
STORE x30, 30 * REGBYTES(sp)
STORE x31, 31 * REGBYTES(sp)
#ifdef ARCH_RISCV_DSP
csrr t0, vxsat
STORE t0, 32 * REGBYTES(sp)
#endif
/* store from_thread sp */
la t0, rt_interrupt_from_thread
@ -237,6 +245,12 @@ PendSV_Handler:
lw t0, (t0)
LOAD sp, (t0)
#ifdef ARCH_RISCV_DSP
LOAD a1, 32 * REGBYTES(sp)
csrw vxsat, a1
#endif
/* restore ra to mepc */
LOAD a1, 0 * REGBYTES(sp)
csrw mepc, a1
@ -277,7 +291,11 @@ PendSV_Handler:
LOAD x30, 30 * REGBYTES(sp)
LOAD x31, 31 * REGBYTES(sp)
#ifdef ARCH_RISCV_DSP
addi sp, sp, 33 * REGBYTES
#else
addi sp, sp, 32 * REGBYTES
#endif
#ifdef ARCH_RISCV_FPU
FLOAD f0, 0 * FREGBYTES(sp)

3
libcpu/risc-v/t-head/e906/cpuport.c → libcpu/risc-v/t-head/e9xx/cpuport.c
View File

@ -53,6 +53,9 @@ struct rt_hw_stack_frame
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
#ifdef ARCH_RISCV_DSP
rt_ubase_t vxsat; /* P-ext vxsat reg */
#endif
#ifdef ARCH_RISCV_FPU
rv_floatreg_t f0; /* f0 */
rv_floatreg_t f1; /* f1 */

0
libcpu/risc-v/t-head/e906/cpuport.h → libcpu/risc-v/t-head/e9xx/cpuport.h
View File