optimize emac and usart driver code
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56794960d1
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1d77744a37
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@ -8,6 +8,7 @@
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* 2022-05-16 shelton first version
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* 2022-07-11 shelton optimize code to improve network throughput
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* performance
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* 2022-10-15 shelton optimize code
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*/
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#include "drv_emac.h"
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@ -355,6 +356,7 @@ static rt_err_t rt_at32_emac_init(rt_device_t dev)
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emac_control_para_init(&mac_control_para);
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mac_control_para.auto_nego = EMAC_AUTO_NEGOTIATION_ON;
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if(emac_phy_init(&mac_control_para) == ERROR)
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{
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LOG_E("emac hardware init failed");
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@ -376,8 +378,19 @@ static rt_err_t rt_at32_emac_init(rt_device_t dev)
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/* set emac dma tx link list */
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emac_dma_descriptor_list_address_set(EMAC_DMA_TRANSMIT, dma_tx_dscr_tab, tx_buff, EMAC_NUM_TX_BUF);
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/* emac interrupt init */
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emac_dma_para_init(&dma_control_para);
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dma_control_para.rsf_enable = TRUE;
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dma_control_para.tsf_enable = TRUE;
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dma_control_para.osf_enable = TRUE;
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dma_control_para.aab_enable = TRUE;
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dma_control_para.usp_enable = TRUE;
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dma_control_para.fb_enable = TRUE;
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dma_control_para.flush_rx_disable = TRUE;
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dma_control_para.rx_dma_pal = EMAC_DMA_PBL_32;
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dma_control_para.tx_dma_pal = EMAC_DMA_PBL_32;
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dma_control_para.priority_ratio = EMAC_DMA_2_RX_1_TX;
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emac_dma_config(&dma_control_para);
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/* emac interrupt init */
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emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_NORMAL_SUMMARY, TRUE);
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emac_dma_interrupt_enable(EMAC_DMA_INTERRUPT_RX, TRUE);
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nvic_irq_enable(EMAC_IRQn, 0x07, 0);
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@ -467,6 +480,7 @@ rt_err_t rt_at32_emac_tx(rt_device_t dev, struct pbuf *p)
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#ifdef EMAC_TX_DUMP
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dump_hex(p->payload, p->tot_len);
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#endif
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/* prepare transmit descriptors to give to dma */
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LOG_D("transmit frame length :%d", p->tot_len);
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2022-05-16 shelton first version
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* 2022-10-15 shelton optimize code
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*/
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#include "drv_common.h"
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@ -228,7 +229,6 @@ static void usart_isr(struct rt_serial_device *serial) {
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if (usart_flag_get(usart_instance->usart_x, USART_RDBF_FLAG) != RESET) {
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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usart_flag_clear(usart_instance->usart_x, USART_RDBF_FLAG);
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}
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else
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{
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