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[bsp] Remove the at91sam9g45 bsp.

This commit is contained in:
armink 2019-01-07 09:12:31 +08:00
parent 56075ce8a3
commit 18dfb50e9b
37 changed files with 0 additions and 15422 deletions
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311
bsp/at91sam9g45/.config
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@ -1,311 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu"
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_RT_USING_DBGU=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_RT_USING_UART1 is not set
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_RT_USING_LED=y

14
bsp/at91sam9g45/SConscript
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@ -1,14 +0,0 @@
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

39
bsp/at91sam9g45/SConstruct
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@ -1,39 +0,0 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-at91sam9g45.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
if GetDepend('RT_USING_WEBSERVER'):
objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
if GetDepend('RT_USING_RTGUI'):
objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
# libc testsuite
objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
# make a building
DoBuilding(TARGET, objs)

11
bsp/at91sam9g45/applications/SConscript
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@ -1,11 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

173
bsp/at91sam9g45/applications/application.c
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@ -1,173 +0,0 @@
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
/**
* @addtogroup at91sam9260
*/
/*@{*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_DFS
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#endif
#ifdef RT_USING_SDIO
#include <drivers/mmcsd_core.h>
#include "at91_mci.h"
#endif
#ifdef RT_USING_LED
#include "led.h"
#endif
static int rt_led_app_init(void);
RT_WEAK int main(void)
{
#ifdef RT_USING_SDIO
int timeout = 0;
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
#if defined(RT_USING_DFS_ROMFS)
if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
{
rt_kprintf("ROM File System initialized!\n");
}
else
rt_kprintf("ROM File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_UFFS)
{
/* mount flash device as flash directory */
if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
rt_kprintf("UFFS File System initialized!\n");
else
rt_kprintf("UFFS File System initialzation failed!\n");
}
#endif
#ifdef RT_USING_SDIO
timeout = 0;
while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
{
rt_thread_delay(1);
}
if (timeout < RT_TICK_PER_SECOND*2)
{
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
}
else
{
rt_kprintf("No SD card found.\n");
}
#endif
}
#endif
rt_led_app_init();
}
#ifdef RT_USING_LED
void rt_led_thread_entry(void* parameter)
{
rt_uint8_t cnt = 0;
led_init();
while(1)
{
/* light on leds for one second */
rt_thread_delay(40);
cnt++;
if (cnt&0x01)
led_on(1);
else
led_off(1);
if (cnt&0x02)
led_on(2);
else
led_off(2);
if (cnt&0x04)
led_on(3);
else
led_off(3);
}
}
#endif
static int rt_led_app_init(void)
{
#ifdef RT_USING_LED
rt_thread_t led_thread;
#if (RT_THREAD_PRIORITY_MAX == 32)
led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL,
512, 20, 20);
#else
led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL,
512, 200, 20);
#endif
if(led_thread != RT_NULL)
rt_thread_startup(led_thread);
#endif
return 0;
}
/* NFSv3 Initialization */
#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
#include <dfs_nfs.h>
void nfs_start(void)
{
nfs_init();
if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
{
rt_kprintf("NFSv3 File System initialized!\n");
}
else
rt_kprintf("NFSv3 File System initialzation failed!\n");
}
#include "finsh.h"
FINSH_FUNCTION_EXPORT(nfs_start, start net filesystem);
#endif
/*@}*/

31
bsp/at91sam9g45/drivers/SConscript
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@ -1,31 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drvers.
src = Split("""
board.c
usart.c
""")
# add Ethernet drvers.
if GetDepend('RT_USING_LED'):
src += ['led.c']
if GetDepend('RT_USING_SDIO'):
src += ['at91_mci.c']
if GetDepend('RT_USING_LWIP'):
src += ['macb.c']
if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
src += ['at91_i2c_gpio.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

130
bsp/at91sam9g45/drivers/at91_i2c_gpio.c
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@ -1,130 +0,0 @@
/*
* File : at91_i2c_gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
*/
#include <rtdevice.h>
#include <rthw.h>
#include <at91sam9g45.h>
static void at91_i2c_gpio_init()
{
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock
AT91C_BASE_PIOA->PIO_PUER = (1 << 23);
AT91C_BASE_PIOA->PIO_PER = (1 << 23);
AT91C_BASE_PIOA->PIO_MDER = (1 << 23);
AT91C_BASE_PIOA->PIO_PUER = (1 << 24);
AT91C_BASE_PIOA->PIO_PER = (1 << 24);
AT91C_BASE_PIOA->PIO_MDER = (1 << 24);
AT91C_BASE_PIOA->PIO_OER = (1 << 23);
AT91C_BASE_PIOA->PIO_OER = (1 << 24);
AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
}
static void at91_set_sda(void *data, rt_int32_t state)
{
if (state)
{
AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
}
else
{
AT91C_BASE_PIOA->PIO_CODR = (1 << 23);
}
}
static void at91_set_scl(void *data, rt_int32_t state)
{
if (state)
{
AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
}
else
{
AT91C_BASE_PIOA->PIO_CODR = (1 << 24);
}
}
static rt_int32_t at91_get_sda(void *data)
{
return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23);
}
static rt_int32_t at91_get_scl(void *data)
{
return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24);
}
static void at91_udelay (rt_uint32_t us)
{
rt_int32_t i;
for (; us > 0; us--)
{
i = 50000;
while(i > 0)
{
i--;
}
}
}
static const struct rt_i2c_bit_ops bit_ops = {
RT_NULL,
at91_set_sda,
at91_set_scl,
at91_get_sda,
at91_get_scl,
at91_udelay,
5,
100
};
int at91_i2c_init(void)
{
struct rt_i2c_bus_device *bus;
bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
if (bus == RT_NULL)
{
rt_kprintf("rt_malloc failed\n");
return -RT_ENOMEM;
}
rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
bus->priv = (void *)&bit_ops;
at91_i2c_gpio_init();
rt_i2c_bit_add_bus(bus, "i2c0");
return 0;
}
INIT_DEVICE_EXPORT(at91_i2c_init);

924
bsp/at91sam9g45/drivers/at91_mci.c
View File

@ -1,924 +0,0 @@
/*
* File : at91_mci.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-07-25 weety first version
*/
#include <rtthread.h>
#include <rthw.h>
#include <drivers/mmcsd_core.h>
#include <at91sam9g45.h>
#include "at91_mci.h"
#define USE_SLOT_B
//#define RT_MCI_DBG
#ifdef RT_MCI_DBG
#define mci_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
#else
#define mci_dbg(fmt, ...)
#endif
#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \
| AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \
| AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE)
#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg))
#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg))
#define REQ_ST_INIT (1U << 0)
#define REQ_ST_CMD (1U << 1)
#define REQ_ST_STOP (1U << 2)
struct at91_mci {
struct rt_mmcsd_host *host;
struct rt_mmcsd_req *req;
struct rt_mmcsd_cmd *cmd;
struct rt_timer timer;
//struct rt_semaphore sem_ack;
rt_uint32_t *buf;
rt_uint32_t current_status;
};
/*
* Reset the controller and restore most of the state
*/
static void at91_reset_host()
{
rt_uint32_t mr;
rt_uint32_t sdcr;
rt_uint32_t dtor;
rt_uint32_t imr;
rt_uint32_t level;
level = rt_hw_interrupt_disable();
imr = at91_mci_read(AT91C_MCI_IMR);
at91_mci_write(AT91C_MCI_IDR, 0xffffffff);
/* save current state */
mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff;
sdcr = at91_mci_read(AT91C_MCI_SDCR);
dtor = at91_mci_read(AT91C_MCI_DTOR);
/* reset the controller */
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST);
/* restore state */
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
at91_mci_write(AT91C_MCI_MR, mr);
at91_mci_write(AT91C_MCI_SDCR, sdcr);
at91_mci_write(AT91C_MCI_DTOR, dtor);
at91_mci_write(AT91C_MCI_IER, imr);
/* make sure sdio interrupts will fire */
at91_mci_read(AT91C_MCI_SR);
rt_hw_interrupt_enable(level);
}
/*
* Enable the controller
*/
static void at91_mci_enable()
{
rt_uint32_t mr;
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
at91_mci_write(AT91C_MCI_IDR, 0xffffffff);
at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC);
mr = AT91C_MCI_PDCMODE | 0x34a;
mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF;
at91_mci_write(AT91C_MCI_MR, mr);
/* use Slot A or B (only one at same time) */
at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */
}
/*
* Disable the controller
*/
static void at91_mci_disable()
{
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST);
}
static void at91_timeout_timer(void *data)
{
struct at91_mci *mci;
mci = (struct at91_mci *)data;
if (mci->req)
{
rt_kprintf("Timeout waiting end of packet\n");
if (mci->current_status == REQ_ST_CMD)
{
if (mci->req->cmd && mci->req->data)
{
mci->req->data->err = -RT_ETIMEOUT;
}
else
{
if (mci->req->cmd)
mci->req->cmd->err = -RT_ETIMEOUT;
}
}
else if (mci->current_status == REQ_ST_STOP)
{
mci->req->stop->err = -RT_ETIMEOUT;
}
at91_reset_host();
mmcsd_req_complete(mci->host);
}
}
/*
* Prepare a dma read
*/
static void at91_mci_init_dma_read(struct at91_mci *mci)
{
rt_uint8_t i;
struct rt_mmcsd_cmd *cmd;
struct rt_mmcsd_data *data;
rt_uint32_t length;
mci_dbg("pre dma read\n");
cmd = mci->cmd;
if (!cmd)
{
mci_dbg("no command\n");
return;
}
data = cmd->data;
if (!data)
{
mci_dbg("no data\n");
return;
}
for (i = 0; i < 1; i++)
{
/* Check to see if this needs filling */
if (i == 0)
{
if (at91_mci_read(AT91C_PDC_RCR) != 0)
{
mci_dbg("Transfer active in current\n");
continue;
}
}
else {
if (at91_mci_read(AT91C_PDC_RNCR) != 0)
{
mci_dbg("Transfer active in next\n");
continue;
}
}
length = data->blksize * data->blks;
mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
if (i == 0)
{
at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf));
at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
}
else
{
at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf));
at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
}
}
mci_dbg("pre dma read done\n");
}
/*
* Send a command
*/
static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
{
rt_uint32_t cmdr, mr;
rt_uint32_t block_length;
struct rt_mmcsd_data *data = cmd->data;
struct rt_mmcsd_host *host = mci->host;
rt_uint32_t blocks;
rt_uint32_t ier = 0;
rt_uint32_t length;
mci->cmd = cmd;
/* Needed for leaving busy state before CMD1 */
if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1))
{
mci_dbg("Clearing timeout\n");
at91_mci_write(AT91C_MCI_ARGR, 0);
at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD);
while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY))
{
/* spin */
mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR));
}
}
cmdr = cmd->cmd_code;
if (resp_type(cmd) == RESP_NONE)
cmdr |= AT91C_MCI_RSPTYP_NONE;
else
{
/* if a response is expected then allow maximum response latancy */
cmdr |= AT91C_MCI_MAXLAT;
/* set 136 bit response for R2, 48 bit response otherwise */
if (resp_type(cmd) == RESP_R2)
cmdr |= AT91C_MCI_RSPTYP_136;
else
cmdr |= AT91C_MCI_RSPTYP_48;
}
if (data)
{
block_length = data->blksize;
blocks = data->blks;
/* always set data start - also set direction flag for read */
if (data->flags & DATA_DIR_READ)
cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START);
else if (data->flags & DATA_DIR_WRITE)
cmdr |= AT91C_MCI_TRCMD_START;
if (data->flags & DATA_STREAM)
cmdr |= AT91C_MCI_TRTYP_STREAM;
if (data->blks > 1)
cmdr |= AT91C_MCI_TRTYP_MULTIPLE;
}
else
{
block_length = 0;
blocks = 0;
}
/*if (cmd->cmd_code == GO_IDLE_STATE)
{
cmdr |= AT91C_MCI_SPCMD_INIT;
}*/
if (cmd->cmd_code == STOP_TRANSMISSION)
cmdr |= AT91C_MCI_TRCMD_STOP;
if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
cmdr |= AT91C_MCI_OPDCMD;
/*
* Set the arguments and send the command
*/
mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR));
if (!data)
{
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
at91_mci_write(AT91C_PDC_RPR, 0);
at91_mci_write(AT91C_PDC_RCR, 0);
at91_mci_write(AT91C_PDC_RNPR, 0);
at91_mci_write(AT91C_PDC_RNCR, 0);
at91_mci_write(AT91C_PDC_TPR, 0);
at91_mci_write(AT91C_PDC_TCR, 0);
at91_mci_write(AT91C_PDC_TNPR, 0);
at91_mci_write(AT91C_PDC_TNCR, 0);
ier = AT91C_MCI_CMDRDY;
}
else
{
/* zero block length and PDC mode */
mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff;
mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0;
mr |= (block_length << 16);
mr |= AT91C_MCI_PDCMODE;
at91_mci_write(AT91C_MCI_MR, mr);
at91_mci_write(AT91C_MCI_BLKR,
AT91C_MCI_BLKR_BCNT(blocks) |
AT91C_MCI_BLKR_BLKLEN(block_length));
/*
* Disable the PDC controller
*/
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
if (cmdr & AT91C_MCI_TRCMD_START)
{
if (cmdr & AT91C_MCI_TRDIR)
{
/*
* Handle a read
*/
mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
at91_mci_init_dma_read(mci);
ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */;
}
else
{
/*
* Handle a write
*/
length = block_length * blocks;
/*
* at91mci MCI1 rev2xx Data Write Operation and
* number of bytes erratum
*/
if (length < 12)
{
length = 12;
mci->buf = rt_malloc(length);
if (!mci->buf)
{
rt_kprintf("rt alloc tx buffer failed\n");
cmd->err = -RT_ENOMEM;
mmcsd_req_complete(mci->host);
return;
}
rt_memset(mci->buf, 0, 12);
rt_memcpy(mci->buf, data->buf, length);
mmu_clean_dcache((rt_uint32_t)mci->buf, length);
at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf));
at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ?
length : length / 4);
}
else
{
mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf));
at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ?
length : length / 4);
}
mci_dbg("Transmitting %d bytes\n", length);
ier = AT91C_MCI_CMDRDY;
}
}
}
/*
* Send the command and then enable the PDC - not the other way round as
* the data sheet says
*/
at91_mci_write(AT91C_MCI_ARGR, cmd->arg);
at91_mci_write(AT91C_MCI_CMDR, cmdr);
if (cmdr & AT91C_MCI_TRCMD_START)
{
if (cmdr & AT91C_MCI_TRDIR)
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN);
}
/* Enable selected interrupts */
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier);
}
/*
* Process the next step in the request
*/
static void at91_mci_process_next(struct at91_mci *mci)
{
if (mci->current_status == REQ_ST_INIT)
{
mci->current_status = REQ_ST_CMD;
at91_mci_send_command(mci, mci->req->cmd);
}
else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
{
mci->current_status = REQ_ST_STOP;
at91_mci_send_command(mci, mci->req->stop);
}
else
{
rt_timer_stop(&mci->timer);
/* the mci controller hangs after some transfers,
* and the workaround is to reset it after each transfer.
*/
at91_reset_host();
mmcsd_req_complete(mci->host);
}
}
/*
* Handle an MMC request
*/
static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
rt_uint32_t timeout = RT_TICK_PER_SECOND;
struct at91_mci *mci = host->private_data;
mci->req = req;
mci->current_status = REQ_ST_INIT;
rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
rt_timer_start(&mci->timer);
at91_mci_process_next(mci);
}
/*
* Handle transmitted data
*/
static void at91_mci_handle_transmitted(struct at91_mci *mci)
{
struct rt_mmcsd_cmd *cmd;
struct rt_mmcsd_data *data;
mci_dbg("Handling the transmit\n");
/* Disable the transfer */
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
/* Now wait for cmd ready */
at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE);
cmd = mci->cmd;
if (!cmd) return;
data = cmd->data;
if (!data) return;
if (data->blks > 1)
{
mci_dbg("multiple write : wait for BLKE...\n");
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE);
} else
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
}
/*
* Handle after a dma read
*/
static void at91_mci_post_dma_read(struct at91_mci *mci)
{
struct rt_mmcsd_cmd *cmd;
struct rt_mmcsd_data *data;
mci_dbg("post dma read\n");
cmd = mci->cmd;
if (!cmd)
{
mci_dbg("no command\n");
return;
}
data = cmd->data;
if (!data)
{
mci_dbg("no data\n");
return;
}
at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX);
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF);
mci_dbg("post dma read done\n");
}
/*Handle after command sent ready*/
static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
{
if (!mci->cmd)
return 1;
else if (!mci->cmd->data)
{
if (mci->current_status == REQ_ST_STOP)
{
/*After multi block write, we must wait for NOTBUSY*/
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
}
else return 1;
}
else if (mci->cmd->data->flags & DATA_DIR_WRITE)
{
/*After sendding multi-block-write command, start DMA transfer*/
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE);
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN);
}
/* command not completed, have to wait */
return 0;
}
/*
* Handle a command that has been completed
*/
static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
{
struct rt_mmcsd_cmd *cmd = mci->cmd;
struct rt_mmcsd_data *data = cmd->data;
at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0));
cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1));
cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2));
cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3));
if (mci->buf)
{
//rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
rt_free(mci->buf);
mci->buf = RT_NULL;
}
mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
status, at91_mci_read(AT91C_MCI_SR),
cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
if (status & AT91C_MCI_ERRORS)
{
if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
{
cmd->err = 0;
}
else
{
if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE))
{
if (data)
{
if (status & AT91C_MCI_DTOE)
data->err = -RT_ETIMEOUT;
else if (status & AT91C_MCI_DCRCE)
data->err = -RT_ERROR;
}
}
else
{
if (status & AT91C_MCI_RTOE)
cmd->err = -RT_ETIMEOUT;
else if (status & AT91C_MCI_RCRCE)
cmd->err = -RT_ERROR;
else
cmd->err = -RT_ERROR;
}
rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
cmd->err, data ? data->err : 0,
cmd->cmd_code);
}
}
else
cmd->err = 0;
at91_mci_process_next(mci);
}
/*
* Handle an interrupt
*/
static void at91_mci_irq(int irq, void *param)
{
struct at91_mci *mci = (struct at91_mci *)param;
rt_int32_t completed = 0;
rt_uint32_t int_status, int_mask;
int_status = at91_mci_read(AT91C_MCI_SR);
int_mask = at91_mci_read(AT91C_MCI_IMR);
mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
int_status & int_mask);
int_status = int_status & int_mask;
if (int_status & AT91C_MCI_ERRORS)
{
completed = 1;
if (int_status & AT91C_MCI_UNRE)
mci_dbg("MMC: Underrun error\n");
if (int_status & AT91C_MCI_OVRE)
mci_dbg("MMC: Overrun error\n");
if (int_status & AT91C_MCI_DTOE)
mci_dbg("MMC: Data timeout\n");
if (int_status & AT91C_MCI_DCRCE)
mci_dbg("MMC: CRC error in data\n");
if (int_status & AT91C_MCI_RTOE)
mci_dbg("MMC: Response timeout\n");
if (int_status & AT91C_MCI_RENDE)
mci_dbg("MMC: Response end bit error\n");
if (int_status & AT91C_MCI_RCRCE)
mci_dbg("MMC: Response CRC error\n");
if (int_status & AT91C_MCI_RDIRE)
mci_dbg("MMC: Response direction error\n");
if (int_status & AT91C_MCI_RINDE)
mci_dbg("MMC: Response index error\n");
}
else
{
/* Only continue processing if no errors */
if (int_status & AT91C_MCI_TXBUFE)
{
mci_dbg("TX buffer empty\n");
at91_mci_handle_transmitted(mci);
}
if (int_status & AT91C_MCI_ENDRX)
{
mci_dbg("ENDRX\n");
at91_mci_post_dma_read(mci);
}
if (int_status & AT91C_MCI_RXBUFF)
{
mci_dbg("RX buffer full\n");
at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS);
at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX);
completed = 1;
}
if (int_status & AT91C_MCI_ENDTX)
mci_dbg("Transmit has ended\n");
if (int_status & AT91C_MCI_NOTBUSY)
{
mci_dbg("Card is ready\n");
//at91_mci_update_bytes_xfered(host);
completed = 1;
}
if (int_status & AT91C_MCI_DTIP)
mci_dbg("Data transfer in progress\n");
if (int_status & AT91C_MCI_BLKE)
{
mci_dbg("Block transfer has ended\n");
if (mci->req->data && mci->req->data->blks > 1)
{
/* multi block write : complete multi write
* command and send stop */
completed = 1;
}
else
{
at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY);
}
}
/*if (int_status & AT91C_MCI_SDIOIRQA)
rt_mmcsd_signal_sdio_irq(host->mmc);*/
if (int_status & AT91C_MCI_SDIOIRQB)
sdio_irq_wakeup(mci->host);
if (int_status & AT91C_MCI_TXRDY)
mci_dbg("Ready to transmit\n");
if (int_status & AT91C_MCI_RXRDY)
mci_dbg("Ready to receive\n");
if (int_status & AT91C_MCI_CMDRDY)
{
mci_dbg("Command ready\n");
completed = at91_mci_handle_cmdrdy(mci);
}
}
if (completed)
{
mci_dbg("Completed command\n");
at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
at91_mci_completed_command(mci, int_status);
}
else
at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB));
}
/*
* Set the IOCFG
*/
static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t clkdiv;
//struct at91_mci *mci = host->private_data;
rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
if (io_cfg->clock == 0)
{
/* Disable the MCI controller */
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS);
clkdiv = 0;
}
else
{
/* Enable the MCI controller */
at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN);
if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
else
clkdiv = (at91_master_clock / io_cfg->clock) / 2;
mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
at91_master_clock / (2 * (clkdiv + 1)));
}
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
{
mci_dbg("MMC: Setting controller bus width to 4\n");
at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS);
}
else
{
mci_dbg("MMC: Setting controller bus width to 1\n");
at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS);
}
/* Set the clock divider */
at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv);
/* maybe switch power to the card */
switch (io_cfg->power_mode)
{
case MMCSD_POWER_OFF:
break;
case MMCSD_POWER_UP:
break;
case MMCSD_POWER_ON:
/*at91_mci_write(AT91C_MCI_ARGR, 0);
at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD);
mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR));
while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY))
{
}
mci_dbg("at91 mci power on\n");*/
break;
default:
rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
break;
}
}
static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
{
at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB);
}
static const struct rt_mmcsd_host_ops ops = {
at91_mci_request,
at91_mci_set_iocfg,
RT_NULL,
at91_mci_enable_sdio_irq,
};
void at91_mci_detect(int irq, void *param)
{
rt_kprintf("mmcsd gpio detected\n");
}
static void mci_gpio_init()
{
#ifdef USE_SLOT_B
AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5);
AT91C_BASE_PIOA->PIO_PUDR = (1 << 8);
AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5);
AT91C_BASE_PIOA->PIO_ASR = (1 << 8);
AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8);
AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7);
AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7);
AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7);
AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7);
#else
AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11);
AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8);
AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8);
#endif
}
int at91_mci_init(void)
{
struct rt_mmcsd_host *host;
struct at91_mci *mci;
host = mmcsd_alloc_host();
if (!host)
{
return -RT_ERROR;
}
mci = rt_malloc(sizeof(struct at91_mci));
if (!mci)
{
rt_kprintf("alloc mci failed\n");
goto err;
}
rt_memset(mci, 0, sizeof(struct at91_mci));
host->ops = &ops;
host->freq_min = 375000;
host->freq_max = 25000000;
host->valid_ocr = VDD_32_33 | VDD_33_34;
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
host->max_seg_size = 65535;
host->max_dma_segs = 2;
host->max_blk_size = 512;
host->max_blk_count = 4096;
mci->host = host;
mci_gpio_init();
AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock
at91_mci_disable();
at91_mci_enable();
/* instal interrupt */
rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq,
(void *)mci, "MMC");
rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7),
at91_mci_detect, RT_NULL, "MMC_DETECT");
rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7));
rt_timer_init(&mci->timer, "mci_timer",
at91_timeout_timer,
mci,
RT_TICK_PER_SECOND,
RT_TIMER_FLAG_PERIODIC);
//rt_timer_start(&mci->timer);
//rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
host->private_data = mci;
mmcsd_change(host);
return 0;
err:
mmcsd_free_host(host);
return -RT_ENOMEM;
}
INIT_DEVICE_EXPORT(at91_mci_init);
#include "finsh.h"
FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
void mci_dump(void)
{
rt_uint32_t i;
rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR));
rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR));
rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR));
for (i = 0; i <= 0x4c; i += 4) {
rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
}
}
FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);

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@ -1,124 +0,0 @@
/*
* File : at91_mci.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-06-09 weety first version
*/
#ifndef __AT91C_MCI_H__
#define __AT91C_MCI_H__
#define AT91C_MCI_CR 0x00 /* Control Register */
#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */
#define AT91C_MCI_MR 0x04 /* Mode Register */
#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
#define AT91C_MCI_DTOMUL_1 (0 << 4)
#define AT91C_MCI_DTOMUL_16 (1 << 4)
#define AT91C_MCI_DTOMUL_128 (2 << 4)
#define AT91C_MCI_DTOMUL_256 (3 << 4)
#define AT91C_MCI_DTOMUL_1K (4 << 4)
#define AT91C_MCI_DTOMUL_4K (5 << 4)
#define AT91C_MCI_DTOMUL_64K (6 << 4)
#define AT91C_MCI_DTOMUL_1M (7 << 4)
#define AT91C_MCI_SDCR 0x0c /* SD Card Register */
#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91C_MCI_ARGR 0x10 /* Argument Register */
#define AT91C_MCI_CMDR 0x14 /* Command Register */
#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */
#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */
#define AT91C_MCI_RSPTYP_NONE (0 << 6)
#define AT91C_MCI_RSPTYP_48 (1 << 6)
#define AT91C_MCI_RSPTYP_136 (2 << 6)
#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */
#define AT91C_MCI_SPCMD_NONE (0 << 8)
#define AT91C_MCI_SPCMD_INIT (1 << 8)
#define AT91C_MCI_SPCMD_SYNC (2 << 8)
#define AT91C_MCI_SPCMD_ICMD (4 << 8)
#define AT91C_MCI_SPCMD_IRESP (5 << 8)
#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */
#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */
#define AT91C_MCI_TRCMD_NONE (0 << 16)
#define AT91C_MCI_TRCMD_START (1 << 16)
#define AT91C_MCI_TRCMD_STOP (2 << 16)
#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */
#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */
#define AT91C_MCI_TRTYP_BLOCK (0 << 19)
#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19)
#define AT91C_MCI_TRTYP_STREAM (2 << 19)
#define AT91C_MCI_BLKR 0x18 /* Block Register */
#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
#define AT91C_MCR_RDR 0x30 /* Receive Data Register */
#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */
#define AT91C_MCI_SR 0x40 /* Status Register */
#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */
#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */
#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */
#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */
#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */
#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */
#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */
#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */
#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */
#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */
#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */
#define AT91C_MCI_OVRE (1U << 30) /* Overrun */
#define AT91C_MCI_UNRE (1U << 31) /* Underrun */
#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */
#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */
#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */
extern int at91_mci_init(void);
#endif

248
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@ -1,248 +0,0 @@
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include <mmu.h>
/**
* @addtogroup at91sam9g45
*/
/*@{*/
#if defined(__CC_ARM)
extern int Image$$ER_ZI$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
#elif (defined (__GNUC__))
extern unsigned char __bss_end__;
#define HEAP_BEGIN (&__bss_end__)
#elif (defined (__ICCARM__))
#pragma section=".noinit"
#define HEAP_BEGIN (__section_end(".noinit"))
#endif
#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000)
extern void rt_hw_interrupt_init(void);
extern void rt_hw_clock_init(void);
extern void rt_hw_get_clock(void);
extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
extern void rt_dbgu_isr(void);
#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M
#define MMU_SECTION_SIZE 0x100000 // 1M
#define PERIPHERALS_ADDR // 1M
#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address
#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address
static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */
{ 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
//{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */
//{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */
//{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */
//{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
//{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
//{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
//{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */
//{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
//{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
//{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
{ 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */
{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */
//{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
};
#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV)
#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20)
static rt_uint32_t pit_cycle; /* write-once */
static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
/**
* This function will handle rtos timer
*/
void rt_timer_handler(int vector, void *param)
{
#ifdef RT_USING_DBGU
if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
{
rt_dbgu_isr();
}
#endif
if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
{
unsigned nr_ticks;
/* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
while (nr_ticks--)
rt_tick_increase();
}
}
static void at91sam9g45_pit_reset(void)
{
/* Disable timer and irqs */
AT91C_BASE_PITC->PITC_PIMR = 0;
/* Clear any pending interrupts, wait for PIT to stop counting */
while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
;
/* Start PIT but don't enable IRQ */
//AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
AT91C_BASE_PITC->PITC_PIMR =
(pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
}
/*
* Set up both clocksource and clockevent support.
*/
static void at91sam9g45_pit_init(void)
{
rt_uint32_t pit_rate;
//rt_uint32_t bits;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get("mck")) / 16;
rt_kprintf("pit_rate=%dHZ\n", pit_rate);
pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
/* Initialize and enable the timer */
at91sam9g45_pit_reset();
}
/**
* This function will init pit for system ticks
*/
void rt_hw_timer_init()
{
at91sam9g45_pit_init();
/* install interrupt handler */
rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
RT_NULL, "system");
rt_hw_interrupt_umask(AT91C_ID_SYS);
}
void at91_tc1_init()
{
AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
writel(0xffff, AT91C_TC0_CV);
}
#define BPS 115200 /* serial console port baudrate */
static void at91_usart_putc(char c)
{
while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
;
AT91C_BASE_DBGU->DBGU_THR = c;
}
/**
* This function is used to display a string on console, normally, it's
* invoked by rt_kprintf
*
* @param str the displayed string
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
if (*str=='\n')
{
at91_usart_putc('\r');
}
at91_usart_putc(*str++);
}
}
static void rt_hw_console_init(void)
{
int div;
int mode = 0;
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
AT91C_US_RXDIS | AT91C_US_TXDIS;
mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
AT91C_US_CHMODE_NORMAL;
mode |= AT91C_US_CHRL_8_BITS;
mode |= AT91C_US_NBSTOP_1_BIT;
mode |= AT91C_US_PAR_NONE;
AT91C_BASE_DBGU->DBGU_MR = mode;
div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
AT91C_BASE_DBGU->DBGU_BRGR = div;
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
}
/**
* This function will init at91sam9g45 board
*/
void rt_hw_board_init()
{
/* initialize the system clock */
rt_hw_clock_init();
/* initialize console */
rt_hw_console_init();
/* initialize mmu */
rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize early device */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* initialize timer0 */
rt_hw_timer_init();
/* initialize board */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
/*@}*/

32
bsp/at91sam9g45/drivers/board.h
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@ -1,32 +0,0 @@
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety add board.h to this bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <at91sam9g45.h>
void rt_hw_board_init(void);
#endif

54
bsp/at91sam9g45/drivers/led.c
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@ -1,54 +0,0 @@
/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rtthread.h>
#include <at91sam9g45.h>
#include "led.h"
// BYHX A-Plus Board
#define LED0 (1UL << 30)
#define LED1 (1UL << 31)
#define LED2 (1UL << 29)
#define LED3 (1UL << 28)
#define LED_ALL (LED0 | LED1 | LED2 | LED3)
void led_init(void)
{
AT91C_BASE_PIOC->PIO_PER = LED_ALL;
AT91C_BASE_PIOC->PIO_OER = LED_ALL;
AT91C_BASE_PIOC->PIO_PPUER = LED_ALL;
AT91C_BASE_PIOC->PIO_SODR = LED_ALL;
}
const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 };
void led_on(int num)
{
if (num < 4) AT91C_BASE_PIOC->PIO_CODR = m_leds[num];
}
void led_off(int num)
{
if (num < 4) AT91C_BASE_PIOC->PIO_SODR = m_leds[num];
}

32
bsp/at91sam9g45/drivers/led.h
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@ -1,32 +0,0 @@
/*
* File : led.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __LED_H__
#define __LED_H__
void led_init(void);
void led_on(int num);
void led_off(int num);
#endif

911
bsp/at91sam9g45/drivers/macb.c
View File

@ -1,911 +0,0 @@
/*
* File : macb.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-03-18 weety first version
*/
#include <rtthread.h>
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include <at91sam9g45.h>
#include "macb.h"
#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
/* Cache macros - Packet buffers would be from pbuf pool which is cached */
#define EMAC_VIRT_NOCACHE(addr) (addr)
#define EMAC_CACHE_INVALIDATE(addr, size) \
mmu_invalidate_dcache((rt_uint32_t)addr, size)
#define EMAC_CACHE_WRITEBACK(addr, size) \
mmu_clean_dcache((rt_uint32_t)addr, size)
#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
/* EMAC has BD's in cached memory - so need cache functions */
#define BD_CACHE_INVALIDATE(addr, size)
#define BD_CACHE_WRITEBACK(addr, size)
#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
/* EMAC internal utility function */
rt_inline unsigned long emac_virt_to_phys(unsigned long addr)
{
return addr;
}
#define AT91SAM9260_SRAM0_VIRT_BASE (0x90000000)
#define MACB_TX_SRAM
#if defined(MACB_TX_SRAM)
#define MACB_TX_RING_SIZE 2
#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE)
#else
#define MACB_TX_RING_SIZE 16
#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE)
#endif
#define MACB_RX_BUFFER_SIZE (4096*4)
#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE)
#define TX_RING_GAP(macb) \
(MACB_TX_RING_SIZE - (macb)->tx_pending)
#define TX_BUFFS_AVAIL(macb) \
(((macb)->tx_tail <= (macb)->tx_head) ? \
(macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \
(macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb))
#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1))
#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1))
/* minimum number of free TX descriptors before waking up TX process */
#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4)
#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
| MACB_BIT(ISR_ROVR))
#define MACB_TX_TIMEOUT 1000
#define MACB_AUTONEG_TIMEOUT 5000000
#define MACB_LINK_TIMEOUT 500000
#define CONFIG_RMII
struct macb_dma_desc {
rt_uint32_t addr;
rt_uint32_t ctrl;
};
#define RXADDR_USED 0x00000001
#define RXADDR_WRAP 0x00000002
#define RXBUF_FRMLEN_MASK 0x00000fff
#define RXBUF_FRAME_START 0x00004000
#define RXBUF_FRAME_END 0x00008000
#define RXBUF_TYPEID_MATCH 0x00400000
#define RXBUF_ADDR4_MATCH 0x00800000
#define RXBUF_ADDR3_MATCH 0x01000000
#define RXBUF_ADDR2_MATCH 0x02000000
#define RXBUF_ADDR1_MATCH 0x04000000
#define RXBUF_BROADCAST 0x80000000
#define TXBUF_FRMLEN_MASK 0x000007ff
#define TXBUF_FRAME_END 0x00008000
#define TXBUF_NOCRC 0x00010000
#define TXBUF_EXHAUSTED 0x08000000
#define TXBUF_UNDERRUN 0x10000000
#define TXBUF_MAXRETRY 0x20000000
#define TXBUF_WRAP 0x40000000
#define TXBUF_USED 0x80000000
/* Duplex, half or full. */
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
#define MAX_ADDR_LEN 6
struct rt_macb_eth
{
/* inherit from ethernet device */
struct eth_device parent;
unsigned int regs;
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
unsigned int rx_pending;
unsigned int tx_pending;
void *rx_buffer;
void *tx_buffer;
struct macb_dma_desc *rx_ring;
struct macb_dma_desc *tx_ring;
unsigned long rx_buffer_dma;
unsigned long tx_buffer_dma;
unsigned long rx_ring_dma;
unsigned long tx_ring_dma;
unsigned int tx_stop;
/* interface address info. */
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
unsigned short phy_addr;
struct rt_semaphore mdio_bus_lock;
struct rt_semaphore tx_lock;
struct rt_semaphore rx_lock;
struct rt_semaphore tx_ack;
rt_uint32_t speed;
rt_uint32_t duplex;
rt_uint32_t link;
struct rt_timer timer;
};
static struct rt_macb_eth macb_device;
static void macb_tx(struct rt_macb_eth *macb);
static void udelay(rt_uint32_t us)
{
rt_uint32_t len;
for (;us > 0; us --)
for (len = 0; len < 10; len++ );
}
static void rt_macb_isr(int irq, void *param)
{
struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
rt_device_t dev = &(macb->parent.parent);
rt_uint32_t status, rsr, tsr;
status = macb_readl(macb, ISR);
while (status) {
if (status & MACB_RX_INT_FLAGS)
{
rsr = macb_readl(macb, RSR);
macb_writel(macb, RSR, rsr);
/* a frame has been received */
eth_device_ready(&(macb_device.parent));
}
if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
MACB_BIT(ISR_RLE)))
{
macb_tx(macb);
}
/*
* Link change detection isn't possible with RMII, so we'll
* add that if/when we get our hands on a full-blown MII PHY.
*/
if (status & MACB_BIT(HRESP))
{
/*
* TODO: Reset the hardware, and maybe move the printk
* to a lower-priority context as well (work queue?)
*/
rt_kprintf("%s: DMA bus error: HRESP not OK\n",
dev->parent.name);
}
status = macb_readl(macb, ISR);
}
}
static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 1)
| MACB_BF(PHYA, macb->phy_addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2)
| MACB_BF(DATA, value));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
rt_sem_release(&macb->mdio_bus_lock);
}
static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER);
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 2)
| MACB_BF(PHYA, macb->phy_addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
frame = macb_readl(macb, MAN);
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
rt_sem_release(&macb->mdio_bus_lock);
return MACB_BFEXT(DATA, frame);
}
static void macb_phy_reset(rt_device_t dev)
{
int i;
rt_uint16_t status, adv;
struct rt_macb_eth *macb = dev->user_data;;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
macb_mdio_write(macb, MII_ADVERTISE, adv);
rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++)
{
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
}
if (status & BMSR_ANEGCOMPLETE)
rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
else
rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
dev->parent.name, status);
}
static int macb_phy_init(rt_device_t dev)
{
struct rt_macb_eth *macb = dev->user_data;
rt_uint32_t ncfgr;
rt_uint16_t phy_id, status, adv, lpa;
int media, speed, duplex;
int i;
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff)
{
rt_kprintf("%s: No PHY present\n", dev->parent.name);
return 0;
}
status = macb_mdio_read(macb, MII_BMSR);
if (!(status & BMSR_LSTATUS))
{
/* Try to re-negotiate if we don't have link already. */
macb_phy_reset(dev);
for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++)
{
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS))
{
rt_kprintf("%s: link down (status: 0x%04x)\n",
dev->parent.name, status);
return 0;
}
else
{
adv = macb_mdio_read(macb, MII_ADVERTISE);
lpa = macb_mdio_read(macb, MII_LPA);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
dev->parent.name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
ncfgr = macb_readl(macb, NCFGR);
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
if (speed)
ncfgr |= MACB_BIT(SPD);
if (duplex)
ncfgr |= MACB_BIT(FD);
macb_writel(macb, NCFGR, ncfgr);
return 1;
}
}
void macb_update_link(void *param)
{
struct rt_macb_eth *macb = (struct rt_macb_eth *)param;
rt_device_t dev = &macb->parent.parent;
int status, status_change = 0;
rt_uint32_t link;
rt_uint32_t media;
rt_uint16_t adv, lpa;
/* Do a fake read */
status = macb_mdio_read(macb, MII_BMSR);
if (status < 0)
return;
/* Read link and autonegotiation status */
status = macb_mdio_read(macb, MII_BMSR);
if (status < 0)
return;
if ((status & BMSR_LSTATUS) == 0)
link = 0;
else
link = 1;
if (link != macb->link)
{
macb->link = link;
status_change = 1;
}
if (status_change)
{
if (macb->link)
{
adv = macb_mdio_read(macb, MII_ADVERTISE);
lpa = macb_mdio_read(macb, MII_LPA);
media = mii_nway_result(lpa & adv);
macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 100 : 10);
macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
dev->parent.name, macb->speed,
DUPLEX_FULL == macb->duplex ? "Full":"Half");
eth_device_linkchange(&macb->parent, RT_TRUE);
}
else
{
rt_kprintf("%s: link down\n", dev->parent.name);
eth_device_linkchange(&macb->parent, RT_FALSE);
}
}
}
/* RT-Thread Device Interface */
/* initialize the interface */
static rt_err_t rt_macb_init(rt_device_t dev)
{
struct rt_macb_eth *macb = dev->user_data;
unsigned long paddr;
rt_uint32_t hwaddr_bottom;
rt_uint16_t hwaddr_top;
int i;
/*
* macb_halt should have been called at some point before now,
* so we'll assume the controller is idle.
*/
/* initialize DMA descriptors */
paddr = macb->rx_buffer_dma;
for (i = 0; i < MACB_RX_RING_SIZE; i++)
{
if (i == (MACB_RX_RING_SIZE - 1))
paddr |= RXADDR_WRAP;
macb->rx_ring[i].addr = paddr;
macb->rx_ring[i].ctrl = 0;
paddr += 128;
}
paddr = macb->tx_buffer_dma;
for (i = 0; i < MACB_TX_RING_SIZE; i++)
{
macb->tx_ring[i].addr = paddr;
if (i == (MACB_TX_RING_SIZE - 1))
macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
else
macb->tx_ring[i].ctrl = TXBUF_USED;
paddr += 1536;
}
macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
/* set hardware address */
hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr));
macb_writel(macb, SA1B, hwaddr_bottom);
hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4)));
macb_writel(macb, SA1T, hwaddr_top);
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#endif /* CONFIG_RMII */
if (!macb_phy_init(dev))
return -RT_ERROR;
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE));
/* Enable interrupts */
macb_writel(macb, IER, (MACB_BIT(RCOMP)
| MACB_BIT(RXUBR)
| MACB_BIT(ISR_TUND)
| MACB_BIT(ISR_RLE)
| MACB_BIT(TXERR)
| MACB_BIT(TCOMP)
| MACB_BIT(ISR_ROVR)
| MACB_BIT(HRESP)));
/* instal interrupt */
rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr,
(void *)macb, "emac");
rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC);
rt_timer_init(&macb->timer, "link_timer",
macb_update_link,
(void *)macb,
RT_TICK_PER_SECOND,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&macb->timer);
return RT_EOK;
}
static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag)
{
return RT_EOK;
}
static rt_err_t rt_macb_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args)
{
switch(cmd)
{
case NIOCTL_GADDR:
/* get mac address */
if(args) rt_memcpy(args, macb_device.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
static void macb_tx(struct rt_macb_eth *macb)
{
unsigned int tail;
unsigned int head;
rt_uint32_t status;
status = macb_readl(macb, TSR);
macb_writel(macb, TSR, status);
/*rt_kprintf("macb_tx status = %02lx\n",
(unsigned long)status);*/
if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE)))
{
int i;
rt_kprintf("%s: TX %s, resetting buffers\n",
macb->parent.parent.parent.name, status & MACB_BIT(UND) ?
"underrun" : "retry limit exceeded");
/* Transfer ongoing, disable transmitter, to avoid confusion */
if (status & MACB_BIT(TGO))
macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE));
head = macb->tx_head;
/*Mark all the buffer as used to avoid sending a lost buffer*/
for (i = 0; i < MACB_TX_RING_SIZE; i++)
macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
/* free transmit buffer in upper layer*/
macb->tx_head = macb->tx_tail = 0;
/* Enable the transmitter again */
if (status & MACB_BIT(TGO))
macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE));
}
if (!(status & MACB_BIT(COMP)))
/*
* This may happen when a buffer becomes complete
* between reading the ISR and scanning the
* descriptors. Nothing to worry about.
*/
return;
head = macb->tx_head;
for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail))
{
rt_uint32_t bufstat;
bufstat = macb->tx_ring[tail].ctrl;
if (!(bufstat & MACB_BIT(TX_USED)))
break;
}
macb->tx_tail = tail;
if ((macb->tx_stop == 1) &&
TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH)
rt_sem_release(&macb->tx_ack);
}
/* ethernet device interface */
/* transmit packet. */
rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
{
unsigned long ctrl;
struct pbuf* q;
rt_uint8_t* bufptr;
rt_uint32_t mapping;
struct rt_macb_eth *macb = dev->user_data;
unsigned int tx_head = macb->tx_head;
rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER);
if (TX_BUFFS_AVAIL(macb) < 1)
{
rt_sem_release(&macb->tx_lock);
rt_kprintf("Tx Ring full!\n");
rt_kprintf("tx_head = %u, tx_tail = %u\n",
macb->tx_head, macb->tx_tail);
return -RT_ERROR;
}
macb->tx_stop = 0;
ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
ctrl |= TXBUF_FRAME_END;
if (tx_head == (MACB_TX_RING_SIZE - 1))
{
ctrl |= TXBUF_WRAP;
}
#if defined(MACB_TX_SRAM)
bufptr = macb->tx_buffer + tx_head * 1536;
#else
mapping = (unsigned long)macb->tx_buffer + tx_head * 1536;
bufptr = (rt_uint8_t *)mapping;
#endif
for (q = p; q != NULL; q = q->next)
{
memcpy(bufptr, q->payload, q->len);
bufptr += q->len;
}
#if !defined(MACB_TX_SRAM)
EMAC_CACHE_WRITEBACK(mapping, p->tot_len);
#endif
macb->tx_ring[tx_head].ctrl = ctrl;
BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
tx_head = NEXT_TX(tx_head);
macb->tx_head = tx_head;
macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART));
if (TX_BUFFS_AVAIL(macb) < 1)
{
macb->tx_stop = 1;
rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER);
}
rt_sem_release(&macb->tx_lock);
return RT_EOK;
}
static void reclaim_rx_buffers(struct rt_macb_eth *macb,
unsigned int new_tail)
{
unsigned int i;
i = macb->rx_tail;
while (i > new_tail)
{
macb->rx_ring[i].addr &= ~RXADDR_USED;
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail)
{
macb->rx_ring[i].addr &= ~RXADDR_USED;
i++;
}
macb->rx_tail = new_tail;
}
/* reception packet. */
struct pbuf *rt_macb_rx(rt_device_t dev)
{
struct rt_macb_eth *macb = dev->user_data;
struct pbuf* p = RT_NULL;
rt_uint32_t len;
unsigned int rx_tail = macb->rx_tail;
void *buffer;
int wrapped = 0;
rt_uint32_t status;
rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER);
for (;;)
{
if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
break;
status = macb->rx_ring[rx_tail].ctrl;
if (status & RXBUF_FRAME_START)
{
if (rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, rx_tail);
wrapped = 0;
}
if (status & RXBUF_FRAME_END)
{
buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail);
len = status & RXBUF_FRMLEN_MASK;
p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM);
if (!p)
{
rt_kprintf("alloc pbuf failed\n");
break;
}
if (wrapped)
{
unsigned int headlen, taillen;
headlen = 128 * (MACB_RX_RING_SIZE
- macb->rx_tail);
taillen = len - headlen;
EMAC_CACHE_INVALIDATE(buffer, headlen);
EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
memcpy((void *)p->payload, buffer, headlen);
memcpy((void *)((unsigned int)p->payload + headlen),
macb->rx_buffer, taillen);
}
else
{
EMAC_CACHE_INVALIDATE(buffer, len);
memcpy((void *)p->payload, buffer, p->len);
}
if (++rx_tail >= MACB_RX_RING_SIZE)
rx_tail = 0;
reclaim_rx_buffers(macb, rx_tail);
break;
}
else
{
if (++rx_tail >= MACB_RX_RING_SIZE)
{
wrapped = 1;
rx_tail = 0;
}
}
}
rt_sem_release(&macb->rx_lock);
return p;
}
void macb_gpio_init()
{
/* Pins used for MII and RMII */
AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20);
AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20);
#ifndef GONFIG_RMII
AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29);
AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29);
#endif
}
rt_err_t macb_initialize()
{
struct rt_macb_eth *macb = &macb_device;
unsigned long macb_hz;
rt_uint32_t ncfgr;
#if defined(MACB_TX_SRAM)
macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE;
macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE;
macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES;
macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES;
#else
macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
if (macb->tx_ring == RT_NULL)
goto err1;
EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring);
macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring);
macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE);
if (macb->tx_buffer == RT_NULL)
goto err2;
macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer);
#endif
macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
if (macb->rx_ring == RT_NULL)
goto err3;
EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring);
macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring);
macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE);
if (macb->rx_buffer == RT_NULL)
goto err4;
macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer);
macb->tx_pending = DEF_TX_RING_PENDING;
macb->regs = AT91SAM9260_BASE_EMAC;
macb->phy_addr = 0x00;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
macb_hz = clk_get_rate(clk_get("mck"));
if (macb_hz < 20000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
else
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
macb_writel(macb, NCFGR, ncfgr);
macb->link = 0;
return RT_EOK;
err4:
rt_free(macb->rx_ring);
macb->rx_ring = RT_NULL;
err3:
#if !defined(MACB_TX_SRAM)
rt_free(macb->tx_buffer);
macb->tx_buffer = RT_NULL;
err2:
rt_free(macb->tx_ring);
macb->tx_ring = RT_NULL;
err1:
#endif
return -RT_ENOMEM;
}
int rt_hw_macb_init(void)
{
rt_err_t ret;
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock
macb_gpio_init();
rt_memset(&macb_device, 0, sizeof(macb_device));
ret = macb_initialize();
if (ret != RT_EOK)
{
rt_kprintf("AT91 EMAC initialized failed\n");
return -1;
}
rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
macb_device.dev_addr[0] = 0x00;
macb_device.dev_addr[1] = 0x60;
macb_device.dev_addr[2] = 0x6E;
macb_device.dev_addr[3] = 0x11;
macb_device.dev_addr[4] = 0x22;
macb_device.dev_addr[5] = 0x33;
macb_device.parent.parent.init = rt_macb_init;
macb_device.parent.parent.open = rt_macb_open;
macb_device.parent.parent.close = rt_macb_close;
macb_device.parent.parent.read = rt_macb_read;
macb_device.parent.parent.write = rt_macb_write;
macb_device.parent.parent.control = rt_macb_control;
macb_device.parent.parent.user_data = &macb_device;
macb_device.parent.eth_rx = rt_macb_rx;
macb_device.parent.eth_tx = rt_macb_tx;
rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO);
eth_device_init(&(macb_device.parent), "e0");
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_macb_init);

346
bsp/at91sam9g45/drivers/macb.h
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@ -1,346 +0,0 @@
/*
* File : macb.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-03-18 weety first version
*/
#ifndef _MACB_H
#define _MACB_H
#include <mii.h>
/* MACB register offsets */
#define MACB_NCR 0x0000
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
#define MACB_RSR 0x0020
#define MACB_ISR 0x0024
#define MACB_IER 0x0028
#define MACB_IDR 0x002c
#define MACB_IMR 0x0030
#define MACB_MAN 0x0034
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
#define MACB_SCF 0x0044
#define MACB_MCF 0x0048
#define MACB_FRO 0x004c
#define MACB_FCSE 0x0050
#define MACB_ALE 0x0054
#define MACB_DTF 0x0058
#define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064
#define MACB_CSE 0x0068
#define MACB_RRE 0x006c
#define MACB_ROVR 0x0070
#define MACB_RSE 0x0074
#define MACB_ELE 0x0078
#define MACB_RJA 0x007c
#define MACB_USF 0x0080
#define MACB_STE 0x0084
#define MACB_RLE 0x0088
#define MACB_TPF 0x008c
#define MACB_HRB 0x0090
#define MACB_HRT 0x0094
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1
#define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2
#define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3
#define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4
#define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5
#define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6
#define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7
#define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8
#define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9
#define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11
#define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
#define MACB_SPD_OFFSET 0
#define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1
#define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2
#define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3
#define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4
#define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5
#define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6
#define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8
#define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12
#define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13
#define MACB_PAE_SIZE 1
#define MACB_RBOF_OFFSET 14
#define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0
#define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1
#define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3
#define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4
#define MACB_BEX_SIZE 1
#define MACB_COMP_OFFSET 5
#define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6
#define MACB_UND_SIZE 1
/* Bitfields in RSR */
#define MACB_BNA_OFFSET 0
#define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1
#define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2
#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
#define MACB_MFD_OFFSET 0
#define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1
#define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3
#define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4
#define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5
#define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6
#define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7
#define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9
#define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10
#define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11
#define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12
#define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
#define MACB_DATA_OFFSET 0
#define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16
#define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23
#define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28
#define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1
#define MACB_EAM_SIZE 1
#define MACB_TX_PAUSE_OFFSET 2
#define MACB_TX_PAUSE_SIZE 1
#define MACB_TX_PAUSE_ZERO_OFFSET 3
#define MACB_TX_PAUSE_ZERO_SIZE 1
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
/* Bitfields in WOL */
#define MACB_IP_OFFSET 0
#define MACB_IP_SIZE 16
#define MACB_MAG_OFFSET 16
#define MACB_MAG_SIZE 1
#define MACB_ARP_OFFSET 17
#define MACB_ARP_SIZE 1
#define MACB_SA1_OFFSET 18
#define MACB_SA1_SIZE 1
#define MACB_WOL_MTI_OFFSET 19
#define MACB_WOL_MTI_SIZE 1
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
#define MACB_CLK_DIV32 2
#define MACB_CLK_DIV64 3
/* Constants for MAN register */
#define MACB_MAN_SOF 1
#define MACB_MAN_WRITE 1
#define MACB_MAN_READ 2
#define MACB_MAN_CODE 2
/* Bit manipulation macros */
#define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET)
#define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET)
#define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1))
#define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \
| MACB_BF(name,value))
/* Register access macros */
#define macb_readl(port,reg) \
readl((port)->regs + MACB_##reg)
#define macb_writel(port,reg,value) \
writel((value), (port)->regs + MACB_##reg)
struct dma_desc {
rt_uint32_t addr;
rt_uint32_t ctrl;
};
/* DMA descriptor bitfields */
#define MACB_RX_USED_OFFSET 0
#define MACB_RX_USED_SIZE 1
#define MACB_RX_WRAP_OFFSET 1
#define MACB_RX_WRAP_SIZE 1
#define MACB_RX_WADDR_OFFSET 2
#define MACB_RX_WADDR_SIZE 30
#define MACB_RX_FRMLEN_OFFSET 0
#define MACB_RX_FRMLEN_SIZE 12
#define MACB_RX_OFFSET_OFFSET 12
#define MACB_RX_OFFSET_SIZE 2
#define MACB_RX_SOF_OFFSET 14
#define MACB_RX_SOF_SIZE 1
#define MACB_RX_EOF_OFFSET 15
#define MACB_RX_EOF_SIZE 1
#define MACB_RX_CFI_OFFSET 16
#define MACB_RX_CFI_SIZE 1
#define MACB_RX_VLAN_PRI_OFFSET 17
#define MACB_RX_VLAN_PRI_SIZE 3
#define MACB_RX_PRI_TAG_OFFSET 20
#define MACB_RX_PRI_TAG_SIZE 1
#define MACB_RX_VLAN_TAG_OFFSET 21
#define MACB_RX_VLAN_TAG_SIZE 1
#define MACB_RX_TYPEID_MATCH_OFFSET 22
#define MACB_RX_TYPEID_MATCH_SIZE 1
#define MACB_RX_SA4_MATCH_OFFSET 23
#define MACB_RX_SA4_MATCH_SIZE 1
#define MACB_RX_SA3_MATCH_OFFSET 24
#define MACB_RX_SA3_MATCH_SIZE 1
#define MACB_RX_SA2_MATCH_OFFSET 25
#define MACB_RX_SA2_MATCH_SIZE 1
#define MACB_RX_SA1_MATCH_OFFSET 26
#define MACB_RX_SA1_MATCH_SIZE 1
#define MACB_RX_EXT_MATCH_OFFSET 28
#define MACB_RX_EXT_MATCH_SIZE 1
#define MACB_RX_UHASH_MATCH_OFFSET 29
#define MACB_RX_UHASH_MATCH_SIZE 1
#define MACB_RX_MHASH_MATCH_OFFSET 30
#define MACB_RX_MHASH_MATCH_SIZE 1
#define MACB_RX_BROADCAST_OFFSET 31
#define MACB_RX_BROADCAST_SIZE 1
#define MACB_TX_FRMLEN_OFFSET 0
#define MACB_TX_FRMLEN_SIZE 11
#define MACB_TX_LAST_OFFSET 15
#define MACB_TX_LAST_SIZE 1
#define MACB_TX_NOCRC_OFFSET 16
#define MACB_TX_NOCRC_SIZE 1
#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
#define MACB_TX_BUF_EXHAUSTED_SIZE 1
#define MACB_TX_UNDERRUN_OFFSET 28
#define MACB_TX_UNDERRUN_SIZE 1
#define MACB_TX_ERROR_OFFSET 29
#define MACB_TX_ERROR_SIZE 1
#define MACB_TX_WRAP_OFFSET 30
#define MACB_TX_WRAP_SIZE 1
#define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1
extern int rt_hw_macb_init();
#endif /* _MACB_H */

191
bsp/at91sam9g45/drivers/mii.h
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@ -1,191 +0,0 @@
/*
* File : mii.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-03-18 weety first version
*/
#ifndef __MII_H__
#define __MII_H__
/* Generic MII registers. */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
/* Flow control flags */
#define FLOW_CTRL_TX 0x01
#define FLOW_CTRL_RX 0x02
/**
* mii_nway_result
* @negotiated: value of MII ANAR and'd with ANLPAR
*
* Given a set of MII abilities, check each bit and returns the
* currently supported media, in the priority order defined by
* IEEE 802.3u. We use LPA_xxx constants but note this is not the
* value of LPA solely, as described above.
*
* The one exception to IEEE 802.3u is that 100baseT4 is placed
* between 100T-full and 100T-half. If your phy does not support
* 100T4 this is fine. If your phy places 100T4 elsewhere in the
* priority order, you will need to roll your own function.
*/
rt_inline unsigned int mii_nway_result (unsigned int negotiated)
{
unsigned int ret;
if (negotiated & LPA_100FULL)
ret = LPA_100FULL;
else if (negotiated & LPA_100BASE4)
ret = LPA_100BASE4;
else if (negotiated & LPA_100HALF)
ret = LPA_100HALF;
else if (negotiated & LPA_10FULL)
ret = LPA_10FULL;
else
ret = LPA_10HALF;
return ret;
}
#endif /* __MII_H__ */

398
bsp/at91sam9g45/drivers/usart.c
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@ -1,398 +0,0 @@
/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
* 2013-07-21 weety using serial component
*/
#include <rtthread.h>
#include <rthw.h>
#include <at91sam9g45.h>
#include <rtdevice.h>
struct at91_uart {
AT91S_USART *port;
int irq;
};
/**
* This function will handle serial port interrupt
*/
void rt_at91_usart_handler(int vector, void *param)
{
int status;
struct at91_uart *uart;
rt_device_t dev = (rt_device_t)param;
uart = (struct at91_uart *)dev->user_data;
status = uart->port->US_CSR;
if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */
{
return;
}
rt_interrupt_enter();
rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
/**
* UART device in RT-Thread
*/
static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
int div;
int mode = 0;
struct at91_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct at91_uart *)serial->parent.user_data;
uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
AT91C_US_RXDIS | AT91C_US_TXDIS;
mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
AT91C_US_CHMODE_NORMAL;
switch (cfg->data_bits)
{
case DATA_BITS_8:
mode |= AT91C_US_CHRL_8_BITS;
break;
case DATA_BITS_7:
mode |= AT91C_US_CHRL_7_BITS;
break;
case DATA_BITS_6:
mode |= AT91C_US_CHRL_6_BITS;
break;
case DATA_BITS_5:
mode |= AT91C_US_CHRL_5_BITS;
break;
default:
mode |= AT91C_US_CHRL_8_BITS;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_2:
mode |= AT91C_US_NBSTOP_2_BIT;
break;
case STOP_BITS_1:
default:
mode |= AT91C_US_NBSTOP_1_BIT;
break;
}
switch (cfg->parity)
{
case PARITY_ODD:
mode |= AT91C_US_PAR_ODD;
break;
case PARITY_EVEN:
mode |= AT91C_US_PAR_EVEN;
break;
case PARITY_NONE:
default:
mode |= AT91C_US_PAR_NONE;
break;
}
uart->port->US_MR = mode;
/* Assume OVER is cleared and fractional baudrate generator is disabled */
div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
uart->port->US_BRGR = div;
uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
uart->port->US_IER = AT91C_US_RXRDY;
return RT_EOK;
}
static rt_err_t at91_usart_control(struct rt_serial_device *serial,
int cmd, void *arg)
{
struct at91_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct at91_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
rt_hw_interrupt_mask(uart->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
rt_hw_interrupt_umask(uart->irq);
break;
}
return RT_EOK;
}
static int at91_usart_putc(struct rt_serial_device *serial, char c)
{
//rt_uint32_t level;
struct at91_uart *uart = serial->parent.user_data;
while (!(uart->port->US_CSR & AT91C_US_TXRDY));
uart->port->US_THR = c;
return 1;
}
static int at91_usart_getc(struct rt_serial_device *serial)
{
int result;
struct at91_uart *uart = serial->parent.user_data;
if (uart->port->US_CSR & AT91C_US_RXRDY)
{
result = uart->port->US_RHR & 0xff;
}
else
{
result = -1;
}
return result;
}
static const struct rt_uart_ops at91_usart_ops =
{
at91_usart_configure,
at91_usart_control,
at91_usart_putc,
at91_usart_getc,
};
#if defined(RT_USING_DBGU)
static struct rt_serial_device serial_dbgu;
struct at91_uart dbgu = {
(AT91PS_USART)AT91C_BASE_DBGU,
AT91C_ID_SYS
};
#endif
#if defined(RT_USING_UART0)
static struct rt_serial_device serial0;
struct at91_uart uart0 = {
AT91C_BASE_US0,
AT91C_ID_US0
};
#endif
#if defined(RT_USING_UART1)
static struct rt_serial_device serial1;
struct at91_uart uart1 = {
AT91C_BASE_US1,
AT91C_ID_US1
};
#endif
#if defined(RT_USING_UART2)
static struct rt_serial_device serial2;
struct at91_uart uart2 = {
AT91C_BASE_US2,
AT91C_ID_US2
};
#endif
#if defined(RT_USING_UART3)
static struct rt_serial_device serial3;
struct at91_uart uart3 = {
AT91C_BASE_US3,
AT91C_ID_US3
};
#endif
void at91_usart_gpio_init(void)
{
#ifdef RT_USING_DBGU
#define DRXD 12 // DBGU rx as Peripheral A on PB12
#define DTXD 13 // DBGU tx as Peripheral A on PB13
AT91C_BASE_PIOB->PIO_IDR, (1<<DRXD)|(1<<DTXD); // Disables the Input Change Interrupt on the I/O line
AT91C_BASE_PIOB->PIO_PPUDR, (1<<DRXD)|(1<<DTXD); // Disables the pull up resistor on the I/O line
AT91C_BASE_PIOB->PIO_ASR, (1<<DRXD)|(1<<DTXD); // Assigns the I/O line to the Peripheral A function
AT91C_BASE_PIOB->PIO_PDR, (1<<DRXD)|(1<<DTXD); // enables peripheral control of the pin
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_SYS;
#endif
#ifdef RT_USING_UART0
#define RXD0 18 // UART0 rx as Peripheral A on PB18
#define TXD0 19 // UART0 tx as Peripheral A on PB19
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US0;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD0)|(1<<TXD0);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD0);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD0);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD0)|(1<<TXD0);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD0)|(1<<TXD0);
#endif
#ifdef RT_USING_UART1
#define TXD1 4 // UART1 tx as Peripheral A on PB4
#define RXD1 5 // UART1 rx as Peripheral A on PB5
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US1;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD1)|(1<<TXD1);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD1);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD1);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD1)|(1<<TXD1);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD1)|(1<<TXD1);
#endif
#ifdef RT_USING_UART2
#define TXD2 6 // UART2 tx as Peripheral A on PB6
#define RXD2 7 // UART2 rx as Peripheral A on PB7
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US2;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD2)|(1<<TXD2);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD2);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD2);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD2)|(1<<TXD2);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD2)|(1<<TXD2);
#endif
#ifdef RT_USING_UART3
#define TXD3 8 // UART3 tx as Peripheral A on PB8
#define RXD3 9 // UART3 rx as Peripheral A on PB9
AT91C_BASE_PMC->PMC_PCER, 1<<AT91C_ID_US3;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD3)|(1<<TXD3);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD3);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD3);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD3)|(1<<TXD3);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD3)|(1<<TXD3);
#endif
}
/**
* This function will handle init uart
*/
int rt_hw_uart_init(void)
{
at91_usart_gpio_init();
#if defined(RT_USING_DBGU)
serial_dbgu.ops = &at91_usart_ops;
serial_dbgu.config.baud_rate = BAUD_RATE_115200;
serial_dbgu.config.bit_order = BIT_ORDER_LSB;
serial_dbgu.config.data_bits = DATA_BITS_8;
serial_dbgu.config.parity = PARITY_NONE;
serial_dbgu.config.stop_bits = STOP_BITS_1;
serial_dbgu.config.invert = NRZ_NORMAL;
serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial_dbgu, "dbgu",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&dbgu);
#endif
#if defined(RT_USING_UART0)
serial0.ops = &at91_usart_ops;
serial0.config.baud_rate = BAUD_RATE_115200;
serial0.config.bit_order = BIT_ORDER_LSB;
serial0.config.data_bits = DATA_BITS_8;
serial0.config.parity = PARITY_NONE;
serial0.config.stop_bits = STOP_BITS_1;
serial0.config.invert = NRZ_NORMAL;
serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
(void *)&(serial0.parent), "UART0");
rt_hw_interrupt_umask(uart0.irq);
#endif
#if defined(RT_USING_UART1)
serial1.ops = &at91_usart_ops;
serial1.config.baud_rate = BAUD_RATE_115200;
serial1.config.bit_order = BIT_ORDER_LSB;
serial1.config.data_bits = DATA_BITS_8;
serial1.config.parity = PARITY_NONE;
serial1.config.stop_bits = STOP_BITS_1;
serial1.config.invert = NRZ_NORMAL;
serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart1);
rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
(void *)&(serial1.parent), "UART1");
rt_hw_interrupt_umask(uart1.irq);
#endif
#if defined(RT_USING_UART2)
serial2.ops = &at91_usart_ops;
serial2.config.baud_rate = BAUD_RATE_115200;
serial2.config.bit_order = BIT_ORDER_LSB;
serial2.config.data_bits = DATA_BITS_8;
serial2.config.parity = PARITY_NONE;
serial2.config.stop_bits = STOP_BITS_1;
serial2.config.invert = NRZ_NORMAL;
serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart2);
rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
(void *)&(serial2.parent), "UART2");
rt_hw_interrupt_umask(uart2.irq);
#endif
#if defined(RT_USING_UART3)
serial3.ops = &at91_usart_ops;
serial3.config.baud_rate = BAUD_RATE_115200;
serial3.config.bit_order = BIT_ORDER_LSB;
serial3.config.data_bits = DATA_BITS_8;
serial3.config.parity = PARITY_NONE;
serial3.config.stop_bits = STOP_BITS_1;
serial3.config.invert = NRZ_NORMAL;
serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart3);
rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
(void *)&(serial3.parent), "UART3");
rt_hw_interrupt_umask(uart3.irq);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
#ifdef RT_USING_DBGU
void rt_dbgu_isr(void)
{
rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
}
#endif

55
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf
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@ -1,55 +0,0 @@
//------------------------------------------------------------------------------
// Linker scatter for running in external SDRAM on the AT91SAM9260
//------------------------------------------------------------------------------
//
// Define a memory region that covers the entire 4 GB addressible space of the
// processor.
//
define memory mem with size = 4G;
//
// Define a region for the on-chip flash.
//
define region FLASH = mem:[from 0x70000000 to 0x707FFFFF];
//
// Define a region for the on-chip SRAM.
//
define region SRAM = mem:[from 0x70800000 to 0x73FFFFFF];
//
// Indicate that the read/write values should be initialized by copying from
// flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone. This includes the
// stack, which if initialized will destroy the return address from the
// initialization code, causing the processor to branch to zero and fault.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the RAM vector table at the start of SRAM.
//
place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite};
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };

98
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld
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@ -1,98 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(start)
SECTIONS
{
. = 0x70000000;
. = ALIGN(4);
.text :
{
*(.init)
*(.text)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
}
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start__ = .;
.bss : { *(.bss)}
__bss_end__ = .;
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
}

40
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat
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@ -1,40 +0,0 @@
;*------------------------------------------------------------------------------
;* Linker scatter for running in external SDRAM on the AT91SAM9260
;*----------------------------------------------------------------------------*/
Load_region 0x70000000 0x00800000
{
Fixed_region 0x70000000
{
* (RESET +First)
.ANY (+RO +RW)
}
ARM_LIB_HEAP +0 EMPTY 0x1000
{
}
ARM_LIB_STACK +0 EMPTY 0x1000
{
}
; Application ZI data (.bss)
ER_ZI +0
{
* (+ZI)
}
;Relocate_region 0x200000 0x1000
;{
; *.o (VECTOR, +First)
;}
;ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
;{
;}
;ARM_LIB_STACK 0x22000000 EMPTY -0x1000
;{
;}
}

26
bsp/at91sam9g45/platform/SConscript
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@ -1,26 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
# The set of source files associated with this SConscript file.
if rtconfig.PLATFORM == 'armcc':
src = Glob('*.c') + Glob('*_rvds.S')
if rtconfig.PLATFORM == 'gcc':
src = Glob('*.c') + Glob('*_gcc.S') + Glob('*_init.S')
if rtconfig.PLATFORM == 'iar':
src = Glob('*.c') + Glob('*_iar.S')
if rtconfig.PLATFORM == 'cl':
src = Glob('*.c')
if rtconfig.PLATFORM == 'mingw':
src = Glob('*.c')
group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

7213
bsp/at91sam9g45/platform/at91sam9g45.h
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208
bsp/at91sam9g45/platform/gpio.h
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@ -1,208 +0,0 @@
/*
* File : gpio.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __GPIO_H__
#define __GPIO_H__
#include <rtthread.h>
#define PIN_BASE AIC_IRQS
#define MAX_GPIO_BANKS 5
#define PIN_IRQS (MAX_GPIO_BANKS*32)
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2)
#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3)
#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4)
#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5)
#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6)
#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7)
#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8)
#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9)
#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10)
#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11)
#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12)
#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13)
#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14)
#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15)
#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16)
#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17)
#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18)
#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19)
#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20)
#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21)
#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22)
#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23)
#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24)
#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25)
#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26)
#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27)
#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28)
#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29)
#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30)
#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31)
#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0)
#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1)
#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2)
#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3)
#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4)
#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5)
#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6)
#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7)
#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8)
#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9)
#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10)
#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11)
#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12)
#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13)
#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14)
#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15)
#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16)
#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17)
#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18)
#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19)
#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20)
#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21)
#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22)
#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23)
#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24)
#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25)
#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26)
#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27)
#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28)
#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29)
#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30)
#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31)
#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0)
#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1)
#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2)
#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3)
#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4)
#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5)
#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6)
#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7)
#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8)
#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9)
#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10)
#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11)
#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12)
#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13)
#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14)
#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15)
#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16)
#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17)
#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18)
#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19)
#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20)
#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21)
#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22)
#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23)
#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24)
#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25)
#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26)
#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27)
#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28)
#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29)
#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30)
#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31)
#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0)
#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1)
#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2)
#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3)
#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4)
#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5)
#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6)
#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7)
#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8)
#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9)
#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10)
#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11)
#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12)
#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13)
#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14)
#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15)
#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16)
#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17)
#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18)
#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19)
#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20)
#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21)
#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22)
#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23)
#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24)
#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25)
#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26)
#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27)
#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28)
#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29)
#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30)
#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31)
#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0)
#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1)
#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2)
#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3)
#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4)
#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5)
#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6)
#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7)
#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8)
#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9)
#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10)
#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11)
#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12)
#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13)
#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14)
#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15)
#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16)
#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17)
#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18)
#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19)
#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20)
#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21)
#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22)
#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23)
#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24)
#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25)
#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26)
#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27)
#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28)
#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29)
#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30)
#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31)
rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
{
return gpio;
}
#endif

453
bsp/at91sam9g45/platform/interrupt.c
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@ -1,453 +0,0 @@
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rthw.h>
#include "at91sam9g45.h"
#include "interrupt.h"
#define AIC_IRQS 32
#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
extern rt_uint32_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
rt_uint32_t at91_extern_irq;
#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static rt_uint32_t at91sam9g45_default_irq_priority[MAX_HANDLERS] = {
7, /* Advanced Interrupt Controller - FIQ */
7, /* System Controller Interrupt */
1, /* Parallel I/O Controller A, */
1, /* Parallel I/O Controller B */
1, /* Parallel I/O Controller C */
0, /* Parallel I/O Controller D/E */
5, /* True Random Number Generator */
5, /* USART 0 */
5, /* USART 1 */
0, /* USART 2 */
2, /* USART 3 */
6, /* High Speed Multimedia Card Interface 0 */
5, /* Two-Wire Interface 0 */
5, /* Two-Wire Interface 1 */
5, /* Serial Peripheral Interface */
0, /* Serial Peripheral Interface */
0, /* Synchronous Serial Controller 0 */
0, /* Synchronous Serial Controller 1 */
0, /* Timer Counter 0,1,2,3,4,5 */
0, /* Pulse Width Modulation Controller */
2, /* Touch Screen ADC Controller */
3, /* DMA Controller */
0, /* USB Host High Speed */
5, /* LCD Controller */
5, /* AC97 Controller */
5, /* Ethernet MAC */
0, /* Image Sensor Interface */
0, /* USB Device High Speed */
0, /* N/A */
0, /* High Speed Multimedia Card Interface 1 */
0, /* Reserved */
0, /* Advanced Interrupt Controller - IRQ */
};
/**
* @addtogroup AT91SAM9G45
*/
/*@{*/
void rt_hw_interrupt_mask(int irq);
void rt_hw_interrupt_umask(int irq);
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
return RT_NULL;
}
rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
{
rt_uint32_t isr, irq_n;
AT91PS_PIO pio;
void *parameter;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return RT_NULL;
}
irq_n = AIC_IRQS + 32*bank;
isr = readl(pio->PIO_ISR);
isr &= readl(pio->PIO_IMR);
while (isr)
{
if (isr & 1)
{
parameter = irq_desc[irq_n].param;
irq_desc[irq_n].handler(irq_n, parameter);
}
isr >>= 1;
irq_n++;
}
return RT_NULL;
}
unsigned int SpuriousCount = 0;
static void DefaultSpuriousHandler( void )
{
SpuriousCount++;
rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
return ;
}
static void DefaultFiqHandler(void)
{
rt_kprintf("Unhandled FIQ occured!!!\n");
while (1);
}
static void DefaultIrqHandler(void)
{
rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
while (1);
}
/*
* Initialize the AIC interrupt controller.
*/
void at91_aic_init(rt_uint32_t *priority)
{
rt_uint32_t i;
/*
* The IVR is used by macro get_irqnr_and_base to read and verify.
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
*/
AT91C_BASE_AIC->AIC_SVR[0] = (rt_uint32_t)DefaultFiqHandler;
for (i = 1; i < AIC_IRQS; i++) {
/* Put irq number in Source Vector Register: */
AT91C_BASE_AIC->AIC_SVR[i] = (rt_uint32_t)DefaultIrqHandler; // no-used
/* Active Low interrupt, with the specified priority */
AT91C_BASE_AIC->AIC_SMR[i] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | priority[i];
//AT91C_AIC_SRCTYPE_FALLING
}
/*
* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
*/
AT91C_BASE_AIC->AIC_SPU = (rt_uint32_t)DefaultSpuriousHandler;
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
for (i = 0; i < 8; i++)
AT91C_BASE_AIC->AIC_EOICR = 0;
/* No debugging in AIC: Debug (Protect) Control Register */
AT91C_BASE_AIC->AIC_DCR = 0;
/* Disable and clear all interrupts initially */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
}
static void at91_gpio_irq_init()
{
int i, idx;
char *name[] = {"PIOA", "PIOB", "PIOC", "PIODE"};
rt_uint32_t aic_pids[] = { AT91C_ID_PIOA, AT91C_ID_PIOB, AT91C_ID_PIOC, AT91C_ID_PIOD_E };
AT91C_BASE_PIOA->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOB->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOC->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOD->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOE->PIO_IDR = 0xffffffff;
for (i = 0; i < 4; i++)
{
idx = aic_pids[i];
irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
irq_desc[idx].counter = 0;
#endif
rt_hw_interrupt_umask(idx);
}
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
register rt_uint32_t idx;
rt_uint32_t *priority = at91sam9g45_default_irq_priority;
at91_extern_irq = (1UL << AT91C_ID_IRQ0);
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* init exceptions table */
for(idx=0; idx < MAX_HANDLERS; idx++)
{
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
irq_desc[idx].counter = 0;
#endif
}
at91_gpio_irq_init();
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
static void at91_gpio_irq_mask(int irq)
{
rt_uint32_t pin, bank;
AT91PS_PIO pio;
bank = (irq - AIC_IRQS)>>5;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return;
}
pin = 1 << ((irq - AIC_IRQS) & 31);
pio->PIO_IDR = pin;
}
/**
* This function will mask a interrupt.
* @param irq the interrupt number
*/
void rt_hw_interrupt_mask(int irq)
{
if (irq >= AIC_IRQS)
{
at91_gpio_irq_mask(irq);
}
else
{
/* Disable interrupt on AIC */
AT91C_BASE_AIC->AIC_IDCR = 1 << irq;
}
}
static void at91_gpio_irq_umask(int irq)
{
rt_uint32_t pin, bank;
AT91PS_PIO pio;
bank = (irq - AIC_IRQS)>>5;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return;
}
pin = 1 << ((irq - AIC_IRQS) & 31);
pio->PIO_IER = pin;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int irq)
{
if (irq >= AIC_IRQS)
{
at91_gpio_irq_umask(irq);
}
else
{
/* Enable interrupt on AIC */
AT91C_BASE_AIC->AIC_IECR = 1 << irq;
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param handler the interrupt service routine to be installed
* @param param the interrupt service function parameter
* @param name the interrupt name
* @return old handler
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = irq_desc[vector].handler;
if (handler != RT_NULL)
{
irq_desc[vector].handler = (rt_isr_handler_t)handler;
irq_desc[vector].param = param;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
irq_desc[vector].counter = 0;
#endif
}
}
return old_handler;
}
/*@}*/
/*
static int at91_aic_set_type(unsigned irq, unsigned type)
{
unsigned int smr, srctype;
switch (type) {
case AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL:
srctype = AT91C_AIC_SRCTYPE_HIGH;
break;
case AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE:
srctype = AT91C_AIC_SRCTYPE_RISING;
break;
case AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE:
// only supported on external interrupts
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
srctype = AT91C_AIC_SRCTYPE_LOW;
else
return -1;
break;
case AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED:
// only supported on external interrupts
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
srctype = AT91C_AIC_SRCTYPE_FALLING;
else
return -1;
break;
default:
return -1;
}
smr = readl(AT91C_AIC_SMR(irq)) & ~AT91C_AIC_SRCTYPE;
AT91C_BASE_AIC->AIC_SMR[irq] = smr | srctype;
return 0;
}
*/
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
{
//volatile rt_uint32_t irqstat;
rt_uint32_t id;
if (fiq_irq == INT_FIQ)
return 0;
//IRQ
/* AIC need this dummy read */
readl(AT91C_AIC_IVR);
/* clear pending register */
id = readl(AT91C_AIC_ISR);
return id;
}
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
{
/* new FIQ generation */
if (fiq_irq == INT_FIQ)
return;
/* new IRQ generation */
// EIOCR must be write any value after interrupt,
// or else can't response next interrupt
AT91C_BASE_AIC->AIC_EOICR = 0x0;
}
#ifdef RT_USING_FINSH
#ifdef RT_USING_INTERRUPT_INFO
void list_irq(void)
{
int irq;
rt_kprintf("number\tcount\tname\n");
for (irq = 0; irq < MAX_HANDLERS; irq++)
{
if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
{
rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
}
}
}
#include <finsh.h>
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
#ifdef FINSH_USING_MSH
int cmd_list_irq(int argc, char** argv)
{
list_irq();
return 0;
}
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
#endif
#endif
#endif

31
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/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#define INT_IRQ 0x00
#define INT_FIQ 0x01
#endif

39
bsp/at91sam9g45/platform/io.h
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/*
* File : io.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define readb(a) (*(volatile unsigned char *)(a))
#define readw(a) (*(volatile unsigned short *)(a))
#define readl(a) (*(volatile unsigned int *)(a))
#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
#endif

52
bsp/at91sam9g45/platform/irq.h
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/*
* File : irq.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __IRQ_H__
#define __IRQ_H__
#ifdef __cplusplus
extern "C" {
#endif
/*
* IRQ line status.
*
* Bits 0-7 are reserved
*
* IRQ types
*/
#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
#ifdef __cplusplus
}
#endif
#endif

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bsp/at91sam9g45/platform/reset.c
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/*
* File : reset.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
*/
#include <rthw.h>
#include <rtthread.h>
#include "at91sam9g45.h"
/**
* @addtogroup AT91SAM926X
*/
/*@{*/
void machine_reset(void)
{
AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST;
}
void machine_shutdown(void)
{
AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW;
}
#ifdef RT_USING_FINSH
#include <finsh.h>
FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
#ifdef FINSH_USING_MSH
int cmd_reset(int argc, char** argv)
{
rt_hw_cpu_reset();
return 0;
}
int cmd_shutdown(int argc, char** argv)
{
rt_hw_cpu_shutdown();
return 0;
}
FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);
FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.);
#endif
#endif
/*@}*/

63
bsp/at91sam9g45/platform/rt_low_level_init.c
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/*
* File : rt_low_level_init.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
/* write register a=address, v=value */
#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v))
/* Processor Reset */
#define AT91C_RSTC_PROCRST (1 << 0)
#define AT91C_RSTC_PERRST (1 << 2)
#define AT91C_RSTC_KEY (0xa5 << 24)
#define AT91C_MATRIX_BASE (0XFFFFEE00)
/* Master Remap Control Register */
#define AT91C_MATRIX_MRCR (AT91C_MATRIX_BASE + 0x100)
/* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */
#define AT91C_MATRIX_RCB0 (1 << 0)
/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91C_MATRIX_RCB1 (1 << 1)
#define AT91C_AIC_BASE (0XFFFFF000)
/* Interrupt DisaBLe Command Register */
#define AT91C_AIC_IDCR (AT91C_AIC_BASE + 0x124)
/* Interrupt Clear Command Register */
#define AT91C_AIC_ICCR (AT91C_AIC_BASE + 0x128)
#define AT91C_WDT_BASE (0XFFFFFD40)
#define AT91C_WDT_CR (AT91C_WDT_BASE + 0x00)
#define AT91C_WDT_CR_KEY (0xA5000000)
#define AT91C_WDT_CR_WDRSTT (0x00000001)
#define AT91C_WDT_MR (AT91C_WDT_BASE + 0x04)
#define AT91C_WDT_MR_WDDIS (0x00008000)
void rt_low_level_init(void)
{
// Mask all IRQs by clearing all bits in the INTMRS
write_reg(AT91C_AIC_IDCR, 0xFFFFFFFF);
write_reg(AT91C_AIC_ICCR, 0xFFFFFFFF);
// Remap internal ram to 0x00000000 Address
write_reg(AT91C_MATRIX_MRCR, AT91C_MATRIX_RCB0 | AT91C_MATRIX_RCB1);
// Disable the watchdog
//write_reg(AT91C_WDT_CR, AT91C_WDT_CR_KEY|AT91C_WDT_CR_WDRSTT);
//write_reg(AT91C_WDT_MR, AT91C_WDT_MR_WDDIS);
}

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/*
* File : rt_low_level_init.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018-06-04 ArdaFu first version
*/
#ifndef __RT_LOW_LEVEL_INIT_H__
#define __RT_LOW_LEVEL_INIT_H__
/*-------- Stack size of CPU modes -------------------------------------------*/
#define UND_STK_SIZE 512
#define SVC_STK_SIZE 4096
#define ABT_STK_SIZE 512
#define IRQ_STK_SIZE 1024
#define FIQ_STK_SIZE 1024
#define SYS_STK_SIZE 512
#define Heap_Size 512
#endif

270
bsp/at91sam9g45/platform/system_clock.c
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@ -1,270 +0,0 @@
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rtthread.h>
#include "at91sam9g45.h"
static rt_list_t clocks;
struct clk {
char name[32];
rt_uint32_t rate_hz;
struct clk *parent;
rt_list_t node;
};
static struct clk clk32k = {
"clk32k",
AT91C_SLOW_CLOCK,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk main_clk = {
"main",
0,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk plla = {
"plla",
0,
&main_clk,
{RT_NULL, RT_NULL},
};
static struct clk mck = {
"mck",
0,
NULL,
{RT_NULL, RT_NULL},
};
static struct clk upllck = {
"upllck",
480*1000*1000,
&main_clk,
{RT_NULL, RT_NULL},
};
static struct clk *const standard_pmc_clocks[] = {
/* four primary clocks */
&clk32k,
&main_clk,
&plla,
/* MCK */
&mck
};
/* clocks cannot be de-registered no refcounting necessary */
struct clk *clk_get(const char *id)
{
struct clk *clk;
rt_list_t *list;
for (list = (&clocks)->next; list != &clocks; list = list->next)
{
clk = (struct clk *)rt_list_entry(list, struct clk, node);
if (rt_strcmp(id, clk->name) == 0)
return clk;
}
return RT_NULL;
}
rt_uint32_t clk_get_rate(struct clk *clk)
{
rt_uint32_t rate;
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
return rate;
}
static void at91_upllck_init(rt_uint32_t main_clock)
{
// EHCI USB use fixed 480MHz clock
}
static struct clk *at91_css_to_clk(unsigned long css)
{
switch (css) {
case AT91C_PMC_CSS_SLOW_CLK:
return &clk32k;
case AT91C_PMC_CSS_MAIN_CLK:
return &main_clk;
case AT91C_PMC_CSS_PLLA_CLK:
return &plla;
case AT91C_PMC_CSS_UPLL_CLK:
return &upllck;
}
return RT_NULL;
}
// TODO: how to auto-set register value by OSC and MCK
/* Settings at 400/133MHz */
// In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we
// configure OSC startup timeout to 64*8/32768=15.6ms, should enough
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
// MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK
// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR
// 12MHz / 3 * (199 + 1) = 800MHz
// OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50
// PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
#define BOARD_PLLACOUNT (0x3F << 8)
#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16))
#define BOARD_DIVA (AT91C_CKGR_DIVA & 3)
// Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK
// => Processor Clock Divider => PCK
// Master clock can refer to doc6438G figure 25-2 on pg298
// PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz),
// MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock)
#define BOARD_PRESCALER (0x00001300) //400/133MHz
#define MHz(n) ((n) * 1000 * 1000)
#define OSC_FREQ MHz(12)
#define PLLA_FREQ MHz(800)
static void at91_plla_init(void)
{
rt_uint32_t pllar, mckr;
// Code refer to doc6438G, 25.10 Programming Sequence
/* Initialize main oscillator
****************************/
// enable main OSC and wait OSC startup time timeout.
AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
/* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */
pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G
AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA
pllar = (pllar & 3) << 14; // OUTA
pllar |= BOARD_DIVA; // PLLA input clock as 4MHz
pllar |= BOARD_MULA; // PLLA output clock as 800MHz
pllar |= BOARD_PLLACOUNT;
pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it
AT91C_BASE_PMC->PMC_PLLAR = pllar;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
/* Wait for the master clock if it was already initialized */
// make sure Master clock in READY status before operate it
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
/* Switch to fast clock
**********************/
/* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */
mckr = AT91C_BASE_PMC->PMC_MCKR;
if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV))
{
mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV);
AT91C_BASE_PMC->PMC_MCKR = mckr;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
}
/* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */
if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK)
{
mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK;
AT91C_BASE_PMC->PMC_MCKR = mckr;
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
}
plla.rate_hz = PLLA_FREQ;
}
#define false 0
#define true 1
int at91_clock_init(rt_uint32_t main_clock)
{
unsigned tmp, freq, mckr, mdiv;
int i;
/*
* When the bootloader initialized the main oscillator correctly,
* there's no problem using the cycle counter. But if it didn't,
* or when using oscillator bypass mode, we must be told the speed
* of the main clock.
*/
if (!main_clock) {
do {
tmp = readl(AT91C_CKGR_MCFR);
} while (!(tmp & AT91C_CKGR_MAINRDY));
main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
at91_plla_init();
at91_upllck_init(main_clock);
/*
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
mckr = readl(AT91C_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */
mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8);
if (mdiv == 8) mdiv = 3;
freq /= mdiv; /* mdiv */
if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */
mck.rate_hz = freq;
/* Register the PMC's standard clocks */
rt_list_init(&clocks);
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
rt_list_insert_after(&clocks, &upllck.node);
/* MCK and CPU clock are "always on" */
//clk_enable(&mck);
/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
(unsigned) main_clock / 1000000,
((unsigned) main_clock % 1000000) / 1000);*///cause blocked
return 0;
}
/**
* @brief System Clock Configuration
*/
void rt_hw_clock_init(void)
{
at91_clock_init(MHz(12));
}

159
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_INTERRUPT_INFO
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "dbgu"
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
#define RT_USING_CPLUSPLUS
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
#define RT_USING_PTHREADS
/* Network */
/* Socket abstraction layer */
/* light weight TCP/IP stack */
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* sample package */
/* samples: kernel and components samples */
/* example package: hello */
#define RT_USING_DBGU
#define RT_USING_LED
#endif

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import os
ARCH = 'arm'
CPU = 'arm926'
# toolchains options
CROSS_TOOL = 'gcc'
#------- toolchains path -------------------------------------------------------
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'D:\arm-2013.11\bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
#BUILD = 'debug'
BUILD = 'release'
CORE = 'arm926ej-s'
MAP_FILE = 'rtthread_at91sam9g45.map'
LINK_FILE = 'link_scripts/at91sam9g45_ram'
TARGET_NAME = 'rtthread.bin'
#------- GCC settings ----------------------------------------------------------
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=arm926ej-s'
CFLAGS = DEVICE
AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
AFLAGS += ' -Iplatform'
LFLAGS = DEVICE
LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
LFLAGS += ' -T ' + LINK_FILE + '.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
POST_ACTION += SIZE + ' $TARGET\n'
#------- Keil settings ---------------------------------------------------------
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
EXEC_PATH += '/arm/armcc/bin/'
DEVICE = ' --cpu=' + CORE
CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
AFLAGS = DEVICE + ' -Iplatform'
LFLAGS = DEVICE + ' --strict'
LFLAGS += ' --info sizes --info totals --info unused --info veneers'
LFLAGS += ' --list ' + MAP_FILE
LFLAGS += ' --scatter ' + LINK_FILE + '.scat'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
POST_ACTION += 'fromelf -z $TARGET\n'
#------- IAR settings ----------------------------------------------------------
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = CORE
CFLAGS = '--cpu=' + DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' -e'
CFLAGS += ' --fpu=none'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = '--cpu '+ DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --fpu none'
AFLAGS += ' -S'
AFLAGS += ' -Iplatform'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = '--config ' + LINK_FILE +'.icf'
LFLAGS += ' --entry __iar_program_start'
LFLAGS += ' --map ' + MAP_FILE
LFLAGS += ' --silent'
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>18432000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>1</RunSim>
<RunTarget>0</RunTarget>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>16</CpuCode>
<Books>
<Book>
<Number>0</Number>
<Title>Datasheet</Title>
<Path>DATASHTS\ATMEL\AT91SAM9260_DS.PDF</Path>
</Book>
<Book>
<Number>1</Number>
<Title>Summary</Title>
<Path>DATASHTS\ATMEL\AT91SAM9260_DC.PDF</Path>
</Book>
</Books>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>0</tLdApp>
<tGomain>0</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<tPdscDbg>1</tPdscDbg>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\jlink\at91sam9260.ini</tIfile>
<pMon>Segger\JLTAgdi.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>JLTAgdi</Key>
<Name>-O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2ARM</Key>
<Name>-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
</TargetOption>
</Target>
</ProjectOpt>

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bsp/at91sam9g45/template.uvproj
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@ -1,407 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
<SchemaVersion>1.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>AT91SAM9260</Device>
<Vendor>Atmel</Vendor>
<Cpu>IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S)</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code")</StartupFile>
<FlashDriverDll>UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00)</FlashDriverDll>
<DeviceId>4210</DeviceId>
<RegisterFile>AT91SAM9260.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile></SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>Atmel\SAM9260\</RegisterFilePath>
<DBRegisterFilePath>Atmel\SAM9260\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>rtthread</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARM.DLL</SimDllName>
<SimDllArguments>-cAT91SAM9260</SimDllArguments>
<SimDlgDll>DARMATS9.DLL</SimDlgDll>
<SimDlgDllArguments>-p91SAM9260</SimDlgDllArguments>
<TargetDllName>SARM.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMATS9.DLL</TargetDlgDll>
<TargetDlgDllArguments>-p91SAM9260</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
<RestoreSysVw>1</RestoreSysVw>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>0</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>1</RestoreTracepoints>
<RestoreSysVw>1</RestoreSysVw>
<UsePdscDebugDescription>1</UsePdscDebugDescription>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>5</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>.\jlink\at91sam9260.ini</InitializationFile>
<Driver>Segger\JLTAgdi.dll</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2ARM.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4>.\jlink\at91sam9260.ini</Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>ARM926EJ-S</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>1</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>1</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x1000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x100000</StartAddress>
<Size>0x8000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x800000</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x100000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x20800000</StartAddress>
<Size>0x1800000</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x200000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x300000</StartAddress>
<Size>0x1000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define>RT_USING_INTERRUPT_INFO</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>.\platform</IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x20000000</TextAddressRange>
<DataAddressRange>0x20800000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\link_scripts\at91sam9g45_ram.scat</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
</Targets>
</Project>