stm32_radio: Adds codec master mode to WM8978 driver.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@391 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
kyle.hu.gz
parent
02a644e7e2
commit
189d475946
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@ -3,6 +3,8 @@
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#include "stm32f10x.h"
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#include "codec.h"
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#define CODEC_MASTER_MODE 0
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/*
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SCLK PA5 SPI1_SCK
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SDIN PA7 SPI1_MOSI
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@ -14,6 +16,7 @@ CSB PC5
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#define codec_reset_csb() do { CODEC_CSB_PORT->BRR = CODEC_CSB_PIN; } while (0)
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void vol(uint16_t v);
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static void codec_send(rt_uint16_t s_data);
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#define DATA_NODE_MAX 5
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/* data node for Tx Mode */
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@ -37,19 +40,8 @@ struct codec_device
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};
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struct codec_device codec;
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struct pll_ratio
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{
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uint8_t n;
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uint8_t k1;
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uint16_t k2;
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uint16_t k3;
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};
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static void delay_ms(unsigned int dt)
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{
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volatile unsigned int u;
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for (u = 0; u < dt * 30; u++);
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}
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static uint16_t r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8;
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static uint16_t zero = 0;
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static void NVIC_Configuration(void)
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{
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@ -83,11 +75,25 @@ static void GPIO_Configuration(void)
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_Init(CODEC_CSB_PORT, &GPIO_InitStructure);
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/* Configure SPI2 pins: CK, WS and SD */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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#if CODEC_MASTER_MODE
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// WS, CK
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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// SD
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#else
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/* Configure SPI2 pins: CK, WS and SD */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_15;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_Init(GPIOB, &GPIO_InitStructure);
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#endif
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#ifdef CODEC_USE_MCO
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/* MCO configure */
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@ -114,9 +120,13 @@ static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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#if CODEC_MASTER_MODE
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while ((SPI2->SR & SPI_SR_CHSIDE) == 1);
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DMA_ClearFlag(DMA1_FLAG_TC5);
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#endif
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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@ -126,6 +136,35 @@ static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#if CODEC_MASTER_MODE
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static void DMA_ZeroFill_I2S()
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{
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DMA_InitTypeDef DMA_InitStructure;
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/* DMA1 Channel2 configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel5, DISABLE);
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DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI2->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) &zero;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = 1;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel5, &DMA_InitStructure);
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/* Enable SPI2 DMA Tx request */
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SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
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//DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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}
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#endif
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static void I2S_Configuration(void)
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{
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I2S_InitTypeDef I2S_InitStructure;
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@ -135,11 +174,14 @@ static void I2S_Configuration(void)
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I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
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I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
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I2S_InitStructure.I2S_AudioFreq = I2S_AudioFreq_44k;
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_High; // I2S_CPOL_Low
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I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
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/* I2S2 Master Transmitter to I2S3 Slave Receiver communication -----------*/
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/* I2S2 configuration */
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx; //I2S_Mode_MasterTx I2S_Mode_SlaveTx
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#if CODEC_MASTER_MODE
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I2S_InitStructure.I2S_Mode = I2S_Mode_SlaveTx;
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#else
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I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
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#endif
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I2S_Init(SPI2, &I2S_InitStructure);
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}
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@ -185,8 +227,6 @@ static rt_err_t codec_init(rt_device_t dev)
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codec_send(REG_OUTPUT | SPKBOOST);
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// Set VMIDSEL[1:0] to required value in register R1.
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K);
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// Wait for VMID supply to settle.
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delay_ms(750);
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// Set L/RMIXEN=1 and DACENL/R=1 in register R3.
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codec_send(REG_POWER_MANAGEMENT3 | LMIXEN | RMIXEN | DACENL | DACENR);
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// Set BIASEN=1 in register R1.
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@ -205,13 +245,13 @@ static rt_err_t codec_init(rt_device_t dev)
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// F_PLL = 11.2896MHz * 4 * 2 = 90.3168MHz
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// R = 90.3168MHz / 12.288MHz = 7.35
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// PLL_N = 7
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// PLL_K = 5872026
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// PLL_K = 5872026 (5921370 for STM32's 44.117KHz fs generated from 72MHz clock)
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codec_send(REG_PLL_N | 7);
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codec_send(REG_PLL_K1 | 0x16);
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codec_send(REG_PLL_K2 | 0xCC);
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codec_send(REG_PLL_K3 | 0x19A);
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codec_send(REG_PLL_K2 | 0x12D);
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codec_send(REG_PLL_K3 | 0x5A);
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codec_send(REG_POWER_MANAGEMENT1 | BUFDCOPEN | BUFIOEN | VMIDSEL_75K | BIASEN | PLLEN);
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codec_send(REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2);
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codec_send(r06);
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// Enable DAC 128x oversampling.
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codec_send(REG_DAC | DACOSR128);
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@ -220,7 +260,7 @@ static rt_err_t codec_init(rt_device_t dev)
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codec_send(REG_BEEP | INVROUT2);
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// Set output volume to -22dB.
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vol(35);
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vol(20);
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return RT_EOK;
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}
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@ -272,7 +312,8 @@ void sample_rate(uint8_t sr)
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if (sr == 44)
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{
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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codec_send(REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2);
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r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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codec_send(r06);
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}
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else
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{
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@ -280,32 +321,38 @@ void sample_rate(uint8_t sr)
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{
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case 8:
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codec_send(REG_ADDITIONAL | SR_8KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV6 | BCLK_DIV8 | (r06 & MS);
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break;
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case 12:
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codec_send(REG_ADDITIONAL | SR_12KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV4 | BCLK_DIV8 | (r06 & MS);
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break;
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case 16:
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codec_send(REG_ADDITIONAL | SR_16KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV3 | BCLK_DIV8 | (r06 & MS);
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break;
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case 24:
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codec_send(REG_ADDITIONAL | SR_24KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV2 | BCLK_DIV8 | (r06 & MS);
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break;
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case 32:
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codec_send(REG_ADDITIONAL | SR_32KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1_5 | BCLK_DIV8 | (r06 & MS);
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break;
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case 48:
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codec_send(REG_ADDITIONAL | SR_48KHZ);
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r06 = REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1 | BCLK_DIV8 | (r06 & MS);
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break;
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default:
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return;
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}
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codec_send(REG_CLOCK_GEN | CLKSEL_MCLK | MCLK_DIV1);
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codec_send(r06);
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}
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}
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@ -323,6 +370,13 @@ static rt_err_t codec_open(rt_device_t dev, rt_uint16_t oflag)
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/* enable I2S */
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I2S_Cmd(SPI2, ENABLE);
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#if CODEC_MASTER_MODE
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DMA_ZeroFill_I2S();
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r06 |= MS;
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codec_send(r06);
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#endif
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return RT_EOK;
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}
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@ -334,6 +388,16 @@ static rt_err_t codec_close(rt_device_t dev)
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/* Disable the I2S2 */
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I2S_Cmd(SPI2, DISABLE);
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}
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#if CODEC_MASTER_MODE
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else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
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{
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DMA_Cmd(DMA1_Channel5, DISABLE);
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I2S_Cmd(SPI2, DISABLE);
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r06 &= ~MS;
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codec_send(r06);
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}
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#endif
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/* remove all data node */
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@ -413,7 +477,7 @@ rt_err_t codec_hw_init(void)
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I2S_Configuration();
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dev = (rt_device_t) &codec;
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dev->type = RT_Device_Class_Unknown;
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dev->type = RT_Device_Class_Sound;
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dev->rx_indicate = RT_NULL;
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dev->tx_complete = RT_NULL;
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dev->init = codec_init;
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@ -495,6 +559,10 @@ void codec_dma_isr()
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}
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else
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{
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#if CODEC_MASTER_MODE
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DMA_ZeroFill_I2S();
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#endif
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rt_kprintf("*\n");
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}
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