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fixed rpi4 eth driver

This commit is contained in:
bigmagic 2020-11-26 11:20:13 +08:00
parent 921f98788e
commit 1641caa378
7 changed files with 252 additions and 131 deletions
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20
bsp/raspberry-pi/raspi4-32/.config
View File

@ -14,7 +14,7 @@ CONFIG_RT_ALIGN_SIZE=4
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
@ -54,6 +54,7 @@ CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
@ -149,6 +150,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
@ -376,6 +378,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
@ -402,6 +405,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
#
# tools packages
@ -449,7 +453,15 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
#
@ -505,6 +517,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
#
# miscellaneous packages
@ -534,11 +548,13 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
@ -584,6 +600,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_DCM is not set
# CONFIG_PKG_USING_EMQ is not set
# CONFIG_PKG_USING_CFGM is not set
# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set
CONFIG_BCM2711_SOC=y
# CONFIG_BSP_SUPPORT_FPU is not set

15
bsp/raspberry-pi/raspi4-32/driver/board.c
View File

@ -16,6 +16,7 @@
#include "cp15.h"
#include "mmu.h"
#include "mbox.h"
struct mem_desc platform_mem_desc[] = {
{0x0, 0x6400000, 0x0, NORMAL_MEM},
@ -36,21 +37,25 @@ void rt_hw_timer_isr(int vector, void *parameter)
void rt_hw_timer_init(void)
{
rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(ARM_TIMER_IRQ);
rt_uint32_t apb_clock = 0;
rt_uint32_t timer_clock = 1000000;
/* timer_clock = apb_clock/(pre_divider + 1) */
ARM_TIMER_PREDIV = (250 - 1);
apb_clock = bcm271x_mbox_clock_get_rate(CORE_CLK_ID);
ARM_TIMER_PREDIV = (apb_clock/timer_clock - 1);
ARM_TIMER_RELOAD = 0;
ARM_TIMER_LOAD = 0;
ARM_TIMER_IRQCLR = 0;
ARM_TIMER_CTRL = 0;
ARM_TIMER_RELOAD = 10000;
ARM_TIMER_LOAD = 10000;
ARM_TIMER_RELOAD = 1000000/RT_TICK_PER_SECOND;
ARM_TIMER_LOAD = 1000000/RT_TICK_PER_SECOND;
/* 23-bit counter, enable interrupt, enable timer */
ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
rt_hw_interrupt_install(ARM_TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(ARM_TIMER_IRQ);
}
void idle_wfi(void)

316
bsp/raspberry-pi/raspi4-32/driver/drv_eth.c
View File

@ -19,6 +19,15 @@
#include "raspi4.h"
#include "drv_eth.h"
//#define ETH_RX_POLL
#define DBG_LEVEL DBG_LOG
#include <rtdbg.h>
#define LOG_TAG "drv.eth"
static int link_speed = 0;
static int link_flag = 0;
#define RECV_CACHE_BUF (1024)
#define SEND_DATA_NO_CACHE (0x08200000)
#define RECV_DATA_NO_CACHE (0x08400000)
@ -34,6 +43,11 @@
#define BIT(nr) (1UL << (nr))
static rt_thread_t link_thread_tid = RT_NULL;
#define LINK_THREAD_STACK_SIZE (1024)
#define LINK_THREAD_PRIORITY (20)
#define LINK_THREAD_TIMESLICE (10)
static rt_uint32_t tx_index = 0;
static rt_uint32_t rx_index = 0;
static rt_uint32_t index_flag = 0;
@ -54,6 +68,7 @@ struct rt_eth_dev
};
static struct rt_eth_dev eth_dev;
static struct rt_semaphore sem_lock;
static struct rt_semaphore link_ack;
static inline rt_uint32_t read32(void *addr)
{
@ -65,19 +80,36 @@ static inline void write32(void *addr, rt_uint32_t value)
(*((volatile unsigned int*)(addr))) = value;
}
void eth_rx_irq(void *param)
static void eth_rx_irq(int irq, void *param)
{
#ifndef ETH_RX_POLL
rt_uint32_t val = 0;
val = read32(MAC_REG + GENET_INTRL2_CPU_STAT);
val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK);
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val);
if (val & GENET_IRQ_RXDMA_DONE)
{
eth_device_ready(&eth_dev.parent);
}
if (val & GENET_IRQ_TXDMA_DONE)
{
//todo
}
#else
eth_device_ready(&eth_dev.parent);
#endif
}
/* We only support RGMII (as used on the RPi4). */
static int bcmgenet_interface_set(void)
{
int phy_mode = PHY_INTERFACE_MODE_RGMII;
switch (phy_mode) {
switch (phy_mode)
{
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_RXID:
write32(MAC_REG + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY);
write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
break;
default:
rt_kprintf("unknown phy mode: %d\n", MAC_REG);
@ -94,10 +126,10 @@ static void bcmgenet_umac_reset(void)
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
reg &= ~BIT(1);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),reg);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
DELAY_MICROS(10);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),0);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), 0);
DELAY_MICROS(10);
write32(MAC_REG + UMAC_CMD, 0);
write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
@ -145,7 +177,7 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
{
int count = 10000;
rt_uint32_t val;
val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value);
val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value);
write32(MAC_REG + MDIO_CMD, val);
rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD);
@ -158,7 +190,6 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
}
static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
@ -179,7 +210,7 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
return reg_val & 0xffff;
}
static int bcmgenet_gmac_write_hwaddr(void)
@ -207,9 +238,9 @@ static int get_ethernet_uid(void)
uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW);
uid = (uid_high << 16 | uid_low);
if(BCM54213PE_VERSION_B1 == uid)
if (BCM54213PE_VERSION_B1 == uid)
{
rt_kprintf("version is B1\n");
LOG_I("version is B1\n");
}
return uid;
}
@ -219,7 +250,7 @@ static void bcmgenet_mdio_init(void)
rt_uint32_t ret = 0;
/*get ethernet uid*/
ret = get_ethernet_uid();
if(ret == 0)
if (ret == 0)
{
return;
}
@ -236,19 +267,21 @@ static void bcmgenet_mdio_init(void)
/* read status reg */
bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS);
bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV);
bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
bcmgenet_mdio_read(1, BCM54213PE_CONTROL);
/* half full duplex capability */
bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY));
bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
/* set mii control */
bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION));
bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, (MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART | MII_CONTROL_PHY_FULL_DUPLEX | MII_CONTROL_SPEED_SELECTION));
}
static void rx_ring_init(void)
{
write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 );
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(MAC_REG + RDMA_READ_PTR, 0x0);
write32(MAC_REG + RDMA_WRITE_PTR, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
@ -257,7 +290,7 @@ static void rx_ring_init(void)
write32(MAC_REG + RDMA_CONS_INDEX, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
}
static void tx_ring_init(void)
@ -268,13 +301,13 @@ static void tx_ring_init(void)
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_WRITE_PTR, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + TDMA_PROD_INDEX, 0x0);
write32(MAC_REG + TDMA_CONS_INDEX, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1);
write32(MAC_REG + TDMA_FLOW_PERIOD,0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
write32(MAC_REG + TDMA_FLOW_PERIOD, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
}
static void rx_descs_init(void)
@ -284,55 +317,21 @@ static void rx_descs_init(void)
void *desc_base = (void *)RX_DESC_BASE;
len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
for (i = 0; i < RX_DESCS; i++) {
for (i = 0; i < RX_DESCS; i++)
{
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI),upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS),len_stat);
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI), upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS), len_stat);
}
}
static int phy_startup(void)
{
int count = 1000000;
while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count))
DELAY_MICROS(1);
if(count > 0)
{
rt_kprintf("bcmgenet: PHY startup ok!\n");
}
else
{
rt_kprintf("bcmgenet: PHY startup err!\n");
return 1;
}
if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0)
{
//todo
}
else
{
rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n");
}
if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY))
{
//todo
}
else
{
rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n");
}
return 0;
}
static int bcmgenet_adjust_link(void)
{
rt_uint32_t speed;
rt_uint32_t phy_dev_speed = SPEED_100;
switch (phy_dev_speed) {
rt_uint32_t phy_dev_speed = link_speed;
switch (phy_dev_speed)
{
case SPEED_1000:
speed = UMAC_SPEED_1000;
break;
@ -358,6 +357,14 @@ static int bcmgenet_adjust_link(void)
return 0;
}
void link_irq(void *param)
{
if ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) != 0)
{
rt_sem_release(&link_ack);
}
}
static int bcmgenet_gmac_eth_start(void)
{
rt_uint32_t ret;
@ -375,23 +382,17 @@ static int bcmgenet_gmac_eth_start(void)
/* Enable RX/TX DMA */
bcmgenet_enable_dma();
/* read PHY properties over the wire from generic PHY set-up */
ret = phy_startup();
if (ret) {
rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret);
return ret;
}
/* Update MAC registers based on PHY property */
ret = bcmgenet_adjust_link();
if (ret) {
if(ret)
{
rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret);
return ret;
}
/* wait tx index clear */
while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count))
DELAY_MICROS(1);
DELAY_MICROS(1);
tx_index = read32(MAC_REG + TDMA_CONS_INDEX);
write32(MAC_REG + TDMA_PROD_INDEX, tx_index);
@ -410,6 +411,8 @@ static int bcmgenet_gmac_eth_start(void)
rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
write32(MAC_REG + UMAC_CMD, rx_tx_en);
//IRQ
write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
return 0;
}
@ -424,6 +427,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
if(prod_index == index_flag)
{
cur_recv_cnt = index_flag;
index_flag = 0x7fffffff;
//no buff
return 0;
}
@ -433,7 +437,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
{
return 0;
}
desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE;
length = read32(desc_base + DMA_DESC_LENGTH_STATUS);
length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
@ -452,6 +456,11 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
cur_recv_cnt = cur_recv_cnt + 1;
if(cur_recv_cnt > 0xffff)
{
cur_recv_cnt = 0;
}
prev_recv_cnt = cur_recv_cnt;
return length;
@ -460,52 +469,120 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
static int bcmgenet_gmac_eth_send(void *packet, int length)
{
void* desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
rt_uint32_t prod_index, cons;
rt_uint32_t tries = 100;
prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
write32((desc_base + DMA_DESC_ADDRESS_LO),SEND_DATA_NO_CACHE);
write32((desc_base + DMA_DESC_ADDRESS_HI),0);
write32((desc_base + DMA_DESC_LENGTH_STATUS),len_stat);
write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE);
write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
if(++tx_index>= TX_DESCS)
tx_index = tx_index + 1;
prod_index = prod_index + 1;
if (prod_index == 0xe000)
{
write32(MAC_REG + TDMA_PROD_INDEX, 0);
prod_index = 0;
}
if (tx_index == 256)
{
tx_index = 0;
}
prod_index++;
/* Start Transmisson */
write32(MAC_REG + TDMA_PROD_INDEX,prod_index);
do {
/* Start Transmisson */
write32(MAC_REG + TDMA_PROD_INDEX, prod_index);
do
{
cons = read32(MAC_REG + TDMA_CONS_INDEX);
} while ((cons & 0xffff) < prod_index && --tries);
if (!tries)
{
rt_kprintf("send err! tries is %d\n", tries);
return -1;
}
return 0;
}
static void link_task_entry(void *param)
{
struct eth_device *eth_device = (struct eth_device *)param;
RT_ASSERT(eth_device != RT_NULL);
struct rt_eth_dev *dev = &eth_dev;
//start mdio
bcmgenet_mdio_init();
//start timer link
rt_timer_init(&dev->link_timer, "link_timer",
link_irq,
NULL,
100,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->link_timer);
//link wait forever
rt_sem_take(&link_ack, RT_WAITING_FOREVER);
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //link up
rt_timer_stop(&dev->link_timer);
//set mac
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_write_hwaddr();
//check link speed
if ((bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 10)) || (bcmgenet_mdio_read(1, BCM54213PE_STATUS) & (1 << 11)))
{
link_speed = 1000;
rt_kprintf("Support link mode Speed 1000M\n");
}
else if ((bcmgenet_mdio_read(1, 0x05) & (1 << 7)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 8)) || (bcmgenet_mdio_read(1, 0x05) & (1 << 9)))
{
link_speed = 100;
rt_kprintf("Support link mode Speed 100M\n");
}
else
{
link_speed = 10;
rt_kprintf("Support link mode Speed 10M\n");
}
bcmgenet_gmac_eth_start();
//irq or poll
#ifdef ETH_RX_POLL
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
eth_rx_irq,
NULL,
1,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->rx_poll_timer);
#else
rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq");
rt_hw_interrupt_umask(ETH_IRQ);
#endif
link_flag = 1;
}
static rt_err_t bcmgenet_eth_init(rt_device_t device)
{
struct eth_device *eth_device = (struct eth_device *)device;
RT_ASSERT(eth_device != RT_NULL);
rt_uint32_t ret = 0;
rt_uint32_t hw_reg = 0;
struct rt_eth_dev *dev = &eth_dev;
/* Read GENET HW version */
rt_uint8_t major = 0;
hw_reg = read32(MAC_REG + SYS_REV_CTRL);
major = (hw_reg >> 24) & 0x0f;
if (major != 6) {
if (major != 6)
{
if (major == 5)
major = 4;
else if (major == 0)
@ -514,13 +591,12 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f);
return RT_ERROR;
}
/* set interface */
ret = bcmgenet_interface_set();
if (ret)
{
return ret;
}
}
/* rbuf clear */
write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0);
@ -530,21 +606,11 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
/* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
bcmgenet_mdio_init();
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_eth_start();
//irq or poll
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
eth_rx_irq,
NULL,
1,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->rx_poll_timer);
link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device,
LINK_THREAD_STACK_SIZE,
LINK_THREAD_PRIORITY, LINK_THREAD_TIMESLICE);
if (link_thread_tid != RT_NULL)
rt_thread_startup(link_thread_tid);
return RT_EOK;
}
@ -554,10 +620,12 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
switch (cmd)
{
case NIOCTL_GADDR:
if (args) rt_memcpy(args, eth_dev.dev_addr, 6);
else return -RT_ERROR;
if (args)
rt_memcpy(args, eth_dev.dev_addr, 6);
else
return -RT_ERROR;
break;
default :
default:
break;
}
return RT_EOK;
@ -565,15 +633,17 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
{
rt_uint32_t sendbuf = SEND_DATA_NO_CACHE;
rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE;
/* lock eth device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
//struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
if (link_flag == 1)
{
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
rt_sem_release(&sem_lock);
bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
rt_sem_release(&sem_lock);
}
return RT_EOK;
}
@ -583,16 +653,17 @@ struct pbuf *rt_eth_rx(rt_device_t device)
int recv_len = 0;
rt_uint32_t addr_point[8];
struct pbuf *pbuf = RT_NULL;
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
if(recv_len > 0)
if (link_flag == 1)
{
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
if (recv_len > 0)
{
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
}
rt_sem_release(&sem_lock);
}
rt_sem_release(&sem_lock);
return pbuf;
}
@ -601,11 +672,11 @@ int rt_hw_eth_init(void)
rt_uint8_t mac_addr[6];
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
memset(&eth_dev, 0, sizeof(eth_dev));
memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
eth_dev.iobase = MAC_REG;
@ -629,9 +700,8 @@ int rt_hw_eth_init(void)
eth_dev.parent.eth_tx = rt_eth_tx;
eth_dev.parent.eth_rx = rt_eth_rx;
eth_device_init(&(eth_dev.parent), "e0");
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
eth_device_linkchange(&eth_dev.parent, RT_FALSE); //link down
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_eth_init);

11
bsp/raspberry-pi/raspi4-32/driver/drv_eth.h
View File

@ -53,6 +53,17 @@
#define MDIO_REG_SHIFT (16)
#define MDIO_REG_MASK (0x1f)
#define GENET_INTRL2_OFF (0x0200)
#define GENET_INTRL2_CPU_STAT (GENET_INTRL2_OFF + 0x00)
#define GENET_INTRL2_CPU_CLEAR (GENET_INTRL2_OFF + 0x08)
#define GENET_INTRL2_CPU_STAT_MASK (GENET_INTRL2_OFF + 0x0c)
#define GENET_INTRL2_CPU_SET_MASK (GENET_INTRL2_OFF + 0x10)
#define GENET_INTRL2_CPU_CLEAR_MASK (GENET_INTRL2_OFF + 0x14)
#define GENET_IRQ_MDIO_ERROR BIT(24)
#define GENET_IRQ_MDIO_DONE BIT(23)
#define GENET_IRQ_TXDMA_DONE BIT(16)
#define GENET_IRQ_RXDMA_DONE BIT(13)
#define CMD_TX_EN BIT(0)
#define CMD_RX_EN BIT(1)
#define UMAC_SPEED_10 (0)

12
bsp/raspberry-pi/raspi4-32/driver/mbox.h
View File

@ -134,6 +134,18 @@ enum {
#define MBOX_ADDR 0x08000000
#define RES_CLK_ID (0x000000000)
#define EMMC_CLK_ID (0x000000001)
#define UART_CLK_ID (0x000000002)
#define ARM_CLK_ID (0x000000003)
#define CORE_CLK_ID (0x000000004)
#define V3D_CLK_ID (0x000000005)
#define H264_CLK_ID (0x000000006)
#define ISP_CLK_ID (0x000000007)
#define SDRAM_CLK_ID (0x000000008)
#define PIXEL_CLK_ID (0x000000009)
#define PWM_CLK_ID (0x00000000a)
int mbox_call(unsigned char ch, int mmu_enable);
int bcm271x_notify_reboot(void);
int bcm271x_notify_xhci_reset(void);

4
bsp/raspberry-pi/raspi4-32/driver/raspi4.h
View File

@ -150,7 +150,9 @@ typedef enum {
//External Mass Media Controller (SD Card)
#define MMC0_BASE_ADDR (PER_BASE+0x300000)
#define MMC2_BASE_ADDR (PER_BASE+0x340000)
#define MMC2_BASE_ADDR (PER_BASE+0x340000)
#define ETH_IRQ (160+29)
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)

5
bsp/raspberry-pi/raspi4-32/rtconfig.h
View File

@ -10,7 +10,7 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
@ -214,6 +214,9 @@
/* system packages */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */