补充KEIL5编译支持文件，解决KEIL5编译问题
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FuChao
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;/**
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;* @file startup_target.s
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;* @author Application Team
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;* @version V1.1.0
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;* @date 2019-10-28
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;* @brief Target Devices vector table.
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;******************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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__CHIPINITIAL EQU 1
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Stack_Size EQU 0x000001000
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000400
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PMU_IRQHandler ; 0: PMU
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DCD RTC_IRQHandler ; 1: RTC
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DCD U32K0_IRQHandler ; 2: U32K0
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DCD U32K1_IRQHandler ; 3: U32K1
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DCD I2C_IRQHandler ; 4: I2C
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DCD SPI1_IRQHandler ; 5: SPI1
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DCD UART0_IRQHandler ; 6: UART0
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DCD UART1_IRQHandler ; 7: UART1
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DCD UART2_IRQHandler ; 8: UART2
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DCD UART3_IRQHandler ; 9: UART3
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DCD UART4_IRQHandler ; 10: UART4
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DCD UART5_IRQHandler ; 11: UART5
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DCD ISO78160_IRQHandler ; 12: ISO78160
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DCD ISO78161_IRQHandler ; 13: ISO78161
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DCD TMR0_IRQHandler ; 14: TMR0
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DCD TMR1_IRQHandler ; 15: TMR1
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DCD TMR2_IRQHandler ; 16: TMR2
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DCD TMR3_IRQHandler ; 17: TMR3
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DCD PWM0_IRQHandler ; 18: PWM0
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DCD PWM1_IRQHandler ; 19: PWM1
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DCD PWM2_IRQHandler ; 20: PWM2
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DCD PWM3_IRQHandler ; 21: PWM3
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DCD DMA_IRQHandler ; 22: DMA
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DCD FLASH_IRQHandler ; 23: FLASH
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DCD ANA_IRQHandler ; 24: ANA
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DCD 0 ; 25: Reserved
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DCD 0 ; 26: Reserved
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DCD SPI2_IRQHandler ; 27: SPI2
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DCD SPI3_IRQHandler ; 28: SPI3
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DCD 0 ; 29: Reserved
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DCD 0 ; 30: Reserved
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DCD 0 ; 31: Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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IF (__CHIPINITIAL != 0)
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AREA |.ARM.__AT_0xC0|, CODE, READONLY
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ELSE
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AREA |.text|, CODE, READONLY
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ENDIF
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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IMPORT SystemInit
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IF (__CHIPINITIAL != 0)
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LDR R0, =__CHIP_INIT
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BLX R0
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ENDIF
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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AREA |.text|, CODE, READONLY
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PMU_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT U32K0_IRQHandler [WEAK]
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EXPORT U32K1_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT UART5_IRQHandler [WEAK]
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EXPORT ISO78160_IRQHandler [WEAK]
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EXPORT ISO78161_IRQHandler [WEAK]
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EXPORT TMR0_IRQHandler [WEAK]
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EXPORT TMR1_IRQHandler [WEAK]
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EXPORT TMR2_IRQHandler [WEAK]
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EXPORT TMR3_IRQHandler [WEAK]
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EXPORT PWM0_IRQHandler [WEAK]
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EXPORT PWM1_IRQHandler [WEAK]
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EXPORT PWM2_IRQHandler [WEAK]
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EXPORT PWM3_IRQHandler [WEAK]
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EXPORT DMA_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT ANA_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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PMU_IRQHandler
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RTC_IRQHandler
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U32K0_IRQHandler
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U32K1_IRQHandler
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I2C_IRQHandler
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SPI1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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UART4_IRQHandler
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UART5_IRQHandler
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ISO78160_IRQHandler
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ISO78161_IRQHandler
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TMR0_IRQHandler
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TMR1_IRQHandler
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TMR2_IRQHandler
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TMR3_IRQHandler
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PWM0_IRQHandler
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PWM1_IRQHandler
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PWM2_IRQHandler
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PWM3_IRQHandler
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DMA_IRQHandler
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FLASH_IRQHandler
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ANA_IRQHandler
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SPI2_IRQHandler
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SPI3_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Chip init.
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;; 1. Load flash configuration
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;; 2. Load ANA_REG(B/C/D/E) information
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;; 3. Load ANA_REG10 information
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IF (__CHIPINITIAL != 0)
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AREA |.ARM.__AT_0xC0|, CODE, READONLY
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__CHIP_INIT PROC
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CONFIG1_START
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;-------------------------------;
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;; 1. Load flash configuration
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; Unlock flash
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LDR R0, =0x000FFFE0
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LDR R1, =0x55AAAA55
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STR R1, [R0]
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; Load configure word 0 to 7
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; Compare bit[7:0]
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LDR R0, =0x00080E00
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LDR R1, =0x20
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LDR R2, =0x000FFFE8
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LDR R3, =0x000FFFF0
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LDR R4, =0x0
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LDR R7, =0x0FF
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FLASH_CONF_START_1
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LDR R5, [R0]
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STR R4, [R2]
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STR R5, [R3]
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LDR R6, [R3]
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ANDS R5, R7
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ANDS R6, R7
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CMP R5, R6
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BNE FLASH_CONF_AGAIN_1
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ADDS R4, #4
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ADDS R0, #4
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CMP R1, R4
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BEQ FLASH_CONF_END_1
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B FLASH_CONF_START_1
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FLASH_CONF_AGAIN_1
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LDR R5, [R0]
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STR R4, [R2]
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STR R5, [R3]
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LDR R6, [R3]
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ANDS R5, R7
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ANDS R6, R7
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CMP R5, R6
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FLASH_CONF_WHILELOOP_1
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BNE FLASH_CONF_WHILELOOP_1
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ADDS R4, #4
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ADDS R0, #4
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CMP R1, R4
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BEQ FLASH_CONF_END_1
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B FLASH_CONF_START_1
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FLASH_CONF_END_1
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; Load configure word 8 to 11
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; Compare bit 31,24,23:16,8,7:0
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LDR R1, =0x30
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LDR R7, =0x81FF81FF
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FLASH_CONF_START_2
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LDR R5, [R0]
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STR R4, [R2]
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STR R5, [R3]
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LDR R6, [R3]
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ANDS R5, R7
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ANDS R6, R7
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CMP R5, R6
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BNE FLASH_CONF_AGAIN_1
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ADDS R4, #4
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ADDS R0, #4
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CMP R1, R4
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BEQ FLASH_CONF_END_2
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B FLASH_CONF_START_2
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FLASH_CONF_AGAIN_2
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LDR R5, [R0]
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STR R4, [R2]
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STR R5, [R3]
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LDR R6, [R3]
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ANDS R5, R7
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ANDS R6, R7
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CMP R5, R6
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FLASH_CONF_WHILELOOP_2
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BNE FLASH_CONF_WHILELOOP_2
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ADDS R4, #4
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ADDS R0, #4
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CMP R1, R4
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BEQ FLASH_CONF_END_2
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B FLASH_CONF_START_2
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FLASH_CONF_END_2
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; Lock flash
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LDR R0, =0x000FFFE0
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LDR R1, =0x0
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STR R1, [R0]
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;-------------------------------;
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;; 2. Load ANA_REG(B/C/D/E) information
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CONFIG2_START
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LDR R4, =0x4001422C
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LDR R5, =0x40014230
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LDR R6, =0x40014234
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LDR R7, =0x40014238
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LDR R0, =0x80DC0
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LDR R0, [R0]
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LDR R1, =0x80DC4
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LDR R1, [R1]
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ADDS R2, R0, R1
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ADDS R2, #0x0FFFFFFFF
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MVNS R2, R2
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LDR R3, =0x80DCC
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LDR R3, [R3]
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CMP R3, R2
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BEQ ANADAT_CHECKSUM1_OK
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B ANADAT_CHECKSUM1_ERR
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ANADAT_CHECKSUM1_OK
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; ANA_REGB
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LDR R1, =0x0FF
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ANDS R1, R0
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STR R1, [R4]
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; ANA_REGC
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LDR R1, =0x0FF00
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ANDS R1, R0
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LSRS R1, R1, #8
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STR R1, [R5]
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; ANA_REGD
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LDR R1, =0x0FF0000
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ANDS R1, R0
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LSRS R1, R1, #16
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STR R1, [R6]
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; ANA_REGE
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LDR R1, =0x0FF000000
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ANDS R1, R0
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LSRS R1, R1, #24
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STR R1, [R7]
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B CONFIG3_START
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ANADAT_CHECKSUM1_ERR
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LDR R0, =0x80DD0
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LDR R0, [R0]
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LDR R1, =0x80DD4
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LDR R1, [R1]
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ADDS R2, R0, R1
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ADDS R2, #0x0FFFFFFFF
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MVNS R2, R2
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LDR R3, =0x80DDC
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LDR R3, [R3]
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CMP R3, R2
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BEQ ANADAT_CHECKSUM2_OK
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B ANADAT_CHECKSUM2_ERR
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ANADAT_CHECKSUM2_OK
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; ANA_REGB
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LDR R1, =0x0FF
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ANDS R1, R0
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STR R1, [R4]
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; ANA_REGC
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LDR R1, =0x0FF00
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ANDS R1, R0
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LSRS R1, R1, #8
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STR R1, [R5]
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; ANA_REGD
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LDR R1, =0x0FF0000
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ANDS R1, R0
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LSRS R1, R1, #16
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STR R1, [R6]
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; ANA_REGE
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LDR R1, =0x0FF000000
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ANDS R1, R0
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LSRS R1, R1, #24
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STR R1, [R7]
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B CONFIG3_START
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ANADAT_CHECKSUM2_ERR
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B ANADAT_CHECKSUM2_ERR
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;-------------------------------;
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;; 2. Load ANA_REG10 information
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CONFIG3_START
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LDR R7, =0x40014240
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LDR R0, =0x80DE0
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LDR R0, [R0]
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LDR R1, =0x80DE4
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LDR R1, [R1]
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MVNS R1, R1
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CMP R1, R0
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BEQ ANADAT10_CHECKSUM1_OK
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B ANADAT10_CHECKSUM1_ERR
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ANADAT10_CHECKSUM1_OK
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; ANA_REG10
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LDR R1, =0x0FF
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ANDS R1, R0
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STR R1, [R7]
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BX LR
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ANADAT10_CHECKSUM1_ERR
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LDR R0, =0x80DE8
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LDR R0, [R0]
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LDR R1, =0x80DEC
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LDR R1, [R1]
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MVNS R1, R1
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CMP R1, R0
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BEQ ANADAT10_CHECKSUM2_OK
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B ANADAT10_CHECKSUM2_ERR
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ANADAT10_CHECKSUM2_OK
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; ANA_REG10
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LDR R1, =0x0FF
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ANDS R1, R0
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STR R1, [R7]
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BX LR
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ANADAT10_CHECKSUM2_ERR
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B ANADAT10_CHECKSUM2_ERR
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NOP
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ENDP
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ENDIF
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END
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/*********************************** END OF FILE ******************************/
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@ -8,10 +8,15 @@ cwd = GetCurrentDir()
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src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
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src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
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src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c']
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src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_cortex.c']
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src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c']
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#add for startup script
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
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if rtconfig.CROSS_TOOL == 'mdk5':
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src += [cwd + '/CMSIS/Vango/V85xx/Source/Keil5/startup_target.S']
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path = [
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cwd + '/CMSIS/Vango/V85xx/Include',
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@ -0,0 +1,393 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
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<SchemaVersion>2.1</SchemaVersion>
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<Header>### uVision Project, (C) Keil Software</Header>
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<Targets>
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<Target>
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<TargetName>Target 1</TargetName>
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<ToolsetNumber>0x4</ToolsetNumber>
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<ToolsetName>ARM-ADS</ToolsetName>
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<uAC6>0</uAC6>
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<TargetOption>
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<TargetCommonOption>
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<Device>V85XX</Device>
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<Vendor>Generic</Vendor>
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<PackID>Vango.V85XX.4.0.2</PackID>
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<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
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<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:V85XX$Device\Include\V85XX.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:V85XX$SVD\V85XX.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>template</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> </SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> </TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>-1</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>1</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
Loading…
Reference in New Issue