mirror of
https://github.com/RT-Thread/rt-thread.git
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arm926内容整理
This commit is contained in:
shaojinchun
parent
377bbdc833
commit
159def753f
@ -10,6 +10,7 @@
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#define NOINT 0xC0
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#define NOINT 0xC0
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.text
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;/*
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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; */
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@ -206,21 +206,7 @@ int __rt_ffs(int value)
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#elif defined(__GNUC__) || defined(__ICCARM__)
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#elif defined(__GNUC__) || defined(__ICCARM__)
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int __rt_ffs(int value)
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int __rt_ffs(int value)
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{
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{
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register rt_uint32_t x;
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return __builtin_ffs(value);
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if (value == 0)
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return value;
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__asm
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(
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"rsb %[temp], %[val], #0\n"
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"and %[temp], %[temp], %[val]\n"
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"clz %[temp], %[temp]\n"
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"rsb %[temp], %[temp], #32\n"
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:[temp] "=r"(x)
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:[val] "r"(value)
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);
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return x;
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}
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}
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#endif
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#endif
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41
libcpu/arm/arm926/machine.c
Normal file
41
libcpu/arm/arm926/machine.c
Normal file
@ -0,0 +1,41 @@
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/*
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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RT_WEAK void machine_reset(void)
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{
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rt_kprintf("reboot system...\n");
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rt_hw_interrupt_disable();
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while (1);
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}
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RT_WEAK void machine_shutdown(void)
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{
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rt_kprintf("shutdown...\n");
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rt_hw_interrupt_disable();
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while (1);
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}
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@ -5,6 +5,7 @@
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2018-02-08 RT-Thread the first version
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*/
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*/
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#ifndef __MMU_H__
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#ifndef __MMU_H__
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@ -45,5 +46,7 @@ struct mem_desc
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};
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};
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
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void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size);
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void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
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void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
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#endif
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#endif
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@ -11,295 +11,320 @@
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* 2015-06-04 aozima Align stack address to 8 byte.
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* 2015-06-04 aozima Align stack address to 8 byte.
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*/
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*/
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#include "rt_low_level_init.h"
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.equ MODE_USR, 0x10
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.equ MODE_FIQ, 0x11
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.equ MODE_IRQ, 0x12
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.equ MODE_SVC, 0x13
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.equ MODE_ABT, 0x17
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.equ MODE_UND, 0x1B
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.equ MODE_SYS, 0x1F
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.equ MODEMASK, 0x1F
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.equ NOINT, 0xC0
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#define S_FRAME_SIZE (18*4) //72
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.equ I_BIT, 0x80
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.equ F_BIT, 0x40
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@#define S_SPSR (17*4) //SPSR
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.equ UND_STACK_SIZE, 0x00000100
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@#define S_CPSR (16*4) //CPSR
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.equ SVC_STACK_SIZE, 0x00000100
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#define S_PC (15*4) //R15
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.equ ABT_STACK_SIZE, 0x00000100
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@#define S_LR (14*4) //R14
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.equ FIQ_STACK_SIZE, 0x00000100
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@#define S_SP (13*4) //R13
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.equ IRQ_STACK_SIZE, 0x00000100
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.equ SYS_STACK_SIZE, 0x00000100
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@#define S_IP (12*4) //R12
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/*
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@#define S_FP (11*4) //R11
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***************************************
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@#define S_R10 (10*4)
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* Interrupt vector table
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@#define S_R9 (9*4)
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***************************************
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@#define S_R8 (8*4)
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*/
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@#define S_R7 (7*4)
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.section .vectors
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@#define S_R6 (6*4)
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.code 32
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@#define S_R5 (5*4)
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@#define S_R4 (4*4)
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@#define S_R3 (3*4)
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@#define S_R2 (2*4)
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@#define S_R1 (1*4)
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@#define S_R0 (0*4)
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#define MODE_SYS 0x1F
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.global system_vectors
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#define MODE_FIQ 0x11
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system_vectors:
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#define MODE_IRQ 0x12
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ldr pc, _vector_reset
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#define MODE_SVC 0x13
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ldr pc, _vector_undef
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#define MODE_ABT 0x17
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ldr pc, _vector_swi
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#define MODE_UND 0x1B
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ldr pc, _vector_pabt
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#define MODEMASK 0x1F
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ldr pc, _vector_dabt
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ldr pc, _vector_resv
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ldr pc, _vector_irq
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ldr pc, _vector_fiq
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#define NOINT 0xC0
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_vector_reset:
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.word reset
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@;----------------------- Stack and Heap Definitions ---------------------------
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_vector_undef:
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.section .nobss, "w"
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.word vector_undef
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_vector_swi:
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.space UND_STK_SIZE
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.word vector_swi
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.align 3
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_vector_pabt:
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.global UND_STACK_START
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.word vector_pabt
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UND_STACK_START:
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_vector_dabt:
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.word vector_dabt
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.space ABT_STK_SIZE
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_vector_resv:
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.align 3
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.word vector_resv
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.global ABT_STACK_START
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_vector_irq:
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ABT_STACK_START:
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.word vector_irq
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_vector_fiq:
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.space FIQ_STK_SIZE
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.word vector_fiq
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.align 3
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.global FIQ_STACK_START
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FIQ_STACK_START:
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.space IRQ_STK_SIZE
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.align 3
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.global IRQ_STACK_START
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IRQ_STACK_START:
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.skip SYS_STK_SIZE
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.align 3
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.global SYS_STACK_START
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SYS_STACK_START:
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.space SVC_STK_SIZE
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.align 3
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.global SVC_STACK_START
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SVC_STACK_START:
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@;--------------Jump vector table-----------------------------------------------
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.section .init, "ax"
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.arm
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.global start
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start:
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LDR PC, vector_reset
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LDR PC, vector_undef
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LDR PC, vector_swi
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LDR PC, vector_pabt
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LDR PC, vector_dabt
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LDR PC, vector_resv
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LDR PC, vector_irq
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LDR PC, vector_fiq
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vector_reset:
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.word Reset_Handler
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vector_undef:
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.word Undef_Handler
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vector_swi:
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.word SWI_Handler
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vector_pabt:
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.word PAbt_Handler
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vector_dabt:
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.word DAbt_Handler
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vector_resv:
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.word Resv_Handler
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vector_irq:
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.word IRQ_Handler
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vector_fiq:
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.word FIQ_Handler
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.balignl 16,0xdeadbeef
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.balignl 16,0xdeadbeef
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@;----------------- Reset Handler ---------------------------------------------
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/*
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.global rt_low_level_init
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***************************************
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.global main
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* Stack and Heap Definitions
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.global Reset_Handler
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***************************************
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Reset_Handler:
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*/
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@; Set the cpu to SVC32 mode
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.section .data
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MRS R0, CPSR
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.space UND_STACK_SIZE
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BIC R0, R0, #MODEMASK
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.align 3
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ORR R0, R0, #MODE_SVC|NOINT
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.global und_stack_start
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MSR CPSR_cxsf, R0
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und_stack_start:
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@; Set CO-Processor
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.space ABT_STACK_SIZE
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@; little-end锛宒isbale I/D Cache MMU, vector table is 0x00000000
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.align 3
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MRC P15, 0, R0, C1, C0, 0 @; Read CP15
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.global abt_stack_start
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LDR R1, =0x00003085 @; set clear bits
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abt_stack_start:
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BIC R0, R0, R1
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MCR P15, 0, R0, C1, C0, 0 @; Write CP15
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@; Call low level init function,
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.space FIQ_STACK_SIZE
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@; disable and clear all IRQs, Init MMU, Init interrupt controller, etc.
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.align 3
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LDR SP, =SVC_STACK_START
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.global fiq_stack_start
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LDR R0, =rt_low_level_init
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fiq_stack_start:
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BLX R0
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|
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Setup_Stack:
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.space IRQ_STACK_SIZE
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@; Setup Stack for each mode
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.align 3
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MRS R0, CPSR
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.global irq_stack_start
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BIC R0, R0, #MODEMASK
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irq_stack_start:
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|
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ORR R1, R0, #MODE_UND|NOINT
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.skip SYS_STACK_SIZE
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MSR CPSR_cxsf, R1 @; Undef mode
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.align 3
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LDR SP, =UND_STACK_START
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.global sys_stack_start
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sys_stack_start:
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|
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ORR R1, R0, #MODE_ABT|NOINT
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.space SVC_STACK_SIZE
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MSR CPSR_cxsf, R1 @; Abort mode
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.align 3
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LDR SP, =ABT_STACK_START
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.global svc_stack_start
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svc_stack_start:
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|
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ORR R1, R0, #MODE_IRQ|NOINT
|
/*
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MSR CPSR_cxsf, R1 @; IRQ mode
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***************************************
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LDR SP, =IRQ_STACK_START
|
* Startup Code
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|
***************************************
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|
*/
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|
.section .text
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.global reset
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|
reset:
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|
/* Enter svc mode and mask interrupts */
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|
mrs r0, cpsr
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|
bic r0, r0, #MODEMASK
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orr r0, r0, #MODE_SVC|NOINT
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|
msr cpsr_cxsf, r0
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|
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ORR R1, R0, #MODE_FIQ|NOINT
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/* init cpu */
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MSR CPSR_cxsf, R1 @; FIQ mode
|
bl cpu_init_crit
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LDR SP, =FIQ_STACK_START
|
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|
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ORR R1, R0, #MODE_SYS|NOINT
|
/* todo:copyself to link address */
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MSR CPSR_cxsf,R1 @; SYS/User mode
|
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LDR SP, =SYS_STACK_START
|
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|
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ORR R1, R0, #MODE_SVC|NOINT
|
/* Copy vector to the correct address */
|
||||||
MSR CPSR_cxsf, R1 @; SVC mode
|
ldr r0, =system_vectors
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||||||
LDR SP, =SVC_STACK_START
|
mrc p15, 0, r2, c1, c0, 0
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||||||
|
ands r2, r2, #(1 << 13)
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||||||
|
ldreq r1, =0x00000000
|
||||||
|
ldrne r1, =0xffff0000
|
||||||
|
ldmia r0!, {r2-r8, r10}
|
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|
stmia r1!, {r2-r8, r10}
|
||||||
|
ldmia r0!, {r2-r8, r10}
|
||||||
|
stmia r1!, {r2-r8, r10}
|
||||||
|
|
||||||
@; clear .bss
|
/* turn off the watchdog */
|
||||||
MOV R0, #0 @; get a zero
|
ldr r0, =0x01C20CB8
|
||||||
LDR R1, =__bss_start__ @; bss start
|
mov r1, #0x0
|
||||||
LDR R2, =__bss_end__ @; bss end
|
str r1, [r0]
|
||||||
|
|
||||||
|
/* mask all IRQs source */
|
||||||
|
ldr r1, =0xffffffff
|
||||||
|
ldr r0, =0x01C20430
|
||||||
|
str r1, [r0], #0x04
|
||||||
|
str r1, [r0]
|
||||||
|
|
||||||
|
/* Call low level init function */
|
||||||
|
ldr sp, =svc_stack_start
|
||||||
|
ldr r0, =rt_low_level_init
|
||||||
|
blx r0
|
||||||
|
|
||||||
|
/* init stack */
|
||||||
|
bl stack_setup
|
||||||
|
|
||||||
|
/* clear bss */
|
||||||
|
mov r0, #0
|
||||||
|
ldr r1, =__bss_start
|
||||||
|
ldr r2, =__bss_end
|
||||||
|
|
||||||
bss_clear_loop:
|
bss_clear_loop:
|
||||||
CMP R1, R2 @; check if data to clear
|
cmp r1, r2
|
||||||
STRLO R0, [R1], #4 @; clear 4 bytes
|
strlo r0, [r1], #4
|
||||||
BLO bss_clear_loop @; loop until done
|
blo bss_clear_loop
|
||||||
|
|
||||||
@; call C++ constructors of global objects
|
/* call c++ constructors of global objects */
|
||||||
LDR R0, =__ctors_start__
|
/*
|
||||||
LDR R1, =__ctors_end__
|
ldr r0, =__ctors_start__
|
||||||
|
ldr r1, =__ctors_end__
|
||||||
|
|
||||||
ctor_loop:
|
ctor_loop:
|
||||||
CMP R0, R1
|
cmp r0, r1
|
||||||
BEQ ctor_end
|
beq ctor_end
|
||||||
LDR R2, [R0], #4
|
ldr r2, [r0], #4
|
||||||
STMFD SP!, {R0-R1}
|
stmfd sp!, {r0-r1}
|
||||||
MOV LR, PC
|
mov lr, pc
|
||||||
BX R2
|
bx r2
|
||||||
LDMFD SP!, {R0-R1}
|
ldmfd sp!, {r0-r1}
|
||||||
B ctor_loop
|
b ctor_loop
|
||||||
ctor_end:
|
ctor_end:
|
||||||
|
*/
|
||||||
|
/* start RT-Thread Kernel */
|
||||||
|
ldr pc, _rtthread_startup
|
||||||
|
_rtthread_startup:
|
||||||
|
.word rtthread_startup
|
||||||
|
|
||||||
@; Enter the C code
|
|
||||||
LDR R0, =rtthread_startup
|
|
||||||
BLX R0
|
|
||||||
|
|
||||||
@;----------------- Exception Handler -----------------------------------------
|
|
||||||
.global rt_hw_trap_udef
|
|
||||||
.global rt_hw_trap_swi
|
|
||||||
.global rt_hw_trap_pabt
|
|
||||||
.global rt_hw_trap_dabt
|
|
||||||
.global rt_hw_trap_resv
|
|
||||||
.global rt_hw_trap_irq
|
|
||||||
.global rt_hw_trap_fiq
|
|
||||||
|
|
||||||
.global rt_interrupt_enter
|
cpu_init_crit:
|
||||||
.global rt_interrupt_leave
|
/* invalidate I/D caches */
|
||||||
.global rt_thread_switch_interrupt_flag
|
mov r0, #0
|
||||||
.global rt_interrupt_from_thread
|
mcr p15, 0, r0, c7, c7, 0
|
||||||
.global rt_interrupt_to_thread
|
mcr p15, 0, r0, c8, c7, 0
|
||||||
|
|
||||||
.align 5
|
/* disable MMU stuff and caches */
|
||||||
Undef_Handler:
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
SUB SP, SP, #S_FRAME_SIZE
|
bic r0, r0, #0x00002300
|
||||||
STMIA SP, {R0 - R12} @; Calling R0-R12
|
bic r0, r0, #0x00000087
|
||||||
ADD R8, SP, #S_PC
|
orr r0, r0, #0x00000002
|
||||||
STMDB R8, {SP, LR} @; Calling SP, LR
|
orr r0, r0, #0x00001000
|
||||||
STR LR, [R8, #0] @; Save calling PC
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
MRS R6, SPSR
|
|
||||||
STR R6, [R8, #4] @; Save CPSR
|
|
||||||
STR R0, [R8, #8] @; Save SPSR
|
|
||||||
MOV R0, SP
|
|
||||||
BL rt_hw_trap_udef
|
|
||||||
|
|
||||||
.align 5
|
bx lr
|
||||||
SWI_Handler:
|
|
||||||
BL rt_hw_trap_swi
|
|
||||||
|
|
||||||
.align 5
|
stack_setup:
|
||||||
PAbt_Handler:
|
/* Setup Stack for each mode */
|
||||||
BL rt_hw_trap_pabt
|
mrs r0, cpsr
|
||||||
|
bic r0, r0, #MODEMASK
|
||||||
|
|
||||||
.align 5
|
orr r1, r0, #MODE_UND|NOINT
|
||||||
DAbt_Handler:
|
msr cpsr_cxsf, r1
|
||||||
SUB SP, SP, #S_FRAME_SIZE
|
ldr sp, =und_stack_start
|
||||||
STMIA SP, {R0 - R12} @; Calling R0-R12
|
|
||||||
ADD R8, SP, #S_PC
|
|
||||||
STMDB R8, {SP, LR} @; Calling SP, LR
|
|
||||||
STR LR, [R8, #0] @; Save calling PC
|
|
||||||
MRS R6, SPSR
|
|
||||||
STR R6, [R8, #4] @; Save CPSR
|
|
||||||
STR R0, [R8, #8] @; Save SPSR
|
|
||||||
MOV R0, SP
|
|
||||||
BL rt_hw_trap_dabt
|
|
||||||
|
|
||||||
.align 5
|
orr r1, r0, #MODE_ABT|NOINT
|
||||||
Resv_Handler:
|
msr cpsr_cxsf, r1
|
||||||
BL rt_hw_trap_resv
|
ldr sp, =abt_stack_start
|
||||||
|
|
||||||
.align 5
|
orr r1, r0, #MODE_IRQ|NOINT
|
||||||
FIQ_Handler:
|
msr cpsr_cxsf, r1
|
||||||
STMFD SP!, {R0-R7,LR}
|
ldr sp, =irq_stack_start
|
||||||
BL rt_hw_trap_fiq
|
|
||||||
LDMFD SP!, {R0-R7,LR}
|
|
||||||
SUBS PC, LR, #4
|
|
||||||
|
|
||||||
.align 5
|
orr r1, r0, #MODE_FIQ|NOINT
|
||||||
IRQ_Handler:
|
msr cpsr_cxsf, r1
|
||||||
STMFD SP!, {R0-R12,LR}
|
ldr sp, =fiq_stack_start
|
||||||
BL rt_interrupt_enter
|
|
||||||
BL rt_hw_trap_irq
|
|
||||||
BL rt_interrupt_leave
|
|
||||||
|
|
||||||
@; If rt_thread_switch_interrupt_flag set,
|
orr r1, r0, #MODE_SYS|NOINT
|
||||||
@; jump to rt_hw_context_switch_interrupt_do and don't return
|
msr cpsr_cxsf,r1
|
||||||
LDR R0, =rt_thread_switch_interrupt_flag
|
ldr sp, =sys_stack_start
|
||||||
LDR R1, [R0]
|
|
||||||
CMP R1, #1
|
|
||||||
BEQ rt_hw_context_switch_interrupt_do
|
|
||||||
|
|
||||||
LDMFD SP!, {R0-R12,LR}
|
orr r1, r0, #MODE_SVC|NOINT
|
||||||
SUBS PC, LR, #4
|
msr cpsr_cxsf, r1
|
||||||
|
ldr sp, =svc_stack_start
|
||||||
|
|
||||||
|
bx lr
|
||||||
|
|
||||||
|
/*
|
||||||
|
***************************************
|
||||||
|
* exception handlers
|
||||||
|
***************************************
|
||||||
|
*/
|
||||||
|
/* Interrupt */
|
||||||
|
vector_fiq:
|
||||||
|
stmfd sp!,{r0-r7,lr}
|
||||||
|
bl rt_hw_trap_fiq
|
||||||
|
ldmfd sp!,{r0-r7,lr}
|
||||||
|
subs pc, lr, #4
|
||||||
|
|
||||||
|
vector_irq:
|
||||||
|
stmfd sp!, {r0-r12,lr}
|
||||||
|
|
||||||
|
bl rt_interrupt_enter
|
||||||
|
bl rt_hw_trap_irq
|
||||||
|
bl rt_interrupt_leave
|
||||||
|
|
||||||
|
ldr r0, =rt_thread_switch_interrupt_flag
|
||||||
|
ldr r1, [r0]
|
||||||
|
cmp r1, #1
|
||||||
|
beq rt_hw_context_switch_interrupt_do
|
||||||
|
|
||||||
|
ldmfd sp!, {r0-r12,lr}
|
||||||
|
subs pc, lr, #4
|
||||||
|
|
||||||
@;------ void rt_hw_context_switch_interrupt_do(rt_base_t flag) -----------------
|
|
||||||
rt_hw_context_switch_interrupt_do:
|
rt_hw_context_switch_interrupt_do:
|
||||||
MOV R1, #0 @; Clear flag
|
mov r1, #0
|
||||||
STR R1, [R0] @; Save to flag variable
|
str r1, [r0]
|
||||||
|
|
||||||
LDMFD SP!, {R0-R12,LR} @; Reload saved registers
|
mov r1, sp
|
||||||
STMFD SP, {R0-R2} @; Save R0-R2
|
add sp, sp, #4*4
|
||||||
SUB R1, SP, #4*3 @; Save old task's SP to R1
|
ldmfd sp!, {r4-r12,lr}
|
||||||
SUB R2, LR, #4 @; Save old task's PC to R2
|
mrs r0, spsr
|
||||||
|
sub r2, lr, #4
|
||||||
|
|
||||||
MRS R0, SPSR @; Get CPSR of interrupt thread
|
msr cpsr_c, #I_BIT|F_BIT|MODE_SVC
|
||||||
|
|
||||||
MSR CPSR_c, #MODE_SVC|NOINT @; Switch to SVC mode and no interrupt
|
stmfd sp!, {r2}
|
||||||
|
stmfd sp!, {r4-r12,lr}
|
||||||
|
ldmfd r1, {r1-r4}
|
||||||
|
stmfd sp!, {r1-r4}
|
||||||
|
stmfd sp!, {r0}
|
||||||
|
|
||||||
STMFD SP!, {R2} @; Push old task's PC
|
ldr r4, =rt_interrupt_from_thread
|
||||||
STMFD SP!, {R3-R12,LR} @; Push old task's LR,R12-R3
|
ldr r5, [r4]
|
||||||
LDMFD R1, {R1-R3}
|
str sp, [r5]
|
||||||
STMFD SP!, {R1-R3} @; Push old task's R2-R0
|
|
||||||
STMFD SP!, {R0} @; Push old task's CPSR
|
|
||||||
|
|
||||||
LDR R4, =rt_interrupt_from_thread
|
ldr r6, =rt_interrupt_to_thread
|
||||||
LDR R5, [R4] @; R5 = stack ptr in old tasks's TCB
|
ldr r6, [r6]
|
||||||
STR SP, [R5] @; Store SP in preempted tasks's TCB
|
ldr sp, [r6]
|
||||||
|
|
||||||
LDR R6, =rt_interrupt_to_thread
|
ldmfd sp!, {r4}
|
||||||
LDR R6, [R6] @; R6 = stack ptr in new tasks's TCB
|
msr spsr_cxsf, r4
|
||||||
LDR SP, [R6] @; Get new task's stack pointer
|
|
||||||
|
|
||||||
LDMFD SP!, {R4} @; Pop new task's SPSR
|
ldmfd sp!, {r0-r12,lr,pc}^
|
||||||
MSR SPSR_cxsf, R4
|
|
||||||
|
|
||||||
LDMFD SP!, {R0-R12,LR,PC}^ @; pop new task's R0-R12,LR & PC SPSR 2 CPSR
|
/* Exception */
|
||||||
|
.macro push_svc_reg
|
||||||
|
sub sp, sp, #17 * 4
|
||||||
|
stmia sp, {r0 - r12}
|
||||||
|
mov r0, sp
|
||||||
|
mrs r6, spsr
|
||||||
|
str lr, [r0, #15*4]
|
||||||
|
str r6, [r0, #16*4]
|
||||||
|
str sp, [r0, #13*4]
|
||||||
|
str lr, [r0, #14*4]
|
||||||
|
.endm
|
||||||
|
|
||||||
|
vector_swi:
|
||||||
|
push_svc_reg
|
||||||
|
bl rt_hw_trap_swi
|
||||||
|
b .
|
||||||
|
|
||||||
|
vector_undef:
|
||||||
|
push_svc_reg
|
||||||
|
bl rt_hw_trap_udef
|
||||||
|
b .
|
||||||
|
|
||||||
|
vector_pabt:
|
||||||
|
push_svc_reg
|
||||||
|
bl rt_hw_trap_pabt
|
||||||
|
b .
|
||||||
|
|
||||||
|
vector_dabt:
|
||||||
|
push_svc_reg
|
||||||
|
bl rt_hw_trap_dabt
|
||||||
|
b .
|
||||||
|
|
||||||
|
vector_resv:
|
||||||
|
push_svc_reg
|
||||||
|
bl rt_hw_trap_resv
|
||||||
|
b .
|
||||||
|
|||||||
@ -41,7 +41,11 @@ struct rt_hw_register
|
|||||||
rt_uint32_t cpsr;
|
rt_uint32_t cpsr;
|
||||||
rt_uint32_t ORIG_r0;
|
rt_uint32_t ORIG_r0;
|
||||||
};
|
};
|
||||||
|
static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
|
||||||
|
void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
|
||||||
|
{
|
||||||
|
rt_exception_hook = exception_handle;
|
||||||
|
}
|
||||||
/**
|
/**
|
||||||
* this function will show registers of CPU
|
* this function will show registers of CPU
|
||||||
*
|
*
|
||||||
@ -74,6 +78,13 @@ void rt_hw_show_register (struct rt_hw_register *regs)
|
|||||||
*/
|
*/
|
||||||
void rt_hw_trap_udef(struct rt_hw_register *regs)
|
void rt_hw_trap_udef(struct rt_hw_register *regs)
|
||||||
{
|
{
|
||||||
|
if (rt_exception_hook != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
result = rt_exception_hook(regs);
|
||||||
|
if (result == RT_EOK) return;
|
||||||
|
}
|
||||||
rt_hw_show_register(regs);
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
rt_kprintf("undefined instruction\n");
|
rt_kprintf("undefined instruction\n");
|
||||||
@ -96,6 +107,13 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
|
|||||||
*/
|
*/
|
||||||
void rt_hw_trap_swi(struct rt_hw_register *regs)
|
void rt_hw_trap_swi(struct rt_hw_register *regs)
|
||||||
{
|
{
|
||||||
|
if (rt_exception_hook != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
result = rt_exception_hook(regs);
|
||||||
|
if (result == RT_EOK) return;
|
||||||
|
}
|
||||||
rt_hw_show_register(regs);
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
rt_kprintf("software interrupt\n");
|
rt_kprintf("software interrupt\n");
|
||||||
@ -112,6 +130,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
|
|||||||
*/
|
*/
|
||||||
void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
||||||
{
|
{
|
||||||
|
if (rt_exception_hook != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
result = rt_exception_hook(regs);
|
||||||
|
if (result == RT_EOK) return;
|
||||||
|
}
|
||||||
rt_hw_show_register(regs);
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
rt_kprintf("prefetch abort\n");
|
rt_kprintf("prefetch abort\n");
|
||||||
@ -133,6 +158,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
|
|||||||
*/
|
*/
|
||||||
void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
||||||
{
|
{
|
||||||
|
if (rt_exception_hook != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
result = rt_exception_hook(regs);
|
||||||
|
if (result == RT_EOK) return;
|
||||||
|
}
|
||||||
rt_hw_show_register(regs);
|
rt_hw_show_register(regs);
|
||||||
|
|
||||||
rt_kprintf("data abort\n");
|
rt_kprintf("data abort\n");
|
||||||
@ -153,55 +185,26 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
|
|||||||
*/
|
*/
|
||||||
void rt_hw_trap_resv(struct rt_hw_register *regs)
|
void rt_hw_trap_resv(struct rt_hw_register *regs)
|
||||||
{
|
{
|
||||||
|
if (rt_exception_hook != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_err_t result;
|
||||||
|
|
||||||
|
result = rt_exception_hook(regs);
|
||||||
|
if (result == RT_EOK) return;
|
||||||
|
}
|
||||||
rt_kprintf("not used\n");
|
rt_kprintf("not used\n");
|
||||||
rt_hw_show_register(regs);
|
rt_hw_show_register(regs);
|
||||||
rt_hw_cpu_shutdown();
|
rt_hw_cpu_shutdown();
|
||||||
}
|
}
|
||||||
|
|
||||||
extern struct rt_irq_desc irq_desc[];
|
extern void rt_interrupt_dispatch(void);
|
||||||
extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
|
|
||||||
extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
|
|
||||||
|
|
||||||
void rt_hw_trap_irq()
|
void rt_hw_trap_irq(void)
|
||||||
{
|
{
|
||||||
rt_isr_handler_t isr_func;
|
rt_interrupt_dispatch();
|
||||||
rt_uint32_t irq;
|
|
||||||
void *param;
|
|
||||||
|
|
||||||
/* get irq number */
|
|
||||||
irq = rt_hw_interrupt_get_active(INT_IRQ);
|
|
||||||
|
|
||||||
/* get interrupt service routine */
|
|
||||||
isr_func = irq_desc[irq].handler;
|
|
||||||
param = irq_desc[irq].param;
|
|
||||||
|
|
||||||
/* turn to interrupt service routine */
|
|
||||||
isr_func(irq, param);
|
|
||||||
|
|
||||||
rt_hw_interrupt_ack(INT_IRQ, irq);
|
|
||||||
#ifdef RT_USING_INTERRUPT_INFO
|
|
||||||
irq_desc[irq].counter ++;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_trap_fiq()
|
void rt_hw_trap_fiq(void)
|
||||||
{
|
{
|
||||||
rt_isr_handler_t isr_func;
|
rt_interrupt_dispatch();
|
||||||
rt_uint32_t irq;
|
|
||||||
void *param;
|
|
||||||
|
|
||||||
/* get irq number */
|
|
||||||
irq = rt_hw_interrupt_get_active(INT_FIQ);
|
|
||||||
|
|
||||||
/* get interrupt service routine */
|
|
||||||
isr_func = irq_desc[irq].handler;
|
|
||||||
param = irq_desc[irq].param;
|
|
||||||
|
|
||||||
/* turn to interrupt service routine */
|
|
||||||
isr_func(irq, param);
|
|
||||||
|
|
||||||
rt_hw_interrupt_ack(INT_FIQ, irq);
|
|
||||||
#ifdef RT_USING_INTERRUPT_INFO
|
|
||||||
irq_desc[irq].counter ++;
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user