support gpio interrupt
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1539 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
luohui2320@gmail.com
parent
7beb4cd4cf
commit
1586a43f6c
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@ -0,0 +1,21 @@
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#ifndef __AT91_PDC_H__
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#define __AT91_PDC_H__
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#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
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#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
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#define AT91_PDC_TPR 0x108 /* Transmit Pointer Register */
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#define AT91_PDC_TCR 0x10c /* Transmit Counter Register */
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#define AT91_PDC_RNPR 0x110 /* Receive Next Pointer Register */
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#define AT91_PDC_RNCR 0x114 /* Receive Next Counter Register */
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#define AT91_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
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#define AT91_PDC_TNCR 0x11c /* Transmit Next Counter Register */
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#define AT91_PDC_PTCR 0x120 /* Transfer Control Register */
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#define AT91_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
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#define AT91_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
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#define AT91_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
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#define AT91_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
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#define AT91_PDC_PTSR 0x124 /* Transfer Status Register */
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#endif
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@ -29,8 +29,10 @@ extern "C" {
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#include "at91_pio.h"
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#include "at91_serial.h"
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#include "at91_tc.h"
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#include "at91_pdc.h"
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#include "io.h"
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#include "irq.h"
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#include "gpio.h"
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/*
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* Peripheral identifiers/interrupts.
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@ -0,0 +1,119 @@
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#include <at91_aic.h>
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#define PIN_BASE AIC_IRQS
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#define MAX_GPIO_BANKS 3
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#define PIN_IRQS (MAX_GPIO_BANKS*32)
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/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
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#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
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#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
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#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
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#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
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#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
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#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
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#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
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#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
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#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
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#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9)
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#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10)
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#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11)
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#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12)
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#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13)
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#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14)
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#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15)
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#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16)
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#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17)
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#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18)
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#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19)
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#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20)
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#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21)
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#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22)
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#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23)
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#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24)
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#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25)
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#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26)
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#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27)
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#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28)
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#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29)
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#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30)
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#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31)
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#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0)
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#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1)
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#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2)
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#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3)
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#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4)
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#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5)
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#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6)
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#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7)
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#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8)
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#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9)
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#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10)
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#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11)
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#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12)
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#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13)
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#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14)
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#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15)
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#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16)
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#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17)
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#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18)
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#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19)
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#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20)
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#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21)
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#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22)
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#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23)
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#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24)
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#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25)
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#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26)
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#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27)
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#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28)
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#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29)
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#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30)
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#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31)
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#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0)
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#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1)
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#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2)
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#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3)
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#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4)
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#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5)
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#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6)
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#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7)
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#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8)
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#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9)
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#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10)
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#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11)
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#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12)
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#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13)
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#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14)
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#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15)
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#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16)
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#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17)
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#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18)
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#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19)
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#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20)
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#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21)
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#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22)
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#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23)
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#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24)
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#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25)
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#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26)
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#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27)
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#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28)
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#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29)
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#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30)
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#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
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static inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
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{
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return gpio;
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}
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#endif
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@ -15,7 +15,7 @@
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#include <rtthread.h>
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#include "at91sam926x.h"
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#define MAX_HANDLERS 32
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#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
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extern rt_uint32_t rt_interrupt_nest;
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@ -82,6 +82,39 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
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return RT_NULL;
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}
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rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector)
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{
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rt_uint32_t isr, pio, irq_n;
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if (vector == AT91SAM9260_ID_PIOA)
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{
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pio = AT91_PIOA;
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irq_n = AIC_IRQS;
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}
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else if (vector == AT91SAM9260_ID_PIOB)
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{
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pio = AT91_PIOB;
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irq_n = AIC_IRQS + 32;
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}
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else if (vector == AT91SAM9260_ID_PIOC)
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{
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pio = AT91_PIOC;
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irq_n = AIC_IRQS + 32*2;
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}
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else
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return;
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isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
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while (isr)
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{
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if (isr & 1)
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{
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isr_table[irq_n](irq_n);
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}
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isr >>= 1;
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irq_n++;
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}
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}
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/*
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* Initialize the AIC interrupt controller.
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*/
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@ -93,7 +126,7 @@ void at91_aic_init(rt_uint32_t *priority)
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* The IVR is used by macro get_irqnr_and_base to read and verify.
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* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
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*/
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for (i = 0; i < MAX_HANDLERS; i++) {
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for (i = 0; i < AIC_IRQS; i++) {
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/* Put irq number in Source Vector Register: */
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at91_sys_write(AT91_AIC_SVR(i), i);
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/* Active Low interrupt, with the specified priority */
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@ -109,7 +142,7 @@ void at91_aic_init(rt_uint32_t *priority)
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* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
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* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
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*/
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at91_sys_write(AT91_AIC_SPU, MAX_HANDLERS);
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at91_sys_write(AT91_AIC_SPU, AIC_IRQS);
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/* No debugging in AIC: Debug (Protect) Control Register */
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at91_sys_write(AT91_AIC_DCR, 0);
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@ -120,6 +153,22 @@ void at91_aic_init(rt_uint32_t *priority)
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}
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static void at91_gpio_irq_init()
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{
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at91_sys_write(AT91_PIOA+PIO_IDR, 0xffffffff);
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at91_sys_write(AT91_PIOB+PIO_IDR, 0xffffffff);
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at91_sys_write(AT91_PIOC+PIO_IDR, 0xffffffff);
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isr_table[AT91SAM9260_ID_PIOA] = (rt_isr_handler_t)at91_gpio_irq_handle;
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isr_table[AT91SAM9260_ID_PIOB] = (rt_isr_handler_t)at91_gpio_irq_handle;
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isr_table[AT91SAM9260_ID_PIOC] = (rt_isr_handler_t)at91_gpio_irq_handle;
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOB);
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rt_hw_interrupt_umask(AT91SAM9260_ID_PIOC);
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}
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/**
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* This function will initialize hardware interrupt
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*/
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@ -141,6 +190,8 @@ void rt_hw_interrupt_init(void)
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isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handle;
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}
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at91_gpio_irq_init();
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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@ -148,14 +199,69 @@ void rt_hw_interrupt_init(void)
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rt_thread_switch_interrput_flag = 0;
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}
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static void at91_gpio_irq_mask(int irq)
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{
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rt_uint32_t pin, pio, bank;
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bank = (irq - AIC_IRQS)>>5;
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if (bank == 0)
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{
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pio = AT91_PIOA;
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}
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else if (bank == 1)
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{
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pio = AT91_PIOB;
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}
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else if (bank == 2)
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{
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pio = AT91_PIOC;
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}
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else
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return;
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pin = 1 << ((irq - AIC_IRQS) & 31);
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at91_sys_write(pio+PIO_IDR, pin);
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}
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/**
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* This function will mask a interrupt.
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* @param vector the interrupt number
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*/
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void rt_hw_interrupt_mask(int irq)
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{
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/* Disable interrupt on AIC */
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at91_sys_write(AT91_AIC_IDCR, 1 << irq);
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_mask(irq);
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}
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else
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{
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/* Disable interrupt on AIC */
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at91_sys_write(AT91_AIC_IDCR, 1 << irq);
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}
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}
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static void at91_gpio_irq_umask(int irq)
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{
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rt_uint32_t pin, pio, bank;
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bank = (irq - AIC_IRQS)>>5;
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if (bank == 0)
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{
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pio = AT91_PIOA;
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}
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else if (bank == 1)
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{
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pio = AT91_PIOB;
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}
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else if (bank == 2)
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{
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pio = AT91_PIOC;
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}
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else
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return;
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pin = 1 << ((irq - AIC_IRQS) & 31);
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at91_sys_write(pio+PIO_IER, pin);
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}
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/**
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@ -164,8 +270,15 @@ void rt_hw_interrupt_mask(int irq)
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*/
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void rt_hw_interrupt_umask(int irq)
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{
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/* Enable interrupt on AIC */
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at91_sys_write(AT91_AIC_IECR, 1 << irq);
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if (irq >= AIC_IRQS)
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{
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at91_gpio_irq_umask(irq);
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}
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else
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{
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/* Enable interrupt on AIC */
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at91_sys_write(AT91_AIC_IECR, 1 << irq);
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}
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}
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/**
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