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[bsp/max32660] add the keil project

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This commit is contained in:
supperthomas 2021-02-11 16:18:33 +08:00
parent 864d1dd703
commit 153b03f310
73 changed files with 37442 additions and 809 deletions
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47
bsp/maxim/MAX32660_EVSYS/.config
View File

@ -64,7 +64,9 @@ CONFIG_RT_USING_HEAP=y
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
# CONFIG_RT_USING_CONSOLE is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@ -72,8 +74,10 @@ CONFIG_RT_VER_NUM=0x40003
#
# RT-Thread Components
#
# CONFIG_RT_USING_COMPONENTS_INIT is not set
# CONFIG_RT_USING_USER_MAIN is not set
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
@ -83,7 +87,21 @@ CONFIG_RT_VER_NUM=0x40003
#
# Command shell
#
# CONFIG_RT_USING_FINSH is not set
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
@ -97,14 +115,14 @@ CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
@ -132,9 +150,9 @@ CONFIG_RT_USING_PIN=y
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
# CONFIG_RT_LIBC_USING_TIME is not set
#
# Network
@ -362,11 +380,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
CONFIG_PKG_USING_NRFX=y
CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
CONFIG_PKG_USING_NRFX_V210=y
# CONFIG_PKG_USING_NRFX_LATEST_VERSION is not set
CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
@ -458,10 +472,15 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
#
# Hardware Drivers Config
#
CONFIG_SOC_MAX32660=y
CONFIG_SOC_MAXIM=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_GPIO is not set
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set

4
bsp/maxim/MAX32660_EVSYS/SConstruct
View File

@ -48,10 +48,10 @@ print(SDK_LIB)
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# include cmsis
#objs.extend(SConscript(os.path.join(libraries_path_prefix, 'cmsis', 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'MAX32660PeriphDriver', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

4
bsp/maxim/MAX32660_EVSYS/applications/application.c
View File

@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2020-04-29 supperthomas first version
* 2021-02-11 supperthomas first version
*
*/
@ -29,4 +29,4 @@ int main(void)
GPIO_OutToggle(&led_pin[0]);
}
return RT_EOK;
}
}

31
bsp/maxim/MAX32660_EVSYS/board/Kconfig
View File

@ -5,7 +5,10 @@ config SOC_MAX32660
config SOC_MAX32660
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select BSP_USING_UART
select BSP_USING_UART1
default y
config SOC_MAXIM
bool
config SOC_MAXIM
@ -16,11 +19,35 @@ menu "On-chip Peripheral Drivers"
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
config BSP_UART0_RX_USING_DMA
bool "Enable UART0 RX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART1
bool "Enable UART1"
default y
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_ON_CHIP_FLASH
select PKG_USING_FAL
bool "Enable on-chip FLASH"
default n
endmenu

31
bsp/maxim/MAX32660_EVSYS/board/SConscript
View File

@ -1,11 +1,28 @@
Import('RTT_ROOT')
Import('rtconfig')
import os
import rtconfig
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
define = ['USE_APP_CONFIG']
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
''')
path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/startup_max32660.S']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH,CPPDEFINES = define)
Return('group')

4
bsp/maxim/MAX32660_EVSYS/board/app_config.h
View File

@ -1,4 +0,0 @@
#ifndef APP_CONFIG_H
#define APP_CONFIG_H
#endif //APP_CONFIG_H

3
bsp/maxim/MAX32660_EVSYS/board/board.c
View File

@ -5,9 +5,10 @@
*
* Change Logs:
* Date Author Notes
* 2020-04-29 supperthomas first version
* 2021-02-11 supperthomas first version
*
*/
#include <rtthread.h>
#include <rthw.h>
#include <stdio.h>

82
bsp/maxim/MAX32660_EVSYS/board/fal_cfg.h
View File

@ -1,82 +0,0 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-05-05 supperthomas this is sample you can change by yourself
*
*/
#ifndef _FAL_CFG_H_
#define _FAL_CFG_H_
#include <rtconfig.h>
#include <board.h>
#if (defined(BSP_USING_QSPI_FLASH)&&defined(BSP_USING_ON_CHIP_FLASH))
#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip"
#define NOR_FLASH_DEV_NAME "norflash0"
extern const struct fal_flash_dev mcu_onchip_flash;
extern struct fal_flash_dev nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&mcu_onchip_flash, \
&nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \
{FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
}
#endif /* FAL_PART_HAS_TABLE_CFG */
#elif defined(BSP_USING_QSPI_FLASH)
#define NOR_FLASH_DEV_NAME "norflash0"
extern struct fal_flash_dev nor_flash0;
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&nor_flash0, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "nor_flash_part_0", NOR_FLASH_DEV_NAME, 0, 1024*1024, 0}, \
{FAL_PART_MAGIC_WORD, "nor_flash_part_1", NOR_FLASH_DEV_NAME, 1024*1024, 7*1024*1024, 0}, \
}
#endif
#elif defined(BSP_USING_ON_CHIP_FLASH)
extern const struct fal_flash_dev mcu_onchip_flash;
#define ON_CHIP_FLASH_DEV_NAME "mcu_onchip"
/* flash device table */
#define FAL_FLASH_DEV_TABLE \
{ \
&mcu_onchip_flash, \
}
/* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */
#define FAL_PART_TABLE \
{ \
{FAL_PART_MAGIC_WORD, "bl", ON_CHIP_FLASH_DEV_NAME, 0, 64*1024, 0}, \
{FAL_PART_MAGIC_WORD, "app_flash", ON_CHIP_FLASH_DEV_NAME, 64*1024, 960*1024, 0}, \
}
#endif
#endif
#endif /* _FAL_CFG_H_ */

104
bsp/maxim/MAX32660_EVSYS/board/linker_scripts/link.lds
View File

@ -1,16 +1,102 @@
/* Linker script to configure memory regions. */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x40000
CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000
MEMORY {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
}
SECTIONS {
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*) /* program code */
*(.rodata*) /* read-only data: "const" */
KEEP(*(.init))
KEEP(*(.fini))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > FLASH
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > FLASH
.data :
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
} > SRAM AT>FLASH
__load_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM
.heap (COPY):
{
. = ALIGN(4);
*(.heap*)
__HeapLimit = ABSOLUTE(__StackLimit);
} > SRAM
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}
INCLUDE "packages/nrfx-v2.1.0/mdk/nrf_common.ld"

715
bsp/maxim/MAX32660_EVSYS/project.uvoptx
View File

@ -26,7 +26,7 @@
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<CLKADS>96000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
@ -117,26 +117,6 @@
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
@ -148,144 +128,19 @@
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MAX32660 -FL040000 -FS00 -FP0($$Device:MAX32660$Flash\MAX32660.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>221</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>7494</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\rtthread\applications/drv_uart.c\221</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>108</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>7106</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\rtthread\applications/drv_uart.c\108</Expression>
</Bp>
<Bp>
<Number>2</Number>
<Type>0</Type>
<LineNumber>91</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>3</Number>
<Type>0</Type>
<LineNumber>92</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>4</Number>
<Type>0</Type>
<LineNumber>206</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>5</Number>
<Type>0</Type>
<LineNumber>209</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
<Bp>
<Number>6</Number>
<Type>0</Type>
<LineNumber>220</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>0</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>0</BreakIfRCount>
<Filename>.\applications\drv_uart.c</Filename>
<ExecCommand></ExecCommand>
<Expression></Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>oflag</ItemText>
</Ww>
<Ww>
<count>1</count>
<WinNumber>1</WinNumber>
<ItemText>flag</ItemText>
</Ww>
</WatchWindow1>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>1</aLwin>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
@ -316,12 +171,6 @@
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<SystemViewers>
<Entry>
<Name>System Viewer\UART1</Name>
<WinId>35905</WinId>
</Entry>
</SystemViewers>
<DebugDescription>
<Enable>1</Enable>
<EnableFlashSeq>1</EnableFlashSeq>
@ -350,246 +199,6 @@
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\CMSIS\system_max32660.c</PathWithFileName>
<FilenameWithoutPath>system_max32660.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\CMSIS\startup_max32660.s</PathWithFileName>
<FilenameWithoutPath>startup_max32660.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</PathWithFileName>
<FilenameWithoutPath>mxc_sys.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c</PathWithFileName>
<FilenameWithoutPath>mxc_assert.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c</PathWithFileName>
<FilenameWithoutPath>mxc_delay.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<File>
<GroupNumber>7</GroupNumber>
<FileNumber>45</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</PathWithFileName>
<FilenameWithoutPath>mxc_sys.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>46</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\nvic_table.c</PathWithFileName>
<FilenameWithoutPath>nvic_table.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>7</GroupNumber>
<FileNumber>47</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\libraries\MAX32660PeriphDriver\Source\uart.c</PathWithFileName>
<FilenameWithoutPath>uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>

213
bsp/maxim/MAX32660_EVSYS/project.uvprojx
View File

@ -335,10 +335,10 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--reduce_paths</MiscControls>
<Define>USE_APP_CONFIG, RT_USING_ARM_LIBC, __RTTHREAD__</Define>
<MiscControls></MiscControls>
<Define>__RTTHREAD__</Define>
<Undefine></Undefine>
<IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;.;..\..\..\include;..\..\..\components\libc\compilers\armlibc;..\..\..\components\libc\compilers\common;..\libraries\CMSIS;..\libraries\MAX32660PeriphDriver\Include;..\..\..\components\finsh</IncludePath>
<IncludePath>applications;.;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;..\libraries\HAL_Drivers;..\..\..\components\finsh;.;..\..\..\include;..\libraries\MAX32660PeriphDriverCMSIS\Device\Maxim\MAX32660\Include;..\libraries\MAX32660PeriphDriver\CMSIS\Core\Include;..\libraries\MAX32660PeriphDriver\Include</IncludePath>
</VariousControls>
</Cads>
<Aads>
@ -353,14 +353,14 @@
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls>--cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74</MiscControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
@ -387,106 +387,6 @@
<FileType>1</FileType>
<FilePath>applications\application.c</FilePath>
</File>
<File>
<FileName>system_max32660.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\CMSIS\system_max32660.c</FilePath>
</File>
<File>
<FileName>startup_max32660.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\CMSIS\startup_max32660.s</FilePath>
</File>
<File>
<FileName>mxc_sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</FilePath>
</File>
<File>
<FileName>mxc_assert.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c</FilePath>
</File>
<File>
<FileName>mxc_delay.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c</FilePath>
</File>
<File>
<FileName>mxc_lock.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c</FilePath>
</File>
<File>
<FileName>mxc_pins.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c</FilePath>
</File>
<File>
<FileName>nvic_table.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\nvic_table.c</FilePath>
</File>
<File>
<FileName>flc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\flc.c</FilePath>
</File>
<File>
<FileName>icc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\icc.c</FilePath>
</File>
<File>
<FileName>lp.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\lp.c</FilePath>
</File>
<File>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\gpio.c</FilePath>
</File>
<File>
<FileName>rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\rtc.c</FilePath>
</File>
<File>
<FileName>tmr.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr.c</FilePath>
</File>
<File>
<FileName>tmr_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\uart.c</FilePath>
</File>
<File>
<FileName>drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>.\applications\drv_uart.c</FilePath>
</File>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
</Group>
<Group>
@ -522,11 +422,6 @@
<Group>
<GroupName>DeviceDrivers</GroupName>
<Files>
<File>
<FileName>pin.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
</File>
<File>
<FileName>serial.c</FileName>
<FileType>1</FileType>
@ -577,6 +472,36 @@
<FileType>1</FileType>
<FilePath>board\board.c</FilePath>
</File>
<File>
<FileName>startup_max32660.s</FileName>
<FileType>2</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\ARM\startup_max32660.s</FilePath>
</File>
<File>
<FileName>drv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\HAL_Drivers\drv_uart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>finsh</GroupName>
<Files>
<File>
<FileName>shell.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\shell.c</FilePath>
</File>
<File>
<FileName>cmd.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\cmd.c</FilePath>
</File>
<File>
<FileName>msh.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\finsh\msh.c</FilePath>
</File>
</Files>
</Group>
<Group>
@ -650,27 +575,77 @@
</Files>
</Group>
<Group>
<GroupName>libc</GroupName>
<GroupName>Libraries</GroupName>
<Files>
<File>
<FileName>libc.c</FileName>
<FileName>system_max32660.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\libc.c</FilePath>
<FilePath>..\libraries\MAX32660PeriphDriver\CMSIS\Device\Maxim\MAX32660\Source\system_max32660.c</FilePath>
</File>
<File>
<FileName>mem_std.c</FileName>
<FileName>gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\mem_std.c</FilePath>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\gpio.c</FilePath>
</File>
<File>
<FileName>stubs.c</FileName>
<FileName>lp.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\armlibc\stubs.c</FilePath>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\lp.c</FilePath>
</File>
<File>
<FileName>time.c</FileName>
<FileName>tmr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\libc\compilers\common\time.c</FilePath>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr.c</FilePath>
</File>
<File>
<FileName>tmr_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\tmr_utils.c</FilePath>
</File>
<File>
<FileName>rtc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\rtc.c</FilePath>
</File>
<File>
<FileName>icc.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\icc.c</FilePath>
</File>
<File>
<FileName>mxc_lock.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_lock.c</FilePath>
</File>
<File>
<FileName>mxc_assert.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_assert.c</FilePath>
</File>
<File>
<FileName>mxc_delay.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_delay.c</FilePath>
</File>
<File>
<FileName>mxc_pins.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_pins.c</FilePath>
</File>
<File>
<FileName>mxc_sys.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\mxc_sys.c</FilePath>
</File>
<File>
<FileName>nvic_table.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\nvic_table.c</FilePath>
</File>
<File>
<FileName>uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\libraries\MAX32660PeriphDriver\Source\uart.c</FilePath>
</File>
</Files>
</Group>

58
bsp/maxim/MAX32660_EVSYS/rtconfig.h
View File

@ -1,32 +1,6 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
#define RT_USING_USER_MAIN
#define RT_TICK_PER_SECOND 1000
#define BSP_USING_UART1
#define BSP_USING_UART0
#define RT_USING_COMPONENTS_INIT
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
@ -36,8 +10,7 @@
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
@ -65,16 +38,36 @@
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
@ -84,15 +77,14 @@
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* Network */
@ -150,8 +142,6 @@
/* peripheral libraries and drivers */
#define PKG_USING_NRFX
#define PKG_USING_NRFX_V210
/* miscellaneous packages */
@ -164,10 +154,12 @@
/* Hardware Drivers Config */
#define SOC_MAX32660
#define SOC_MAXIM
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_UART1
#endif

72
bsp/maxim/MAX32660_EVSYS/rtconfig.py
View File

@ -3,7 +3,7 @@ import os
# toolchains options
ARCH='arm'
CPU='cortex-m4'
CROSS_TOOL='keil'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
@ -13,7 +13,7 @@ if os.getenv('RTT_CC'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'D:/SourceryGCC/bin'
EXEC_PATH = r'C:\Users\XXYYZZ'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil_v5'
@ -53,6 +53,8 @@ if PLATFORM == 'gcc':
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
@ -64,16 +66,15 @@ elif PLATFORM == 'armcc':
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --device DARMSTM'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
DEVICE = ' --cpu Cortex-M4.fp'
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
AFLAGS = DEVICE + ' --apcs=interwork '
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"'
CFLAGS += ' --c99'
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
EXEC_PATH += '/arm/bin40/'
CFLAGS += ' -D__MICROLIB '
AFLAGS += ' --pd "__MICROLIB SETA 1" '
LFLAGS += ' --library_type=microlib '
EXEC_PATH += '/ARM/ARMCC/bin/'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
@ -82,3 +83,52 @@ elif PLATFORM == 'armcc':
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
CXX = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = '-Dewarm'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=VFPv4_sp'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu VFPv4_sp'
AFLAGS += ' -S'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = ' --config "board/linker_scripts/link.icf"'
LFLAGS += ' --entry __iar_program_start'
CXXFLAGS = CFLAGS
EXEC_PATH = EXEC_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'

2
bsp/maxim/MAX32660_EVSYS/template.uvoptx
View File

@ -26,7 +26,7 @@
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<CLKADS>96000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>

12
bsp/maxim/MAX32660_EVSYS/template.uvprojx
View File

@ -10,7 +10,7 @@
<TargetName>rtthread</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
@ -188,7 +188,7 @@
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
@ -335,7 +335,7 @@
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--reduce_paths</MiscControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
@ -353,14 +353,14 @@
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls>--cpreproc_opts=-DBLE_STACK_SUPPORT_REQD,-DNRF_SD_BLE_API_VERSION=4,-DS132,-DSOFTDEVICE_PRESENT,-DSWI_DISABLE0,-DCONFIG_GPIO_AS_PINRESET,-DNRF52,-DNRF52832_XXAA,-DNRF52_PAN_12,-DNRF52_PAN_15,-DNRF52_PAN_20,-DNRF52_PAN_31,-DNRF52_PAN_36,-DNRF52_PAN_51,-DNRF52_PAN_54,-DNRF52_PAN_55,-DNRF52_PAN_58,-DNRF52_PAN_64,-DNRF52_PAN_74</MiscControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
@ -369,7 +369,7 @@
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>

34
bsp/maxim/libraries/HAL_Drivers/SConscript Normal file
View File

@ -0,0 +1,34 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
src += ['drv_soft_i2c.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

9
bsp/maxim/MAX32660_EVSYS/applications/drv_uart.c → bsp/maxim/libraries/HAL_Drivers/drv_uart.c
View File

@ -1,16 +1,19 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-08 Supperthomas first version
* 2021-02-11 supperthomas first version
*
*/
#include "board.h"
#include "uart.h"
#include "rtdevice.h"
#ifdef RT_USING_SERIAL
#define UART0_CONFIG \
{ \
@ -44,7 +47,7 @@ struct mcu_uart
};
#ifdef RT_USING_SERIAL
//#define DRV_DEBUG
//#define LOG_TAG "drv.usart"

0
bsp/maxim/MAX32660_EVSYS/applications/drv_usart.h → bsp/maxim/libraries/HAL_Drivers/drv_usart.h
View File

2
bsp/maxim/libraries/CMSIS/RTE_Components.h → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/RTE_Components.h
View File

@ -19,6 +19,6 @@
#define BOARD EvKit_V1 /* Target Board */
#define RTE_USING_FINSH
#define TARGET 32660 /* Target Device Part Number */
#define TARGET_REV 0x4131 /* Target Device Revision Number */
#define TARGET_REV 0x4131 /* Target Device Revision Number */
#endif /* RTE_COMPONENTS_H */

411
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Core/Include/cachel1_armv7.h Normal file
View File

@ -0,0 +1,411 @@
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.0
* @date 03. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.2.0
* @date 28. January 2020
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2019 IAR Systems
// Copyright (c) 2017-2019 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#endif /* __CMSIS_ICCARM_H__ */

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file pmu_armv8.h
* @brief CMSIS PMU API for Armv8.1-M PMU
* @version V1.0.0
* @date 24. March 2020
******************************************************************************/
/*
* Copyright (c) 2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_PMU_ARMV8_H
#define ARM_PMU_ARMV8_H
/**
* \brief PMU Events
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
* */
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
/** \brief PMU Functions */
__STATIC_INLINE void ARM_PMU_Enable(void);
__STATIC_INLINE void ARM_PMU_Disable(void);
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
/**
\brief Set event to count for PMU eventer counter
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
/**
\brief Enable counters
\param [in] mask Counters to enable
\note Enables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
PMU->CNTENSET = mask;
}
/**
\brief Disable counters
\param [in] mask Counters to enable
\note Disables one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
PMU->CNTENCLR = mask;
}
/**
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
return PMU->CCNTR;
}
/**
\brief Read event counter
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
return PMU->EVCNTR[num];
}
/**
\brief Read counter overflow status
\return Counter overflow status bits for the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
return PMU->OVSSET;
}
/**
\brief Clear counter overflow status
\param [in] mask Counter overflow status bits to clear
\note Clears overflow status bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
PMU->OVSCLR = mask;
}
/**
\brief Enable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to set
\note Sets overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
PMU->INTENSET = mask;
}
/**
\brief Disable counter overflow interrupt request
\param [in] mask Counter overflow interrupt request bits to clear
\note Clears overflow interrupt request bits for one or more of the following:
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
PMU->INTENCLR = mask;
}
/**
\brief Software increment event counter
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
PMU->SWINC = mask;
}
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/**
* @file bbfc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _BBFC_REGS_H_
#define _BBFC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup bbfc
* @defgroup bbfc_registers BBFC_Registers
* @brief Registers, Bit Masks and Bit Positions for the BBFC Peripheral Module.
* @details Battery-Backed Function Control.
*/
/**
* @ingroup bbfc_registers
* Structure type to access the BBFC Registers.
*/
typedef struct {
__IO uint32_t bbfcr0; /**< <tt>\b 0x00:</tt> BBFC BBFCR0 Register */
} mxc_bbfc_regs_t;
/* Register offsets for module BBFC */
/**
* @ingroup bbfc_registers
* @defgroup BBFC_Register_Offsets Register Offsets
* @brief BBFC Peripheral Register Offsets from the BBFC Base Peripheral Address.
* @{
*/
#define MXC_R_BBFC_BBFCR0 ((uint32_t)0x00000000UL) /**< Offset from BBFC Base Address: <tt> 0x0000</tt> */
/**@} end of group bbfc_registers */
/**
* @ingroup bbfc_registers
* @defgroup BBFC_BBFCR0 BBFC_BBFCR0
* @brief Function Control Register 0.
* @{
*/
#define MXC_F_BBFC_BBFCR0_CKPDRV_POS 0 /**< BBFCR0_CKPDRV Position */
#define MXC_F_BBFC_BBFCR0_CKPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKPDRV_POS)) /**< BBFCR0_CKPDRV Mask */
#define MXC_F_BBFC_BBFCR0_CKNPDRV_POS 4 /**< BBFCR0_CKNPDRV Position */
#define MXC_F_BBFC_BBFCR0_CKNPDRV ((uint32_t)(0xFUL << MXC_F_BBFC_BBFCR0_CKNPDRV_POS)) /**< BBFCR0_CKNPDRV Mask */
#define MXC_F_BBFC_BBFCR0_RDSDLLEN_POS 8 /**< BBFCR0_RDSDLLEN Position */
#define MXC_F_BBFC_BBFCR0_RDSDLLEN ((uint32_t)(0x1UL << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS)) /**< BBFCR0_RDSDLLEN Mask */
#define MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS ((uint32_t)0x0UL) /**< BBFCR0_RDSDLLEN_DIS Value */
#define MXC_S_BBFC_BBFCR0_RDSDLLEN_DIS (MXC_V_BBFC_BBFCR0_RDSDLLEN_DIS << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_DIS Setting */
#define MXC_V_BBFC_BBFCR0_RDSDLLEN_EN ((uint32_t)0x1UL) /**< BBFCR0_RDSDLLEN_EN Value */
#define MXC_S_BBFC_BBFCR0_RDSDLLEN_EN (MXC_V_BBFC_BBFCR0_RDSDLLEN_EN << MXC_F_BBFC_BBFCR0_RDSDLLEN_POS) /**< BBFCR0_RDSDLLEN_EN Setting */
/**@} end of group BBFC_BBFCR0_Register */
#ifdef __cplusplus
}
#endif
#endif /* _BBFC_REGS_H_ */

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/**
* @file bbsir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _BBSIR_REGS_H_
#define _BBSIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup bbsir
* @defgroup bbsir_registers BBSIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the BBSIR Peripheral Module.
* @details Battery-Backed Registers.
*/
/**
* @ingroup bbsir_registers
* Structure type to access the BBSIR Registers.
*/
typedef struct {
__IO uint32_t rsv0; /**< <tt>\b 0x00:</tt> BBSIR RSV0 Register */
__R uint32_t rsv_0x4;
__I uint32_t bb_sir2; /**< <tt>\b 0x08:</tt> BBSIR BB_SIR2 Register */
__I uint32_t bb_sir3; /**< <tt>\b 0x0C:</tt> BBSIR BB_SIR3 Register */
} mxc_bbsir_regs_t;
/* Register offsets for module BBSIR */
/**
* @ingroup bbsir_registers
* @defgroup BBSIR_Register_Offsets Register Offsets
* @brief BBSIR Peripheral Register Offsets from the BBSIR Base Peripheral Address.
* @{
*/
#define MXC_R_BBSIR_RSV0 ((uint32_t)0x00000000UL) /**< Offset from BBSIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_BBSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from BBSIR Base Address: <tt> 0x0008</tt> */
#define MXC_R_BBSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from BBSIR Base Address: <tt> 0x000C</tt> */
/**@} end of group bbsir_registers */
#ifdef __cplusplus
}
#endif
#endif /* _BBSIR_REGS_H_ */

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/**
* @file dma_regs.h
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _DMA_REGS_H_
#define _DMA_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup dma
* @defgroup dma_registers DMA_Registers
* @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module.
* @details DMA Controller Fully programmable, chaining capable DMA channels.
*/
/**
* @ingroup dma_registers
* Structure type to access the DMA Registers.
*/
typedef struct {
__IO uint32_t cfg; /**< <tt>\b 0x100:</tt> DMA CFG Register */
__IO uint32_t st; /**< <tt>\b 0x104:</tt> DMA ST Register */
__IO uint32_t src; /**< <tt>\b 0x108:</tt> DMA SRC Register */
__IO uint32_t dst; /**< <tt>\b 0x10C:</tt> DMA DST Register */
__IO uint32_t cnt; /**< <tt>\b 0x110:</tt> DMA CNT Register */
__IO uint32_t src_rld; /**< <tt>\b 0x114:</tt> DMA SRC_RLD Register */
__IO uint32_t dst_rld; /**< <tt>\b 0x118:</tt> DMA DST_RLD Register */
__IO uint32_t cnt_rld; /**< <tt>\b 0x11C:</tt> DMA CNT_RLD Register */
} mxc_dma_ch_regs_t;
typedef struct {
__IO uint32_t cn; /**< <tt>\b 0x000:</tt> DMA CN Register */
__I uint32_t intr; /**< <tt>\b 0x004:</tt> DMA INTR Register */
__R uint32_t rsv_0x8_0xff[62];
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
} mxc_dma_regs_t;
/* Register offsets for module DMA */
/**
* @ingroup dma_registers
* @defgroup DMA_Register_Offsets Register Offsets
* @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address.
* @{
*/
#define MXC_R_DMA_CFG ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
#define MXC_R_DMA_ST ((uint32_t)0x00000104UL) /**< Offset from DMA Base Address: <tt> 0x0104</tt> */
#define MXC_R_DMA_SRC ((uint32_t)0x00000108UL) /**< Offset from DMA Base Address: <tt> 0x0108</tt> */
#define MXC_R_DMA_DST ((uint32_t)0x0000010CUL) /**< Offset from DMA Base Address: <tt> 0x010C</tt> */
#define MXC_R_DMA_CNT ((uint32_t)0x00000110UL) /**< Offset from DMA Base Address: <tt> 0x0110</tt> */
#define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000114UL) /**< Offset from DMA Base Address: <tt> 0x0114</tt> */
#define MXC_R_DMA_DST_RLD ((uint32_t)0x00000118UL) /**< Offset from DMA Base Address: <tt> 0x0118</tt> */
#define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000011CUL) /**< Offset from DMA Base Address: <tt> 0x011C</tt> */
#define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */
#define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */
#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */
/**@} end of group dma_registers */
/**
* @ingroup dma_registers
* @defgroup DMA_CN DMA_CN
* @brief DMA Control Register.
* @{
*/
#define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */
#define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */
#define MXC_V_DMA_CN_CH0_IEN_DIS ((uint32_t)0x0UL) /**< CN_CH0_IEN_DIS Value */
#define MXC_S_DMA_CN_CH0_IEN_DIS (MXC_V_DMA_CN_CH0_IEN_DIS << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_DIS Setting */
#define MXC_V_DMA_CN_CH0_IEN_EN ((uint32_t)0x1UL) /**< CN_CH0_IEN_EN Value */
#define MXC_S_DMA_CN_CH0_IEN_EN (MXC_V_DMA_CN_CH0_IEN_EN << MXC_F_DMA_CN_CH0_IEN_POS) /**< CN_CH0_IEN_EN Setting */
#define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */
#define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */
#define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */
#define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */
#define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */
#define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */
/**@} end of group DMA_CN_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_INTR DMA_INTR
* @brief DMA Interrupt Register.
* @{
*/
#define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */
#define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */
#define MXC_V_DMA_INTR_CH0_IPEND_INACTIVE ((uint32_t)0x0UL) /**< INTR_CH0_IPEND_INACTIVE Value */
#define MXC_S_DMA_INTR_CH0_IPEND_INACTIVE (MXC_V_DMA_INTR_CH0_IPEND_INACTIVE << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_INACTIVE Setting */
#define MXC_V_DMA_INTR_CH0_IPEND_PENDING ((uint32_t)0x1UL) /**< INTR_CH0_IPEND_PENDING Value */
#define MXC_S_DMA_INTR_CH0_IPEND_PENDING (MXC_V_DMA_INTR_CH0_IPEND_PENDING << MXC_F_DMA_INTR_CH0_IPEND_POS) /**< INTR_CH0_IPEND_PENDING Setting */
#define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */
#define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */
#define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */
#define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */
#define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */
#define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */
/**@} end of group DMA_INTR_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CFG DMA_CFG
* @brief DMA Channel Configuration Register.
* @{
*/
#define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */
#define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */
#define MXC_V_DMA_CFG_CHEN_DIS ((uint32_t)0x0UL) /**< CFG_CHEN_DIS Value */
#define MXC_S_DMA_CFG_CHEN_DIS (MXC_V_DMA_CFG_CHEN_DIS << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_DIS Setting */
#define MXC_V_DMA_CFG_CHEN_EN ((uint32_t)0x1UL) /**< CFG_CHEN_EN Value */
#define MXC_S_DMA_CFG_CHEN_EN (MXC_V_DMA_CFG_CHEN_EN << MXC_F_DMA_CFG_CHEN_POS) /**< CFG_CHEN_EN Setting */
#define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */
#define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */
#define MXC_V_DMA_CFG_RLDEN_DIS ((uint32_t)0x0UL) /**< CFG_RLDEN_DIS Value */
#define MXC_S_DMA_CFG_RLDEN_DIS (MXC_V_DMA_CFG_RLDEN_DIS << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_DIS Setting */
#define MXC_V_DMA_CFG_RLDEN_EN ((uint32_t)0x1UL) /**< CFG_RLDEN_EN Value */
#define MXC_S_DMA_CFG_RLDEN_EN (MXC_V_DMA_CFG_RLDEN_EN << MXC_F_DMA_CFG_RLDEN_POS) /**< CFG_RLDEN_EN Setting */
#define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */
#define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */
#define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */
#define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */
#define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */
#define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */
#define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */
#define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */
#define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */
#define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */
#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
#define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */
#define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */
#define MXC_V_DMA_CFG_REQWAIT_DIS ((uint32_t)0x0UL) /**< CFG_REQWAIT_DIS Value */
#define MXC_S_DMA_CFG_REQWAIT_DIS (MXC_V_DMA_CFG_REQWAIT_DIS << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_DIS Setting */
#define MXC_V_DMA_CFG_REQWAIT_EN ((uint32_t)0x1UL) /**< CFG_REQWAIT_EN Value */
#define MXC_S_DMA_CFG_REQWAIT_EN (MXC_V_DMA_CFG_REQWAIT_EN << MXC_F_DMA_CFG_REQWAIT_POS) /**< CFG_REQWAIT_EN Setting */
#define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */
#define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */
#define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */
#define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */
#define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */
#define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */
#define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */
#define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */
#define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */
#define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */
#define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */
#define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */
#define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */
#define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */
#define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */
#define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */
#define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */
#define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */
#define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */
#define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */
#define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */
#define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */
#define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */
#define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */
#define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */
#define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */
#define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */
#define MXC_F_DMA_CFG_SRCINC_POS 18 /**< CFG_SRCINC Position */
#define MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) /**< CFG_SRCINC Mask */
#define MXC_V_DMA_CFG_SRCINC_DIS ((uint32_t)0x0UL) /**< CFG_SRCINC_DIS Value */
#define MXC_S_DMA_CFG_SRCINC_DIS (MXC_V_DMA_CFG_SRCINC_DIS << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_DIS Setting */
#define MXC_V_DMA_CFG_SRCINC_EN ((uint32_t)0x1UL) /**< CFG_SRCINC_EN Value */
#define MXC_S_DMA_CFG_SRCINC_EN (MXC_V_DMA_CFG_SRCINC_EN << MXC_F_DMA_CFG_SRCINC_POS) /**< CFG_SRCINC_EN Setting */
#define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */
#define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */
#define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */
#define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */
#define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */
#define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */
#define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */
#define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */
#define MXC_F_DMA_CFG_DSTINC_POS 22 /**< CFG_DSTINC Position */
#define MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) /**< CFG_DSTINC Mask */
#define MXC_V_DMA_CFG_DSTINC_DIS ((uint32_t)0x0UL) /**< CFG_DSTINC_DIS Value */
#define MXC_S_DMA_CFG_DSTINC_DIS (MXC_V_DMA_CFG_DSTINC_DIS << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_DIS Setting */
#define MXC_V_DMA_CFG_DSTINC_EN ((uint32_t)0x1UL) /**< CFG_DSTINC_EN Value */
#define MXC_S_DMA_CFG_DSTINC_EN (MXC_V_DMA_CFG_DSTINC_EN << MXC_F_DMA_CFG_DSTINC_POS) /**< CFG_DSTINC_EN Setting */
#define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */
#define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */
#define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */
#define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */
#define MXC_V_DMA_CFG_CHDIEN_DIS ((uint32_t)0x0UL) /**< CFG_CHDIEN_DIS Value */
#define MXC_S_DMA_CFG_CHDIEN_DIS (MXC_V_DMA_CFG_CHDIEN_DIS << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_DIS Setting */
#define MXC_V_DMA_CFG_CHDIEN_EN ((uint32_t)0x1UL) /**< CFG_CHDIEN_EN Value */
#define MXC_S_DMA_CFG_CHDIEN_EN (MXC_V_DMA_CFG_CHDIEN_EN << MXC_F_DMA_CFG_CHDIEN_POS) /**< CFG_CHDIEN_EN Setting */
#define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */
#define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */
#define MXC_V_DMA_CFG_CTZIEN_DIS ((uint32_t)0x0UL) /**< CFG_CTZIEN_DIS Value */
#define MXC_S_DMA_CFG_CTZIEN_DIS (MXC_V_DMA_CFG_CTZIEN_DIS << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_DIS Setting */
#define MXC_V_DMA_CFG_CTZIEN_EN ((uint32_t)0x1UL) /**< CFG_CTZIEN_EN Value */
#define MXC_S_DMA_CFG_CTZIEN_EN (MXC_V_DMA_CFG_CTZIEN_EN << MXC_F_DMA_CFG_CTZIEN_POS) /**< CFG_CTZIEN_EN Setting */
/**@} end of group DMA_CFG_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_ST DMA_ST
* @brief DMA Channel Status Register.
* @{
*/
#define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */
#define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */
#define MXC_V_DMA_ST_CH_ST_DIS ((uint32_t)0x0UL) /**< ST_CH_ST_DIS Value */
#define MXC_S_DMA_ST_CH_ST_DIS (MXC_V_DMA_ST_CH_ST_DIS << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_DIS Setting */
#define MXC_V_DMA_ST_CH_ST_EN ((uint32_t)0x1UL) /**< ST_CH_ST_EN Value */
#define MXC_S_DMA_ST_CH_ST_EN (MXC_V_DMA_ST_CH_ST_EN << MXC_F_DMA_ST_CH_ST_POS) /**< ST_CH_ST_EN Setting */
#define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */
#define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */
#define MXC_V_DMA_ST_IPEND_INACTIVE ((uint32_t)0x0UL) /**< ST_IPEND_INACTIVE Value */
#define MXC_S_DMA_ST_IPEND_INACTIVE (MXC_V_DMA_ST_IPEND_INACTIVE << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_INACTIVE Setting */
#define MXC_V_DMA_ST_IPEND_PENDING ((uint32_t)0x1UL) /**< ST_IPEND_PENDING Value */
#define MXC_S_DMA_ST_IPEND_PENDING (MXC_V_DMA_ST_IPEND_PENDING << MXC_F_DMA_ST_IPEND_POS) /**< ST_IPEND_PENDING Setting */
#define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */
#define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */
#define MXC_V_DMA_ST_CTZ_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_CTZ_ST_NOEVENT Value */
#define MXC_S_DMA_ST_CTZ_ST_NOEVENT (MXC_V_DMA_ST_CTZ_ST_NOEVENT << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_CTZ_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_CTZ_ST_OCCURRED Value */
#define MXC_S_DMA_ST_CTZ_ST_OCCURRED (MXC_V_DMA_ST_CTZ_ST_OCCURRED << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_CTZ_ST_CLEAR ((uint32_t)0x1UL) /**< ST_CTZ_ST_CLEAR Value */
#define MXC_S_DMA_ST_CTZ_ST_CLEAR (MXC_V_DMA_ST_CTZ_ST_CLEAR << MXC_F_DMA_ST_CTZ_ST_POS) /**< ST_CTZ_ST_CLEAR Setting */
#define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */
#define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */
#define MXC_V_DMA_ST_RLD_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_RLD_ST_NOEVENT Value */
#define MXC_S_DMA_ST_RLD_ST_NOEVENT (MXC_V_DMA_ST_RLD_ST_NOEVENT << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_RLD_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_RLD_ST_OCCURRED Value */
#define MXC_S_DMA_ST_RLD_ST_OCCURRED (MXC_V_DMA_ST_RLD_ST_OCCURRED << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_RLD_ST_CLEAR ((uint32_t)0x1UL) /**< ST_RLD_ST_CLEAR Value */
#define MXC_S_DMA_ST_RLD_ST_CLEAR (MXC_V_DMA_ST_RLD_ST_CLEAR << MXC_F_DMA_ST_RLD_ST_POS) /**< ST_RLD_ST_CLEAR Setting */
#define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */
#define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */
#define MXC_V_DMA_ST_BUS_ERR_NOEVENT ((uint32_t)0x0UL) /**< ST_BUS_ERR_NOEVENT Value */
#define MXC_S_DMA_ST_BUS_ERR_NOEVENT (MXC_V_DMA_ST_BUS_ERR_NOEVENT << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_NOEVENT Setting */
#define MXC_V_DMA_ST_BUS_ERR_OCCURRED ((uint32_t)0x1UL) /**< ST_BUS_ERR_OCCURRED Value */
#define MXC_S_DMA_ST_BUS_ERR_OCCURRED (MXC_V_DMA_ST_BUS_ERR_OCCURRED << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_OCCURRED Setting */
#define MXC_V_DMA_ST_BUS_ERR_CLEAR ((uint32_t)0x1UL) /**< ST_BUS_ERR_CLEAR Value */
#define MXC_S_DMA_ST_BUS_ERR_CLEAR (MXC_V_DMA_ST_BUS_ERR_CLEAR << MXC_F_DMA_ST_BUS_ERR_POS) /**< ST_BUS_ERR_CLEAR Setting */
#define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */
#define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */
#define MXC_V_DMA_ST_TO_ST_NOEVENT ((uint32_t)0x0UL) /**< ST_TO_ST_NOEVENT Value */
#define MXC_S_DMA_ST_TO_ST_NOEVENT (MXC_V_DMA_ST_TO_ST_NOEVENT << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_NOEVENT Setting */
#define MXC_V_DMA_ST_TO_ST_OCCURRED ((uint32_t)0x1UL) /**< ST_TO_ST_OCCURRED Value */
#define MXC_S_DMA_ST_TO_ST_OCCURRED (MXC_V_DMA_ST_TO_ST_OCCURRED << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_OCCURRED Setting */
#define MXC_V_DMA_ST_TO_ST_CLEAR ((uint32_t)0x1UL) /**< ST_TO_ST_CLEAR Value */
#define MXC_S_DMA_ST_TO_ST_CLEAR (MXC_V_DMA_ST_TO_ST_CLEAR << MXC_F_DMA_ST_TO_ST_POS) /**< ST_TO_ST_CLEAR Setting */
/**@} end of group DMA_ST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC DMA_SRC
* @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or
* 4, depending on the data width of each AHB cycle. For peripheral transfers, some
* or all of the actual address bits are fixed. If SRCINC=0, this register remains
* constant. In the case where a count-to-zero condition occurs while RLDEN=1, the
* register is reloaded with the contents of DMA_SRC_RLD.
* @{
*/
#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */
#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */
/**@} end of group DMA_SRC_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST DMA_DST
* @brief Destination Device Address. For peripheral transfers, some or all of the actual
* address bits are fixed. If DSTINC=1, this register is incremented on every AHB
* write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the
* data width of each AHB cycle. In the case where a count-to-zero condition occurs
* while RLDEN=1, the register is reloaded with DMA_DST_RLD.
* @{
*/
#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */
#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */
/**@} end of group DMA_DST_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT DMA_CNT
* @brief DMA Counter. The user loads this register with the number of bytes to transfer.
* This counter decreases on every AHB cycle into the DMA FIFO. The decrement will
* be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter
* reaches 0, a count-to-zero condition is triggered.
* @{
*/
#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */
#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */
/**@} end of group DMA_CNT_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_SRC_RLD DMA_SRC_RLD
* @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC
* upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */
#define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */
/**@} end of group DMA_SRC_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_DST_RLD DMA_DST_RLD
* @brief Destination Address Reload Value. The value of this register is loaded into
* DMA0_DST upon a count-to-zero condition.
* @{
*/
#define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */
#define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */
/**@} end of group DMA_DST_RLD_Register */
/**
* @ingroup dma_registers
* @defgroup DMA_CNT_RLD DMA_CNT_RLD
* @brief DMA Channel Count Reload Register.
* @{
*/
#define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */
#define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */
#define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */
#define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */
#define MXC_V_DMA_CNT_RLD_RLDEN_DIS ((uint32_t)0x0UL) /**< CNT_RLD_RLDEN_DIS Value */
#define MXC_S_DMA_CNT_RLD_RLDEN_DIS (MXC_V_DMA_CNT_RLD_RLDEN_DIS << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_DIS Setting */
#define MXC_V_DMA_CNT_RLD_RLDEN_EN ((uint32_t)0x1UL) /**< CNT_RLD_RLDEN_EN Value */
#define MXC_S_DMA_CNT_RLD_RLDEN_EN (MXC_V_DMA_CNT_RLD_RLDEN_EN << MXC_F_DMA_CNT_RLD_RLDEN_POS) /**< CNT_RLD_RLDEN_EN Setting */
/**@} end of group DMA_CNT_RLD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _DMA_REGS_H_ */

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/**
* @file flc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _FLC_REGS_H_
#define _FLC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup flc
* @defgroup flc_registers FLC_Registers
* @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
* @details Flash Memory Control.
*/
/**
* @ingroup flc_registers
* Structure type to access the FLC Registers.
*/
typedef struct {
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
__IO uint32_t cn; /**< <tt>\b 0x08:</tt> FLC CN Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
__R uint32_t rsv_0x28_0x2f[2];
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t acntl; /**< <tt>\b 0x40:</tt> FLC ACNTL Register */
} mxc_flc_regs_t;
/* Register offsets for module FLC */
/**
* @ingroup flc_registers
* @defgroup FLC_Register_Offsets Register Offsets
* @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
* @{
*/
#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_registers */
/**
* @ingroup flc_registers
* @defgroup FLC_ADDR FLC_ADDR
* @brief Flash Write Address.
* @{
*/
#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
/**@} end of group FLC_ADDR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CLKDIV FLC_CLKDIV
* @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
* MHz clock for Flash controller.
* @{
*/
#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
/**@} end of group FLC_CLKDIV_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_CN FLC_CN
* @brief Flash Control Register.
* @{
*/
#define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */
#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
#define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
#define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
#define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */
#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
#define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
#define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
#define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */
#define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */
#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
#define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */
#define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
/**@} end of group FLC_CN_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_INTR FLC_INTR
* @brief Flash Interrupt Register.
* @{
*/
#define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
#define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
#define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
#define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
#define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
#define MXC_S_FLC_INTR_DONEIE_DISABLE (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
#define MXC_S_FLC_INTR_DONEIE_ENABLE (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
#define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
/**@} end of group FLC_INTR_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_DATA FLC_DATA
* @brief Flash Write Data.
* @{
*/
#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
/**@} end of group FLC_DATA_Register */
/**
* @ingroup flc_registers
* @defgroup FLC_ACNTL FLC_ACNTL
* @brief Access Control Register. Writing the ACNTL register with the following values in
* the order shown, allows read and write access to the system and user Information
* block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
* 0x9608b2c1. When unlocked, a write of any word will disable access to system and
* user information block. Readback of this register is always zero.
* @{
*/
#define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
/**@} end of group FLC_ACNTL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _FLC_REGS_H_ */

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/**
* @file gcr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GCR_REGS_H_
#define _GCR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gcr
* @defgroup gcr_registers GCR_Registers
* @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
* @details Global Control Registers.
*/
/**
* @ingroup gcr_registers
* Structure type to access the GCR Registers.
*/
typedef struct {
__IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */
__IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
__IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
__R uint32_t rsv_0x10_0x17[2];
__IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
__R uint32_t rsv_0x1c_0x23[2];
__IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
__IO uint32_t memckcn; /**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
__IO uint32_t memzcn; /**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
__R uint32_t rsv_0x30;
__IO uint32_t scck; /**< <tt>\b 0x34:</tt> GCR SCCK Register */
__IO uint32_t mpri0; /**< <tt>\b 0x38:</tt> GCR MPRI0 Register */
__IO uint32_t mpri1; /**< <tt>\b 0x3C:</tt> GCR MPRI1 Register */
__IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */
__IO uint32_t rstr1; /**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
__IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
__IO uint32_t evten; /**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
__I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */
__IO uint32_t syssie; /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
} mxc_gcr_regs_t;
/* Register offsets for module GCR */
/**
* @ingroup gcr_registers
* @defgroup GCR_Register_Offsets Register Offsets
* @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
* @{
*/
#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
#define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */
#define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
#define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
#define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
#define MXC_R_GCR_SCCK ((uint32_t)0x00000034UL) /**< Offset from GCR Base Address: <tt> 0x0034</tt> */
#define MXC_R_GCR_MPRI0 ((uint32_t)0x00000038UL) /**< Offset from GCR Base Address: <tt> 0x0038</tt> */
#define MXC_R_GCR_MPRI1 ((uint32_t)0x0000003CUL) /**< Offset from GCR Base Address: <tt> 0x003C</tt> */
#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
#define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
#define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
/**@} end of group gcr_registers */
/**
* @ingroup gcr_registers
* @defgroup GCR_SCON GCR_SCON
* @brief System Control.
* @{
*/
#define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
#define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
#define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
#define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
#define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
#define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
#define MXC_F_GCR_SCON_FPU_DIS_POS 5 /**< SCON_FPU_DIS Position */
#define MXC_F_GCR_SCON_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FPU_DIS_POS)) /**< SCON_FPU_DIS Mask */
#define MXC_V_GCR_SCON_FPU_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_FPU_DIS_ENABLE Value */
#define MXC_S_GCR_SCON_FPU_DIS_ENABLE (MXC_V_GCR_SCON_FPU_DIS_ENABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_ENABLE Setting */
#define MXC_V_GCR_SCON_FPU_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_FPU_DIS_DISABLE Value */
#define MXC_S_GCR_SCON_FPU_DIS_DISABLE (MXC_V_GCR_SCON_FPU_DIS_DISABLE << MXC_F_GCR_SCON_FPU_DIS_POS) /**< SCON_FPU_DIS_DISABLE Setting */
#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
#define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */
#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
#define MXC_F_GCR_SCON_SWD_DIS_POS 14 /**< SCON_SWD_DIS Position */
#define MXC_F_GCR_SCON_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SWD_DIS_POS)) /**< SCON_SWD_DIS Mask */
#define MXC_V_GCR_SCON_SWD_DIS_ENABLE ((uint32_t)0x0UL) /**< SCON_SWD_DIS_ENABLE Value */
#define MXC_S_GCR_SCON_SWD_DIS_ENABLE (MXC_V_GCR_SCON_SWD_DIS_ENABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_ENABLE Setting */
#define MXC_V_GCR_SCON_SWD_DIS_DISABLE ((uint32_t)0x1UL) /**< SCON_SWD_DIS_DISABLE Value */
#define MXC_S_GCR_SCON_SWD_DIS_DISABLE (MXC_V_GCR_SCON_SWD_DIS_DISABLE << MXC_F_GCR_SCON_SWD_DIS_POS) /**< SCON_SWD_DIS_DISABLE Setting */
/**@} end of group GCR_SCON_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RSTR0 GCR_RSTR0
* @brief Reset.
* @{
*/
#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
#define MXC_V_GCR_RSTR0_DMA_RFU ((uint32_t)0x0UL) /**< RSTR0_DMA_RFU Value */
#define MXC_S_GCR_RSTR0_DMA_RFU (MXC_V_GCR_RSTR0_DMA_RFU << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RFU Setting */
#define MXC_V_GCR_RSTR0_DMA_RESET ((uint32_t)0x1UL) /**< RSTR0_DMA_RESET Value */
#define MXC_S_GCR_RSTR0_DMA_RESET (MXC_V_GCR_RSTR0_DMA_RESET << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET Setting */
#define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_DMA_RESET_DONE (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */
#define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
#define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
#define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
#define MXC_V_GCR_RSTR0_WDT_RFU ((uint32_t)0x0UL) /**< RSTR0_WDT_RFU Value */
#define MXC_S_GCR_RSTR0_WDT_RFU (MXC_V_GCR_RSTR0_WDT_RFU << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RFU Setting */
#define MXC_V_GCR_RSTR0_WDT_RESET ((uint32_t)0x1UL) /**< RSTR0_WDT_RESET Value */
#define MXC_S_GCR_RSTR0_WDT_RESET (MXC_V_GCR_RSTR0_WDT_RESET << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET Setting */
#define MXC_V_GCR_RSTR0_WDT_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_WDT_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_WDT_RESET_DONE (MXC_V_GCR_RSTR0_WDT_RESET_DONE << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_WDT_BUSY ((uint32_t)0x1UL) /**< RSTR0_WDT_BUSY Value */
#define MXC_S_GCR_RSTR0_WDT_BUSY (MXC_V_GCR_RSTR0_WDT_BUSY << MXC_F_GCR_RSTR0_WDT_POS) /**< RSTR0_WDT_BUSY Setting */
#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
#define MXC_V_GCR_RSTR0_GPIO0_RFU ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RFU Value */
#define MXC_S_GCR_RSTR0_GPIO0_RFU (MXC_V_GCR_RSTR0_GPIO0_RFU << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RFU Setting */
#define MXC_V_GCR_RSTR0_GPIO0_RESET ((uint32_t)0x1UL) /**< RSTR0_GPIO0_RESET Value */
#define MXC_S_GCR_RSTR0_GPIO0_RESET (MXC_V_GCR_RSTR0_GPIO0_RESET << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET Setting */
#define MXC_V_GCR_RSTR0_GPIO0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_GPIO0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_GPIO0_RESET_DONE (MXC_V_GCR_RSTR0_GPIO0_RESET_DONE << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_GPIO0_BUSY ((uint32_t)0x1UL) /**< RSTR0_GPIO0_BUSY Value */
#define MXC_S_GCR_RSTR0_GPIO0_BUSY (MXC_V_GCR_RSTR0_GPIO0_BUSY << MXC_F_GCR_RSTR0_GPIO0_POS) /**< RSTR0_GPIO0_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
#define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
#define MXC_V_GCR_RSTR0_TIMER0_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER0_RFU (MXC_V_GCR_RSTR0_TIMER0_RFU << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER0_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER0_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER0_RESET (MXC_V_GCR_RSTR0_TIMER0_RESET << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER0_RESET_DONE (MXC_V_GCR_RSTR0_TIMER0_RESET_DONE << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER0_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER0_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER0_BUSY (MXC_V_GCR_RSTR0_TIMER0_BUSY << MXC_F_GCR_RSTR0_TIMER0_POS) /**< RSTR0_TIMER0_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
#define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
#define MXC_V_GCR_RSTR0_TIMER1_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER1_RFU (MXC_V_GCR_RSTR0_TIMER1_RFU << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER1_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER1_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER1_RESET (MXC_V_GCR_RSTR0_TIMER1_RESET << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER1_RESET_DONE (MXC_V_GCR_RSTR0_TIMER1_RESET_DONE << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER1_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER1_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER1_BUSY (MXC_V_GCR_RSTR0_TIMER1_BUSY << MXC_F_GCR_RSTR0_TIMER1_POS) /**< RSTR0_TIMER1_BUSY Setting */
#define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
#define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
#define MXC_V_GCR_RSTR0_TIMER2_RFU ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RFU Value */
#define MXC_S_GCR_RSTR0_TIMER2_RFU (MXC_V_GCR_RSTR0_TIMER2_RFU << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RFU Setting */
#define MXC_V_GCR_RSTR0_TIMER2_RESET ((uint32_t)0x1UL) /**< RSTR0_TIMER2_RESET Value */
#define MXC_S_GCR_RSTR0_TIMER2_RESET (MXC_V_GCR_RSTR0_TIMER2_RESET << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET Setting */
#define MXC_V_GCR_RSTR0_TIMER2_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_TIMER2_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_TIMER2_RESET_DONE (MXC_V_GCR_RSTR0_TIMER2_RESET_DONE << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_TIMER2_BUSY ((uint32_t)0x1UL) /**< RSTR0_TIMER2_BUSY Value */
#define MXC_S_GCR_RSTR0_TIMER2_BUSY (MXC_V_GCR_RSTR0_TIMER2_BUSY << MXC_F_GCR_RSTR0_TIMER2_POS) /**< RSTR0_TIMER2_BUSY Setting */
#define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
#define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
#define MXC_V_GCR_RSTR0_UART0_RFU ((uint32_t)0x0UL) /**< RSTR0_UART0_RFU Value */
#define MXC_S_GCR_RSTR0_UART0_RFU (MXC_V_GCR_RSTR0_UART0_RFU << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RFU Setting */
#define MXC_V_GCR_RSTR0_UART0_RESET ((uint32_t)0x1UL) /**< RSTR0_UART0_RESET Value */
#define MXC_S_GCR_RSTR0_UART0_RESET (MXC_V_GCR_RSTR0_UART0_RESET << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET Setting */
#define MXC_V_GCR_RSTR0_UART0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_UART0_RESET_DONE (MXC_V_GCR_RSTR0_UART0_RESET_DONE << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_UART0_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART0_BUSY Value */
#define MXC_S_GCR_RSTR0_UART0_BUSY (MXC_V_GCR_RSTR0_UART0_BUSY << MXC_F_GCR_RSTR0_UART0_POS) /**< RSTR0_UART0_BUSY Setting */
#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
#define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
#define MXC_V_GCR_RSTR0_UART1_RFU ((uint32_t)0x0UL) /**< RSTR0_UART1_RFU Value */
#define MXC_S_GCR_RSTR0_UART1_RFU (MXC_V_GCR_RSTR0_UART1_RFU << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RFU Setting */
#define MXC_V_GCR_RSTR0_UART1_RESET ((uint32_t)0x1UL) /**< RSTR0_UART1_RESET Value */
#define MXC_S_GCR_RSTR0_UART1_RESET (MXC_V_GCR_RSTR0_UART1_RESET << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET Setting */
#define MXC_V_GCR_RSTR0_UART1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_UART1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_UART1_RESET_DONE (MXC_V_GCR_RSTR0_UART1_RESET_DONE << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_UART1_BUSY ((uint32_t)0x1UL) /**< RSTR0_UART1_BUSY Value */
#define MXC_S_GCR_RSTR0_UART1_BUSY (MXC_V_GCR_RSTR0_UART1_BUSY << MXC_F_GCR_RSTR0_UART1_POS) /**< RSTR0_UART1_BUSY Setting */
#define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
#define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
#define MXC_V_GCR_RSTR0_SPI0_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI0_RFU Value */
#define MXC_S_GCR_RSTR0_SPI0_RFU (MXC_V_GCR_RSTR0_SPI0_RFU << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RFU Setting */
#define MXC_V_GCR_RSTR0_SPI0_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI0_RESET Value */
#define MXC_S_GCR_RSTR0_SPI0_RESET (MXC_V_GCR_RSTR0_SPI0_RESET << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET Setting */
#define MXC_V_GCR_RSTR0_SPI0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SPI0_RESET_DONE (MXC_V_GCR_RSTR0_SPI0_RESET_DONE << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SPI0_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI0_BUSY Value */
#define MXC_S_GCR_RSTR0_SPI0_BUSY (MXC_V_GCR_RSTR0_SPI0_BUSY << MXC_F_GCR_RSTR0_SPI0_POS) /**< RSTR0_SPI0_BUSY Setting */
#define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
#define MXC_V_GCR_RSTR0_SPI1_RFU ((uint32_t)0x0UL) /**< RSTR0_SPI1_RFU Value */
#define MXC_S_GCR_RSTR0_SPI1_RFU (MXC_V_GCR_RSTR0_SPI1_RFU << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RFU Setting */
#define MXC_V_GCR_RSTR0_SPI1_RESET ((uint32_t)0x1UL) /**< RSTR0_SPI1_RESET Value */
#define MXC_S_GCR_RSTR0_SPI1_RESET (MXC_V_GCR_RSTR0_SPI1_RESET << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET Setting */
#define MXC_V_GCR_RSTR0_SPI1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SPI1_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SPI1_RESET_DONE (MXC_V_GCR_RSTR0_SPI1_RESET_DONE << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SPI1_BUSY ((uint32_t)0x1UL) /**< RSTR0_SPI1_BUSY Value */
#define MXC_S_GCR_RSTR0_SPI1_BUSY (MXC_V_GCR_RSTR0_SPI1_BUSY << MXC_F_GCR_RSTR0_SPI1_POS) /**< RSTR0_SPI1_BUSY Setting */
#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
#define MXC_V_GCR_RSTR0_I2C0_RFU ((uint32_t)0x0UL) /**< RSTR0_I2C0_RFU Value */
#define MXC_S_GCR_RSTR0_I2C0_RFU (MXC_V_GCR_RSTR0_I2C0_RFU << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RFU Setting */
#define MXC_V_GCR_RSTR0_I2C0_RESET ((uint32_t)0x1UL) /**< RSTR0_I2C0_RESET Value */
#define MXC_S_GCR_RSTR0_I2C0_RESET (MXC_V_GCR_RSTR0_I2C0_RESET << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET Setting */
#define MXC_V_GCR_RSTR0_I2C0_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_I2C0_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_I2C0_RESET_DONE (MXC_V_GCR_RSTR0_I2C0_RESET_DONE << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_I2C0_BUSY ((uint32_t)0x1UL) /**< RSTR0_I2C0_BUSY Value */
#define MXC_S_GCR_RSTR0_I2C0_BUSY (MXC_V_GCR_RSTR0_I2C0_BUSY << MXC_F_GCR_RSTR0_I2C0_POS) /**< RSTR0_I2C0_BUSY Setting */
#define MXC_F_GCR_RSTR0_RTC_POS 17 /**< RSTR0_RTC Position */
#define MXC_F_GCR_RSTR0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS)) /**< RSTR0_RTC Mask */
#define MXC_V_GCR_RSTR0_RTC_RFU ((uint32_t)0x0UL) /**< RSTR0_RTC_RFU Value */
#define MXC_S_GCR_RSTR0_RTC_RFU (MXC_V_GCR_RSTR0_RTC_RFU << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RFU Setting */
#define MXC_V_GCR_RSTR0_RTC_RESET ((uint32_t)0x1UL) /**< RSTR0_RTC_RESET Value */
#define MXC_S_GCR_RSTR0_RTC_RESET (MXC_V_GCR_RSTR0_RTC_RESET << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET Setting */
#define MXC_V_GCR_RSTR0_RTC_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_RTC_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_RTC_RESET_DONE (MXC_V_GCR_RSTR0_RTC_RESET_DONE << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_RTC_BUSY ((uint32_t)0x1UL) /**< RSTR0_RTC_BUSY Value */
#define MXC_S_GCR_RSTR0_RTC_BUSY (MXC_V_GCR_RSTR0_RTC_BUSY << MXC_F_GCR_RSTR0_RTC_POS) /**< RSTR0_RTC_BUSY Setting */
#define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
#define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
#define MXC_V_GCR_RSTR0_SRST_RFU ((uint32_t)0x0UL) /**< RSTR0_SRST_RFU Value */
#define MXC_S_GCR_RSTR0_SRST_RFU (MXC_V_GCR_RSTR0_SRST_RFU << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RFU Setting */
#define MXC_V_GCR_RSTR0_SRST_RESET ((uint32_t)0x1UL) /**< RSTR0_SRST_RESET Value */
#define MXC_S_GCR_RSTR0_SRST_RESET (MXC_V_GCR_RSTR0_SRST_RESET << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET Setting */
#define MXC_V_GCR_RSTR0_SRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SRST_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SRST_RESET_DONE (MXC_V_GCR_RSTR0_SRST_RESET_DONE << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_SRST_BUSY Value */
#define MXC_S_GCR_RSTR0_SRST_BUSY (MXC_V_GCR_RSTR0_SRST_BUSY << MXC_F_GCR_RSTR0_SRST_POS) /**< RSTR0_SRST_BUSY Setting */
#define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
#define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
#define MXC_V_GCR_RSTR0_PRST_RFU ((uint32_t)0x0UL) /**< RSTR0_PRST_RFU Value */
#define MXC_S_GCR_RSTR0_PRST_RFU (MXC_V_GCR_RSTR0_PRST_RFU << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RFU Setting */
#define MXC_V_GCR_RSTR0_PRST_RESET ((uint32_t)0x1UL) /**< RSTR0_PRST_RESET Value */
#define MXC_S_GCR_RSTR0_PRST_RESET (MXC_V_GCR_RSTR0_PRST_RESET << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET Setting */
#define MXC_V_GCR_RSTR0_PRST_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_PRST_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_PRST_RESET_DONE (MXC_V_GCR_RSTR0_PRST_RESET_DONE << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_PRST_BUSY ((uint32_t)0x1UL) /**< RSTR0_PRST_BUSY Value */
#define MXC_S_GCR_RSTR0_PRST_BUSY (MXC_V_GCR_RSTR0_PRST_BUSY << MXC_F_GCR_RSTR0_PRST_POS) /**< RSTR0_PRST_BUSY Setting */
#define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
#define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
#define MXC_V_GCR_RSTR0_SYSTEM_RFU ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RFU Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RFU (MXC_V_GCR_RSTR0_SYSTEM_RFU << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RFU Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_RESET ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_RESET Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RESET (MXC_V_GCR_RSTR0_SYSTEM_RESET << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_SYSTEM_RESET_DONE Value */
#define MXC_S_GCR_RSTR0_SYSTEM_RESET_DONE (MXC_V_GCR_RSTR0_SYSTEM_RESET_DONE << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_RESET_DONE Setting */
#define MXC_V_GCR_RSTR0_SYSTEM_BUSY ((uint32_t)0x1UL) /**< RSTR0_SYSTEM_BUSY Value */
#define MXC_S_GCR_RSTR0_SYSTEM_BUSY (MXC_V_GCR_RSTR0_SYSTEM_BUSY << MXC_F_GCR_RSTR0_SYSTEM_POS) /**< RSTR0_SYSTEM_BUSY Setting */
/**@} end of group GCR_RSTR0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_CLKCN GCR_CLKCN
* @brief Clock Control.
* @{
*/
#define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
#define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
#define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
#define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
#define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
#define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
#define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
#define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
#define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
#define MXC_V_GCR_CLKCN_CLKSEL_NANORING ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_NANORING Value */
#define MXC_S_GCR_CLKCN_CLKSEL_NANORING (MXC_V_GCR_CLKCN_CLKSEL_NANORING << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_NANORING Setting */
#define MXC_V_GCR_CLKCN_CLKSEL_HFXIN ((uint32_t)0x6UL) /**< CLKCN_CLKSEL_HFXIN Value */
#define MXC_S_GCR_CLKCN_CLKSEL_HFXIN (MXC_V_GCR_CLKCN_CLKSEL_HFXIN << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HFXIN Setting */
#define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
#define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
#define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
#define MXC_S_GCR_CLKCN_CKRDY_BUSY (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
#define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
#define MXC_S_GCR_CLKCN_CKRDY_READY (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
#define MXC_F_GCR_CLKCN_X32K_EN_POS 17 /**< CLKCN_X32K_EN Position */
#define MXC_F_GCR_CLKCN_X32K_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_EN_POS)) /**< CLKCN_X32K_EN Mask */
#define MXC_V_GCR_CLKCN_X32K_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_X32K_EN_DIS Value */
#define MXC_S_GCR_CLKCN_X32K_EN_DIS (MXC_V_GCR_CLKCN_X32K_EN_DIS << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_DIS Setting */
#define MXC_V_GCR_CLKCN_X32K_EN_EN ((uint32_t)0x1UL) /**< CLKCN_X32K_EN_EN Value */
#define MXC_S_GCR_CLKCN_X32K_EN_EN (MXC_V_GCR_CLKCN_X32K_EN_EN << MXC_F_GCR_CLKCN_X32K_EN_POS) /**< CLKCN_X32K_EN_EN Setting */
#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
#define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
#define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
#define MXC_S_GCR_CLKCN_HIRC_EN_DIS (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
#define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
#define MXC_S_GCR_CLKCN_HIRC_EN_EN (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
#define MXC_F_GCR_CLKCN_X32K_RDY_POS 25 /**< CLKCN_X32K_RDY Position */
#define MXC_F_GCR_CLKCN_X32K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_X32K_RDY_POS)) /**< CLKCN_X32K_RDY Mask */
#define MXC_V_GCR_CLKCN_X32K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_X32K_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_X32K_RDY_NOT (MXC_V_GCR_CLKCN_X32K_RDY_NOT << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_X32K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_X32K_RDY_READY Value */
#define MXC_S_GCR_CLKCN_X32K_RDY_READY (MXC_V_GCR_CLKCN_X32K_RDY_READY << MXC_F_GCR_CLKCN_X32K_RDY_POS) /**< CLKCN_X32K_RDY_READY Setting */
#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
#define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
#define MXC_S_GCR_CLKCN_HIRC_RDY_READY (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
#define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
#define MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_LIRC8K_RDY_NOT Value */
#define MXC_S_GCR_CLKCN_LIRC8K_RDY_NOT (MXC_V_GCR_CLKCN_LIRC8K_RDY_NOT << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_NOT Setting */
#define MXC_V_GCR_CLKCN_LIRC8K_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_LIRC8K_RDY_READY Value */
#define MXC_S_GCR_CLKCN_LIRC8K_RDY_READY (MXC_V_GCR_CLKCN_LIRC8K_RDY_READY << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS) /**< CLKCN_LIRC8K_RDY_READY Setting */
/**@} end of group GCR_CLKCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PM GCR_PM
* @brief Power Management.
* @{
*/
#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
#define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
#define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
#define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
#define MXC_S_GCR_PM_GPIOWKEN_DIS (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
#define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */
#define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
#define MXC_F_GCR_PM_RTCWKEN_POS 5 /**< PM_RTCWKEN Position */
#define MXC_F_GCR_PM_RTCWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTCWKEN_POS)) /**< PM_RTCWKEN Mask */
#define MXC_V_GCR_PM_RTCWKEN_DIS ((uint32_t)0x0UL) /**< PM_RTCWKEN_DIS Value */
#define MXC_S_GCR_PM_RTCWKEN_DIS (MXC_V_GCR_PM_RTCWKEN_DIS << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_DIS Setting */
#define MXC_V_GCR_PM_RTCWKEN_EN ((uint32_t)0x1UL) /**< PM_RTCWKEN_EN Value */
#define MXC_S_GCR_PM_RTCWKEN_EN (MXC_V_GCR_PM_RTCWKEN_EN << MXC_F_GCR_PM_RTCWKEN_POS) /**< PM_RTCWKEN_EN Setting */
#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
#define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
#define MXC_S_GCR_PM_HIRCPD_ACTIVE (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
/**@} end of group GCR_PM_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PCKDIV GCR_PCKDIV
* @brief Peripheral Clock Divider.
* @{
*/
#define MXC_F_GCR_PCKDIV_AONCD_POS 0 /**< PCKDIV_AONCD Position */
#define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
#define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
/**@} end of group GCR_PCKDIV_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PERCKCN0 GCR_PERCKCN0
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
#define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
#define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
#define MXC_S_GCR_PERCKCN0_GPIO0D_EN (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
#define MXC_V_GCR_PERCKCN0_DMAD_EN ((uint32_t)0x0UL) /**< PERCKCN0_DMAD_EN Value */
#define MXC_S_GCR_PERCKCN0_DMAD_EN (MXC_V_GCR_PERCKCN0_DMAD_EN << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_EN Setting */
#define MXC_V_GCR_PERCKCN0_DMAD_DIS ((uint32_t)0x1UL) /**< PERCKCN0_DMAD_DIS Value */
#define MXC_S_GCR_PERCKCN0_DMAD_DIS (MXC_V_GCR_PERCKCN0_DMAD_DIS << MXC_F_GCR_PERCKCN0_DMAD_POS) /**< PERCKCN0_DMAD_DIS Setting */
#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
#define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
#define MXC_V_GCR_PERCKCN0_SPI0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI0D_EN Value */
#define MXC_S_GCR_PERCKCN0_SPI0D_EN (MXC_V_GCR_PERCKCN0_SPI0D_EN << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_SPI0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_SPI0D_DIS (MXC_V_GCR_PERCKCN0_SPI0D_DIS << MXC_F_GCR_PERCKCN0_SPI0D_POS) /**< PERCKCN0_SPI0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
#define MXC_V_GCR_PERCKCN0_SPI1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_SPI1D_EN Value */
#define MXC_S_GCR_PERCKCN0_SPI1D_EN (MXC_V_GCR_PERCKCN0_SPI1D_EN << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_SPI1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_SPI1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_SPI1D_DIS (MXC_V_GCR_PERCKCN0_SPI1D_DIS << MXC_F_GCR_PERCKCN0_SPI1D_POS) /**< PERCKCN0_SPI1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
#define MXC_V_GCR_PERCKCN0_UART0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART0D_EN Value */
#define MXC_S_GCR_PERCKCN0_UART0D_EN (MXC_V_GCR_PERCKCN0_UART0D_EN << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_UART0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_UART0D_DIS (MXC_V_GCR_PERCKCN0_UART0D_DIS << MXC_F_GCR_PERCKCN0_UART0D_POS) /**< PERCKCN0_UART0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_UART1D_POS 10 /**< PERCKCN0_UART1D Position */
#define MXC_F_GCR_PERCKCN0_UART1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART1D_POS)) /**< PERCKCN0_UART1D Mask */
#define MXC_V_GCR_PERCKCN0_UART1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_UART1D_EN Value */
#define MXC_S_GCR_PERCKCN0_UART1D_EN (MXC_V_GCR_PERCKCN0_UART1D_EN << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_UART1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_UART1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_UART1D_DIS (MXC_V_GCR_PERCKCN0_UART1D_DIS << MXC_F_GCR_PERCKCN0_UART1D_POS) /**< PERCKCN0_UART1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
#define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
#define MXC_V_GCR_PERCKCN0_I2C0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C0D_EN Value */
#define MXC_S_GCR_PERCKCN0_I2C0D_EN (MXC_V_GCR_PERCKCN0_I2C0D_EN << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_I2C0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_I2C0D_DIS (MXC_V_GCR_PERCKCN0_I2C0D_DIS << MXC_F_GCR_PERCKCN0_I2C0D_POS) /**< PERCKCN0_I2C0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
#define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
#define MXC_V_GCR_PERCKCN0_T0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T0D_EN Value */
#define MXC_S_GCR_PERCKCN0_T0D_EN (MXC_V_GCR_PERCKCN0_T0D_EN << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T0D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T0D_DIS (MXC_V_GCR_PERCKCN0_T0D_DIS << MXC_F_GCR_PERCKCN0_T0D_POS) /**< PERCKCN0_T0D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
#define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
#define MXC_V_GCR_PERCKCN0_T1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T1D_EN Value */
#define MXC_S_GCR_PERCKCN0_T1D_EN (MXC_V_GCR_PERCKCN0_T1D_EN << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T1D_DIS (MXC_V_GCR_PERCKCN0_T1D_DIS << MXC_F_GCR_PERCKCN0_T1D_POS) /**< PERCKCN0_T1D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
#define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
#define MXC_V_GCR_PERCKCN0_T2D_EN ((uint32_t)0x0UL) /**< PERCKCN0_T2D_EN Value */
#define MXC_S_GCR_PERCKCN0_T2D_EN (MXC_V_GCR_PERCKCN0_T2D_EN << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_EN Setting */
#define MXC_V_GCR_PERCKCN0_T2D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_T2D_DIS Value */
#define MXC_S_GCR_PERCKCN0_T2D_DIS (MXC_V_GCR_PERCKCN0_T2D_DIS << MXC_F_GCR_PERCKCN0_T2D_POS) /**< PERCKCN0_T2D_DIS Setting */
#define MXC_F_GCR_PERCKCN0_I2C1D_POS 28 /**< PERCKCN0_I2C1D Position */
#define MXC_F_GCR_PERCKCN0_I2C1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C1D_POS)) /**< PERCKCN0_I2C1D Mask */
#define MXC_V_GCR_PERCKCN0_I2C1D_EN ((uint32_t)0x0UL) /**< PERCKCN0_I2C1D_EN Value */
#define MXC_S_GCR_PERCKCN0_I2C1D_EN (MXC_V_GCR_PERCKCN0_I2C1D_EN << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_EN Setting */
#define MXC_V_GCR_PERCKCN0_I2C1D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_I2C1D_DIS Value */
#define MXC_S_GCR_PERCKCN0_I2C1D_DIS (MXC_V_GCR_PERCKCN0_I2C1D_DIS << MXC_F_GCR_PERCKCN0_I2C1D_POS) /**< PERCKCN0_I2C1D_DIS Setting */
/**@} end of group GCR_PERCKCN0_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEMCKCN GCR_MEMCKCN
* @brief Memory Clock Control Register.
* @{
*/
#define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
#define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 8 /**< MEMCKCN_SYSRAM0LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 9 /**< MEMCKCN_SYSRAM1LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM1LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM1LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM1LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS) /**< MEMCKCN_SYSRAM1LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 10 /**< MEMCKCN_SYSRAM2LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM2LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM2LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM2LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS) /**< MEMCKCN_SYSRAM2LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 11 /**< MEMCKCN_SYSRAM3LS Position */
#define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM3LS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM3LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM3LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS) /**< MEMCKCN_SYSRAM3LS_LIGHT_SLEEP Setting */
#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 12 /**< MEMCKCN_ICACHELS Position */
#define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
#define MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_ICACHELS_ACTIVE Value */
#define MXC_S_GCR_MEMCKCN_ICACHELS_ACTIVE (MXC_V_GCR_MEMCKCN_ICACHELS_ACTIVE << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_ACTIVE Setting */
#define MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Value */
#define MXC_S_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_ICACHELS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_ICACHELS_POS) /**< MEMCKCN_ICACHELS_LIGHT_SLEEP Setting */
/**@} end of group GCR_MEMCKCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_MEMZCN GCR_MEMZCN
* @brief Memory Zeroize Control.
* @{
*/
#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
#define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
#define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
#define MXC_S_GCR_MEMZCN_SRAM0Z_START (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 1 /**< MEMZCN_ICACHEZ Position */
#define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
#define MXC_V_GCR_MEMZCN_ICACHEZ_NOP ((uint32_t)0x0UL) /**< MEMZCN_ICACHEZ_NOP Value */
#define MXC_S_GCR_MEMZCN_ICACHEZ_NOP (MXC_V_GCR_MEMZCN_ICACHEZ_NOP << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_NOP Setting */
#define MXC_V_GCR_MEMZCN_ICACHEZ_START ((uint32_t)0x1UL) /**< MEMZCN_ICACHEZ_START Value */
#define MXC_S_GCR_MEMZCN_ICACHEZ_START (MXC_V_GCR_MEMZCN_ICACHEZ_START << MXC_F_GCR_MEMZCN_ICACHEZ_POS) /**< MEMZCN_ICACHEZ_START Setting */
/**@} end of group GCR_MEMZCN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYSST GCR_SYSST
* @brief System Status Register.
* @{
*/
#define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
#define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
#define MXC_F_GCR_SYSST_CODEINTERR_POS 1 /**< SYSST_CODEINTERR Position */
#define MXC_F_GCR_SYSST_CODEINTERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEINTERR_POS)) /**< SYSST_CODEINTERR Mask */
#define MXC_V_GCR_SYSST_CODEINTERR_NORM ((uint32_t)0x0UL) /**< SYSST_CODEINTERR_NORM Value */
#define MXC_S_GCR_SYSST_CODEINTERR_NORM (MXC_V_GCR_SYSST_CODEINTERR_NORM << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_NORM Setting */
#define MXC_V_GCR_SYSST_CODEINTERR_CODE ((uint32_t)0x1UL) /**< SYSST_CODEINTERR_CODE Value */
#define MXC_S_GCR_SYSST_CODEINTERR_CODE (MXC_V_GCR_SYSST_CODEINTERR_CODE << MXC_F_GCR_SYSST_CODEINTERR_POS) /**< SYSST_CODEINTERR_CODE Setting */
#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */
#define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */
#define MXC_V_GCR_SYSST_SCMEMF_NORM ((uint32_t)0x0UL) /**< SYSST_SCMEMF_NORM Value */
#define MXC_S_GCR_SYSST_SCMEMF_NORM (MXC_V_GCR_SYSST_SCMEMF_NORM << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_NORM Setting */
#define MXC_V_GCR_SYSST_SCMEMF_MEMORY ((uint32_t)0x1UL) /**< SYSST_SCMEMF_MEMORY Value */
#define MXC_S_GCR_SYSST_SCMEMF_MEMORY (MXC_V_GCR_SYSST_SCMEMF_MEMORY << MXC_F_GCR_SYSST_SCMEMF_POS) /**< SYSST_SCMEMF_MEMORY Setting */
/**@} end of group GCR_SYSST_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_RSTR1 GCR_RSTR1
* @brief Reset 1.
* @{
*/
#define MXC_F_GCR_RSTR1_I2C1_POS 0 /**< RSTR1_I2C1 Position */
#define MXC_F_GCR_RSTR1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C1_POS)) /**< RSTR1_I2C1 Mask */
#define MXC_V_GCR_RSTR1_I2C1_RFU ((uint32_t)0x0UL) /**< RSTR1_I2C1_RFU Value */
#define MXC_S_GCR_RSTR1_I2C1_RFU (MXC_V_GCR_RSTR1_I2C1_RFU << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RFU Setting */
#define MXC_V_GCR_RSTR1_I2C1_RESET ((uint32_t)0x1UL) /**< RSTR1_I2C1_RESET Value */
#define MXC_S_GCR_RSTR1_I2C1_RESET (MXC_V_GCR_RSTR1_I2C1_RESET << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET Setting */
#define MXC_V_GCR_RSTR1_I2C1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_I2C1_RESET_DONE Value */
#define MXC_S_GCR_RSTR1_I2C1_RESET_DONE (MXC_V_GCR_RSTR1_I2C1_RESET_DONE << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_RESET_DONE Setting */
#define MXC_V_GCR_RSTR1_I2C1_BUSY ((uint32_t)0x1UL) /**< RSTR1_I2C1_BUSY Value */
#define MXC_S_GCR_RSTR1_I2C1_BUSY (MXC_V_GCR_RSTR1_I2C1_BUSY << MXC_F_GCR_RSTR1_I2C1_POS) /**< RSTR1_I2C1_BUSY Setting */
/**@} end of group GCR_RSTR1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_PERCKCN1 GCR_PERCKCN1
* @brief Peripheral Clock Disable.
* @{
*/
#define MXC_F_GCR_PERCKCN1_FLCD_POS 3 /**< PERCKCN1_FLCD Position */
#define MXC_F_GCR_PERCKCN1_FLCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_FLCD_POS)) /**< PERCKCN1_FLCD Mask */
#define MXC_V_GCR_PERCKCN1_FLCD_EN ((uint32_t)0x0UL) /**< PERCKCN1_FLCD_EN Value */
#define MXC_S_GCR_PERCKCN1_FLCD_EN (MXC_V_GCR_PERCKCN1_FLCD_EN << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_EN Setting */
#define MXC_V_GCR_PERCKCN1_FLCD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_FLCD_DIS Value */
#define MXC_S_GCR_PERCKCN1_FLCD_DIS (MXC_V_GCR_PERCKCN1_FLCD_DIS << MXC_F_GCR_PERCKCN1_FLCD_POS) /**< PERCKCN1_FLCD_DIS Setting */
#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
#define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
#define MXC_V_GCR_PERCKCN1_ICACHED_EN ((uint32_t)0x0UL) /**< PERCKCN1_ICACHED_EN Value */
#define MXC_S_GCR_PERCKCN1_ICACHED_EN (MXC_V_GCR_PERCKCN1_ICACHED_EN << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_EN Setting */
#define MXC_V_GCR_PERCKCN1_ICACHED_DIS ((uint32_t)0x1UL) /**< PERCKCN1_ICACHED_DIS Value */
#define MXC_S_GCR_PERCKCN1_ICACHED_DIS (MXC_V_GCR_PERCKCN1_ICACHED_DIS << MXC_F_GCR_PERCKCN1_ICACHED_POS) /**< PERCKCN1_ICACHED_DIS Setting */
/**@} end of group GCR_PERCKCN1_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_EVTEN GCR_EVTEN
* @brief Event Enable Register.
* @{
*/
#define MXC_F_GCR_EVTEN_DMAEVENT_POS 0 /**< EVTEN_DMAEVENT Position */
#define MXC_F_GCR_EVTEN_DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_DMAEVENT_POS)) /**< EVTEN_DMAEVENT Mask */
#define MXC_F_GCR_EVTEN_RXEVENT_POS 1 /**< EVTEN_RXEVENT Position */
#define MXC_F_GCR_EVTEN_RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_RXEVENT_POS)) /**< EVTEN_RXEVENT Mask */
/**@} end of group GCR_EVTEN_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_REVISION GCR_REVISION
* @brief Revision Register.
* @{
*/
#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
/**@} end of group GCR_REVISION_Register */
/**
* @ingroup gcr_registers
* @defgroup GCR_SYSSIE GCR_SYSSIE
* @brief System Status Interrupt Enable Register.
* @{
*/
#define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
#define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
#define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
#define MXC_S_GCR_SYSSIE_ICEULIE_DIS (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
#define MXC_S_GCR_SYSSIE_ICEULIE_EN (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
#define MXC_F_GCR_SYSSIE_CIEIE_POS 1 /**< SYSSIE_CIEIE Position */
#define MXC_F_GCR_SYSSIE_CIEIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_CIEIE_POS)) /**< SYSSIE_CIEIE Mask */
#define MXC_V_GCR_SYSSIE_CIEIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_CIEIE_DIS Value */
#define MXC_S_GCR_SYSSIE_CIEIE_DIS (MXC_V_GCR_SYSSIE_CIEIE_DIS << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_CIEIE_EN ((uint32_t)0x1UL) /**< SYSSIE_CIEIE_EN Value */
#define MXC_S_GCR_SYSSIE_CIEIE_EN (MXC_V_GCR_SYSSIE_CIEIE_EN << MXC_F_GCR_SYSSIE_CIEIE_POS) /**< SYSSIE_CIEIE_EN Setting */
#define MXC_F_GCR_SYSSIE_SCMFIE_POS 5 /**< SYSSIE_SCMFIE Position */
#define MXC_F_GCR_SYSSIE_SCMFIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_SCMFIE_POS)) /**< SYSSIE_SCMFIE Mask */
#define MXC_V_GCR_SYSSIE_SCMFIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_SCMFIE_DIS Value */
#define MXC_S_GCR_SYSSIE_SCMFIE_DIS (MXC_V_GCR_SYSSIE_SCMFIE_DIS << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_DIS Setting */
#define MXC_V_GCR_SYSSIE_SCMFIE_EN ((uint32_t)0x1UL) /**< SYSSIE_SCMFIE_EN Value */
#define MXC_S_GCR_SYSSIE_SCMFIE_EN (MXC_V_GCR_SYSSIE_SCMFIE_EN << MXC_F_GCR_SYSSIE_SCMFIE_POS) /**< SYSSIE_SCMFIE_EN Setting */
/**@} end of group GCR_SYSSIE_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GCR_REGS_H_ */

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/**
* @file gpio_regs.h
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup gpio
* @defgroup gpio_registers GPIO_Registers
* @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
* @details Individual I/O for each GPIO
*/
/**
* @ingroup gpio_registers
* Structure type to access the GPIO Registers.
*/
typedef struct {
__IO uint32_t en; /**< <tt>\b 0x00:</tt> GPIO EN Register */
__IO uint32_t en_set; /**< <tt>\b 0x04:</tt> GPIO EN_SET Register */
__IO uint32_t en_clr; /**< <tt>\b 0x08:</tt> GPIO EN_CLR Register */
__IO uint32_t out_en; /**< <tt>\b 0x0C:</tt> GPIO OUT_EN Register */
__IO uint32_t out_en_set; /**< <tt>\b 0x10:</tt> GPIO OUT_EN_SET Register */
__IO uint32_t out_en_clr; /**< <tt>\b 0x14:</tt> GPIO OUT_EN_CLR Register */
__IO uint32_t out; /**< <tt>\b 0x18:</tt> GPIO OUT Register */
__O uint32_t out_set; /**< <tt>\b 0x1C:</tt> GPIO OUT_SET Register */
__O uint32_t out_clr; /**< <tt>\b 0x20:</tt> GPIO OUT_CLR Register */
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
__IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
__R uint32_t rsv_0x30;
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
__R uint32_t rsv_0x44;
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
__R uint32_t rsv_0x58;
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
__IO uint32_t en1; /**< <tt>\b 0x68:</tt> GPIO EN1 Register */
__IO uint32_t en1_set; /**< <tt>\b 0x6C:</tt> GPIO EN1_SET Register */
__IO uint32_t en1_clr; /**< <tt>\b 0x70:</tt> GPIO EN1_CLR Register */
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
__R uint32_t rsv_0x80_0xa7[10];
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
__IO uint32_t ds; /**< <tt>\b 0xB0:</tt> GPIO DS Register */
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
__R uint32_t rsv_0xbc;
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
} mxc_gpio_regs_t;
/* Register offsets for module GPIO */
/**
* @ingroup gpio_registers
* @defgroup GPIO_Register_Offsets Register Offsets
* @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address.
* @{
*/
#define MXC_R_GPIO_EN ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> 0x0000</tt> */
#define MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> 0x0004</tt> */
#define MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> 0x0008</tt> */
#define MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> 0x000C</tt> */
#define MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> 0x0010</tt> */
#define MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> 0x0014</tt> */
#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> 0x0018</tt> */
#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> 0x001C</tt> */
#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> 0x0020</tt> */
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
#define MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> 0x0040</tt> */
#define MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> 0x0048</tt> */
#define MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> 0x004C</tt> */
#define MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> 0x0050</tt> */
#define MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> 0x0054</tt> */
#define MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> 0x005C</tt> */
#define MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> 0x0060</tt> */
#define MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> 0x0064</tt> */
#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> 0x0068</tt> */
#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> 0x006C</tt> */
#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> 0x0070</tt> */
#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> 0x0074</tt> */
#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> 0x0078</tt> */
#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> 0x007C</tt> */
#define MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> 0x00A8</tt> */
#define MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> 0x00AC</tt> */
#define MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> 0x00B0</tt> */
#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> 0x00B4</tt> */
#define MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> 0x00B8</tt> */
#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> 0x00C0</tt> */
/**@} end of group gpio_registers */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN GPIO_EN
* @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one
* GPIO pin on the associated port.
* @{
*/
#define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */
#define MXC_F_GPIO_EN_GPIO_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */
#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */
#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */
#define MXC_V_GPIO_EN_GPIO_EN_GPIO ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */
#define MXC_S_GPIO_EN_GPIO_EN_GPIO (MXC_V_GPIO_EN_GPIO_EN_GPIO << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */
/**@} end of group GPIO_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN_SET GPIO_EN_SET
* @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this
* register sets the bits in the same positions in GPIO_EN to 1, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */
#define MXC_F_GPIO_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */
/**@} end of group GPIO_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN_CLR GPIO_EN_CLR
* @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */
#define MXC_F_GPIO_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */
/**@} end of group GPIO_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN GPIO_OUT_EN
* @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one
* GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS 0 /**< OUT_EN_GPIO_OUT_EN Position */
#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN Mask */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS Setting */
#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */
#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN Setting */
/**@} end of group GPIO_OUT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_SET GPIO_OUT_EN_SET
* @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits
* in this register sets the bits in the same positions in GPIO_OUT_EN to 1,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */
#define MXC_F_GPIO_OUT_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */
/**@} end of group GPIO_OUT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_EN_CLR GPIO_OUT_EN_CLR
* @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more
* bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0,
* without affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */
#define MXC_F_GPIO_OUT_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */
/**@} end of group GPIO_OUT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT GPIO_OUT
* @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the
* associated port. This register can be written either directly, or by using the
* GPIO_OUT_SET and GPIO_OUT_CLR registers.
* @{
*/
#define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */
#define MXC_F_GPIO_OUT_GPIO_OUT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */
#define MXC_V_GPIO_OUT_GPIO_OUT_LOW ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_LOW (MXC_V_GPIO_OUT_GPIO_OUT_LOW << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */
#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */
#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH (MXC_V_GPIO_OUT_GPIO_OUT_HIGH << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */
/**@} end of group GPIO_OUT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_SET GPIO_OUT_SET
* @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits
* in the same positions in GPIO_OUT to 1, without affecting other bits in that
* register.
* @{
*/
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS 0 /**< OUT_SET_GPIO_OUT_SET Position */
#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< OUT_SET_GPIO_OUT_SET Mask */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO Setting */
#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */
#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_SET Setting */
/**@} end of group GPIO_OUT_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_OUT_CLR GPIO_OUT_CLR
* @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_OUT to 0, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS 0 /**< OUT_CLR_GPIO_OUT_CLR Position */
#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< OUT_CLR_GPIO_OUT_CLR Mask */
/**@} end of group GPIO_OUT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_IN GPIO_IN
* @brief GPIO Input Register. Read-only register to read from the logic states of the
* GPIO pins on this port.
* @{
*/
#define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */
#define MXC_F_GPIO_IN_GPIO_IN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */
/**@} end of group GPIO_IN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_MOD GPIO_INT_MOD
* @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt
* mode setting for the associated GPIO pin on this port.
* @{
*/
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS 0 /**< INT_MOD_GPIO_INT_MOD Position */
#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< INT_MOD_GPIO_INT_MOD Mask */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_LEVEL Setting */
#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */
#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< INT_MOD_GPIO_INT_MOD_EDGE Setting */
/**@} end of group GPIO_INT_MOD_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_POL GPIO_INT_POL
* @brief GPIO Interrupt Polarity Register. Each bit in this register controls the
* interrupt polarity setting for one GPIO pin in the associated port.
* @{
*/
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS 0 /**< INT_POL_GPIO_INT_POL Position */
#define MXC_F_GPIO_INT_POL_GPIO_INT_POL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< INT_POL_GPIO_INT_POL Mask */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_FALLING Setting */
#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */
#define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< INT_POL_GPIO_INT_POL_RISING Setting */
/**@} end of group GPIO_INT_POL_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN GPIO_INT_EN
* @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO
* interrupt enable for the associated pin on the GPIO port.
* @{
*/
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS 0 /**< INT_EN_GPIO_INT_EN Position */
#define MXC_F_GPIO_INT_EN_GPIO_INT_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN Mask */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS Setting */
#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */
#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN Setting */
/**@} end of group GPIO_INT_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_SET GPIO_INT_EN_SET
* @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets
* the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */
#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< INT_EN_SET_GPIO_INT_EN_SET Mask */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Setting */
#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */
#define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Setting */
/**@} end of group GPIO_INT_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN_CLR GPIO_INT_EN_CLR
* @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_INT_EN to 0, without affecting
* other bits in that register.
* @{
*/
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */
#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< INT_EN_CLR_GPIO_INT_EN_CLR Mask */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Setting */
#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */
#define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Setting */
/**@} end of group GPIO_INT_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_STAT GPIO_INT_STAT
* @brief GPIO Interrupt Status Register. Each bit in this register contains the pending
* interrupt status for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS 0 /**< INT_STAT_GPIO_INT_STAT Position */
#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< INT_STAT_GPIO_INT_STAT Mask */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_NO Setting */
#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */
#define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< INT_STAT_GPIO_INT_STAT_PENDING Setting */
/**@} end of group GPIO_INT_STAT_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_CLR GPIO_INT_CLR
* @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the
* bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits
* in that register.
* @{
*/
#define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */
#define MXC_F_GPIO_INT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */
/**@} end of group GPIO_INT_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN GPIO_WAKE_EN
* @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup
* enable for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS 0 /**< WAKE_EN_GPIO_WAKE_EN Position */
#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< WAKE_EN_GPIO_WAKE_EN Mask */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS Setting */
#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */
#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN Setting */
/**@} end of group GPIO_WAKE_EN_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_SET GPIO_WAKE_EN_SET
* @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the
* bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in
* that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */
#define MXC_F_GPIO_WAKE_EN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL Mask */
/**@} end of group GPIO_WAKE_EN_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_WAKE_EN_CLR GPIO_WAKE_EN_CLR
* @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears
* the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */
#define MXC_F_GPIO_WAKE_EN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL Mask */
/**@} end of group GPIO_WAKE_EN_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_DUAL_EDGE GPIO_INT_DUAL_EDGE
* @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual
* edge mode for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */
#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Mask */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Setting */
#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */
#define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Setting */
/**@} end of group GPIO_INT_DUAL_EDGE_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG1 GPIO_PAD_CFG1
* @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */
#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< PAD_CFG1_GPIO_PAD_CFG1 Mask */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Setting */
#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */
#define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Setting */
/**@} end of group GPIO_PAD_CFG1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PAD_CFG2 GPIO_PAD_CFG2
* @brief GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for
* the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */
#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< PAD_CFG2_GPIO_PAD_CFG2 Mask */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Setting */
#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */
#define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Setting */
/**@} end of group GPIO_PAD_CFG2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1 GPIO_EN1
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */
#define MXC_F_GPIO_EN1_GPIO_EN1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */
#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */
#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */
#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting */
/**@} end of group GPIO_EN1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_SET GPIO_EN1_SET
* @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN1 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */
#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */
/**@} end of group GPIO_EN1_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN1_CLR GPIO_EN1_CLR
* @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register
* clears the bits in the same positions in GPIO_EN1 to 0, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */
#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */
/**@} end of group GPIO_EN1_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2 GPIO_EN2
* @brief GPIO Alternate Function Enable Register. Each bit in this register selects
* between primary/secondary functions for the associated GPIO pin in this port.
* @{
*/
#define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */
#define MXC_F_GPIO_EN2_GPIO_EN2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */
#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */
#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */
#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting */
/**@} end of group GPIO_EN2_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_SET GPIO_EN2_SET
* @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register
* sets the bits in the same positions in GPIO_EN2 to 1, without affecting other
* bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */
#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */
/**@} end of group GPIO_EN2_SET_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_EN2_CLR GPIO_EN2_CLR
* @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this
* register clears the bits in the same positions in GPIO_EN2 to 0, without
* affecting other bits in that register.
* @{
*/
#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */
#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */
/**@} end of group GPIO_EN2_CLR_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS GPIO_DS
* @brief GPIO Drive Strength Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */
#define MXC_F_GPIO_DS_DS ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */
#define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */
#define MXC_S_GPIO_DS_DS_LD (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */
#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */
#define MXC_S_GPIO_DS_DS_HD (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */
/**@} end of group GPIO_DS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_DS1 GPIO_DS1
* @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive
* strength for the associated GPIO pin in this port. Refer to the Datasheet for
* sink/source current of GPIO pins in each mode.
* @{
*/
#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */
#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */
/**@} end of group GPIO_DS1_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_PS GPIO_PS
* @brief GPIO Pull Select Mode.
* @{
*/
#define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */
#define MXC_F_GPIO_PS_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask */
/**@} end of group GPIO_PS_Register */
/**
* @ingroup gpio_registers
* @defgroup GPIO_VSSEL GPIO_VSSEL
* @brief GPIO Voltage Select.
* @{
*/
#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */
#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */
/**@} end of group GPIO_VSSEL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _GPIO_REGS_H_ */

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/**
* @file i2c_regs.h
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _I2C_REGS_H_
#define _I2C_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup i2c
* @defgroup i2c_registers I2C_Registers
* @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
* @details Inter-Integrated Circuit.
*/
/**
* @ingroup i2c_registers
* Structure type to access the I2C Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
__IO uint32_t master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
__IO uint32_t slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
} mxc_i2c_regs_t;
/* Register offsets for module I2C */
/**
* @ingroup i2c_registers
* @defgroup I2C_Register_Offsets Register Offsets
* @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
* @{
*/
#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */
#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */
#define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */
#define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */
#define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */
#define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */
#define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */
#define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */
#define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */
#define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */
#define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */
#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */
#define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */
#define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */
#define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */
#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */
#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */
#define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */
#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */
/**@} end of group i2c_registers */
/**
* @ingroup i2c_registers
* @defgroup I2C_CTRL I2C_CTRL
* @brief Control Register0.
* @{
*/
#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
#define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
#define MXC_V_I2C_CTRL_I2C_EN_DIS ((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
#define MXC_S_I2C_CTRL_I2C_EN_DIS (MXC_V_I2C_CTRL_I2C_EN_DIS << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
#define MXC_V_I2C_CTRL_I2C_EN_EN ((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value */
#define MXC_S_I2C_CTRL_I2C_EN_EN (MXC_V_I2C_CTRL_I2C_EN_EN << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
#define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
#define MXC_V_I2C_CTRL_MST_SLAVE_MODE ((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
#define MXC_S_I2C_CTRL_MST_SLAVE_MODE (MXC_V_I2C_CTRL_MST_SLAVE_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
#define MXC_V_I2C_CTRL_MST_MASTER_MODE ((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
#define MXC_S_I2C_CTRL_MST_MASTER_MODE (MXC_V_I2C_CTRL_MST_MASTER_MODE << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
#define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */
#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS ((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS (MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS Setting */
#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN ((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN (MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN Setting */
#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
#define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
#define MXC_V_I2C_CTRL_RX_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
#define MXC_S_I2C_CTRL_RX_MODE_DIS (MXC_V_I2C_CTRL_RX_MODE_DIS << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_RX_MODE_EN ((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
#define MXC_S_I2C_CTRL_RX_MODE_EN (MXC_V_I2C_CTRL_RX_MODE_EN << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
#define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */
#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK ((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK (MXC_V_I2C_CTRL_RX_MODE_ACK_ACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting */
#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK ((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK (MXC_V_I2C_CTRL_RX_MODE_ACK_NACK << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting */
#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW ((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW (MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Setting */
#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL ((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL (MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting */
#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW ((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW (MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Setting */
#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA ((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA (MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting */
#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
#define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE ((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Setting */
#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE ((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE (MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Setting */
#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
#define MXC_V_I2C_CTRL_READ_WRITE ((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
#define MXC_S_I2C_CTRL_READ_WRITE (MXC_V_I2C_CTRL_READ_WRITE << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
#define MXC_V_I2C_CTRL_READ_READ ((uint32_t)0x1UL) /**< CTRL_READ_READ Value */
#define MXC_S_I2C_CTRL_READ_READ (MXC_V_I2C_CTRL_READ_READ << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**< CTRL_SCL_CLK_STRECH_DIS Mask */
#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN ((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_EN Setting */
#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS ((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS (MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Setting */
#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
#define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */
#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS (MXC_V_I2C_CTRL_SCL_PP_MODE_DIS << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN ((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN (MXC_V_I2C_CTRL_SCL_PP_MODE_EN << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting */
#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
#define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
#define MXC_V_I2C_CTRL_HS_MODE_DIS ((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
#define MXC_S_I2C_CTRL_HS_MODE_DIS (MXC_V_I2C_CTRL_HS_MODE_DIS << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
#define MXC_V_I2C_CTRL_HS_MODE_EN ((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
#define MXC_S_I2C_CTRL_HS_MODE_EN (MXC_V_I2C_CTRL_HS_MODE_EN << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
/**@} end of group I2C_CTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_STATUS I2C_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
#define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */
#define MXC_V_I2C_STATUS_BUS_IDLE ((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
#define MXC_S_I2C_STATUS_BUS_IDLE (MXC_V_I2C_STATUS_BUS_IDLE << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
#define MXC_V_I2C_STATUS_BUS_BUSY ((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
#define MXC_S_I2C_STATUS_BUS_BUSY (MXC_V_I2C_STATUS_BUS_BUSY << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
#define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY (MXC_V_I2C_STATUS_RX_EMPTY_EMPTY << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting */
#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL ((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL (MXC_V_I2C_STATUS_RX_FULL_NOT_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting */
#define MXC_V_I2C_STATUS_RX_FULL_FULL ((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
#define MXC_S_I2C_STATUS_RX_FULL_FULL (MXC_V_I2C_STATUS_RX_FULL_FULL << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
#define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY (MXC_V_I2C_STATUS_TX_EMPTY_EMPTY << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting */
#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY ((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY (MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY Setting */
#define MXC_V_I2C_STATUS_TX_FULL_EMPTY ((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
#define MXC_S_I2C_STATUS_TX_FULL_EMPTY (MXC_V_I2C_STATUS_TX_FULL_EMPTY << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
#define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */
#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Value */
#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK Setting */
#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK ((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Value */
#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK (MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK << MXC_F_I2C_STATUS_CLK_MODE_POS) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK Setting */
#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
#define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
#define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
#define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */
#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
#define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
#define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
#define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
#define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
#define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
#define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
#define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
#define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
#define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
/**@} end of group I2C_STATUS_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_FL0 I2C_INT_FL0
* @brief Interrupt Status Register.
* @{
*/
#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
#define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
#define MXC_V_I2C_INT_FL0_DONE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DONE_INACTIVE (MXC_V_I2C_INT_FL0_DONE_INACTIVE << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DONE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
#define MXC_S_I2C_INT_FL0_DONE_PENDING (MXC_V_I2C_INT_FL0_DONE_PENDING << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
#define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */
#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE (MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING (MXC_V_I2C_INT_FL0_RX_MODE_PENDING << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING Setting */
#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */
#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */
#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING ((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING (MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**< INT_FL0_GEN_CALL_ADDR_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
#define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */
#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING (MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
#define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */
#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING (MXC_V_I2C_INT_FL0_RX_THRESH_PENDING << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
#define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */
#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE (MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING (MXC_V_I2C_INT_FL0_TX_THRESH_PENDING << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING Setting */
#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
#define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
#define MXC_V_I2C_INT_FL0_STOP_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_STOP_INACTIVE (MXC_V_I2C_INT_FL0_STOP_INACTIVE << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_STOP_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
#define MXC_S_I2C_INT_FL0_STOP_PENDING (MXC_V_I2C_INT_FL0_STOP_PENDING << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
#define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */
#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING (MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
#define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE (MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING (MXC_V_I2C_INT_FL0_ARB_ER_PENDING << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
#define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE (MXC_V_I2C_INT_FL0_TO_ER_INACTIVE << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_TO_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_TO_ER_PENDING (MXC_V_I2C_INT_FL0_TO_ER_PENDING << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */
#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */
#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING (MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**< INT_FL0_ADDR_NACK_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
#define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */
#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE (MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING (MXC_V_I2C_INT_FL0_DATA_ER_PENDING << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */
#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */
#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING (MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
#define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */
#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE (MXC_V_I2C_INT_FL0_START_ER_INACTIVE << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_START_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_START_ER_PENDING (MXC_V_I2C_INT_FL0_START_ER_PENDING << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
#define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */
#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE ((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE (MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE Setting */
#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING ((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING (MXC_V_I2C_INT_FL0_STOP_ER_PENDING << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING Setting */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */
/**@} end of group I2C_INT_FL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_EN0 I2C_INT_EN0
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
#define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
#define MXC_V_I2C_INT_EN0_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
#define MXC_S_I2C_INT_EN0_DONE_DIS (MXC_V_I2C_INT_EN0_DONE_DIS << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
#define MXC_V_I2C_INT_EN0_DONE_EN ((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
#define MXC_S_I2C_INT_EN0_DONE_EN (MXC_V_I2C_INT_EN0_DONE_EN << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
#define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */
#define MXC_V_I2C_INT_EN0_RX_MODE_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
#define MXC_S_I2C_INT_EN0_RX_MODE_DIS (MXC_V_I2C_INT_EN0_RX_MODE_DIS << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
#define MXC_V_I2C_INT_EN0_RX_MODE_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
#define MXC_S_I2C_INT_EN0_RX_MODE_EN (MXC_V_I2C_INT_EN0_RX_MODE_EN << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 /**< INT_EN0_GEN_CTRL_ADDR Position */
#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**< INT_EN0_GEN_CTRL_ADDR Mask */
#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS ((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_DIS Setting */
#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN ((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN (MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
#define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */
#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS (MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN (MXC_V_I2C_INT_EN0_ADDR_MATCH_EN << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN Setting */
#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
#define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */
#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS (MXC_V_I2C_INT_EN0_RX_THRESH_DIS << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS Setting */
#define MXC_V_I2C_INT_EN0_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
#define MXC_S_I2C_INT_EN0_RX_THRESH_EN (MXC_V_I2C_INT_EN0_RX_THRESH_EN << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting */
#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
#define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */
#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS (MXC_V_I2C_INT_EN0_TX_THRESH_DIS << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS Setting */
#define MXC_V_I2C_INT_EN0_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
#define MXC_S_I2C_INT_EN0_TX_THRESH_EN (MXC_V_I2C_INT_EN0_TX_THRESH_EN << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting */
#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
#define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
#define MXC_V_I2C_INT_EN0_STOP_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
#define MXC_S_I2C_INT_EN0_STOP_DIS (MXC_V_I2C_INT_EN0_STOP_DIS << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
#define MXC_V_I2C_INT_EN0_STOP_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
#define MXC_S_I2C_INT_EN0_STOP_EN (MXC_V_I2C_INT_EN0_STOP_EN << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
#define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */
#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS (MXC_V_I2C_INT_EN0_ADDR_ACK_DIS << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN (MXC_V_I2C_INT_EN0_ADDR_ACK_EN << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting */
#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
#define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
#define MXC_V_I2C_INT_EN0_ARB_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_ARB_ER_DIS (MXC_V_I2C_INT_EN0_ARB_ER_DIS << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_ARB_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
#define MXC_S_I2C_INT_EN0_ARB_ER_EN (MXC_V_I2C_INT_EN0_ARB_ER_EN << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
#define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
#define MXC_V_I2C_INT_EN0_TO_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_TO_ER_DIS (MXC_V_I2C_INT_EN0_TO_ER_DIS << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_TO_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
#define MXC_S_I2C_INT_EN0_TO_ER_EN (MXC_V_I2C_INT_EN0_TO_ER_EN << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
#define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER Mask */
#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS (MXC_V_I2C_INT_EN0_ADDR_ER_DIS << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_ADDR_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
#define MXC_S_I2C_INT_EN0_ADDR_ER_EN (MXC_V_I2C_INT_EN0_ADDR_ER_EN << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
#define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */
#define MXC_V_I2C_INT_EN0_DATA_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_DATA_ER_DIS (MXC_V_I2C_INT_EN0_DATA_ER_DIS << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_DATA_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
#define MXC_S_I2C_INT_EN0_DATA_ER_EN (MXC_V_I2C_INT_EN0_DATA_ER_EN << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */
#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */
#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN (MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**< INT_EN0_DO_NOT_RESP_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
#define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */
#define MXC_V_I2C_INT_EN0_START_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_START_ER_DIS (MXC_V_I2C_INT_EN0_START_ER_DIS << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_START_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
#define MXC_S_I2C_INT_EN0_START_ER_EN (MXC_V_I2C_INT_EN0_START_ER_EN << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
#define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */
#define MXC_V_I2C_INT_EN0_STOP_ER_DIS ((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
#define MXC_S_I2C_INT_EN0_STOP_ER_DIS (MXC_V_I2C_INT_EN0_STOP_ER_DIS << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
#define MXC_V_I2C_INT_EN0_STOP_ER_EN ((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
#define MXC_S_I2C_INT_EN0_STOP_ER_EN (MXC_V_I2C_INT_EN0_STOP_ER_EN << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */
#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS ((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS Setting */
#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN ((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN (MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN Setting */
/**@} end of group I2C_INT_EN0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_FL1 I2C_INT_FL1
* @brief Interrupt Status Register 1.
* @{
*/
#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */
#define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */
#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_INACTIVE Setting */
#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING (MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**< INT_FL1_RX_OVERFLOW_PENDING Setting */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */
#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE ((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Setting */
#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING ((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING (MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**< INT_FL1_TX_UNDERFLOW_PENDING Setting */
/**@} end of group I2C_INT_FL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_INT_EN1 I2C_INT_EN1
* @brief Interrupt Staus Register 1.
* @{
*/
#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */
#define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */
#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS (MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS Setting */
#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN (MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN Setting */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */
#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS ((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS Setting */
#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN ((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN (MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN Setting */
/**@} end of group I2C_INT_EN1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO_LEN I2C_FIFO_LEN
* @brief FIFO Configuration Register.
* @{
*/
#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
#define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */
#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
#define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */
/**@} end of group I2C_FIFO_LEN_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0
* @brief Receive Control Register 0.
* @{
*/
#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
#define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND ((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND (MXC_V_I2C_RX_CTRL0_DNR_RESPOND << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY ((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY (MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Setting */
#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
#define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */
#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED (MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Setting */
#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH (MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH Setting */
#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
#define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */
/**@} end of group I2C_RX_CTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1
* @brief Receive Control Register 1.
* @{
*/
#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
#define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */
#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
#define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */
/**@} end of group I2C_RX_CTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0
* @brief Transmit Control Register 0.
* @{
*/
#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */
#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */
#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN ((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_EN Setting */
#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS ((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS (MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**< TX_CTRL0_TX_READY_MODE_DIS Setting */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */
#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED ((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED (MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Setting */
#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH ((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH (MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH Setting */
#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
#define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */
/**@} end of group I2C_TX_CTRL0_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1
* @brief Transmit Control Register 1.
* @{
*/
#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
#define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */
#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
#define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST Mask */
#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW ((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW (MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Setting */
#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION ((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION (MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Setting */
#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
#define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO Mask */
/**@} end of group I2C_TX_CTRL1_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_FIFO I2C_FIFO
* @brief Data Register.
* @{
*/
#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
/**@} end of group I2C_FIFO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL
* @brief Master Control Register.
* @{
*/
#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
#define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */
#define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */
#define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */
#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
#define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */
#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */
#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */
#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Setting */
#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Setting */
#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 /**< MASTER_CTRL_MASTER_CODE Position */
#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**< MASTER_CTRL_MASTER_CODE Mask */
#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */
#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN ((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_EN Setting */
#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS ((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS (MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Setting */
/**@} end of group I2C_MASTER_CTRL_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLK_LO I2C_CLK_LO
* @brief Clock Low Register.
* @{
*/
#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
#define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
/**@} end of group I2C_CLK_LO_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_CLK_HI I2C_CLK_HI
* @brief Clock high Register.
* @{
*/
#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
#define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
/**@} end of group I2C_CLK_HI_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_HS_CLK I2C_HS_CLK
* @brief HS-Mode Clock Control Register
* @{
*/
#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */
/**@} end of group I2C_HS_CLK_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_TIMEOUT I2C_TIMEOUT
* @brief Timeout Register
* @{
*/
#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
/**@} end of group I2C_TIMEOUT_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR
* @brief Slave Address Register.
* @{
*/
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */
#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS ((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Setting */
#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS ((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS (MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Setting */
/**@} end of group I2C_SLAVE_ADDR_Register */
/**
* @ingroup i2c_registers
* @defgroup I2C_DMA I2C_DMA
* @brief DMA Register.
* @{
*/
#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
#define MXC_S_I2C_DMA_TX_EN_DIS (MXC_V_I2C_DMA_TX_EN_DIS << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
#define MXC_S_I2C_DMA_TX_EN_EN (MXC_V_I2C_DMA_TX_EN_EN << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
#define MXC_S_I2C_DMA_RX_EN_DIS (MXC_V_I2C_DMA_RX_EN_DIS << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
#define MXC_S_I2C_DMA_RX_EN_EN (MXC_V_I2C_DMA_RX_EN_EN << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
/**@} end of group I2C_DMA_Register */
#ifdef __cplusplus
}
#endif
#endif /* _I2C_REGS_H_ */

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@ -0,0 +1,167 @@
/**
* @file icc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _ICC_REGS_H_
#define _ICC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup icc
* @defgroup icc_registers ICC_Registers
* @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module.
* @details Instruction Cache Controller Registers
*/
/**
* @ingroup icc_registers
* Structure type to access the ICC Registers.
*/
typedef struct {
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
__I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> ICC MEMCFG Register */
__R uint32_t rsv_0x8_0xff[62];
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
__R uint32_t rsv_0x104_0x6ff[383];
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
} mxc_icc_regs_t;
/* Register offsets for module ICC */
/**
* @ingroup icc_registers
* @defgroup ICC_Register_Offsets Register Offsets
* @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address.
* @{
*/
#define MXC_R_ICC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: <tt> 0x0000</tt> */
#define MXC_R_ICC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: <tt> 0x0004</tt> */
#define MXC_R_ICC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: <tt> 0x0100</tt> */
#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: <tt> 0x0700</tt> */
/**@} end of group icc_registers */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_ID ICC_CACHE_ID
* @brief Cache ID Register.
* @{
*/
#define MXC_F_ICC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
#define MXC_F_ICC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
#define MXC_F_ICC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
#define MXC_F_ICC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
#define MXC_F_ICC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
#define MXC_F_ICC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_ICC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
/**@} end of group ICC_CACHE_ID_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_MEMCFG ICC_MEMCFG
* @brief Memory Configuration Register.
* @{
*/
#define MXC_F_ICC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
#define MXC_F_ICC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
#define MXC_F_ICC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
#define MXC_F_ICC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_ICC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
/**@} end of group ICC_MEMCFG_Register */
/**
* @ingroup icc_registers
* @defgroup ICC_CACHE_CTRL ICC_CACHE_CTRL
* @brief Cache Control and Status Register.
* @{
*/
#define MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
#define MXC_F_ICC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_EN_DIS Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_DIS (MXC_V_ICC_CACHE_CTRL_CACHE_EN_DIS << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_DIS Setting */
#define MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_EN_EN Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_EN_EN (MXC_V_ICC_CACHE_CTRL_CACHE_EN_EN << MXC_F_ICC_CACHE_CTRL_CACHE_EN_POS) /**< CACHE_CTRL_CACHE_EN_EN Setting */
#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
#define MXC_F_ICC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY ((uint32_t)0x0UL) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_NOTREADY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_NOTREADY Setting */
#define MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY ((uint32_t)0x1UL) /**< CACHE_CTRL_CACHE_RDY_READY Value */
#define MXC_S_ICC_CACHE_CTRL_CACHE_RDY_READY (MXC_V_ICC_CACHE_CTRL_CACHE_RDY_READY << MXC_F_ICC_CACHE_CTRL_CACHE_RDY_POS) /**< CACHE_CTRL_CACHE_RDY_READY Setting */
/**@} end of group ICC_CACHE_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _ICC_REGS_H_ */

0
bsp/maxim/libraries/CMSIS/max32660.h → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/max32660.h
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51
bsp/maxim/libraries/CMSIS/mxc_config.h → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/mxc_device.h
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@ -1,8 +1,3 @@
/**
* @file mxc_config.h
* @brief Top-level include file for device configuration.
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
@ -34,20 +29,44 @@
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-08-09 18:45:02 -0500 (Thu, 09 Aug 2018) $
* $Revision: 36818 $
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
#ifndef _MXC_CONFIG_H
#define _MXC_CONFIG_H
/**
* @file mxc_device.h
* @brief contains device and revision specific definitions
*/
#ifndef _MXC_DEVICE_H_
#define _MXC_DEVICE_H_
#if !defined __GNUC__
#include "RTE_Components.h"
#endif /* not __GNUC__ */
#include "max32660.h"
#include "mxc_device.h"
#include "mxc_errors.h"
#include "mxc_pins.h"
#ifndef TARGET
#error TARGET NOT DEFINED
#endif
#endif /* _CONFIG_H */
// Create a string definition for the TARGET
#define STRING_ARG(arg) #arg
#define STRING_NAME(name) STRING_ARG(name)
#define TARGET_NAME STRING_NAME(TARGET)
// Define which revisions of the IP we are using
#ifndef TARGET_REV
#error TARGET_REV NOT DEFINED
#endif
#if(TARGET_REV == 0x4131)
// A1
#define MXC_PBM_REV 0
#define MXC_TMR_REV 0
#define MXC_UART_REV 1
#else
#error TARGET_REV NOT SUPPORTED
#endif // if(TARGET_REV == ...)
#endif /* _MXC_DEVICE_H_ */

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/**
* @file pwrseq_regs.h
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup pwrseq
* @defgroup pwrseq_registers PWRSEQ_Registers
* @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module.
* @details Power Sequencer / Low Power Control Register.
*/
/**
* @ingroup pwrseq_registers
* Structure type to access the PWRSEQ Registers.
*/
typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__R uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_Register_Offsets Register Offsets
* @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address.
* @{
*/
#define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */
#define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */
#define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
/**@} end of group pwrseq_registers */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL
* @brief Low Power Control Register.
* @{
*/
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
#define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */
/**@} end of group PWRSEQ_LP_CTRL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL
* @brief Low Power Mode Wakeup Flags for GPIO0
* @{
*/
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */
/**@} end of group PWRSEQ_LP_WAKEFL_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN
* @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup
* functionality for GPIO0.
* @{
*/
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */
/**@} end of group PWRSEQ_LPWK_EN_Register */
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD
* @brief Low Power Memory Shutdown Control.
* @{
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */
/**@} end of group PWRSEQ_LPMEMSD_Register */
#ifdef __cplusplus
}
#endif
#endif /* _PWRSEQ_REGS_H_ */

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/**
* @file rtc_regs.h
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _RTC_REGS_H_
#define _RTC_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup rtc
* @defgroup rtc_registers RTC_Registers
* @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module.
* @details Real Time Clock and Alarm.
*/
/**
* @ingroup rtc_registers
* Structure type to access the RTC Registers.
*/
typedef struct {
__IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */
__IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */
__IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */
__IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */
__IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */
__IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
} mxc_rtc_regs_t;
/* Register offsets for module RTC */
/**
* @ingroup rtc_registers
* @defgroup RTC_Register_Offsets Register Offsets
* @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address.
* @{
*/
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
#define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
#define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
/**@} end of group rtc_registers */
/**
* @ingroup rtc_registers
* @defgroup RTC_SSEC RTC_SSEC
* @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented
* when this register rolls over from 0xFF to 0x00.
* @{
*/
#define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
#define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
/**@} end of group RTC_SSEC_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RAS RTC_RAS
* @brief Time-of-day Alarm.
* @{
*/
#define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
#define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
/**@} end of group RTC_RAS_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_RSSA RTC_RSSA
* @brief RTC sub-second alarm. This register contains the reload value for the sub-
* second alarm.
* @{
*/
#define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
#define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
/**@} end of group RTC_RSSA_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_CTRL RTC_CTRL
* @brief RTC Control Register.
* @{
*/
#define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */
#define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */
#define MXC_V_RTC_CTRL_RTCE_DIS ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */
#define MXC_S_RTC_CTRL_RTCE_DIS (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */
#define MXC_V_RTC_CTRL_RTCE_EN ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */
#define MXC_S_RTC_CTRL_RTCE_EN (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */
#define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */
#define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */
#define MXC_V_RTC_CTRL_ADE_DIS ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */
#define MXC_S_RTC_CTRL_ADE_DIS (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */
#define MXC_V_RTC_CTRL_ADE_EN ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */
#define MXC_S_RTC_CTRL_ADE_EN (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */
#define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */
#define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */
#define MXC_V_RTC_CTRL_ASE_DIS ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */
#define MXC_S_RTC_CTRL_ASE_DIS (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */
#define MXC_V_RTC_CTRL_ASE_EN ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */
#define MXC_S_RTC_CTRL_ASE_EN (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */
#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */
#define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */
#define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */
#define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */
#define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */
#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
#define MXC_V_RTC_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */
#define MXC_S_RTC_CTRL_RDY_BUSY (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */
#define MXC_V_RTC_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */
#define MXC_S_RTC_CTRL_RDY_READY (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */
#define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */
#define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */
#define MXC_V_RTC_CTRL_RDYE_DIS ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */
#define MXC_S_RTC_CTRL_RDYE_DIS (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */
#define MXC_V_RTC_CTRL_RDYE_EN ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */
#define MXC_S_RTC_CTRL_RDYE_EN (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */
#define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */
#define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */
#define MXC_V_RTC_CTRL_ALDF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */
#define MXC_S_RTC_CTRL_ALDF_INACTIVE (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */
#define MXC_V_RTC_CTRL_ALDF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */
#define MXC_S_RTC_CTRL_ALDF_PENDING (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */
#define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */
#define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */
#define MXC_V_RTC_CTRL_ALSF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */
#define MXC_S_RTC_CTRL_ALSF_INACTIVE (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */
#define MXC_V_RTC_CTRL_ALSF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */
#define MXC_S_RTC_CTRL_ALSF_PENDING (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */
#define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */
#define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */
#define MXC_V_RTC_CTRL_SQE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */
#define MXC_S_RTC_CTRL_SQE_INACTIVE (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */
#define MXC_V_RTC_CTRL_SQE_PENDING ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */
#define MXC_S_RTC_CTRL_SQE_PENDING (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */
#define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */
#define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */
#define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */
#define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */
#define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
#define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
#define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
#define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
#define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
#define MXC_V_RTC_CTRL_WE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */
#define MXC_S_RTC_CTRL_WE_INACTIVE (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */
#define MXC_V_RTC_CTRL_WE_PENDING ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */
#define MXC_S_RTC_CTRL_WE_PENDING (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */
/**@} end of group RTC_CTRL_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_TRIM RTC_TRIM
* @brief RTC Trim Register.
* @{
*/
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
#define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
#define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
/**@} end of group RTC_TRIM_Register */
/**
* @ingroup rtc_registers
* @defgroup RTC_OSCCTRL RTC_OSCCTRL
* @brief RTC Oscillator Control Register.
* @{
*/
#define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
#define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
#define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */
#define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */
#define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */
#define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */
#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
#define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */
#define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */
/**@} end of group RTC_OSCCTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _RTC_REGS_H_ */

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/**
* @file sir_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SIR_REGS_H_
#define _SIR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup sir
* @defgroup sir_registers SIR_Registers
* @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module.
* @details System Initialization Registers.
*/
/**
* @ingroup sir_registers
* Structure type to access the SIR Registers.
*/
typedef struct {
__I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */
__I uint32_t erraddr; /**< <tt>\b 0x04:</tt> SIR ERRADDR Register */
__R uint32_t rsv_0x8_0xff[62];
__I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */
__I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */
} mxc_sir_regs_t;
/* Register offsets for module SIR */
/**
* @ingroup sir_registers
* @defgroup SIR_Register_Offsets Register Offsets
* @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address.
* @{
*/
#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */
#define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */
#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */
#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */
/**@} end of group sir_registers */
/**
* @ingroup sir_registers
* @defgroup SIR_SISTAT SIR_SISTAT
* @brief System Initialization Status Register.
* @{
*/
#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */
#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */
#define MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET ((uint32_t)0x0UL) /**< SISTAT_MAGIC_MAGICNOTSET Value */
#define MXC_S_SIR_SISTAT_MAGIC_MAGICNOTSET (MXC_V_SIR_SISTAT_MAGIC_MAGICNOTSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICNOTSET Setting */
#define MXC_V_SIR_SISTAT_MAGIC_MAGICSET ((uint32_t)0x1UL) /**< SISTAT_MAGIC_MAGICSET Value */
#define MXC_S_SIR_SISTAT_MAGIC_MAGICSET (MXC_V_SIR_SISTAT_MAGIC_MAGICSET << MXC_F_SIR_SISTAT_MAGIC_POS) /**< SISTAT_MAGIC_MAGICSET Setting */
#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */
#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */
#define MXC_V_SIR_SISTAT_CRCERR_NOERROR ((uint32_t)0x0UL) /**< SISTAT_CRCERR_NOERROR Value */
#define MXC_S_SIR_SISTAT_CRCERR_NOERROR (MXC_V_SIR_SISTAT_CRCERR_NOERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_NOERROR Setting */
#define MXC_V_SIR_SISTAT_CRCERR_ERROR ((uint32_t)0x1UL) /**< SISTAT_CRCERR_ERROR Value */
#define MXC_S_SIR_SISTAT_CRCERR_ERROR (MXC_V_SIR_SISTAT_CRCERR_ERROR << MXC_F_SIR_SISTAT_CRCERR_POS) /**< SISTAT_CRCERR_ERROR Setting */
/**@} end of group SIR_SISTAT_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_ERRADDR SIR_ERRADDR
* @brief Read-only field set by the SIB block if a CRC error occurs during the read of
* the OTP memory. Contains the failing address in OTP memory (when CRCERR equals
* 1).
* @{
*/
#define MXC_F_SIR_ERRADDR_ERRADDR_POS 0 /**< ERRADDR_ERRADDR Position */
#define MXC_F_SIR_ERRADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ERRADDR_ERRADDR_POS)) /**< ERRADDR_ERRADDR Mask */
/**@} end of group SIR_ERRADDR_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_FSTAT SIR_FSTAT
* @brief funcstat register.
* @{
*/
#define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */
#define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */
#define MXC_V_SIR_FSTAT_FPU_NO ((uint32_t)0x0UL) /**< FSTAT_FPU_NO Value */
#define MXC_S_SIR_FSTAT_FPU_NO (MXC_V_SIR_FSTAT_FPU_NO << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_NO Setting */
#define MXC_V_SIR_FSTAT_FPU_YES ((uint32_t)0x1UL) /**< FSTAT_FPU_YES Value */
#define MXC_S_SIR_FSTAT_FPU_YES (MXC_V_SIR_FSTAT_FPU_YES << MXC_F_SIR_FSTAT_FPU_POS) /**< FSTAT_FPU_YES Setting */
#define MXC_F_SIR_FSTAT_USB_POS 1 /**< FSTAT_USB Position */
#define MXC_F_SIR_FSTAT_USB ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_USB_POS)) /**< FSTAT_USB Mask */
#define MXC_V_SIR_FSTAT_USB_NO ((uint32_t)0x0UL) /**< FSTAT_USB_NO Value */
#define MXC_S_SIR_FSTAT_USB_NO (MXC_V_SIR_FSTAT_USB_NO << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_NO Setting */
#define MXC_V_SIR_FSTAT_USB_YES ((uint32_t)0x1UL) /**< FSTAT_USB_YES Value */
#define MXC_S_SIR_FSTAT_USB_YES (MXC_V_SIR_FSTAT_USB_YES << MXC_F_SIR_FSTAT_USB_POS) /**< FSTAT_USB_YES Setting */
#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */
#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */
#define MXC_V_SIR_FSTAT_ADC_NO ((uint32_t)0x0UL) /**< FSTAT_ADC_NO Value */
#define MXC_S_SIR_FSTAT_ADC_NO (MXC_V_SIR_FSTAT_ADC_NO << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_NO Setting */
#define MXC_V_SIR_FSTAT_ADC_YES ((uint32_t)0x1UL) /**< FSTAT_ADC_YES Value */
#define MXC_S_SIR_FSTAT_ADC_YES (MXC_V_SIR_FSTAT_ADC_YES << MXC_F_SIR_FSTAT_ADC_POS) /**< FSTAT_ADC_YES Setting */
#define MXC_F_SIR_FSTAT_XIP_POS 3 /**< FSTAT_XIP Position */
#define MXC_F_SIR_FSTAT_XIP ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_XIP_POS)) /**< FSTAT_XIP Mask */
#define MXC_V_SIR_FSTAT_XIP_NO ((uint32_t)0x0UL) /**< FSTAT_XIP_NO Value */
#define MXC_S_SIR_FSTAT_XIP_NO (MXC_V_SIR_FSTAT_XIP_NO << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_NO Setting */
#define MXC_V_SIR_FSTAT_XIP_YES ((uint32_t)0x1UL) /**< FSTAT_XIP_YES Value */
#define MXC_S_SIR_FSTAT_XIP_YES (MXC_V_SIR_FSTAT_XIP_YES << MXC_F_SIR_FSTAT_XIP_POS) /**< FSTAT_XIP_YES Setting */
#define MXC_F_SIR_FSTAT_PBM_POS 4 /**< FSTAT_PBM Position */
#define MXC_F_SIR_FSTAT_PBM ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_PBM_POS)) /**< FSTAT_PBM Mask */
#define MXC_V_SIR_FSTAT_PBM_NO ((uint32_t)0x0UL) /**< FSTAT_PBM_NO Value */
#define MXC_S_SIR_FSTAT_PBM_NO (MXC_V_SIR_FSTAT_PBM_NO << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_NO Setting */
#define MXC_V_SIR_FSTAT_PBM_YES ((uint32_t)0x1UL) /**< FSTAT_PBM_YES Value */
#define MXC_S_SIR_FSTAT_PBM_YES (MXC_V_SIR_FSTAT_PBM_YES << MXC_F_SIR_FSTAT_PBM_POS) /**< FSTAT_PBM_YES Setting */
#define MXC_F_SIR_FSTAT_HBC_POS 5 /**< FSTAT_HBC Position */
#define MXC_F_SIR_FSTAT_HBC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_HBC_POS)) /**< FSTAT_HBC Mask */
#define MXC_V_SIR_FSTAT_HBC_NO ((uint32_t)0x0UL) /**< FSTAT_HBC_NO Value */
#define MXC_S_SIR_FSTAT_HBC_NO (MXC_V_SIR_FSTAT_HBC_NO << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_NO Setting */
#define MXC_V_SIR_FSTAT_HBC_YES ((uint32_t)0x1UL) /**< FSTAT_HBC_YES Value */
#define MXC_S_SIR_FSTAT_HBC_YES (MXC_V_SIR_FSTAT_HBC_YES << MXC_F_SIR_FSTAT_HBC_POS) /**< FSTAT_HBC_YES Setting */
#define MXC_F_SIR_FSTAT_SDHC_POS 6 /**< FSTAT_SDHC Position */
#define MXC_F_SIR_FSTAT_SDHC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SDHC_POS)) /**< FSTAT_SDHC Mask */
#define MXC_V_SIR_FSTAT_SDHC_NO ((uint32_t)0x0UL) /**< FSTAT_SDHC_NO Value */
#define MXC_S_SIR_FSTAT_SDHC_NO (MXC_V_SIR_FSTAT_SDHC_NO << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_NO Setting */
#define MXC_V_SIR_FSTAT_SDHC_YES ((uint32_t)0x1UL) /**< FSTAT_SDHC_YES Value */
#define MXC_S_SIR_FSTAT_SDHC_YES (MXC_V_SIR_FSTAT_SDHC_YES << MXC_F_SIR_FSTAT_SDHC_POS) /**< FSTAT_SDHC_YES Setting */
#define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */
#define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */
#define MXC_V_SIR_FSTAT_SMPHR_NO ((uint32_t)0x0UL) /**< FSTAT_SMPHR_NO Value */
#define MXC_S_SIR_FSTAT_SMPHR_NO (MXC_V_SIR_FSTAT_SMPHR_NO << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_NO Setting */
#define MXC_V_SIR_FSTAT_SMPHR_YES ((uint32_t)0x1UL) /**< FSTAT_SMPHR_YES Value */
#define MXC_S_SIR_FSTAT_SMPHR_YES (MXC_V_SIR_FSTAT_SMPHR_YES << MXC_F_SIR_FSTAT_SMPHR_POS) /**< FSTAT_SMPHR_YES Setting */
#define MXC_F_SIR_FSTAT_SCACHE_POS 8 /**< FSTAT_SCACHE Position */
#define MXC_F_SIR_FSTAT_SCACHE ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SCACHE_POS)) /**< FSTAT_SCACHE Mask */
#define MXC_V_SIR_FSTAT_SCACHE_NO ((uint32_t)0x0UL) /**< FSTAT_SCACHE_NO Value */
#define MXC_S_SIR_FSTAT_SCACHE_NO (MXC_V_SIR_FSTAT_SCACHE_NO << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_NO Setting */
#define MXC_V_SIR_FSTAT_SCACHE_YES ((uint32_t)0x1UL) /**< FSTAT_SCACHE_YES Value */
#define MXC_S_SIR_FSTAT_SCACHE_YES (MXC_V_SIR_FSTAT_SCACHE_YES << MXC_F_SIR_FSTAT_SCACHE_POS) /**< FSTAT_SCACHE_YES Setting */
/**@} end of group SIR_FSTAT_Register */
/**
* @ingroup sir_registers
* @defgroup SIR_SFSTAT SIR_SFSTAT
* @brief secfuncstat register.
* @{
*/
#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */
#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */
#define MXC_V_SIR_SFSTAT_TRNG_NO ((uint32_t)0x0UL) /**< SFSTAT_TRNG_NO Value */
#define MXC_S_SIR_SFSTAT_TRNG_NO (MXC_V_SIR_SFSTAT_TRNG_NO << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_NO Setting */
#define MXC_V_SIR_SFSTAT_TRNG_YES ((uint32_t)0x1UL) /**< SFSTAT_TRNG_YES Value */
#define MXC_S_SIR_SFSTAT_TRNG_YES (MXC_V_SIR_SFSTAT_TRNG_YES << MXC_F_SIR_SFSTAT_TRNG_POS) /**< SFSTAT_TRNG_YES Setting */
#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */
#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */
#define MXC_V_SIR_SFSTAT_AES_NO ((uint32_t)0x0UL) /**< SFSTAT_AES_NO Value */
#define MXC_S_SIR_SFSTAT_AES_NO (MXC_V_SIR_SFSTAT_AES_NO << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_NO Setting */
#define MXC_V_SIR_SFSTAT_AES_YES ((uint32_t)0x1UL) /**< SFSTAT_AES_YES Value */
#define MXC_S_SIR_SFSTAT_AES_YES (MXC_V_SIR_SFSTAT_AES_YES << MXC_F_SIR_SFSTAT_AES_POS) /**< SFSTAT_AES_YES Setting */
#define MXC_F_SIR_SFSTAT_SHA_POS 4 /**< SFSTAT_SHA Position */
#define MXC_F_SIR_SFSTAT_SHA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SHA_POS)) /**< SFSTAT_SHA Mask */
#define MXC_V_SIR_SFSTAT_SHA_NO ((uint32_t)0x0UL) /**< SFSTAT_SHA_NO Value */
#define MXC_S_SIR_SFSTAT_SHA_NO (MXC_V_SIR_SFSTAT_SHA_NO << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_NO Setting */
#define MXC_V_SIR_SFSTAT_SHA_YES ((uint32_t)0x1UL) /**< SFSTAT_SHA_YES Value */
#define MXC_S_SIR_SFSTAT_SHA_YES (MXC_V_SIR_SFSTAT_SHA_YES << MXC_F_SIR_SFSTAT_SHA_POS) /**< SFSTAT_SHA_YES Setting */
#define MXC_F_SIR_SFSTAT_MAA_POS 5 /**< SFSTAT_MAA Position */
#define MXC_F_SIR_SFSTAT_MAA ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_MAA_POS)) /**< SFSTAT_MAA Mask */
#define MXC_V_SIR_SFSTAT_MAA_NO ((uint32_t)0x0UL) /**< SFSTAT_MAA_NO Value */
#define MXC_S_SIR_SFSTAT_MAA_NO (MXC_V_SIR_SFSTAT_MAA_NO << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_NO Setting */
#define MXC_V_SIR_SFSTAT_MAA_YES ((uint32_t)0x1UL) /**< SFSTAT_MAA_YES Value */
#define MXC_S_SIR_SFSTAT_MAA_YES (MXC_V_SIR_SFSTAT_MAA_YES << MXC_F_SIR_SFSTAT_MAA_POS) /**< SFSTAT_MAA_YES Setting */
/**@} end of group SIR_SFSTAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SIR_REGS_H_ */

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/**
* @file smon_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SMON_REGS_H_
#define _SMON_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup smon
* @defgroup smon_registers SMON_Registers
* @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module.
* @details The Security Monitor block used to monitor system threat conditions.
*/
/**
* @ingroup smon_registers
* Structure type to access the SMON Registers.
*/
typedef struct {
__IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */
__IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON INTSCN Register */
__IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */
__I uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */
__I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON DLRTC Register */
__R uint32_t rsv_0x14_0x33[8];
__I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */
} mxc_smon_regs_t;
/* Register offsets for module SMON */
/**
* @ingroup smon_registers
* @defgroup SMON_Register_Offsets Register Offsets
* @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address.
* @{
*/
#define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */
#define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */
#define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */
#define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */
#define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */
#define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */
/**@} end of group smon_registers */
/**
* @ingroup smon_registers
* @defgroup SMON_EXTSCN SMON_EXTSCN
* @brief External Sensor Control Register.
* @{
*/
#define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN0_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN0_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN0_DIS (MXC_V_SMON_EXTSCN_EXTS_EN0_DIS << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN0_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN0_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN0_EN (MXC_V_SMON_EXTSCN_EXTS_EN0_EN << MXC_F_SMON_EXTSCN_EXTS_EN0_POS) /**< EXTSCN_EXTS_EN0_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN1_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN1_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN1_DIS (MXC_V_SMON_EXTSCN_EXTS_EN1_DIS << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN1_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN1_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN1_EN (MXC_V_SMON_EXTSCN_EXTS_EN1_EN << MXC_F_SMON_EXTSCN_EXTS_EN1_POS) /**< EXTSCN_EXTS_EN1_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN2_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN2_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN2_DIS (MXC_V_SMON_EXTSCN_EXTS_EN2_DIS << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN2_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN2_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN2_EN (MXC_V_SMON_EXTSCN_EXTS_EN2_EN << MXC_F_SMON_EXTSCN_EXTS_EN2_POS) /**< EXTSCN_EXTS_EN2_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN3_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN3_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN3_DIS (MXC_V_SMON_EXTSCN_EXTS_EN3_DIS << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN3_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN3_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN3_EN (MXC_V_SMON_EXTSCN_EXTS_EN3_EN << MXC_F_SMON_EXTSCN_EXTS_EN3_POS) /**< EXTSCN_EXTS_EN3_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN4_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN4_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN4_DIS (MXC_V_SMON_EXTSCN_EXTS_EN4_DIS << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN4_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN4_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN4_EN (MXC_V_SMON_EXTSCN_EXTS_EN4_EN << MXC_F_SMON_EXTSCN_EXTS_EN4_POS) /**< EXTSCN_EXTS_EN4_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */
#define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */
#define MXC_V_SMON_EXTSCN_EXTS_EN5_DIS ((uint32_t)0x0UL) /**< EXTSCN_EXTS_EN5_DIS Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN5_DIS (MXC_V_SMON_EXTSCN_EXTS_EN5_DIS << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_DIS Setting */
#define MXC_V_SMON_EXTSCN_EXTS_EN5_EN ((uint32_t)0x1UL) /**< EXTSCN_EXTS_EN5_EN Value */
#define MXC_S_SMON_EXTSCN_EXTS_EN5_EN (MXC_V_SMON_EXTSCN_EXTS_EN5_EN << MXC_F_SMON_EXTSCN_EXTS_EN5_POS) /**< EXTSCN_EXTS_EN5_EN Setting */
#define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */
#define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */
#define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */
#define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */
#define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */
#define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */
#define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */
#define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */
#define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */
#define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */
#define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */
#define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */
#define MXC_V_SMON_EXTSCN_BUSY_IDLE ((uint32_t)0x0UL) /**< EXTSCN_BUSY_IDLE Value */
#define MXC_S_SMON_EXTSCN_BUSY_IDLE (MXC_V_SMON_EXTSCN_BUSY_IDLE << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_IDLE Setting */
#define MXC_V_SMON_EXTSCN_BUSY_BUSY ((uint32_t)0x1UL) /**< EXTSCN_BUSY_BUSY Value */
#define MXC_S_SMON_EXTSCN_BUSY_BUSY (MXC_V_SMON_EXTSCN_BUSY_BUSY << MXC_F_SMON_EXTSCN_BUSY_POS) /**< EXTSCN_BUSY_BUSY Setting */
#define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */
#define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */
#define MXC_V_SMON_EXTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< EXTSCN_LOCK_UNLOCKED Value */
#define MXC_S_SMON_EXTSCN_LOCK_UNLOCKED (MXC_V_SMON_EXTSCN_LOCK_UNLOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_UNLOCKED Setting */
#define MXC_V_SMON_EXTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< EXTSCN_LOCK_LOCKED Value */
#define MXC_S_SMON_EXTSCN_LOCK_LOCKED (MXC_V_SMON_EXTSCN_LOCK_LOCKED << MXC_F_SMON_EXTSCN_LOCK_POS) /**< EXTSCN_LOCK_LOCKED Setting */
/**@} end of group SMON_EXTSCN_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_INTSCN SMON_INTSCN
* @brief Internal Sensor Control Register.
* @{
*/
#define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */
#define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */
#define MXC_V_SMON_INTSCN_SHIELD_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_SHIELD_EN_DIS Value */
#define MXC_S_SMON_INTSCN_SHIELD_EN_DIS (MXC_V_SMON_INTSCN_SHIELD_EN_DIS << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_SHIELD_EN_EN ((uint32_t)0x1UL) /**< INTSCN_SHIELD_EN_EN Value */
#define MXC_S_SMON_INTSCN_SHIELD_EN_EN (MXC_V_SMON_INTSCN_SHIELD_EN_EN << MXC_F_SMON_INTSCN_SHIELD_EN_POS) /**< INTSCN_SHIELD_EN_EN Setting */
#define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */
#define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */
#define MXC_V_SMON_INTSCN_TEMP_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_TEMP_EN_DIS Value */
#define MXC_S_SMON_INTSCN_TEMP_EN_DIS (MXC_V_SMON_INTSCN_TEMP_EN_DIS << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_TEMP_EN_EN ((uint32_t)0x1UL) /**< INTSCN_TEMP_EN_EN Value */
#define MXC_S_SMON_INTSCN_TEMP_EN_EN (MXC_V_SMON_INTSCN_TEMP_EN_EN << MXC_F_SMON_INTSCN_TEMP_EN_POS) /**< INTSCN_TEMP_EN_EN Setting */
#define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */
#define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */
#define MXC_V_SMON_INTSCN_VBAT_EN_DIS ((uint32_t)0x0UL) /**< INTSCN_VBAT_EN_DIS Value */
#define MXC_S_SMON_INTSCN_VBAT_EN_DIS (MXC_V_SMON_INTSCN_VBAT_EN_DIS << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_DIS Setting */
#define MXC_V_SMON_INTSCN_VBAT_EN_EN ((uint32_t)0x1UL) /**< INTSCN_VBAT_EN_EN Value */
#define MXC_S_SMON_INTSCN_VBAT_EN_EN (MXC_V_SMON_INTSCN_VBAT_EN_EN << MXC_F_SMON_INTSCN_VBAT_EN_POS) /**< INTSCN_VBAT_EN_EN Setting */
#define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */
#define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */
#define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C ((uint32_t)0x0UL) /**< INTSCN_LOTEMP_SEL_NEG50C Value */
#define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG50C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG50C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG50C Setting */
#define MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C ((uint32_t)0x1UL) /**< INTSCN_LOTEMP_SEL_NEG30C Value */
#define MXC_S_SMON_INTSCN_LOTEMP_SEL_NEG30C (MXC_V_SMON_INTSCN_LOTEMP_SEL_NEG30C << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS) /**< INTSCN_LOTEMP_SEL_NEG30C Setting */
#define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */
#define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */
#define MXC_V_SMON_INTSCN_VCORELOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCORELOEN_DIS Value */
#define MXC_S_SMON_INTSCN_VCORELOEN_DIS (MXC_V_SMON_INTSCN_VCORELOEN_DIS << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VCORELOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCORELOEN_EN Value */
#define MXC_S_SMON_INTSCN_VCORELOEN_EN (MXC_V_SMON_INTSCN_VCORELOEN_EN << MXC_F_SMON_INTSCN_VCORELOEN_POS) /**< INTSCN_VCORELOEN_EN Setting */
#define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */
#define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */
#define MXC_V_SMON_INTSCN_VCOREHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VCOREHIEN_DIS Value */
#define MXC_S_SMON_INTSCN_VCOREHIEN_DIS (MXC_V_SMON_INTSCN_VCOREHIEN_DIS << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VCOREHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VCOREHIEN_EN Value */
#define MXC_S_SMON_INTSCN_VCOREHIEN_EN (MXC_V_SMON_INTSCN_VCOREHIEN_EN << MXC_F_SMON_INTSCN_VCOREHIEN_POS) /**< INTSCN_VCOREHIEN_EN Setting */
#define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */
#define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */
#define MXC_V_SMON_INTSCN_VDDLOEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDLOEN_DIS Value */
#define MXC_S_SMON_INTSCN_VDDLOEN_DIS (MXC_V_SMON_INTSCN_VDDLOEN_DIS << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VDDLOEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDLOEN_EN Value */
#define MXC_S_SMON_INTSCN_VDDLOEN_EN (MXC_V_SMON_INTSCN_VDDLOEN_EN << MXC_F_SMON_INTSCN_VDDLOEN_POS) /**< INTSCN_VDDLOEN_EN Setting */
#define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */
#define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */
#define MXC_V_SMON_INTSCN_VDDHIEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VDDHIEN_DIS Value */
#define MXC_S_SMON_INTSCN_VDDHIEN_DIS (MXC_V_SMON_INTSCN_VDDHIEN_DIS << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VDDHIEN_EN ((uint32_t)0x1UL) /**< INTSCN_VDDHIEN_EN Value */
#define MXC_S_SMON_INTSCN_VDDHIEN_EN (MXC_V_SMON_INTSCN_VDDHIEN_EN << MXC_F_SMON_INTSCN_VDDHIEN_POS) /**< INTSCN_VDDHIEN_EN Setting */
#define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */
#define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */
#define MXC_V_SMON_INTSCN_VGLEN_DIS ((uint32_t)0x0UL) /**< INTSCN_VGLEN_DIS Value */
#define MXC_S_SMON_INTSCN_VGLEN_DIS (MXC_V_SMON_INTSCN_VGLEN_DIS << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_DIS Setting */
#define MXC_V_SMON_INTSCN_VGLEN_EN ((uint32_t)0x1UL) /**< INTSCN_VGLEN_EN Value */
#define MXC_S_SMON_INTSCN_VGLEN_EN (MXC_V_SMON_INTSCN_VGLEN_EN << MXC_F_SMON_INTSCN_VGLEN_POS) /**< INTSCN_VGLEN_EN Setting */
#define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */
#define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */
#define MXC_V_SMON_INTSCN_LOCK_UNLOCKED ((uint32_t)0x0UL) /**< INTSCN_LOCK_UNLOCKED Value */
#define MXC_S_SMON_INTSCN_LOCK_UNLOCKED (MXC_V_SMON_INTSCN_LOCK_UNLOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_UNLOCKED Setting */
#define MXC_V_SMON_INTSCN_LOCK_LOCKED ((uint32_t)0x1UL) /**< INTSCN_LOCK_LOCKED Value */
#define MXC_S_SMON_INTSCN_LOCK_LOCKED (MXC_V_SMON_INTSCN_LOCK_LOCKED << MXC_F_SMON_INTSCN_LOCK_POS) /**< INTSCN_LOCK_LOCKED Setting */
/**@} end of group SMON_INTSCN_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECALM SMON_SECALM
* @brief Security Alarm Register.
* @{
*/
#define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */
#define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */
#define MXC_V_SMON_SECALM_DRS_COMPLETE ((uint32_t)0x0UL) /**< SECALM_DRS_COMPLETE Value */
#define MXC_S_SMON_SECALM_DRS_COMPLETE (MXC_V_SMON_SECALM_DRS_COMPLETE << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_COMPLETE Setting */
#define MXC_V_SMON_SECALM_DRS_START ((uint32_t)0x1UL) /**< SECALM_DRS_START Value */
#define MXC_S_SMON_SECALM_DRS_START (MXC_V_SMON_SECALM_DRS_START << MXC_F_SMON_SECALM_DRS_POS) /**< SECALM_DRS_START Setting */
#define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */
#define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */
#define MXC_V_SMON_SECALM_KEYWIPE_COMPLETE ((uint32_t)0x0UL) /**< SECALM_KEYWIPE_COMPLETE Value */
#define MXC_S_SMON_SECALM_KEYWIPE_COMPLETE (MXC_V_SMON_SECALM_KEYWIPE_COMPLETE << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_COMPLETE Setting */
#define MXC_V_SMON_SECALM_KEYWIPE_START ((uint32_t)0x1UL) /**< SECALM_KEYWIPE_START Value */
#define MXC_S_SMON_SECALM_KEYWIPE_START (MXC_V_SMON_SECALM_KEYWIPE_START << MXC_F_SMON_SECALM_KEYWIPE_POS) /**< SECALM_KEYWIPE_START Setting */
#define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */
#define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */
#define MXC_V_SMON_SECALM_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_SHIELDF_NOEVENT Value */
#define MXC_S_SMON_SECALM_SHIELDF_NOEVENT (MXC_V_SMON_SECALM_SHIELDF_NOEVENT << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_NOEVENT Setting */
#define MXC_V_SMON_SECALM_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_SHIELDF_OCCURRED Value */
#define MXC_S_SMON_SECALM_SHIELDF_OCCURRED (MXC_V_SMON_SECALM_SHIELDF_OCCURRED << MXC_F_SMON_SECALM_SHIELDF_POS) /**< SECALM_SHIELDF_OCCURRED Setting */
#define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */
#define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */
#define MXC_V_SMON_SECALM_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_LOTEMP_NOEVENT Value */
#define MXC_S_SMON_SECALM_LOTEMP_NOEVENT (MXC_V_SMON_SECALM_LOTEMP_NOEVENT << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_NOEVENT Setting */
#define MXC_V_SMON_SECALM_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_LOTEMP_OCCURRED Value */
#define MXC_S_SMON_SECALM_LOTEMP_OCCURRED (MXC_V_SMON_SECALM_LOTEMP_OCCURRED << MXC_F_SMON_SECALM_LOTEMP_POS) /**< SECALM_LOTEMP_OCCURRED Setting */
#define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */
#define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */
#define MXC_V_SMON_SECALM_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECALM_HITEMP_NOEVENT Value */
#define MXC_S_SMON_SECALM_HITEMP_NOEVENT (MXC_V_SMON_SECALM_HITEMP_NOEVENT << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_NOEVENT Setting */
#define MXC_V_SMON_SECALM_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECALM_HITEMP_OCCURRED Value */
#define MXC_S_SMON_SECALM_HITEMP_OCCURRED (MXC_V_SMON_SECALM_HITEMP_OCCURRED << MXC_F_SMON_SECALM_HITEMP_POS) /**< SECALM_HITEMP_OCCURRED Setting */
#define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */
#define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */
#define MXC_V_SMON_SECALM_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATLO_NOEVENT Value */
#define MXC_S_SMON_SECALM_BATLO_NOEVENT (MXC_V_SMON_SECALM_BATLO_NOEVENT << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATLO_OCCURRED Value */
#define MXC_S_SMON_SECALM_BATLO_OCCURRED (MXC_V_SMON_SECALM_BATLO_OCCURRED << MXC_F_SMON_SECALM_BATLO_POS) /**< SECALM_BATLO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */
#define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */
#define MXC_V_SMON_SECALM_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_BATHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_BATHI_NOEVENT (MXC_V_SMON_SECALM_BATHI_NOEVENT << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_BATHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_BATHI_OCCURRED (MXC_V_SMON_SECALM_BATHI_OCCURRED << MXC_F_SMON_SECALM_BATHI_POS) /**< SECALM_BATHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */
#define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */
#define MXC_V_SMON_SECALM_EXTF_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTF_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTF_NOEVENT (MXC_V_SMON_SECALM_EXTF_NOEVENT << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTF_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTF_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTF_OCCURRED (MXC_V_SMON_SECALM_EXTF_OCCURRED << MXC_F_SMON_SECALM_EXTF_POS) /**< SECALM_EXTF_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */
#define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */
#define MXC_V_SMON_SECALM_VDDLO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDLO_NOEVENT Value */
#define MXC_S_SMON_SECALM_VDDLO_NOEVENT (MXC_V_SMON_SECALM_VDDLO_NOEVENT << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VDDLO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDLO_OCCURRED Value */
#define MXC_S_SMON_SECALM_VDDLO_OCCURRED (MXC_V_SMON_SECALM_VDDLO_OCCURRED << MXC_F_SMON_SECALM_VDDLO_POS) /**< SECALM_VDDLO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */
#define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */
#define MXC_V_SMON_SECALM_VCORELO_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCORELO_NOEVENT Value */
#define MXC_S_SMON_SECALM_VCORELO_NOEVENT (MXC_V_SMON_SECALM_VCORELO_NOEVENT << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VCORELO_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCORELO_OCCURRED Value */
#define MXC_S_SMON_SECALM_VCORELO_OCCURRED (MXC_V_SMON_SECALM_VCORELO_OCCURRED << MXC_F_SMON_SECALM_VCORELO_POS) /**< SECALM_VCORELO_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */
#define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */
#define MXC_V_SMON_SECALM_VCOREHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VCOREHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_VCOREHI_NOEVENT (MXC_V_SMON_SECALM_VCOREHI_NOEVENT << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VCOREHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VCOREHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_VCOREHI_OCCURRED (MXC_V_SMON_SECALM_VCOREHI_OCCURRED << MXC_F_SMON_SECALM_VCOREHI_POS) /**< SECALM_VCOREHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */
#define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */
#define MXC_V_SMON_SECALM_VDDHI_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VDDHI_NOEVENT Value */
#define MXC_S_SMON_SECALM_VDDHI_NOEVENT (MXC_V_SMON_SECALM_VDDHI_NOEVENT << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VDDHI_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VDDHI_OCCURRED Value */
#define MXC_S_SMON_SECALM_VDDHI_OCCURRED (MXC_V_SMON_SECALM_VDDHI_OCCURRED << MXC_F_SMON_SECALM_VDDHI_POS) /**< SECALM_VDDHI_OCCURRED Setting */
#define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */
#define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */
#define MXC_V_SMON_SECALM_VGL_NOEVENT ((uint32_t)0x0UL) /**< SECALM_VGL_NOEVENT Value */
#define MXC_S_SMON_SECALM_VGL_NOEVENT (MXC_V_SMON_SECALM_VGL_NOEVENT << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_NOEVENT Setting */
#define MXC_V_SMON_SECALM_VGL_OCCURRED ((uint32_t)0x1UL) /**< SECALM_VGL_OCCURRED Value */
#define MXC_S_SMON_SECALM_VGL_OCCURRED (MXC_V_SMON_SECALM_VGL_OCCURRED << MXC_F_SMON_SECALM_VGL_POS) /**< SECALM_VGL_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */
#define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT0_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT0_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT0_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT0_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT0_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT0_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT0_POS) /**< SECALM_EXTSTAT0_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */
#define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT1_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT1_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT1_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT1_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT1_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT1_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT1_POS) /**< SECALM_EXTSTAT1_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */
#define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT2_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT2_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT2_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT2_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT2_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT2_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT2_POS) /**< SECALM_EXTSTAT2_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */
#define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT3_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT3_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT3_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT3_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT3_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT3_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT3_POS) /**< SECALM_EXTSTAT3_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */
#define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT4_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT4_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT4_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT4_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT4_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT4_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT4_POS) /**< SECALM_EXTSTAT4_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */
#define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */
#define MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSTAT5_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSTAT5_NOEVENT (MXC_V_SMON_SECALM_EXTSTAT5_NOEVENT << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSTAT5_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSTAT5_OCCURRED (MXC_V_SMON_SECALM_EXTSTAT5_OCCURRED << MXC_F_SMON_SECALM_EXTSTAT5_POS) /**< SECALM_EXTSTAT5_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */
#define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN0_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN0_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN0_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN0_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN0_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN0_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN0_POS) /**< SECALM_EXTSWARN0_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */
#define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN1_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN1_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN1_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN1_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN1_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN1_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN1_POS) /**< SECALM_EXTSWARN1_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */
#define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN2_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN2_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN2_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN2_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN2_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN2_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN2_POS) /**< SECALM_EXTSWARN2_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */
#define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN3_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN3_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN3_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN3_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN3_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN3_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN3_POS) /**< SECALM_EXTSWARN3_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */
#define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN4_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN4_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN4_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN4_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN4_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN4_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN4_POS) /**< SECALM_EXTSWARN4_OCCURRED Setting */
#define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */
#define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */
#define MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT ((uint32_t)0x0UL) /**< SECALM_EXTSWARN5_NOEVENT Value */
#define MXC_S_SMON_SECALM_EXTSWARN5_NOEVENT (MXC_V_SMON_SECALM_EXTSWARN5_NOEVENT << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_NOEVENT Setting */
#define MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED ((uint32_t)0x1UL) /**< SECALM_EXTSWARN5_OCCURRED Value */
#define MXC_S_SMON_SECALM_EXTSWARN5_OCCURRED (MXC_V_SMON_SECALM_EXTSWARN5_OCCURRED << MXC_F_SMON_SECALM_EXTSWARN5_POS) /**< SECALM_EXTSWARN5_OCCURRED Setting */
/**@} end of group SMON_SECALM_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECDIAG SMON_SECDIAG
* @brief Security Diagnostic Register.
* @{
*/
#define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */
#define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */
#define MXC_V_SMON_SECDIAG_BORF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BORF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BORF_NOEVENT (MXC_V_SMON_SECDIAG_BORF_NOEVENT << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BORF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BORF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BORF_OCCURRED (MXC_V_SMON_SECDIAG_BORF_OCCURRED << MXC_F_SMON_SECDIAG_BORF_POS) /**< SECDIAG_BORF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */
#define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */
#define MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_SHIELDF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_SHIELDF_NOEVENT (MXC_V_SMON_SECDIAG_SHIELDF_NOEVENT << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_SHIELDF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_SHIELDF_OCCURRED (MXC_V_SMON_SECDIAG_SHIELDF_OCCURRED << MXC_F_SMON_SECDIAG_SHIELDF_POS) /**< SECDIAG_SHIELDF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */
#define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */
#define MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_LOTEMP_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_LOTEMP_NOEVENT (MXC_V_SMON_SECDIAG_LOTEMP_NOEVENT << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_LOTEMP_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_LOTEMP_OCCURRED (MXC_V_SMON_SECDIAG_LOTEMP_OCCURRED << MXC_F_SMON_SECDIAG_LOTEMP_POS) /**< SECDIAG_LOTEMP_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */
#define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */
#define MXC_V_SMON_SECDIAG_HITEMP_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_HITEMP_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_HITEMP_NOEVENT (MXC_V_SMON_SECDIAG_HITEMP_NOEVENT << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_HITEMP_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_HITEMP_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_HITEMP_OCCURRED (MXC_V_SMON_SECDIAG_HITEMP_OCCURRED << MXC_F_SMON_SECDIAG_HITEMP_POS) /**< SECDIAG_HITEMP_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */
#define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */
#define MXC_V_SMON_SECDIAG_BATLO_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATLO_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BATLO_NOEVENT (MXC_V_SMON_SECDIAG_BATLO_NOEVENT << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BATLO_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATLO_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BATLO_OCCURRED (MXC_V_SMON_SECDIAG_BATLO_OCCURRED << MXC_F_SMON_SECDIAG_BATLO_POS) /**< SECDIAG_BATLO_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */
#define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */
#define MXC_V_SMON_SECDIAG_BATHI_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_BATHI_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_BATHI_NOEVENT (MXC_V_SMON_SECDIAG_BATHI_NOEVENT << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_BATHI_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_BATHI_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_BATHI_OCCURRED (MXC_V_SMON_SECDIAG_BATHI_OCCURRED << MXC_F_SMON_SECDIAG_BATHI_POS) /**< SECDIAG_BATHI_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */
#define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */
#define MXC_V_SMON_SECDIAG_DYNF_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_DYNF_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_DYNF_NOEVENT (MXC_V_SMON_SECDIAG_DYNF_NOEVENT << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_DYNF_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_DYNF_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_DYNF_OCCURRED (MXC_V_SMON_SECDIAG_DYNF_OCCURRED << MXC_F_SMON_SECDIAG_DYNF_POS) /**< SECDIAG_DYNF_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */
#define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */
#define MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE ((uint32_t)0x0UL) /**< SECDIAG_AESKT_INCOMPLETE Value */
#define MXC_S_SMON_SECDIAG_AESKT_INCOMPLETE (MXC_V_SMON_SECDIAG_AESKT_INCOMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_INCOMPLETE Setting */
#define MXC_V_SMON_SECDIAG_AESKT_COMPLETE ((uint32_t)0x1UL) /**< SECDIAG_AESKT_COMPLETE Value */
#define MXC_S_SMON_SECDIAG_AESKT_COMPLETE (MXC_V_SMON_SECDIAG_AESKT_COMPLETE << MXC_F_SMON_SECDIAG_AESKT_POS) /**< SECDIAG_AESKT_COMPLETE Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT0_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT0_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT0_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT0_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT0_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT0_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT0_POS) /**< SECDIAG_EXTSTAT0_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT1_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT1_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT1_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT1_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT1_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT1_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT1_POS) /**< SECDIAG_EXTSTAT1_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT2_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT2_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT2_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT2_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT2_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT2_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT2_POS) /**< SECDIAG_EXTSTAT2_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT3_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT3_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT3_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT3_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT3_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT3_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT3_POS) /**< SECDIAG_EXTSTAT3_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT4_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT4_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT4_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT4_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT4_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT4_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT4_POS) /**< SECDIAG_EXTSTAT4_OCCURRED Setting */
#define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */
#define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */
#define MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT ((uint32_t)0x0UL) /**< SECDIAG_EXTSTAT5_NOEVENT Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT5_NOEVENT (MXC_V_SMON_SECDIAG_EXTSTAT5_NOEVENT << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_NOEVENT Setting */
#define MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED ((uint32_t)0x1UL) /**< SECDIAG_EXTSTAT5_OCCURRED Value */
#define MXC_S_SMON_SECDIAG_EXTSTAT5_OCCURRED (MXC_V_SMON_SECDIAG_EXTSTAT5_OCCURRED << MXC_F_SMON_SECDIAG_EXTSTAT5_POS) /**< SECDIAG_EXTSTAT5_OCCURRED Setting */
/**@} end of group SMON_SECDIAG_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_DLRTC SMON_DLRTC
* @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second
* register when the last DRS event occurred.
* @{
*/
#define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */
#define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */
/**@} end of group SMON_DLRTC_Register */
/**
* @ingroup smon_registers
* @defgroup SMON_SECST SMON_SECST
* @brief Security Monitor Status Register.
* @{
*/
#define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */
#define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */
#define MXC_V_SMON_SECST_EXTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_EXTSRS_ALLOWED Value */
#define MXC_S_SMON_SECST_EXTSRS_ALLOWED (MXC_V_SMON_SECST_EXTSRS_ALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_EXTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_EXTSRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_EXTSRS_NOTALLOWED (MXC_V_SMON_SECST_EXTSRS_NOTALLOWED << MXC_F_SMON_SECST_EXTSRS_POS) /**< SECST_EXTSRS_NOTALLOWED Setting */
#define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */
#define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */
#define MXC_V_SMON_SECST_INTSRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_INTSRS_ALLOWED Value */
#define MXC_S_SMON_SECST_INTSRS_ALLOWED (MXC_V_SMON_SECST_INTSRS_ALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_INTSRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_INTSRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_INTSRS_NOTALLOWED (MXC_V_SMON_SECST_INTSRS_NOTALLOWED << MXC_F_SMON_SECST_INTSRS_POS) /**< SECST_INTSRS_NOTALLOWED Setting */
#define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */
#define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */
#define MXC_V_SMON_SECST_SECALRS_ALLOWED ((uint32_t)0x0UL) /**< SECST_SECALRS_ALLOWED Value */
#define MXC_S_SMON_SECST_SECALRS_ALLOWED (MXC_V_SMON_SECST_SECALRS_ALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_ALLOWED Setting */
#define MXC_V_SMON_SECST_SECALRS_NOTALLOWED ((uint32_t)0x1UL) /**< SECST_SECALRS_NOTALLOWED Value */
#define MXC_S_SMON_SECST_SECALRS_NOTALLOWED (MXC_V_SMON_SECST_SECALRS_NOTALLOWED << MXC_F_SMON_SECST_SECALRS_POS) /**< SECST_SECALRS_NOTALLOWED Setting */
/**@} end of group SMON_SECST_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SMON_REGS_H_ */

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/**
* @file spi17y_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPI17Y_REGS_H_
#define _SPI17Y_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spi17y
* @defgroup spi17y_registers SPI17Y_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module.
* @details SPI peripheral.
*/
/**
* @ingroup spi17y_registers
* Structure type to access the SPI17Y Registers.
*/
typedef struct {
union{
__IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPI17Y DATA32 Register */
__IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPI17Y DATA16 Register */
__IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPI17Y DATA8 Register */
};
__IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI17Y CTRL0 Register */
__IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI17Y CTRL1 Register */
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI17Y CTRL2 Register */
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI17Y SS_TIME Register */
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI17Y CLK_CFG Register */
__R uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI17Y DMA Register */
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI17Y INT_FL Register */
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI17Y INT_EN Register */
__IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI17Y WAKE_FL Register */
__IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI17Y WAKE_EN Register */
__I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI17Y STAT Register */
} mxc_spi17y_regs_t;
/* Register offsets for module SPI17Y */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_Register_Offsets Register Offsets
* @brief SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address.
* @{
*/
#define MXC_R_SPI17Y_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI17Y Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPI17Y_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI17Y Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPI17Y_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI17Y Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPI17Y_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI17Y Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPI17Y_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI17Y Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPI17Y_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI17Y Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPI17Y_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI17Y Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPI17Y_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI17Y Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPI17Y_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI17Y Base Address: <tt> 0x0024</tt> */
#define MXC_R_SPI17Y_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI17Y Base Address: <tt> 0x0028</tt> */
#define MXC_R_SPI17Y_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI17Y Base Address: <tt> 0x002C</tt> */
#define MXC_R_SPI17Y_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI17Y Base Address: <tt> 0x0030</tt> */
/**@} end of group spi17y_registers */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA32 SPI17Y_DATA32
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA32_DATA_POS 0 /**< DATA32_DATA Position */
#define MXC_F_SPI17Y_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI17Y_DATA32_DATA_POS)) /**< DATA32_DATA Mask */
/**@} end of group SPI17Y_DATA32_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA16 SPI17Y_DATA16
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA16_DATA_POS 0 /**< DATA16_DATA Position */
#define MXC_F_SPI17Y_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI17Y_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
/**@} end of group SPI17Y_DATA16_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DATA8 SPI17Y_DATA8
* @brief Register for reading and writing the FIFO.
* @{
*/
#define MXC_F_SPI17Y_DATA8_DATA_POS 0 /**< DATA8_DATA Position */
#define MXC_F_SPI17Y_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI17Y_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
/**@} end of group SPI17Y_DATA8_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL0 SPI17Y_CTRL0
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL0_EN_POS 0 /**< CTRL0_EN Position */
#define MXC_F_SPI17Y_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_EN_POS)) /**< CTRL0_EN Mask */
#define MXC_V_SPI17Y_CTRL0_EN_DIS ((uint32_t)0x0UL) /**< CTRL0_EN_DIS Value */
#define MXC_S_SPI17Y_CTRL0_EN_DIS (MXC_V_SPI17Y_CTRL0_EN_DIS << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_DIS Setting */
#define MXC_V_SPI17Y_CTRL0_EN_EN ((uint32_t)0x1UL) /**< CTRL0_EN_EN Value */
#define MXC_S_SPI17Y_CTRL0_EN_EN (MXC_V_SPI17Y_CTRL0_EN_EN << MXC_F_SPI17Y_CTRL0_EN_POS) /**< CTRL0_EN_EN Setting */
#define MXC_F_SPI17Y_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */
#define MXC_F_SPI17Y_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */
#define MXC_V_SPI17Y_CTRL0_MASTER_DIS ((uint32_t)0x0UL) /**< CTRL0_MASTER_DIS Value */
#define MXC_S_SPI17Y_CTRL0_MASTER_DIS (MXC_V_SPI17Y_CTRL0_MASTER_DIS << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_DIS Setting */
#define MXC_V_SPI17Y_CTRL0_MASTER_EN ((uint32_t)0x1UL) /**< CTRL0_MASTER_EN Value */
#define MXC_S_SPI17Y_CTRL0_MASTER_EN (MXC_V_SPI17Y_CTRL0_MASTER_EN << MXC_F_SPI17Y_CTRL0_MASTER_POS) /**< CTRL0_MASTER_EN Setting */
#define MXC_F_SPI17Y_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */
#define MXC_F_SPI17Y_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */
#define MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT ((uint32_t)0x0UL) /**< CTRL0_SS_IO_OUTPUT Value */
#define MXC_S_SPI17Y_CTRL0_SS_IO_OUTPUT (MXC_V_SPI17Y_CTRL0_SS_IO_OUTPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_OUTPUT Setting */
#define MXC_V_SPI17Y_CTRL0_SS_IO_INPUT ((uint32_t)0x1UL) /**< CTRL0_SS_IO_INPUT Value */
#define MXC_S_SPI17Y_CTRL0_SS_IO_INPUT (MXC_V_SPI17Y_CTRL0_SS_IO_INPUT << MXC_F_SPI17Y_CTRL0_SS_IO_POS) /**< CTRL0_SS_IO_INPUT Setting */
#define MXC_F_SPI17Y_CTRL0_START_POS 5 /**< CTRL0_START Position */
#define MXC_F_SPI17Y_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_START_POS)) /**< CTRL0_START Mask */
#define MXC_V_SPI17Y_CTRL0_START_START ((uint32_t)0x1UL) /**< CTRL0_START_START Value */
#define MXC_S_SPI17Y_CTRL0_START_START (MXC_V_SPI17Y_CTRL0_START_START << MXC_F_SPI17Y_CTRL0_START_POS) /**< CTRL0_START_START Setting */
#define MXC_F_SPI17Y_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */
#define MXC_F_SPI17Y_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */
#define MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT ((uint32_t)0x0UL) /**< CTRL0_SS_CTRL_DEASSERT Value */
#define MXC_S_SPI17Y_CTRL0_SS_CTRL_DEASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_DEASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_DEASSERT Setting */
#define MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT ((uint32_t)0x1UL) /**< CTRL0_SS_CTRL_ASSERT Value */
#define MXC_S_SPI17Y_CTRL0_SS_CTRL_ASSERT (MXC_V_SPI17Y_CTRL0_SS_CTRL_ASSERT << MXC_F_SPI17Y_CTRL0_SS_CTRL_POS) /**< CTRL0_SS_CTRL_ASSERT Setting */
#define MXC_F_SPI17Y_CTRL0_SS_POS 16 /**< CTRL0_SS Position */
#define MXC_F_SPI17Y_CTRL0_SS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL0_SS_POS)) /**< CTRL0_SS Mask */
#define MXC_V_SPI17Y_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS0 (MXC_V_SPI17Y_CTRL0_SS_SS0 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS1 (MXC_V_SPI17Y_CTRL0_SS_SS1 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS2 (MXC_V_SPI17Y_CTRL0_SS_SS2 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */
#define MXC_V_SPI17Y_CTRL0_SS_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_SS3 Value */
#define MXC_S_SPI17Y_CTRL0_SS_SS3 (MXC_V_SPI17Y_CTRL0_SS_SS3 << MXC_F_SPI17Y_CTRL0_SS_POS) /**< CTRL0_SS_SS3 Setting */
/**@} end of group SPI17Y_CTRL0_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL1 SPI17Y_CTRL1
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */
#define MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */
#define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */
#define MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI17Y_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */
/**@} end of group SPI17Y_CTRL1_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CTRL2 SPI17Y_CTRL2
* @brief Register for controlling SPI peripheral.
* @{
*/
#define MXC_F_SPI17Y_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */
#define MXC_F_SPI17Y_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */
#define MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE ((uint32_t)0x0UL) /**< CTRL2_CPHA_RISING_EDGE Value */
#define MXC_S_SPI17Y_CTRL2_CPHA_RISING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_RISING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_RISING_EDGE Setting */
#define MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE ((uint32_t)0x1UL) /**< CTRL2_CPHA_FALLING_EDGE Value */
#define MXC_S_SPI17Y_CTRL2_CPHA_FALLING_EDGE (MXC_V_SPI17Y_CTRL2_CPHA_FALLING_EDGE << MXC_F_SPI17Y_CTRL2_CPHA_POS) /**< CTRL2_CPHA_FALLING_EDGE Setting */
#define MXC_F_SPI17Y_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */
#define MXC_F_SPI17Y_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */
#define MXC_V_SPI17Y_CTRL2_CPOL_NORMAL ((uint32_t)0x0UL) /**< CTRL2_CPOL_NORMAL Value */
#define MXC_S_SPI17Y_CTRL2_CPOL_NORMAL (MXC_V_SPI17Y_CTRL2_CPOL_NORMAL << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_NORMAL Setting */
#define MXC_V_SPI17Y_CTRL2_CPOL_INVERTED ((uint32_t)0x1UL) /**< CTRL2_CPOL_INVERTED Value */
#define MXC_S_SPI17Y_CTRL2_CPOL_INVERTED (MXC_V_SPI17Y_CTRL2_CPOL_INVERTED << MXC_F_SPI17Y_CTRL2_CPOL_POS) /**< CTRL2_CPOL_INVERTED Setting */
#define MXC_F_SPI17Y_CTRL2_SCLK_INV_POS 4 /**< CTRL2_SCLK_INV Position */
#define MXC_F_SPI17Y_CTRL2_SCLK_INV ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_SCLK_INV_POS)) /**< CTRL2_SCLK_INV Mask */
#define MXC_F_SPI17Y_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */
#define MXC_F_SPI17Y_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI17Y_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */
#define MXC_V_SPI17Y_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */
#define MXC_S_SPI17Y_CTRL2_NUMBITS_0 (MXC_V_SPI17Y_CTRL2_NUMBITS_0 << MXC_F_SPI17Y_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */
#define MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */
#define MXC_F_SPI17Y_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */
#define MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */
#define MXC_S_SPI17Y_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI17Y_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI17Y_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */
#define MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */
#define MXC_F_SPI17Y_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */
#define MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS ((uint32_t)0x0UL) /**< CTRL2_THREE_WIRE_DIS Value */
#define MXC_S_SPI17Y_CTRL2_THREE_WIRE_DIS (MXC_V_SPI17Y_CTRL2_THREE_WIRE_DIS << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_DIS Setting */
#define MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN ((uint32_t)0x1UL) /**< CTRL2_THREE_WIRE_EN Value */
#define MXC_S_SPI17Y_CTRL2_THREE_WIRE_EN (MXC_V_SPI17Y_CTRL2_THREE_WIRE_EN << MXC_F_SPI17Y_CTRL2_THREE_WIRE_POS) /**< CTRL2_THREE_WIRE_EN Setting */
#define MXC_F_SPI17Y_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */
#define MXC_F_SPI17Y_CTRL2_SS_POL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SS_POL_SS3_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SS_POL_SS3_HIGH (MXC_V_SPI17Y_CTRL2_SS_POL_SS3_HIGH << MXC_F_SPI17Y_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS3_HIGH Setting */
#define MXC_F_SPI17Y_CTRL2_SRPOL_POS 24 /**< CTRL2_SRPOL Position */
#define MXC_F_SPI17Y_CTRL2_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CTRL2_SRPOL_POS)) /**< CTRL2_SRPOL Mask */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SRPOL_SR0_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR0_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR0_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR0_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SRPOL_SR1_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR1_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR1_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR1_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SRPOL_SR2_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR2_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR2_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR2_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SRPOL_SR3_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR3_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR3_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR3_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL2_SRPOL_SR4_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR4_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR4_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR4_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL2_SRPOL_SR5_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR5_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR5_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR5_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL2_SRPOL_SR6_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR6_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR6_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR6_HIGH Setting */
#define MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL2_SRPOL_SR7_HIGH Value */
#define MXC_S_SPI17Y_CTRL2_SRPOL_SR7_HIGH (MXC_V_SPI17Y_CTRL2_SRPOL_SR7_HIGH << MXC_F_SPI17Y_CTRL2_SRPOL_POS) /**< CTRL2_SRPOL_SR7_HIGH Setting */
/**@} end of group SPI17Y_CTRL2_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_SS_TIME SPI17Y_SS_TIME
* @brief Register for controlling SPI peripheral/Slave Select Timing.
* @{
*/
#define MXC_F_SPI17Y_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */
#define MXC_F_SPI17Y_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */
#define MXC_V_SPI17Y_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */
#define MXC_S_SPI17Y_SS_TIME_PRE_256 (MXC_V_SPI17Y_SS_TIME_PRE_256 << MXC_F_SPI17Y_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */
#define MXC_F_SPI17Y_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */
#define MXC_F_SPI17Y_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */
#define MXC_V_SPI17Y_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */
#define MXC_S_SPI17Y_SS_TIME_POST_256 (MXC_V_SPI17Y_SS_TIME_POST_256 << MXC_F_SPI17Y_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */
#define MXC_F_SPI17Y_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */
#define MXC_F_SPI17Y_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI17Y_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */
#define MXC_V_SPI17Y_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */
#define MXC_S_SPI17Y_SS_TIME_INACT_256 (MXC_V_SPI17Y_SS_TIME_INACT_256 << MXC_F_SPI17Y_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */
/**@} end of group SPI17Y_SS_TIME_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_CLK_CFG SPI17Y_CLK_CFG
* @brief Register for controlling SPI clock rate.
* @{
*/
#define MXC_F_SPI17Y_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */
#define MXC_F_SPI17Y_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */
#define MXC_V_SPI17Y_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */
#define MXC_S_SPI17Y_CLK_CFG_LO_DIS (MXC_V_SPI17Y_CLK_CFG_LO_DIS << MXC_F_SPI17Y_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */
#define MXC_F_SPI17Y_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */
#define MXC_F_SPI17Y_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI17Y_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */
#define MXC_V_SPI17Y_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */
#define MXC_S_SPI17Y_CLK_CFG_HI_DIS (MXC_V_SPI17Y_CLK_CFG_HI_DIS << MXC_F_SPI17Y_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */
#define MXC_F_SPI17Y_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */
#define MXC_F_SPI17Y_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI17Y_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */
/**@} end of group SPI17Y_CLK_CFG_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_DMA SPI17Y_DMA
* @brief Register for controlling DMA.
* @{
*/
#define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
#define MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */
#define MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_FIFO_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_TX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_FIFO_EN_EN Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_TX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_TX_FIFO_EN_POS) /**< DMA_TX_FIFO_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
#define MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_CLEAR Value */
#define MXC_S_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_TX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_CLEAR Setting */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPI17Y_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPI17Y_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPI17Y_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_TX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_TX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_TX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_EN Value */
#define MXC_S_SPI17Y_DMA_TX_DMA_EN_EN (MXC_V_SPI17Y_DMA_TX_DMA_EN_EN << MXC_F_SPI17Y_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI17Y_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
#define MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */
#define MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_FIFO_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_EN_DIS (MXC_V_SPI17Y_DMA_RX_FIFO_EN_DIS << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_FIFO_EN_EN Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_EN_EN (MXC_V_SPI17Y_DMA_RX_FIFO_EN_EN << MXC_F_SPI17Y_DMA_RX_FIFO_EN_POS) /**< DMA_RX_FIFO_EN_EN Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
#define MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_CLEAR Value */
#define MXC_S_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR (MXC_V_SPI17Y_DMA_RX_FIFO_CLEAR_CLEAR << MXC_F_SPI17Y_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_CLEAR Setting */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPI17Y_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI17Y_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPI17Y_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPI17Y_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
#define MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DIS Value */
#define MXC_S_SPI17Y_DMA_RX_DMA_EN_DIS (MXC_V_SPI17Y_DMA_RX_DMA_EN_DIS << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DIS Setting */
#define MXC_V_SPI17Y_DMA_RX_DMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_EN Value */
#define MXC_S_SPI17Y_DMA_RX_DMA_EN_EN (MXC_V_SPI17Y_DMA_RX_DMA_EN_EN << MXC_F_SPI17Y_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_EN Setting */
/**@} end of group SPI17Y_DMA_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_INT_FL SPI17Y_INT_FL
* @brief Register for reading and clearing interrupt flags. All bits are write 1 to
* clear.
* @{
*/
#define MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */
#define MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */
#define MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS) /**< INT_FL_TX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */
#define MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */
#define MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_EMPTY_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_INT_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS) /**< INT_FL_TX_EMPTY_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */
#define MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */
#define MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_INT_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS) /**< INT_FL_RX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */
#define MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */
#define MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_FULL_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_INT_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_INT_FL_RX_FULL_POS) /**< INT_FL_RX_FULL_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */
#define MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */
#define MXC_V_SPI17Y_INT_FL_SSA_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSA_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_SSA_CLEAR (MXC_V_SPI17Y_INT_FL_SSA_CLEAR << MXC_F_SPI17Y_INT_FL_SSA_POS) /**< INT_FL_SSA_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */
#define MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */
#define MXC_V_SPI17Y_INT_FL_SSD_CLEAR ((uint32_t)0x1UL) /**< INT_FL_SSD_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_SSD_CLEAR (MXC_V_SPI17Y_INT_FL_SSD_CLEAR << MXC_F_SPI17Y_INT_FL_SSD_POS) /**< INT_FL_SSD_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */
#define MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */
#define MXC_V_SPI17Y_INT_FL_FAULT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_FAULT_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_FAULT_CLEAR (MXC_V_SPI17Y_INT_FL_FAULT_CLEAR << MXC_F_SPI17Y_INT_FL_FAULT_POS) /**< INT_FL_FAULT_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */
#define MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */
#define MXC_V_SPI17Y_INT_FL_ABORT_CLEAR ((uint32_t)0x1UL) /**< INT_FL_ABORT_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_ABORT_CLEAR (MXC_V_SPI17Y_INT_FL_ABORT_CLEAR << MXC_F_SPI17Y_INT_FL_ABORT_POS) /**< INT_FL_ABORT_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */
#define MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */
#define MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR ((uint32_t)0x1UL) /**< INT_FL_M_DONE_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_M_DONE_CLEAR (MXC_V_SPI17Y_INT_FL_M_DONE_CLEAR << MXC_F_SPI17Y_INT_FL_M_DONE_POS) /**< INT_FL_M_DONE_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */
#define MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */
#define MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_OVR_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_TX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_TX_OVR_POS) /**< INT_FL_TX_OVR_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */
#define MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */
#define MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_TX_UND_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_TX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_TX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_TX_UND_POS) /**< INT_FL_TX_UND_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */
#define MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */
#define MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_OVR_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_OVR_CLEAR (MXC_V_SPI17Y_INT_FL_RX_OVR_CLEAR << MXC_F_SPI17Y_INT_FL_RX_OVR_POS) /**< INT_FL_RX_OVR_CLEAR Setting */
#define MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */
#define MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */
#define MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR ((uint32_t)0x1UL) /**< INT_FL_RX_UND_CLEAR Value */
#define MXC_S_SPI17Y_INT_FL_RX_UND_CLEAR (MXC_V_SPI17Y_INT_FL_RX_UND_CLEAR << MXC_F_SPI17Y_INT_FL_RX_UND_POS) /**< INT_FL_RX_UND_CLEAR Setting */
/**@} end of group SPI17Y_INT_FL_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_INT_EN SPI17Y_INT_EN
* @brief Register for enabling interrupts.
* @{
*/
#define MXC_F_SPI17Y_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */
#define MXC_F_SPI17Y_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */
#define MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_THRESH_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_TX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_TX_THRESH_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_THRESH_EN (MXC_V_SPI17Y_INT_EN_TX_THRESH_EN << MXC_F_SPI17Y_INT_EN_TX_THRESH_POS) /**< INT_EN_TX_THRESH_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */
#define MXC_F_SPI17Y_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */
#define MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_EMPTY_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_INT_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< INT_EN_TX_EMPTY_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_EMPTY_EN (MXC_V_SPI17Y_INT_EN_TX_EMPTY_EN << MXC_F_SPI17Y_INT_EN_TX_EMPTY_POS) /**< INT_EN_TX_EMPTY_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */
#define MXC_F_SPI17Y_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */
#define MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_THRESH_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_THRESH_DIS (MXC_V_SPI17Y_INT_EN_RX_THRESH_DIS << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< INT_EN_RX_THRESH_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_THRESH_EN (MXC_V_SPI17Y_INT_EN_RX_THRESH_EN << MXC_F_SPI17Y_INT_EN_RX_THRESH_POS) /**< INT_EN_RX_THRESH_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */
#define MXC_F_SPI17Y_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */
#define MXC_V_SPI17Y_INT_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_FULL_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_FULL_DIS (MXC_V_SPI17Y_INT_EN_RX_FULL_DIS << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< INT_EN_RX_FULL_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_FULL_EN (MXC_V_SPI17Y_INT_EN_RX_FULL_EN << MXC_F_SPI17Y_INT_EN_RX_FULL_POS) /**< INT_EN_RX_FULL_EN Setting */
#define MXC_F_SPI17Y_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */
#define MXC_F_SPI17Y_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */
#define MXC_V_SPI17Y_INT_EN_SSA_DIS ((uint32_t)0x0UL) /**< INT_EN_SSA_DIS Value */
#define MXC_S_SPI17Y_INT_EN_SSA_DIS (MXC_V_SPI17Y_INT_EN_SSA_DIS << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_SSA_EN ((uint32_t)0x1UL) /**< INT_EN_SSA_EN Value */
#define MXC_S_SPI17Y_INT_EN_SSA_EN (MXC_V_SPI17Y_INT_EN_SSA_EN << MXC_F_SPI17Y_INT_EN_SSA_POS) /**< INT_EN_SSA_EN Setting */
#define MXC_F_SPI17Y_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */
#define MXC_F_SPI17Y_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */
#define MXC_V_SPI17Y_INT_EN_SSD_DIS ((uint32_t)0x0UL) /**< INT_EN_SSD_DIS Value */
#define MXC_S_SPI17Y_INT_EN_SSD_DIS (MXC_V_SPI17Y_INT_EN_SSD_DIS << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_SSD_EN ((uint32_t)0x1UL) /**< INT_EN_SSD_EN Value */
#define MXC_S_SPI17Y_INT_EN_SSD_EN (MXC_V_SPI17Y_INT_EN_SSD_EN << MXC_F_SPI17Y_INT_EN_SSD_POS) /**< INT_EN_SSD_EN Setting */
#define MXC_F_SPI17Y_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */
#define MXC_F_SPI17Y_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */
#define MXC_V_SPI17Y_INT_EN_FAULT_DIS ((uint32_t)0x0UL) /**< INT_EN_FAULT_DIS Value */
#define MXC_S_SPI17Y_INT_EN_FAULT_DIS (MXC_V_SPI17Y_INT_EN_FAULT_DIS << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_FAULT_EN ((uint32_t)0x1UL) /**< INT_EN_FAULT_EN Value */
#define MXC_S_SPI17Y_INT_EN_FAULT_EN (MXC_V_SPI17Y_INT_EN_FAULT_EN << MXC_F_SPI17Y_INT_EN_FAULT_POS) /**< INT_EN_FAULT_EN Setting */
#define MXC_F_SPI17Y_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */
#define MXC_F_SPI17Y_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */
#define MXC_V_SPI17Y_INT_EN_ABORT_DIS ((uint32_t)0x0UL) /**< INT_EN_ABORT_DIS Value */
#define MXC_S_SPI17Y_INT_EN_ABORT_DIS (MXC_V_SPI17Y_INT_EN_ABORT_DIS << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_ABORT_EN ((uint32_t)0x1UL) /**< INT_EN_ABORT_EN Value */
#define MXC_S_SPI17Y_INT_EN_ABORT_EN (MXC_V_SPI17Y_INT_EN_ABORT_EN << MXC_F_SPI17Y_INT_EN_ABORT_POS) /**< INT_EN_ABORT_EN Setting */
#define MXC_F_SPI17Y_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */
#define MXC_F_SPI17Y_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */
#define MXC_V_SPI17Y_INT_EN_M_DONE_DIS ((uint32_t)0x0UL) /**< INT_EN_M_DONE_DIS Value */
#define MXC_S_SPI17Y_INT_EN_M_DONE_DIS (MXC_V_SPI17Y_INT_EN_M_DONE_DIS << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_M_DONE_EN ((uint32_t)0x1UL) /**< INT_EN_M_DONE_EN Value */
#define MXC_S_SPI17Y_INT_EN_M_DONE_EN (MXC_V_SPI17Y_INT_EN_M_DONE_EN << MXC_F_SPI17Y_INT_EN_M_DONE_POS) /**< INT_EN_M_DONE_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */
#define MXC_F_SPI17Y_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */
#define MXC_V_SPI17Y_INT_EN_TX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_OVR_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_OVR_DIS (MXC_V_SPI17Y_INT_EN_TX_OVR_DIS << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_TX_OVR_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_OVR_EN (MXC_V_SPI17Y_INT_EN_TX_OVR_EN << MXC_F_SPI17Y_INT_EN_TX_OVR_POS) /**< INT_EN_TX_OVR_EN Setting */
#define MXC_F_SPI17Y_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */
#define MXC_F_SPI17Y_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */
#define MXC_V_SPI17Y_INT_EN_TX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_TX_UND_DIS Value */
#define MXC_S_SPI17Y_INT_EN_TX_UND_DIS (MXC_V_SPI17Y_INT_EN_TX_UND_DIS << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_TX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_TX_UND_EN Value */
#define MXC_S_SPI17Y_INT_EN_TX_UND_EN (MXC_V_SPI17Y_INT_EN_TX_UND_EN << MXC_F_SPI17Y_INT_EN_TX_UND_POS) /**< INT_EN_TX_UND_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */
#define MXC_F_SPI17Y_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */
#define MXC_V_SPI17Y_INT_EN_RX_OVR_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_OVR_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_OVR_DIS (MXC_V_SPI17Y_INT_EN_RX_OVR_DIS << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_OVR_EN ((uint32_t)0x1UL) /**< INT_EN_RX_OVR_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_OVR_EN (MXC_V_SPI17Y_INT_EN_RX_OVR_EN << MXC_F_SPI17Y_INT_EN_RX_OVR_POS) /**< INT_EN_RX_OVR_EN Setting */
#define MXC_F_SPI17Y_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */
#define MXC_F_SPI17Y_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */
#define MXC_V_SPI17Y_INT_EN_RX_UND_DIS ((uint32_t)0x0UL) /**< INT_EN_RX_UND_DIS Value */
#define MXC_S_SPI17Y_INT_EN_RX_UND_DIS (MXC_V_SPI17Y_INT_EN_RX_UND_DIS << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_DIS Setting */
#define MXC_V_SPI17Y_INT_EN_RX_UND_EN ((uint32_t)0x1UL) /**< INT_EN_RX_UND_EN Value */
#define MXC_S_SPI17Y_INT_EN_RX_UND_EN (MXC_V_SPI17Y_INT_EN_RX_UND_EN << MXC_F_SPI17Y_INT_EN_RX_UND_POS) /**< INT_EN_RX_UND_EN Setting */
/**@} end of group SPI17Y_INT_EN_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_WAKE_FL SPI17Y_WAKE_FL
* @brief Register for wake up flags. All bits in this register are write 1 to clear.
* @{
*/
#define MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_TX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_THRESH_POS) /**< WAKE_FL_TX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */
#define MXC_F_SPI17Y_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */
#define MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_TX_EMPTY_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR (MXC_V_SPI17Y_WAKE_FL_TX_EMPTY_CLEAR << MXC_F_SPI17Y_WAKE_FL_TX_EMPTY_POS) /**< WAKE_FL_TX_EMPTY_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_THRESH_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_RX_THRESH_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_THRESH_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_THRESH_POS) /**< WAKE_FL_RX_THRESH_CLEAR Setting */
#define MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */
#define MXC_F_SPI17Y_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */
#define MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR ((uint32_t)0x1UL) /**< WAKE_FL_RX_FULL_CLEAR Value */
#define MXC_S_SPI17Y_WAKE_FL_RX_FULL_CLEAR (MXC_V_SPI17Y_WAKE_FL_RX_FULL_CLEAR << MXC_F_SPI17Y_WAKE_FL_RX_FULL_POS) /**< WAKE_FL_RX_FULL_CLEAR Setting */
/**@} end of group SPI17Y_WAKE_FL_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_WAKE_EN SPI17Y_WAKE_EN
* @brief Register for wake up enable.
* @{
*/
#define MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_THRESH_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_THRESH_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_TX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_TX_THRESH_POS) /**< WAKE_EN_TX_THRESH_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */
#define MXC_F_SPI17Y_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */
#define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS ((uint32_t)0x0UL) /**< WAKE_EN_TX_EMPTY_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_DIS (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_DIS << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN ((uint32_t)0x1UL) /**< WAKE_EN_TX_EMPTY_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_TX_EMPTY_EN (MXC_V_SPI17Y_WAKE_EN_TX_EMPTY_EN << MXC_F_SPI17Y_WAKE_EN_TX_EMPTY_POS) /**< WAKE_EN_TX_EMPTY_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */
#define MXC_F_SPI17Y_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */
#define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_THRESH_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_DIS (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_DIS << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_THRESH_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_THRESH_EN (MXC_V_SPI17Y_WAKE_EN_RX_THRESH_EN << MXC_F_SPI17Y_WAKE_EN_RX_THRESH_POS) /**< WAKE_EN_RX_THRESH_EN Setting */
#define MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */
#define MXC_F_SPI17Y_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */
#define MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS ((uint32_t)0x0UL) /**< WAKE_EN_RX_FULL_DIS Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_FULL_DIS (MXC_V_SPI17Y_WAKE_EN_RX_FULL_DIS << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_DIS Setting */
#define MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN ((uint32_t)0x1UL) /**< WAKE_EN_RX_FULL_EN Value */
#define MXC_S_SPI17Y_WAKE_EN_RX_FULL_EN (MXC_V_SPI17Y_WAKE_EN_RX_FULL_EN << MXC_F_SPI17Y_WAKE_EN_RX_FULL_POS) /**< WAKE_EN_RX_FULL_EN Setting */
/**@} end of group SPI17Y_WAKE_EN_Register */
/**
* @ingroup spi17y_registers
* @defgroup SPI17Y_STAT SPI17Y_STAT
* @brief SPI Status register.
* @{
*/
#define MXC_F_SPI17Y_STAT_BUSY_POS 0 /**< STAT_BUSY Position */
#define MXC_F_SPI17Y_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI17Y_STAT_BUSY_POS)) /**< STAT_BUSY Mask */
#define MXC_V_SPI17Y_STAT_BUSY_NOT ((uint32_t)0x0UL) /**< STAT_BUSY_NOT Value */
#define MXC_S_SPI17Y_STAT_BUSY_NOT (MXC_V_SPI17Y_STAT_BUSY_NOT << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_NOT Setting */
#define MXC_V_SPI17Y_STAT_BUSY_ACTIVE ((uint32_t)0x1UL) /**< STAT_BUSY_ACTIVE Value */
#define MXC_S_SPI17Y_STAT_BUSY_ACTIVE (MXC_V_SPI17Y_STAT_BUSY_ACTIVE << MXC_F_SPI17Y_STAT_BUSY_POS) /**< STAT_BUSY_ACTIVE Setting */
/**@} end of group SPI17Y_STAT_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPI17Y_REGS_H_ */

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bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h Normal file
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/**
* @file spimss_regs.h
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _SPIMSS_REGS_H_
#define _SPIMSS_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup spimss
* @defgroup spimss_registers SPIMSS_Registers
* @brief Registers, Bit Masks and Bit Positions for the SPIMSS Peripheral Module.
* @details Serial Peripheral Interface.
*/
/**
* @ingroup spimss_registers
* Structure type to access the SPIMSS Registers.
*/
typedef struct {
union{
__IO uint16_t data16; /**< <tt>\b 0x00:</tt> SPIMSS DATA16 Register */
__IO uint8_t data8[2]; /**< <tt>\b 0x00:</tt> SPIMSS DATA8 Register */
};
__R uint16_t rsv_0x2;
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
__IO uint32_t status; /**< <tt>\b 0x08:</tt> SPIMSS STATUS Register */
__IO uint32_t mod; /**< <tt>\b 0x0C:</tt> SPIMSS MOD Register */
__R uint32_t rsv_0x10;
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */
} mxc_spimss_regs_t;
/* Register offsets for module SPIMSS */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_Register_Offsets Register Offsets
* @brief SPIMSS Peripheral Register Offsets from the SPIMSS Base Peripheral Address.
* @{
*/
#define MXC_R_SPIMSS_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIMSS Base Address: <tt> 0x0000</tt> */
#define MXC_R_SPIMSS_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIMSS Base Address: <tt> 0x0004</tt> */
#define MXC_R_SPIMSS_STATUS ((uint32_t)0x00000008UL) /**< Offset from SPIMSS Base Address: <tt> 0x0008</tt> */
#define MXC_R_SPIMSS_MOD ((uint32_t)0x0000000CUL) /**< Offset from SPIMSS Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPIMSS_BRG ((uint32_t)0x00000014UL) /**< Offset from SPIMSS Base Address: <tt> 0x0014</tt> */
#define MXC_R_SPIMSS_DMA ((uint32_t)0x00000018UL) /**< Offset from SPIMSS Base Address: <tt> 0x0018</tt> */
#define MXC_R_SPIMSS_I2S_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIMSS Base Address: <tt> 0x001C</tt> */
/**@} end of group spimss_registers */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA16 SPIMSS_DATA16
* @brief SPI 16-bit Data Access
* @{
*/
#define MXC_F_SPIMSS_DATA16_DATA_POS 0 /**< DATA16_DATA Position */
#define MXC_F_SPIMSS_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIMSS_DATA16_DATA_POS)) /**< DATA16_DATA Mask */
/**@} end of group SPIMSS_DATA16_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DATA8 SPIMSS_DATA8
* @brief SPI Data 8-bit access
* @{
*/
#define MXC_F_SPIMSS_DATA8_DATA_POS 0 /**< DATA8_DATA Position */
#define MXC_F_SPIMSS_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIMSS_DATA8_DATA_POS)) /**< DATA8_DATA Mask */
/**@} end of group SPIMSS_DATA8_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_CTRL SPIMSS_CTRL
* @brief SPI Control Register.
* @{
*/
#define MXC_F_SPIMSS_CTRL_SPIEN_POS 0 /**< CTRL_SPIEN Position */
#define MXC_F_SPIMSS_CTRL_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_SPIEN_POS)) /**< CTRL_SPIEN Mask */
#define MXC_V_SPIMSS_CTRL_SPIEN_DISABLE ((uint32_t)0x0UL) /**< CTRL_SPIEN_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_SPIEN_DISABLE (MXC_V_SPIMSS_CTRL_SPIEN_DISABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_SPIEN_ENABLE ((uint32_t)0x1UL) /**< CTRL_SPIEN_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_SPIEN_ENABLE (MXC_V_SPIMSS_CTRL_SPIEN_ENABLE << MXC_F_SPIMSS_CTRL_SPIEN_POS) /**< CTRL_SPIEN_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_MMEN_POS 1 /**< CTRL_MMEN Position */
#define MXC_F_SPIMSS_CTRL_MMEN ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_MMEN_POS)) /**< CTRL_MMEN Mask */
#define MXC_V_SPIMSS_CTRL_MMEN_SLAVE ((uint32_t)0x0UL) /**< CTRL_MMEN_SLAVE Value */
#define MXC_S_SPIMSS_CTRL_MMEN_SLAVE (MXC_V_SPIMSS_CTRL_MMEN_SLAVE << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_SLAVE Setting */
#define MXC_V_SPIMSS_CTRL_MMEN_MASTER ((uint32_t)0x1UL) /**< CTRL_MMEN_MASTER Value */
#define MXC_S_SPIMSS_CTRL_MMEN_MASTER (MXC_V_SPIMSS_CTRL_MMEN_MASTER << MXC_F_SPIMSS_CTRL_MMEN_POS) /**< CTRL_MMEN_MASTER Setting */
#define MXC_F_SPIMSS_CTRL_WOR_POS 2 /**< CTRL_WOR Position */
#define MXC_F_SPIMSS_CTRL_WOR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_WOR_POS)) /**< CTRL_WOR Mask */
#define MXC_V_SPIMSS_CTRL_WOR_DISABLE ((uint32_t)0x0UL) /**< CTRL_WOR_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_WOR_DISABLE (MXC_V_SPIMSS_CTRL_WOR_DISABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_WOR_ENABLE ((uint32_t)0x1UL) /**< CTRL_WOR_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_WOR_ENABLE (MXC_V_SPIMSS_CTRL_WOR_ENABLE << MXC_F_SPIMSS_CTRL_WOR_POS) /**< CTRL_WOR_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_CLKPOL_POS 3 /**< CTRL_CLKPOL Position */
#define MXC_F_SPIMSS_CTRL_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_CLKPOL_POS)) /**< CTRL_CLKPOL Mask */
#define MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO ((uint32_t)0x0UL) /**< CTRL_CLKPOL_IDLELO Value */
#define MXC_S_SPIMSS_CTRL_CLKPOL_IDLELO (MXC_V_SPIMSS_CTRL_CLKPOL_IDLELO << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLELO Setting */
#define MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI ((uint32_t)0x1UL) /**< CTRL_CLKPOL_IDLEHI Value */
#define MXC_S_SPIMSS_CTRL_CLKPOL_IDLEHI (MXC_V_SPIMSS_CTRL_CLKPOL_IDLEHI << MXC_F_SPIMSS_CTRL_CLKPOL_POS) /**< CTRL_CLKPOL_IDLEHI Setting */
#define MXC_F_SPIMSS_CTRL_PHASE_POS 4 /**< CTRL_PHASE Position */
#define MXC_F_SPIMSS_CTRL_PHASE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_PHASE_POS)) /**< CTRL_PHASE Mask */
#define MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE ((uint32_t)0x0UL) /**< CTRL_PHASE_ACTIVEEDGE Value */
#define MXC_S_SPIMSS_CTRL_PHASE_ACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_ACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_ACTIVEEDGE Setting */
#define MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE ((uint32_t)0x1UL) /**< CTRL_PHASE_INACTIVEEDGE Value */
#define MXC_S_SPIMSS_CTRL_PHASE_INACTIVEEDGE (MXC_V_SPIMSS_CTRL_PHASE_INACTIVEEDGE << MXC_F_SPIMSS_CTRL_PHASE_POS) /**< CTRL_PHASE_INACTIVEEDGE Setting */
#define MXC_F_SPIMSS_CTRL_BIRQ_POS 5 /**< CTRL_BIRQ Position */
#define MXC_F_SPIMSS_CTRL_BIRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_BIRQ_POS)) /**< CTRL_BIRQ Mask */
#define MXC_V_SPIMSS_CTRL_BIRQ_DISABLE ((uint32_t)0x0UL) /**< CTRL_BIRQ_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_BIRQ_DISABLE (MXC_V_SPIMSS_CTRL_BIRQ_DISABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_BIRQ_ENABLE ((uint32_t)0x1UL) /**< CTRL_BIRQ_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_BIRQ_ENABLE (MXC_V_SPIMSS_CTRL_BIRQ_ENABLE << MXC_F_SPIMSS_CTRL_BIRQ_POS) /**< CTRL_BIRQ_ENABLE Setting */
#define MXC_F_SPIMSS_CTRL_STR_POS 6 /**< CTRL_STR Position */
#define MXC_F_SPIMSS_CTRL_STR ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_STR_POS)) /**< CTRL_STR Mask */
#define MXC_V_SPIMSS_CTRL_STR_COMPLETE ((uint32_t)0x0UL) /**< CTRL_STR_COMPLETE Value */
#define MXC_S_SPIMSS_CTRL_STR_COMPLETE (MXC_V_SPIMSS_CTRL_STR_COMPLETE << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_COMPLETE Setting */
#define MXC_V_SPIMSS_CTRL_STR_START ((uint32_t)0x1UL) /**< CTRL_STR_START Value */
#define MXC_S_SPIMSS_CTRL_STR_START (MXC_V_SPIMSS_CTRL_STR_START << MXC_F_SPIMSS_CTRL_STR_POS) /**< CTRL_STR_START Setting */
#define MXC_F_SPIMSS_CTRL_IRQE_POS 7 /**< CTRL_IRQE Position */
#define MXC_F_SPIMSS_CTRL_IRQE ((uint32_t)(0x1UL << MXC_F_SPIMSS_CTRL_IRQE_POS)) /**< CTRL_IRQE Mask */
#define MXC_V_SPIMSS_CTRL_IRQE_DISABLE ((uint32_t)0x0UL) /**< CTRL_IRQE_DISABLE Value */
#define MXC_S_SPIMSS_CTRL_IRQE_DISABLE (MXC_V_SPIMSS_CTRL_IRQE_DISABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_DISABLE Setting */
#define MXC_V_SPIMSS_CTRL_IRQE_ENABLE ((uint32_t)0x1UL) /**< CTRL_IRQE_ENABLE Value */
#define MXC_S_SPIMSS_CTRL_IRQE_ENABLE (MXC_V_SPIMSS_CTRL_IRQE_ENABLE << MXC_F_SPIMSS_CTRL_IRQE_POS) /**< CTRL_IRQE_ENABLE Setting */
/**@} end of group SPIMSS_CTRL_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_STATUS SPIMSS_STATUS
* @brief SPI Status Register.
* @{
*/
#define MXC_F_SPIMSS_STATUS_SLAS_POS 0 /**< STATUS_SLAS Position */
#define MXC_F_SPIMSS_STATUS_SLAS ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_SLAS_POS)) /**< STATUS_SLAS Mask */
#define MXC_V_SPIMSS_STATUS_SLAS_SELECTED ((uint32_t)0x0UL) /**< STATUS_SLAS_SELECTED Value */
#define MXC_S_SPIMSS_STATUS_SLAS_SELECTED (MXC_V_SPIMSS_STATUS_SLAS_SELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_SELECTED Setting */
#define MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED ((uint32_t)0x1UL) /**< STATUS_SLAS_NOTSELECTED Value */
#define MXC_S_SPIMSS_STATUS_SLAS_NOTSELECTED (MXC_V_SPIMSS_STATUS_SLAS_NOTSELECTED << MXC_F_SPIMSS_STATUS_SLAS_POS) /**< STATUS_SLAS_NOTSELECTED Setting */
#define MXC_F_SPIMSS_STATUS_TXST_POS 1 /**< STATUS_TXST Position */
#define MXC_F_SPIMSS_STATUS_TXST ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TXST_POS)) /**< STATUS_TXST Mask */
#define MXC_V_SPIMSS_STATUS_TXST_IDLE ((uint32_t)0x0UL) /**< STATUS_TXST_IDLE Value */
#define MXC_S_SPIMSS_STATUS_TXST_IDLE (MXC_V_SPIMSS_STATUS_TXST_IDLE << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_IDLE Setting */
#define MXC_V_SPIMSS_STATUS_TXST_BUSY ((uint32_t)0x1UL) /**< STATUS_TXST_BUSY Value */
#define MXC_S_SPIMSS_STATUS_TXST_BUSY (MXC_V_SPIMSS_STATUS_TXST_BUSY << MXC_F_SPIMSS_STATUS_TXST_POS) /**< STATUS_TXST_BUSY Setting */
#define MXC_F_SPIMSS_STATUS_TUND_POS 2 /**< STATUS_TUND Position */
#define MXC_F_SPIMSS_STATUS_TUND ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TUND_POS)) /**< STATUS_TUND Mask */
#define MXC_V_SPIMSS_STATUS_TUND_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TUND_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_TUND_NOEVENT (MXC_V_SPIMSS_STATUS_TUND_NOEVENT << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_TUND_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TUND_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_TUND_OCCURRED (MXC_V_SPIMSS_STATUS_TUND_OCCURRED << MXC_F_SPIMSS_STATUS_TUND_POS) /**< STATUS_TUND_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_ROVR_POS 3 /**< STATUS_ROVR Position */
#define MXC_F_SPIMSS_STATUS_ROVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ROVR_POS)) /**< STATUS_ROVR Mask */
#define MXC_V_SPIMSS_STATUS_ROVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ROVR_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_ROVR_NOEVENT (MXC_V_SPIMSS_STATUS_ROVR_NOEVENT << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_ROVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ROVR_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_ROVR_OCCURRED (MXC_V_SPIMSS_STATUS_ROVR_OCCURRED << MXC_F_SPIMSS_STATUS_ROVR_POS) /**< STATUS_ROVR_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_ABT_POS 4 /**< STATUS_ABT Position */
#define MXC_F_SPIMSS_STATUS_ABT ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_ABT_POS)) /**< STATUS_ABT Mask */
#define MXC_V_SPIMSS_STATUS_ABT_NOEVENT ((uint32_t)0x0UL) /**< STATUS_ABT_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_ABT_NOEVENT (MXC_V_SPIMSS_STATUS_ABT_NOEVENT << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_ABT_OCCURRED ((uint32_t)0x1UL) /**< STATUS_ABT_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_ABT_OCCURRED (MXC_V_SPIMSS_STATUS_ABT_OCCURRED << MXC_F_SPIMSS_STATUS_ABT_POS) /**< STATUS_ABT_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_COL_POS 5 /**< STATUS_COL Position */
#define MXC_F_SPIMSS_STATUS_COL ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_COL_POS)) /**< STATUS_COL Mask */
#define MXC_V_SPIMSS_STATUS_COL_NOEVENT ((uint32_t)0x0UL) /**< STATUS_COL_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_COL_NOEVENT (MXC_V_SPIMSS_STATUS_COL_NOEVENT << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_COL_OCCURRED ((uint32_t)0x1UL) /**< STATUS_COL_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_COL_OCCURRED (MXC_V_SPIMSS_STATUS_COL_OCCURRED << MXC_F_SPIMSS_STATUS_COL_POS) /**< STATUS_COL_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_TOVR_POS 6 /**< STATUS_TOVR Position */
#define MXC_F_SPIMSS_STATUS_TOVR ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_TOVR_POS)) /**< STATUS_TOVR Mask */
#define MXC_V_SPIMSS_STATUS_TOVR_NOEVENT ((uint32_t)0x0UL) /**< STATUS_TOVR_NOEVENT Value */
#define MXC_S_SPIMSS_STATUS_TOVR_NOEVENT (MXC_V_SPIMSS_STATUS_TOVR_NOEVENT << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_NOEVENT Setting */
#define MXC_V_SPIMSS_STATUS_TOVR_OCCURRED ((uint32_t)0x1UL) /**< STATUS_TOVR_OCCURRED Value */
#define MXC_S_SPIMSS_STATUS_TOVR_OCCURRED (MXC_V_SPIMSS_STATUS_TOVR_OCCURRED << MXC_F_SPIMSS_STATUS_TOVR_POS) /**< STATUS_TOVR_OCCURRED Setting */
#define MXC_F_SPIMSS_STATUS_IRQ_POS 7 /**< STATUS_IRQ Position */
#define MXC_F_SPIMSS_STATUS_IRQ ((uint32_t)(0x1UL << MXC_F_SPIMSS_STATUS_IRQ_POS)) /**< STATUS_IRQ Mask */
#define MXC_V_SPIMSS_STATUS_IRQ_INACTIVE ((uint32_t)0x0UL) /**< STATUS_IRQ_INACTIVE Value */
#define MXC_S_SPIMSS_STATUS_IRQ_INACTIVE (MXC_V_SPIMSS_STATUS_IRQ_INACTIVE << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_INACTIVE Setting */
#define MXC_V_SPIMSS_STATUS_IRQ_PENDING ((uint32_t)0x1UL) /**< STATUS_IRQ_PENDING Value */
#define MXC_S_SPIMSS_STATUS_IRQ_PENDING (MXC_V_SPIMSS_STATUS_IRQ_PENDING << MXC_F_SPIMSS_STATUS_IRQ_POS) /**< STATUS_IRQ_PENDING Setting */
/**@} end of group SPIMSS_STATUS_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_MOD SPIMSS_MOD
* @brief SPI Mode Register.
* @{
*/
#define MXC_F_SPIMSS_MOD_SSV_POS 0 /**< MOD_SSV Position */
#define MXC_F_SPIMSS_MOD_SSV ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSV_POS)) /**< MOD_SSV Mask */
#define MXC_V_SPIMSS_MOD_SSV_LO ((uint32_t)0x0UL) /**< MOD_SSV_LO Value */
#define MXC_S_SPIMSS_MOD_SSV_LO (MXC_V_SPIMSS_MOD_SSV_LO << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_LO Setting */
#define MXC_V_SPIMSS_MOD_SSV_HI ((uint32_t)0x1UL) /**< MOD_SSV_HI Value */
#define MXC_S_SPIMSS_MOD_SSV_HI (MXC_V_SPIMSS_MOD_SSV_HI << MXC_F_SPIMSS_MOD_SSV_POS) /**< MOD_SSV_HI Setting */
#define MXC_F_SPIMSS_MOD_SSIO_POS 1 /**< MOD_SSIO Position */
#define MXC_F_SPIMSS_MOD_SSIO ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSIO_POS)) /**< MOD_SSIO Mask */
#define MXC_V_SPIMSS_MOD_SSIO_INPUT ((uint32_t)0x0UL) /**< MOD_SSIO_INPUT Value */
#define MXC_S_SPIMSS_MOD_SSIO_INPUT (MXC_V_SPIMSS_MOD_SSIO_INPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_INPUT Setting */
#define MXC_V_SPIMSS_MOD_SSIO_OUTPUT ((uint32_t)0x1UL) /**< MOD_SSIO_OUTPUT Value */
#define MXC_S_SPIMSS_MOD_SSIO_OUTPUT (MXC_V_SPIMSS_MOD_SSIO_OUTPUT << MXC_F_SPIMSS_MOD_SSIO_POS) /**< MOD_SSIO_OUTPUT Setting */
#define MXC_F_SPIMSS_MOD_NUMBITS_POS 2 /**< MOD_NUMBITS Position */
#define MXC_F_SPIMSS_MOD_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIMSS_MOD_NUMBITS_POS)) /**< MOD_NUMBITS Mask */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS16 ((uint32_t)0x0UL) /**< MOD_NUMBITS_BITS16 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS16 (MXC_V_SPIMSS_MOD_NUMBITS_BITS16 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS16 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS1 ((uint32_t)0x1UL) /**< MOD_NUMBITS_BITS1 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS1 (MXC_V_SPIMSS_MOD_NUMBITS_BITS1 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS1 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS2 ((uint32_t)0x2UL) /**< MOD_NUMBITS_BITS2 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS2 (MXC_V_SPIMSS_MOD_NUMBITS_BITS2 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS2 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS3 ((uint32_t)0x3UL) /**< MOD_NUMBITS_BITS3 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS3 (MXC_V_SPIMSS_MOD_NUMBITS_BITS3 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS3 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS4 ((uint32_t)0x4UL) /**< MOD_NUMBITS_BITS4 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS4 (MXC_V_SPIMSS_MOD_NUMBITS_BITS4 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS4 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS5 ((uint32_t)0x5UL) /**< MOD_NUMBITS_BITS5 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS5 (MXC_V_SPIMSS_MOD_NUMBITS_BITS5 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS5 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS6 ((uint32_t)0x6UL) /**< MOD_NUMBITS_BITS6 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS6 (MXC_V_SPIMSS_MOD_NUMBITS_BITS6 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS6 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS7 ((uint32_t)0x7UL) /**< MOD_NUMBITS_BITS7 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS7 (MXC_V_SPIMSS_MOD_NUMBITS_BITS7 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS7 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS8 ((uint32_t)0x8UL) /**< MOD_NUMBITS_BITS8 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS8 (MXC_V_SPIMSS_MOD_NUMBITS_BITS8 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS8 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS9 ((uint32_t)0x9UL) /**< MOD_NUMBITS_BITS9 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS9 (MXC_V_SPIMSS_MOD_NUMBITS_BITS9 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS9 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS10 ((uint32_t)0xAUL) /**< MOD_NUMBITS_BITS10 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS10 (MXC_V_SPIMSS_MOD_NUMBITS_BITS10 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS10 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS11 ((uint32_t)0xBUL) /**< MOD_NUMBITS_BITS11 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS11 (MXC_V_SPIMSS_MOD_NUMBITS_BITS11 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS11 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS12 ((uint32_t)0xCUL) /**< MOD_NUMBITS_BITS12 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS12 (MXC_V_SPIMSS_MOD_NUMBITS_BITS12 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS12 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS13 ((uint32_t)0xDUL) /**< MOD_NUMBITS_BITS13 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS13 (MXC_V_SPIMSS_MOD_NUMBITS_BITS13 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS13 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS14 ((uint32_t)0xEUL) /**< MOD_NUMBITS_BITS14 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS14 (MXC_V_SPIMSS_MOD_NUMBITS_BITS14 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS14 Setting */
#define MXC_V_SPIMSS_MOD_NUMBITS_BITS15 ((uint32_t)0xFUL) /**< MOD_NUMBITS_BITS15 Value */
#define MXC_S_SPIMSS_MOD_NUMBITS_BITS15 (MXC_V_SPIMSS_MOD_NUMBITS_BITS15 << MXC_F_SPIMSS_MOD_NUMBITS_POS) /**< MOD_NUMBITS_BITS15 Setting */
#define MXC_F_SPIMSS_MOD_TX_LJ_POS 7 /**< MOD_TX_LJ Position */
#define MXC_F_SPIMSS_MOD_TX_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_TX_LJ_POS)) /**< MOD_TX_LJ Mask */
#define MXC_V_SPIMSS_MOD_TX_LJ_DISABLE ((uint32_t)0x0UL) /**< MOD_TX_LJ_DISABLE Value */
#define MXC_S_SPIMSS_MOD_TX_LJ_DISABLE (MXC_V_SPIMSS_MOD_TX_LJ_DISABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_DISABLE Setting */
#define MXC_V_SPIMSS_MOD_TX_LJ_ENABLE ((uint32_t)0x1UL) /**< MOD_TX_LJ_ENABLE Value */
#define MXC_S_SPIMSS_MOD_TX_LJ_ENABLE (MXC_V_SPIMSS_MOD_TX_LJ_ENABLE << MXC_F_SPIMSS_MOD_TX_LJ_POS) /**< MOD_TX_LJ_ENABLE Setting */
#define MXC_F_SPIMSS_MOD_SSL1_POS 8 /**< MOD_SSL1 Position */
#define MXC_F_SPIMSS_MOD_SSL1 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL1_POS)) /**< MOD_SSL1 Mask */
#define MXC_V_SPIMSS_MOD_SSL1_HI ((uint32_t)0x0UL) /**< MOD_SSL1_HI Value */
#define MXC_S_SPIMSS_MOD_SSL1_HI (MXC_V_SPIMSS_MOD_SSL1_HI << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL1_LO ((uint32_t)0x1UL) /**< MOD_SSL1_LO Value */
#define MXC_S_SPIMSS_MOD_SSL1_LO (MXC_V_SPIMSS_MOD_SSL1_LO << MXC_F_SPIMSS_MOD_SSL1_POS) /**< MOD_SSL1_LO Setting */
#define MXC_F_SPIMSS_MOD_SSL2_POS 9 /**< MOD_SSL2 Position */
#define MXC_F_SPIMSS_MOD_SSL2 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL2_POS)) /**< MOD_SSL2 Mask */
#define MXC_V_SPIMSS_MOD_SSL2_HI ((uint32_t)0x0UL) /**< MOD_SSL2_HI Value */
#define MXC_S_SPIMSS_MOD_SSL2_HI (MXC_V_SPIMSS_MOD_SSL2_HI << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL2_LO ((uint32_t)0x1UL) /**< MOD_SSL2_LO Value */
#define MXC_S_SPIMSS_MOD_SSL2_LO (MXC_V_SPIMSS_MOD_SSL2_LO << MXC_F_SPIMSS_MOD_SSL2_POS) /**< MOD_SSL2_LO Setting */
#define MXC_F_SPIMSS_MOD_SSL3_POS 10 /**< MOD_SSL3 Position */
#define MXC_F_SPIMSS_MOD_SSL3 ((uint32_t)(0x1UL << MXC_F_SPIMSS_MOD_SSL3_POS)) /**< MOD_SSL3 Mask */
#define MXC_V_SPIMSS_MOD_SSL3_HI ((uint32_t)0x0UL) /**< MOD_SSL3_HI Value */
#define MXC_S_SPIMSS_MOD_SSL3_HI (MXC_V_SPIMSS_MOD_SSL3_HI << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_HI Setting */
#define MXC_V_SPIMSS_MOD_SSL3_LO ((uint32_t)0x1UL) /**< MOD_SSL3_LO Value */
#define MXC_S_SPIMSS_MOD_SSL3_LO (MXC_V_SPIMSS_MOD_SSL3_LO << MXC_F_SPIMSS_MOD_SSL3_POS) /**< MOD_SSL3_LO Setting */
/**@} end of group SPIMSS_MOD_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_BRG SPIMSS_BRG
* @brief Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for
* the SPI Baud Rate Generator. The reload value must be greater than or equal to
* 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by
* 4).
* @{
*/
#define MXC_F_SPIMSS_BRG_BRG_POS 0 /**< BRG_BRG Position */
#define MXC_F_SPIMSS_BRG_BRG ((uint32_t)(0xFFFFUL << MXC_F_SPIMSS_BRG_BRG_POS)) /**< BRG_BRG Mask */
/**@} end of group SPIMSS_BRG_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_DMA SPIMSS_DMA
* @brief SPI DMA Register.
* @{
*/
#define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_TX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LEVEL_POS) /**< DMA_TX_FIFO_LEVEL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS 4 /**< DMA_TX_FIFO_CLEAR Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */
#define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_TX_FIFO_CLEAR_COMPLETE Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_COMPLETE Setting */
#define MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_TX_FIFO_CLEAR_START Value */
#define MXC_S_SPIMSS_DMA_TX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_TX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_TX_FIFO_CLEAR_POS) /**< DMA_TX_FIFO_CLEAR_START Setting */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */
#define MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_TX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_DMA_TX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_TX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_DMA_TX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_TX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS) /**< DMA_TX_DMA_EN_ENABLE Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 ((uint32_t)0x0UL) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRY1 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 ((uint32_t)0x1UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES2 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 ((uint32_t)0x2UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES3 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 ((uint32_t)0x3UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES4 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 ((uint32_t)0x4UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES5 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 ((uint32_t)0x5UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES6 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 ((uint32_t)0x6UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES7 Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 ((uint32_t)0x7UL) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 (MXC_V_SPIMSS_DMA_RX_FIFO_LEVEL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LEVEL_POS) /**< DMA_RX_FIFO_LEVEL_ENTRIES8 Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS 20 /**< DMA_RX_FIFO_CLEAR Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */
#define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE ((uint32_t)0x0UL) /**< DMA_RX_FIFO_CLEAR_COMPLETE Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_COMPLETE << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_COMPLETE Setting */
#define MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START ((uint32_t)0x1UL) /**< DMA_RX_FIFO_CLEAR_START Value */
#define MXC_S_SPIMSS_DMA_RX_FIFO_CLEAR_START (MXC_V_SPIMSS_DMA_RX_FIFO_CLEAR_START << MXC_F_SPIMSS_DMA_RX_FIFO_CLEAR_POS) /**< DMA_RX_FIFO_CLEAR_START Setting */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */
#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */
#define MXC_F_SPIMSS_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */
#define MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE ((uint32_t)0x0UL) /**< DMA_RX_DMA_EN_DISABLE Value */
#define MXC_S_SPIMSS_DMA_RX_DMA_EN_DISABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_DISABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_DISABLE Setting */
#define MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE ((uint32_t)0x1UL) /**< DMA_RX_DMA_EN_ENABLE Value */
#define MXC_S_SPIMSS_DMA_RX_DMA_EN_ENABLE (MXC_V_SPIMSS_DMA_RX_DMA_EN_ENABLE << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS) /**< DMA_RX_DMA_EN_ENABLE Setting */
/**@} end of group SPIMSS_DMA_Register */
/**
* @ingroup spimss_registers
* @defgroup SPIMSS_I2S_CTRL SPIMSS_I2S_CTRL
* @brief I2S Control Register.
* @{
*/
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_EN_DISABLE Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_DISABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_DISABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_DISABLE Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_EN_ENABLE Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_EN_ENABLE (MXC_V_SPIMSS_I2S_CTRL_I2S_EN_ENABLE << MXC_F_SPIMSS_I2S_CTRL_I2S_EN_POS) /**< I2S_CTRL_I2S_EN_ENABLE Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MUTE_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MUTE_REPLACED Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_MUTE_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_MUTE_POS) /**< I2S_CTRL_I2S_MUTE_REPLACED Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_PAUSE_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_PAUSE_HALT Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT (MXC_V_SPIMSS_I2S_CTRL_I2S_PAUSE_HALT << MXC_F_SPIMSS_I2S_CTRL_I2S_PAUSE_POS) /**< I2S_CTRL_I2S_PAUSE_HALT Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_STEREOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_STEREOPHONIC Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC (MXC_V_SPIMSS_I2S_CTRL_I2S_MONO_MONOPHONIC << MXC_F_SPIMSS_I2S_CTRL_I2S_MONO_POS) /**< I2S_CTRL_I2S_MONO_MONOPHONIC Setting */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
#define MXC_F_SPIMSS_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL ((uint32_t)0x0UL) /**< I2S_CTRL_I2S_LJ_NORMAL Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_NORMAL << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_NORMAL Setting */
#define MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED ((uint32_t)0x1UL) /**< I2S_CTRL_I2S_LJ_REPLACED Value */
#define MXC_S_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED (MXC_V_SPIMSS_I2S_CTRL_I2S_LJ_REPLACED << MXC_F_SPIMSS_I2S_CTRL_I2S_LJ_POS) /**< I2S_CTRL_I2S_LJ_REPLACED Setting */
/**@} end of group SPIMSS_I2S_CTRL_Register */
#ifdef __cplusplus
}
#endif
#endif /* _SPIMSS_REGS_H_ */

0
bsp/maxim/libraries/CMSIS/system_max32660.h → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/system_max32660.h
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bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h Normal file
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@ -0,0 +1,233 @@
/**
* @file tmr_regs.h
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _TMR_REGS_H_
#define _TMR_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup tmr
* @defgroup tmr_registers TMR_Registers
* @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module.
* @details 32-bit reloadable timer that can be used for timing and event counting.
*/
/**
* @ingroup tmr_registers
* Structure type to access the TMR Registers.
*/
typedef struct {
__IO uint32_t cnt; /**< <tt>\b 0x00:</tt> TMR CNT Register */
__IO uint32_t cmp; /**< <tt>\b 0x04:</tt> TMR CMP Register */
__IO uint32_t pwm; /**< <tt>\b 0x08:</tt> TMR PWM Register */
__IO uint32_t intr; /**< <tt>\b 0x0C:</tt> TMR INTR Register */
__IO uint32_t cn; /**< <tt>\b 0x10:</tt> TMR CN Register */
__IO uint32_t nolcmp; /**< <tt>\b 0x14:</tt> TMR NOLCMP Register */
} mxc_tmr_regs_t;
/* Register offsets for module TMR */
/**
* @ingroup tmr_registers
* @defgroup TMR_Register_Offsets Register Offsets
* @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address.
* @{
*/
#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: <tt> 0x0000</tt> */
#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: <tt> 0x0004</tt> */
#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: <tt> 0x0008</tt> */
#define MXC_R_TMR_INTR ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: <tt> 0x000C</tt> */
#define MXC_R_TMR_CN ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: <tt> 0x0010</tt> */
#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: <tt> 0x0014</tt> */
/**@} end of group tmr_registers */
/**
* @ingroup tmr_registers
* @defgroup TMR_INTR TMR_INTR
* @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the
* associated interrupt.
* @{
*/
#define MXC_F_TMR_INTR_IRQ_CLR_POS 0 /**< INTR_IRQ_CLR Position */
#define MXC_F_TMR_INTR_IRQ_CLR ((uint32_t)(0x1UL << MXC_F_TMR_INTR_IRQ_CLR_POS)) /**< INTR_IRQ_CLR Mask */
/**@} end of group TMR_INTR_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_CN TMR_CN
* @brief Timer Control Register.
* @{
*/
#define MXC_F_TMR_CN_TMODE_POS 0 /**< CN_TMODE Position */
#define MXC_F_TMR_CN_TMODE ((uint32_t)(0x7UL << MXC_F_TMR_CN_TMODE_POS)) /**< CN_TMODE Mask */
#define MXC_V_TMR_CN_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CN_TMODE_ONESHOT Value */
#define MXC_S_TMR_CN_TMODE_ONESHOT (MXC_V_TMR_CN_TMODE_ONESHOT << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_ONESHOT Setting */
#define MXC_V_TMR_CN_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CN_TMODE_CONTINUOUS Value */
#define MXC_S_TMR_CN_TMODE_CONTINUOUS (MXC_V_TMR_CN_TMODE_CONTINUOUS << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CONTINUOUS Setting */
#define MXC_V_TMR_CN_TMODE_COUNTER ((uint32_t)0x2UL) /**< CN_TMODE_COUNTER Value */
#define MXC_S_TMR_CN_TMODE_COUNTER (MXC_V_TMR_CN_TMODE_COUNTER << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COUNTER Setting */
#define MXC_V_TMR_CN_TMODE_PWM ((uint32_t)0x3UL) /**< CN_TMODE_PWM Value */
#define MXC_S_TMR_CN_TMODE_PWM (MXC_V_TMR_CN_TMODE_PWM << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_PWM Setting */
#define MXC_V_TMR_CN_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CN_TMODE_CAPTURE Value */
#define MXC_S_TMR_CN_TMODE_CAPTURE (MXC_V_TMR_CN_TMODE_CAPTURE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURE Setting */
#define MXC_V_TMR_CN_TMODE_COMPARE ((uint32_t)0x5UL) /**< CN_TMODE_COMPARE Value */
#define MXC_S_TMR_CN_TMODE_COMPARE (MXC_V_TMR_CN_TMODE_COMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_COMPARE Setting */
#define MXC_V_TMR_CN_TMODE_GATED ((uint32_t)0x6UL) /**< CN_TMODE_GATED Value */
#define MXC_S_TMR_CN_TMODE_GATED (MXC_V_TMR_CN_TMODE_GATED << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_GATED Setting */
#define MXC_V_TMR_CN_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CN_TMODE_CAPTURECOMPARE Value */
#define MXC_S_TMR_CN_TMODE_CAPTURECOMPARE (MXC_V_TMR_CN_TMODE_CAPTURECOMPARE << MXC_F_TMR_CN_TMODE_POS) /**< CN_TMODE_CAPTURECOMPARE Setting */
#define MXC_F_TMR_CN_PRES_POS 3 /**< CN_PRES Position */
#define MXC_F_TMR_CN_PRES ((uint32_t)(0x7UL << MXC_F_TMR_CN_PRES_POS)) /**< CN_PRES Mask */
#define MXC_V_TMR_CN_PRES_DIV1 ((uint32_t)0x0UL) /**< CN_PRES_DIV1 Value */
#define MXC_S_TMR_CN_PRES_DIV1 (MXC_V_TMR_CN_PRES_DIV1 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV1 Setting */
#define MXC_V_TMR_CN_PRES_DIV2 ((uint32_t)0x1UL) /**< CN_PRES_DIV2 Value */
#define MXC_S_TMR_CN_PRES_DIV2 (MXC_V_TMR_CN_PRES_DIV2 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV2 Setting */
#define MXC_V_TMR_CN_PRES_DIV4 ((uint32_t)0x2UL) /**< CN_PRES_DIV4 Value */
#define MXC_S_TMR_CN_PRES_DIV4 (MXC_V_TMR_CN_PRES_DIV4 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV4 Setting */
#define MXC_V_TMR_CN_PRES_DIV8 ((uint32_t)0x3UL) /**< CN_PRES_DIV8 Value */
#define MXC_S_TMR_CN_PRES_DIV8 (MXC_V_TMR_CN_PRES_DIV8 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV8 Setting */
#define MXC_V_TMR_CN_PRES_DIV16 ((uint32_t)0x4UL) /**< CN_PRES_DIV16 Value */
#define MXC_S_TMR_CN_PRES_DIV16 (MXC_V_TMR_CN_PRES_DIV16 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV16 Setting */
#define MXC_V_TMR_CN_PRES_DIV32 ((uint32_t)0x5UL) /**< CN_PRES_DIV32 Value */
#define MXC_S_TMR_CN_PRES_DIV32 (MXC_V_TMR_CN_PRES_DIV32 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV32 Setting */
#define MXC_V_TMR_CN_PRES_DIV64 ((uint32_t)0x6UL) /**< CN_PRES_DIV64 Value */
#define MXC_S_TMR_CN_PRES_DIV64 (MXC_V_TMR_CN_PRES_DIV64 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV64 Setting */
#define MXC_V_TMR_CN_PRES_DIV128 ((uint32_t)0x7UL) /**< CN_PRES_DIV128 Value */
#define MXC_S_TMR_CN_PRES_DIV128 (MXC_V_TMR_CN_PRES_DIV128 << MXC_F_TMR_CN_PRES_POS) /**< CN_PRES_DIV128 Setting */
#define MXC_F_TMR_CN_TPOL_POS 6 /**< CN_TPOL Position */
#define MXC_F_TMR_CN_TPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_TPOL_POS)) /**< CN_TPOL Mask */
#define MXC_V_TMR_CN_TPOL_ACTIVEHI ((uint32_t)0x0UL) /**< CN_TPOL_ACTIVEHI Value */
#define MXC_S_TMR_CN_TPOL_ACTIVEHI (MXC_V_TMR_CN_TPOL_ACTIVEHI << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVEHI Setting */
#define MXC_V_TMR_CN_TPOL_ACTIVELO ((uint32_t)0x1UL) /**< CN_TPOL_ACTIVELO Value */
#define MXC_S_TMR_CN_TPOL_ACTIVELO (MXC_V_TMR_CN_TPOL_ACTIVELO << MXC_F_TMR_CN_TPOL_POS) /**< CN_TPOL_ACTIVELO Setting */
#define MXC_F_TMR_CN_TEN_POS 7 /**< CN_TEN Position */
#define MXC_F_TMR_CN_TEN ((uint32_t)(0x1UL << MXC_F_TMR_CN_TEN_POS)) /**< CN_TEN Mask */
#define MXC_V_TMR_CN_TEN_DIS ((uint32_t)0x0UL) /**< CN_TEN_DIS Value */
#define MXC_S_TMR_CN_TEN_DIS (MXC_V_TMR_CN_TEN_DIS << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_DIS Setting */
#define MXC_V_TMR_CN_TEN_EN ((uint32_t)0x1UL) /**< CN_TEN_EN Value */
#define MXC_S_TMR_CN_TEN_EN (MXC_V_TMR_CN_TEN_EN << MXC_F_TMR_CN_TEN_POS) /**< CN_TEN_EN Setting */
#define MXC_F_TMR_CN_PRES3_POS 8 /**< CN_PRES3 Position */
#define MXC_F_TMR_CN_PRES3 ((uint32_t)(0x1UL << MXC_F_TMR_CN_PRES3_POS)) /**< CN_PRES3 Mask */
#define MXC_F_TMR_CN_PWMSYNC_POS 9 /**< CN_PWMSYNC Position */
#define MXC_F_TMR_CN_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMSYNC_POS)) /**< CN_PWMSYNC Mask */
#define MXC_V_TMR_CN_PWMSYNC_DIS ((uint32_t)0x0UL) /**< CN_PWMSYNC_DIS Value */
#define MXC_S_TMR_CN_PWMSYNC_DIS (MXC_V_TMR_CN_PWMSYNC_DIS << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_DIS Setting */
#define MXC_V_TMR_CN_PWMSYNC_EN ((uint32_t)0x1UL) /**< CN_PWMSYNC_EN Value */
#define MXC_S_TMR_CN_PWMSYNC_EN (MXC_V_TMR_CN_PWMSYNC_EN << MXC_F_TMR_CN_PWMSYNC_POS) /**< CN_PWMSYNC_EN Setting */
#define MXC_F_TMR_CN_NOLHPOL_POS 10 /**< CN_NOLHPOL Position */
#define MXC_F_TMR_CN_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLHPOL_POS)) /**< CN_NOLHPOL Mask */
#define MXC_V_TMR_CN_NOLHPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLHPOL_DIS Value */
#define MXC_S_TMR_CN_NOLHPOL_DIS (MXC_V_TMR_CN_NOLHPOL_DIS << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_DIS Setting */
#define MXC_V_TMR_CN_NOLHPOL_EN ((uint32_t)0x1UL) /**< CN_NOLHPOL_EN Value */
#define MXC_S_TMR_CN_NOLHPOL_EN (MXC_V_TMR_CN_NOLHPOL_EN << MXC_F_TMR_CN_NOLHPOL_POS) /**< CN_NOLHPOL_EN Setting */
#define MXC_F_TMR_CN_NOLLPOL_POS 11 /**< CN_NOLLPOL Position */
#define MXC_F_TMR_CN_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CN_NOLLPOL_POS)) /**< CN_NOLLPOL Mask */
#define MXC_V_TMR_CN_NOLLPOL_DIS ((uint32_t)0x0UL) /**< CN_NOLLPOL_DIS Value */
#define MXC_S_TMR_CN_NOLLPOL_DIS (MXC_V_TMR_CN_NOLLPOL_DIS << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_DIS Setting */
#define MXC_V_TMR_CN_NOLLPOL_EN ((uint32_t)0x1UL) /**< CN_NOLLPOL_EN Value */
#define MXC_S_TMR_CN_NOLLPOL_EN (MXC_V_TMR_CN_NOLLPOL_EN << MXC_F_TMR_CN_NOLLPOL_POS) /**< CN_NOLLPOL_EN Setting */
#define MXC_F_TMR_CN_PWMCKBD_POS 12 /**< CN_PWMCKBD Position */
#define MXC_F_TMR_CN_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CN_PWMCKBD_POS)) /**< CN_PWMCKBD Mask */
#define MXC_V_TMR_CN_PWMCKBD_DIS ((uint32_t)0x1UL) /**< CN_PWMCKBD_DIS Value */
#define MXC_S_TMR_CN_PWMCKBD_DIS (MXC_V_TMR_CN_PWMCKBD_DIS << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_DIS Setting */
#define MXC_V_TMR_CN_PWMCKBD_EN ((uint32_t)0x0UL) /**< CN_PWMCKBD_EN Value */
#define MXC_S_TMR_CN_PWMCKBD_EN (MXC_V_TMR_CN_PWMCKBD_EN << MXC_F_TMR_CN_PWMCKBD_POS) /**< CN_PWMCKBD_EN Setting */
/**@} end of group TMR_CN_Register */
/**
* @ingroup tmr_registers
* @defgroup TMR_NOLCMP TMR_NOLCMP
* @brief Timer Non-Overlapping Compare Register.
* @{
*/
#define MXC_F_TMR_NOLCMP_NOLLCMP_POS 0 /**< NOLCMP_NOLLCMP Position */
#define MXC_F_TMR_NOLCMP_NOLLCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLLCMP_POS)) /**< NOLCMP_NOLLCMP Mask */
#define MXC_F_TMR_NOLCMP_NOLHCMP_POS 8 /**< NOLCMP_NOLHCMP Position */
#define MXC_F_TMR_NOLCMP_NOLHCMP ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_NOLHCMP_POS)) /**< NOLCMP_NOLHCMP Mask */
/**@} end of group TMR_NOLCMP_Register */
#ifdef __cplusplus
}
#endif
#endif /* _TMR_REGS_H_ */

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@ -0,0 +1,450 @@
/**
* @file uart_regs.h
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup uart
* @defgroup uart_registers UART_Registers
* @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module.
* @details UART
*/
/**
* @ingroup uart_registers
* Structure type to access the UART Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> UART CTRL Register */
__IO uint32_t thresh_ctrl; /**< <tt>\b 0x04:</tt> UART THRESH_CTRL Register */
__I uint32_t status; /**< <tt>\b 0x08:</tt> UART STATUS Register */
__IO uint32_t int_en; /**< <tt>\b 0x0C:</tt> UART INT_EN Register */
__IO uint32_t int_fl; /**< <tt>\b 0x10:</tt> UART INT_FL Register */
__IO uint32_t baud0; /**< <tt>\b 0x14:</tt> UART BAUD0 Register */
__IO uint32_t baud1; /**< <tt>\b 0x18:</tt> UART BAUD1 Register */
__IO uint32_t fifo; /**< <tt>\b 0x1C:</tt> UART FIFO Register */
__IO uint32_t dma; /**< <tt>\b 0x20:</tt> UART DMA Register */
__IO uint32_t tx_fifo; /**< <tt>\b 0x24:</tt> UART TX_FIFO Register */
} mxc_uart_regs_t;
/* Register offsets for module UART */
/**
* @ingroup uart_registers
* @defgroup UART_Register_Offsets Register Offsets
* @brief UART Peripheral Register Offsets from the UART Base Peripheral Address.
* @{
*/
#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */
#define MXC_R_UART_THRESH_CTRL ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */
#define MXC_R_UART_STATUS ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */
#define MXC_R_UART_INT_EN ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */
#define MXC_R_UART_INT_FL ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */
#define MXC_R_UART_BAUD0 ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */
#define MXC_R_UART_BAUD1 ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */
#define MXC_R_UART_FIFO ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */
#define MXC_R_UART_DMA ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */
#define MXC_R_UART_TX_FIFO ((uint32_t)0x00000024UL) /**< Offset from UART Base Address: <tt> 0x0024</tt> */
/**@} end of group uart_registers */
/**
* @ingroup uart_registers
* @defgroup UART_CTRL UART_CTRL
* @brief Control Register.
* @{
*/
#define MXC_F_UART_CTRL_ENABLE_POS 0 /**< CTRL_ENABLE Position */
#define MXC_F_UART_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_ENABLE_POS)) /**< CTRL_ENABLE Mask */
#define MXC_V_UART_CTRL_ENABLE_DIS ((uint32_t)0x0UL) /**< CTRL_ENABLE_DIS Value */
#define MXC_S_UART_CTRL_ENABLE_DIS (MXC_V_UART_CTRL_ENABLE_DIS << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_DIS Setting */
#define MXC_V_UART_CTRL_ENABLE_EN ((uint32_t)0x1UL) /**< CTRL_ENABLE_EN Value */
#define MXC_S_UART_CTRL_ENABLE_EN (MXC_V_UART_CTRL_ENABLE_EN << MXC_F_UART_CTRL_ENABLE_POS) /**< CTRL_ENABLE_EN Setting */
#define MXC_F_UART_CTRL_PARITY_EN_POS 1 /**< CTRL_PARITY_EN Position */
#define MXC_F_UART_CTRL_PARITY_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARITY_EN_POS)) /**< CTRL_PARITY_EN Mask */
#define MXC_V_UART_CTRL_PARITY_EN_DIS ((uint32_t)0x0UL) /**< CTRL_PARITY_EN_DIS Value */
#define MXC_S_UART_CTRL_PARITY_EN_DIS (MXC_V_UART_CTRL_PARITY_EN_DIS << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_DIS Setting */
#define MXC_V_UART_CTRL_PARITY_EN_EN ((uint32_t)0x1UL) /**< CTRL_PARITY_EN_EN Value */
#define MXC_S_UART_CTRL_PARITY_EN_EN (MXC_V_UART_CTRL_PARITY_EN_EN << MXC_F_UART_CTRL_PARITY_EN_POS) /**< CTRL_PARITY_EN_EN Setting */
#define MXC_F_UART_CTRL_PARITY_POS 2 /**< CTRL_PARITY Position */
#define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x3UL << MXC_F_UART_CTRL_PARITY_POS)) /**< CTRL_PARITY Mask */
#define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)0x0UL) /**< CTRL_PARITY_EVEN Value */
#define MXC_S_UART_CTRL_PARITY_EVEN (MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_EVEN Setting */
#define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)0x1UL) /**< CTRL_PARITY_ODD Value */
#define MXC_S_UART_CTRL_PARITY_ODD (MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_ODD Setting */
#define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)0x2UL) /**< CTRL_PARITY_MARK Value */
#define MXC_S_UART_CTRL_PARITY_MARK (MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_MARK Setting */
#define MXC_V_UART_CTRL_PARITY_SPACE ((uint32_t)0x3UL) /**< CTRL_PARITY_SPACE Value */
#define MXC_S_UART_CTRL_PARITY_SPACE (MXC_V_UART_CTRL_PARITY_SPACE << MXC_F_UART_CTRL_PARITY_POS) /**< CTRL_PARITY_SPACE Setting */
#define MXC_F_UART_CTRL_PARMD_POS 4 /**< CTRL_PARMD Position */
#define MXC_F_UART_CTRL_PARMD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PARMD_POS)) /**< CTRL_PARMD Mask */
#define MXC_V_UART_CTRL_PARMD_1 ((uint32_t)0x0UL) /**< CTRL_PARMD_1 Value */
#define MXC_S_UART_CTRL_PARMD_1 (MXC_V_UART_CTRL_PARMD_1 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_1 Setting */
#define MXC_V_UART_CTRL_PARMD_0 ((uint32_t)0x1UL) /**< CTRL_PARMD_0 Value */
#define MXC_S_UART_CTRL_PARMD_0 (MXC_V_UART_CTRL_PARMD_0 << MXC_F_UART_CTRL_PARMD_POS) /**< CTRL_PARMD_0 Setting */
#define MXC_F_UART_CTRL_TX_FLUSH_POS 5 /**< CTRL_TX_FLUSH Position */
#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */
#define MXC_F_UART_CTRL_RX_FLUSH_POS 6 /**< CTRL_RX_FLUSH Position */
#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */
#define MXC_F_UART_CTRL_BITACC_POS 7 /**< CTRL_BITACC Position */
#define MXC_F_UART_CTRL_BITACC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BITACC_POS)) /**< CTRL_BITACC Mask */
#define MXC_V_UART_CTRL_BITACC_FRAME ((uint32_t)0x0UL) /**< CTRL_BITACC_FRAME Value */
#define MXC_S_UART_CTRL_BITACC_FRAME (MXC_V_UART_CTRL_BITACC_FRAME << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_FRAME Setting */
#define MXC_V_UART_CTRL_BITACC_BIT ((uint32_t)0x1UL) /**< CTRL_BITACC_BIT Value */
#define MXC_S_UART_CTRL_BITACC_BIT (MXC_V_UART_CTRL_BITACC_BIT << MXC_F_UART_CTRL_BITACC_POS) /**< CTRL_BITACC_BIT Setting */
#define MXC_F_UART_CTRL_CHAR_SIZE_POS 8 /**< CTRL_CHAR_SIZE Position */
#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */
#define MXC_V_UART_CTRL_CHAR_SIZE_5 ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_5 (MXC_V_UART_CTRL_CHAR_SIZE_5 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_6 ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_6 (MXC_V_UART_CTRL_CHAR_SIZE_6 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_7 ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_7 (MXC_V_UART_CTRL_CHAR_SIZE_7 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7 Setting */
#define MXC_V_UART_CTRL_CHAR_SIZE_8 ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8 Value */
#define MXC_S_UART_CTRL_CHAR_SIZE_8 (MXC_V_UART_CTRL_CHAR_SIZE_8 << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8 Setting */
#define MXC_F_UART_CTRL_STOPBITS_POS 10 /**< CTRL_STOPBITS Position */
#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */
#define MXC_V_UART_CTRL_STOPBITS_1 ((uint32_t)0x0UL) /**< CTRL_STOPBITS_1 Value */
#define MXC_S_UART_CTRL_STOPBITS_1 (MXC_V_UART_CTRL_STOPBITS_1 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1 Setting */
#define MXC_V_UART_CTRL_STOPBITS_1_5 ((uint32_t)0x1UL) /**< CTRL_STOPBITS_1_5 Value */
#define MXC_S_UART_CTRL_STOPBITS_1_5 (MXC_V_UART_CTRL_STOPBITS_1_5 << MXC_F_UART_CTRL_STOPBITS_POS) /**< CTRL_STOPBITS_1_5 Setting */
#define MXC_F_UART_CTRL_FLOW_CTRL_POS 11 /**< CTRL_FLOW_CTRL Position */
#define MXC_F_UART_CTRL_FLOW_CTRL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_CTRL_POS)) /**< CTRL_FLOW_CTRL Mask */
#define MXC_V_UART_CTRL_FLOW_CTRL_EN ((uint32_t)0x1UL) /**< CTRL_FLOW_CTRL_EN Value */
#define MXC_S_UART_CTRL_FLOW_CTRL_EN (MXC_V_UART_CTRL_FLOW_CTRL_EN << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_EN Setting */
#define MXC_V_UART_CTRL_FLOW_CTRL_DIS ((uint32_t)0x0UL) /**< CTRL_FLOW_CTRL_DIS Value */
#define MXC_S_UART_CTRL_FLOW_CTRL_DIS (MXC_V_UART_CTRL_FLOW_CTRL_DIS << MXC_F_UART_CTRL_FLOW_CTRL_POS) /**< CTRL_FLOW_CTRL_DIS Setting */
#define MXC_F_UART_CTRL_FLOW_POL_POS 12 /**< CTRL_FLOW_POL Position */
#define MXC_F_UART_CTRL_FLOW_POL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FLOW_POL_POS)) /**< CTRL_FLOW_POL Mask */
#define MXC_V_UART_CTRL_FLOW_POL_0 ((uint32_t)0x0UL) /**< CTRL_FLOW_POL_0 Value */
#define MXC_S_UART_CTRL_FLOW_POL_0 (MXC_V_UART_CTRL_FLOW_POL_0 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_0 Setting */
#define MXC_V_UART_CTRL_FLOW_POL_1 ((uint32_t)0x1UL) /**< CTRL_FLOW_POL_1 Value */
#define MXC_S_UART_CTRL_FLOW_POL_1 (MXC_V_UART_CTRL_FLOW_POL_1 << MXC_F_UART_CTRL_FLOW_POL_POS) /**< CTRL_FLOW_POL_1 Setting */
#define MXC_F_UART_CTRL_NULL_MODEM_POS 13 /**< CTRL_NULL_MODEM Position */
#define MXC_F_UART_CTRL_NULL_MODEM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_NULL_MODEM_POS)) /**< CTRL_NULL_MODEM Mask */
#define MXC_V_UART_CTRL_NULL_MODEM_DIS ((uint32_t)0x0UL) /**< CTRL_NULL_MODEM_DIS Value */
#define MXC_S_UART_CTRL_NULL_MODEM_DIS (MXC_V_UART_CTRL_NULL_MODEM_DIS << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_DIS Setting */
#define MXC_V_UART_CTRL_NULL_MODEM_EN ((uint32_t)0x1UL) /**< CTRL_NULL_MODEM_EN Value */
#define MXC_S_UART_CTRL_NULL_MODEM_EN (MXC_V_UART_CTRL_NULL_MODEM_EN << MXC_F_UART_CTRL_NULL_MODEM_POS) /**< CTRL_NULL_MODEM_EN Setting */
#define MXC_F_UART_CTRL_BREAK_POS 14 /**< CTRL_BREAK Position */
#define MXC_F_UART_CTRL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BREAK_POS)) /**< CTRL_BREAK Mask */
#define MXC_V_UART_CTRL_BREAK_DIS ((uint32_t)0x0UL) /**< CTRL_BREAK_DIS Value */
#define MXC_S_UART_CTRL_BREAK_DIS (MXC_V_UART_CTRL_BREAK_DIS << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_DIS Setting */
#define MXC_V_UART_CTRL_BREAK_EN ((uint32_t)0x1UL) /**< CTRL_BREAK_EN Value */
#define MXC_S_UART_CTRL_BREAK_EN (MXC_V_UART_CTRL_BREAK_EN << MXC_F_UART_CTRL_BREAK_POS) /**< CTRL_BREAK_EN Setting */
#define MXC_F_UART_CTRL_CLKSEL_POS 15 /**< CTRL_CLKSEL Position */
#define MXC_F_UART_CTRL_CLKSEL ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */
#define MXC_V_UART_CTRL_CLKSEL_SYSTEM ((uint32_t)0x0UL) /**< CTRL_CLKSEL_SYSTEM Value */
#define MXC_S_UART_CTRL_CLKSEL_SYSTEM (MXC_V_UART_CTRL_CLKSEL_SYSTEM << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_SYSTEM Setting */
#define MXC_V_UART_CTRL_CLKSEL_ALTERNATE ((uint32_t)0x1UL) /**< CTRL_CLKSEL_ALTERNATE Value */
#define MXC_S_UART_CTRL_CLKSEL_ALTERNATE (MXC_V_UART_CTRL_CLKSEL_ALTERNATE << MXC_F_UART_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ALTERNATE Setting */
#define MXC_F_UART_CTRL_RX_TO_POS 16 /**< CTRL_RX_TO Position */
#define MXC_F_UART_CTRL_RX_TO ((uint32_t)(0xFFUL << MXC_F_UART_CTRL_RX_TO_POS)) /**< CTRL_RX_TO Mask */
/**@} end of group UART_CTRL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_THRESH_CTRL UART_THRESH_CTRL
* @brief Threshold Control register.
* @{
*/
#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS 0 /**< THRESH_CTRL_RX_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) /**< THRESH_CTRL_RX_FIFO_THRESH Mask */
#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS 8 /**< THRESH_CTRL_TX_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) /**< THRESH_CTRL_TX_FIFO_THRESH Mask */
#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS 16 /**< THRESH_CTRL_RTS_FIFO_THRESH Position */
#define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH ((uint32_t)(0x3FUL << MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) /**< THRESH_CTRL_RTS_FIFO_THRESH Mask */
/**@} end of group UART_THRESH_CTRL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_STATUS UART_STATUS
* @brief Status Register.
* @{
*/
#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */
#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */
#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */
#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */
#define MXC_F_UART_STATUS_PARITY_POS 2 /**< STATUS_PARITY Position */
#define MXC_F_UART_STATUS_PARITY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_PARITY_POS)) /**< STATUS_PARITY Mask */
#define MXC_F_UART_STATUS_BREAK_POS 3 /**< STATUS_BREAK Position */
#define MXC_F_UART_STATUS_BREAK ((uint32_t)(0x1UL << MXC_F_UART_STATUS_BREAK_POS)) /**< STATUS_BREAK Mask */
#define MXC_F_UART_STATUS_RX_EMPTY_POS 4 /**< STATUS_RX_EMPTY Position */
#define MXC_F_UART_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */
#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */
#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
#define MXC_F_UART_STATUS_TX_EMPTY_POS 6 /**< STATUS_TX_EMPTY Position */
#define MXC_F_UART_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */
#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */
#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
#define MXC_F_UART_STATUS_RX_FIFO_CNT_POS 8 /**< STATUS_RX_FIFO_CNT Position */
#define MXC_F_UART_STATUS_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) /**< STATUS_RX_FIFO_CNT Mask */
#define MXC_F_UART_STATUS_TX_FIFO_CNT_POS 16 /**< STATUS_TX_FIFO_CNT Position */
#define MXC_F_UART_STATUS_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) /**< STATUS_TX_FIFO_CNT Mask */
#define MXC_F_UART_STATUS_RX_TO_POS 24 /**< STATUS_RX_TO Position */
#define MXC_F_UART_STATUS_RX_TO ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_TO_POS)) /**< STATUS_RX_TO Mask */
/**@} end of group UART_STATUS_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_EN UART_INT_EN
* @brief Interrupt Enable Register.
* @{
*/
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS 0 /**< INT_EN_RX_FRAME_ERROR Position */
#define MXC_F_UART_INT_EN_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) /**< INT_EN_RX_FRAME_ERROR Mask */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS 1 /**< INT_EN_RX_PARITY_ERROR Position */
#define MXC_F_UART_INT_EN_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) /**< INT_EN_RX_PARITY_ERROR Mask */
#define MXC_F_UART_INT_EN_CTS_CHANGE_POS 2 /**< INT_EN_CTS_CHANGE Position */
#define MXC_F_UART_INT_EN_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_CHANGE_POS)) /**< INT_EN_CTS_CHANGE Mask */
#define MXC_F_UART_INT_EN_RX_OVERRUN_POS 3 /**< INT_EN_RX_OVERRUN Position */
#define MXC_F_UART_INT_EN_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OVERRUN_POS)) /**< INT_EN_RX_OVERRUN Mask */
#define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS 4 /**< INT_EN_RX_FIFO_THRESH Position */
#define MXC_F_UART_INT_EN_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) /**< INT_EN_RX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_EN_TX_FIFO_ALMOST_EMPTY Position */
#define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_EN_TX_FIFO_ALMOST_EMPTY Mask */
#define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS 6 /**< INT_EN_TX_FIFO_THRESH Position */
#define MXC_F_UART_INT_EN_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) /**< INT_EN_TX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_EN_BREAK_POS 7 /**< INT_EN_BREAK Position */
#define MXC_F_UART_INT_EN_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_BREAK_POS)) /**< INT_EN_BREAK Mask */
#define MXC_F_UART_INT_EN_RX_TIMEOUT_POS 8 /**< INT_EN_RX_TIMEOUT Position */
#define MXC_F_UART_INT_EN_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) /**< INT_EN_RX_TIMEOUT Mask */
#define MXC_F_UART_INT_EN_LAST_BREAK_POS 9 /**< INT_EN_LAST_BREAK Position */
#define MXC_F_UART_INT_EN_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_LAST_BREAK_POS)) /**< INT_EN_LAST_BREAK Mask */
/**@} end of group UART_INT_EN_Register */
/**
* @ingroup uart_registers
* @defgroup UART_INT_FL UART_INT_FL
* @brief Interrupt Status Flags.
* @{
*/
#define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS 0 /**< INT_FL_RX_FRAME_ERROR Position */
#define MXC_F_UART_INT_FL_RX_FRAME_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) /**< INT_FL_RX_FRAME_ERROR Mask */
#define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS 1 /**< INT_FL_RX_PARITY_ERROR Position */
#define MXC_F_UART_INT_FL_RX_PARITY_ERROR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) /**< INT_FL_RX_PARITY_ERROR Mask */
#define MXC_F_UART_INT_FL_CTS_CHANGE_POS 2 /**< INT_FL_CTS_CHANGE Position */
#define MXC_F_UART_INT_FL_CTS_CHANGE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_CHANGE_POS)) /**< INT_FL_CTS_CHANGE Mask */
#define MXC_F_UART_INT_FL_RX_OVERRUN_POS 3 /**< INT_FL_RX_OVERRUN Position */
#define MXC_F_UART_INT_FL_RX_OVERRUN ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OVERRUN_POS)) /**< INT_FL_RX_OVERRUN Mask */
#define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS 4 /**< INT_FL_RX_FIFO_THRESH Position */
#define MXC_F_UART_INT_FL_RX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) /**< INT_FL_RX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS 5 /**< INT_FL_TX_FIFO_ALMOST_EMPTY Position */
#define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) /**< INT_FL_TX_FIFO_ALMOST_EMPTY Mask */
#define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS 6 /**< INT_FL_TX_FIFO_THRESH Position */
#define MXC_F_UART_INT_FL_TX_FIFO_THRESH ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) /**< INT_FL_TX_FIFO_THRESH Mask */
#define MXC_F_UART_INT_FL_BREAK_POS 7 /**< INT_FL_BREAK Position */
#define MXC_F_UART_INT_FL_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_BREAK_POS)) /**< INT_FL_BREAK Mask */
#define MXC_F_UART_INT_FL_RX_TIMEOUT_POS 8 /**< INT_FL_RX_TIMEOUT Position */
#define MXC_F_UART_INT_FL_RX_TIMEOUT ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) /**< INT_FL_RX_TIMEOUT Mask */
#define MXC_F_UART_INT_FL_LAST_BREAK_POS 9 /**< INT_FL_LAST_BREAK Position */
#define MXC_F_UART_INT_FL_LAST_BREAK ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_LAST_BREAK_POS)) /**< INT_FL_LAST_BREAK Mask */
/**@} end of group UART_INT_FL_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD0 UART_BAUD0
* @brief Baud rate register. Integer portion.
* @{
*/
#define MXC_F_UART_BAUD0_IBAUD_POS 0 /**< BAUD0_IBAUD Position */
#define MXC_F_UART_BAUD0_IBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD0_IBAUD_POS)) /**< BAUD0_IBAUD Mask */
#define MXC_F_UART_BAUD0_FACTOR_POS 16 /**< BAUD0_FACTOR Position */
#define MXC_F_UART_BAUD0_FACTOR ((uint32_t)(0x3UL << MXC_F_UART_BAUD0_FACTOR_POS)) /**< BAUD0_FACTOR Mask */
#define MXC_V_UART_BAUD0_FACTOR_128 ((uint32_t)0x0UL) /**< BAUD0_FACTOR_128 Value */
#define MXC_S_UART_BAUD0_FACTOR_128 (MXC_V_UART_BAUD0_FACTOR_128 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_128 Setting */
#define MXC_V_UART_BAUD0_FACTOR_64 ((uint32_t)0x1UL) /**< BAUD0_FACTOR_64 Value */
#define MXC_S_UART_BAUD0_FACTOR_64 (MXC_V_UART_BAUD0_FACTOR_64 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_64 Setting */
#define MXC_V_UART_BAUD0_FACTOR_32 ((uint32_t)0x2UL) /**< BAUD0_FACTOR_32 Value */
#define MXC_S_UART_BAUD0_FACTOR_32 (MXC_V_UART_BAUD0_FACTOR_32 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_32 Setting */
#define MXC_V_UART_BAUD0_FACTOR_16 ((uint32_t)0x3UL) /**< BAUD0_FACTOR_16 Value */
#define MXC_S_UART_BAUD0_FACTOR_16 (MXC_V_UART_BAUD0_FACTOR_16 << MXC_F_UART_BAUD0_FACTOR_POS) /**< BAUD0_FACTOR_16 Setting */
/**@} end of group UART_BAUD0_Register */
/**
* @ingroup uart_registers
* @defgroup UART_BAUD1 UART_BAUD1
* @brief Baud rate register. Decimal Setting.
* @{
*/
#define MXC_F_UART_BAUD1_DBAUD_POS 0 /**< BAUD1_DBAUD Position */
#define MXC_F_UART_BAUD1_DBAUD ((uint32_t)(0xFFFUL << MXC_F_UART_BAUD1_DBAUD_POS)) /**< BAUD1_DBAUD Mask */
/**@} end of group UART_BAUD1_Register */
/**
* @ingroup uart_registers
* @defgroup UART_FIFO UART_FIFO
* @brief FIFO Data buffer.
* @{
*/
#define MXC_F_UART_FIFO_FIFO_POS 0 /**< FIFO_FIFO Position */
#define MXC_F_UART_FIFO_FIFO ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_FIFO_POS)) /**< FIFO_FIFO Mask */
/**@} end of group UART_FIFO_Register */
/**
* @ingroup uart_registers
* @defgroup UART_DMA UART_DMA
* @brief DMA Configuration.
* @{
*/
#define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
#define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
#define MXC_V_UART_DMA_TDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_TDMA_EN_DIS Value */
#define MXC_S_UART_DMA_TDMA_EN_DIS (MXC_V_UART_DMA_TDMA_EN_DIS << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_DIS Setting */
#define MXC_V_UART_DMA_TDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_TDMA_EN_EN Value */
#define MXC_S_UART_DMA_TDMA_EN_EN (MXC_V_UART_DMA_TDMA_EN_EN << MXC_F_UART_DMA_TDMA_EN_POS) /**< DMA_TDMA_EN_EN Setting */
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
#define MXC_V_UART_DMA_RXDMA_EN_DIS ((uint32_t)0x0UL) /**< DMA_RXDMA_EN_DIS Value */
#define MXC_S_UART_DMA_RXDMA_EN_DIS (MXC_V_UART_DMA_RXDMA_EN_DIS << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_DIS Setting */
#define MXC_V_UART_DMA_RXDMA_EN_EN ((uint32_t)0x1UL) /**< DMA_RXDMA_EN_EN Value */
#define MXC_S_UART_DMA_RXDMA_EN_EN (MXC_V_UART_DMA_RXDMA_EN_EN << MXC_F_UART_DMA_RXDMA_EN_POS) /**< DMA_RXDMA_EN_EN Setting */
#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
#define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */
#define MXC_F_UART_DMA_RXDMA_LEVEL_POS 16 /**< DMA_RXDMA_LEVEL Position */
#define MXC_F_UART_DMA_RXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_RXDMA_LEVEL_POS)) /**< DMA_RXDMA_LEVEL Mask */
/**@} end of group UART_DMA_Register */
/**
* @ingroup uart_registers
* @defgroup UART_TX_FIFO UART_TX_FIFO
* @brief Transmit FIFO Status register.
* @{
*/
#define MXC_F_UART_TX_FIFO_DATA_POS 0 /**< TX_FIFO_DATA Position */
#define MXC_F_UART_TX_FIFO_DATA ((uint32_t)(0x7FUL << MXC_F_UART_TX_FIFO_DATA_POS)) /**< TX_FIFO_DATA Mask */
/**@} end of group UART_TX_FIFO_Register */
#ifdef __cplusplus
}
#endif
#endif /* _UART_REGS_H_ */

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/**
* @file wdt_regs.h
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
*/
/* ****************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
*
*************************************************************************** */
#ifndef _WDT_REGS_H_
#define _WDT_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined (__ICCARM__)
#pragma system_include
#endif
#if defined (__CC_ARM)
#pragma anon_unions
#endif
/// @cond
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/// @endcond
/* **** Definitions **** */
/**
* @ingroup wdt
* @defgroup wdt_registers WDT_Registers
* @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module.
* @details Watchdog Timer 0
*/
/**
* @ingroup wdt_registers
* Structure type to access the WDT Registers.
*/
typedef struct {
__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> WDT CTRL Register */
__O uint32_t rst; /**< <tt>\b 0x04:</tt> WDT RST Register */
} mxc_wdt_regs_t;
/* Register offsets for module WDT */
/**
* @ingroup wdt_registers
* @defgroup WDT_Register_Offsets Register Offsets
* @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address.
* @{
*/
#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: <tt> 0x0000</tt> */
#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: <tt> 0x0004</tt> */
/**@} end of group wdt_registers */
/**
* @ingroup wdt_registers
* @defgroup WDT_CTRL WDT_CTRL
* @brief Watchdog Timer Control Register.
* @{
*/
#define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< CTRL_INT_PERIOD Position */
#define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< CTRL_INT_PERIOD Mask */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_INT_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_INT_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_INT_PERIOD_POS) /**< CTRL_INT_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< CTRL_RST_PERIOD Position */
#define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< CTRL_RST_PERIOD Mask */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_PERIOD_WDT2POW31 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW31 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW31 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW31 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_PERIOD_WDT2POW30 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW30 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW30 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW30 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_PERIOD_WDT2POW29 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW29 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW29 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW29 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_PERIOD_WDT2POW28 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW28 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW28 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW28 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_PERIOD_WDT2POW27 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW27 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW27 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW27 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_PERIOD_WDT2POW26 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW26 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW26 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW26 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_PERIOD_WDT2POW25 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW25 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW25 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW25 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_PERIOD_WDT2POW24 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW24 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW24 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW24 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_PERIOD_WDT2POW23 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW23 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW23 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW23 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_PERIOD_WDT2POW22 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW22 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW22 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW22 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_PERIOD_WDT2POW21 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW21 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW21 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW21 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_PERIOD_WDT2POW20 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW20 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW20 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW20 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_PERIOD_WDT2POW19 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW19 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW19 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW19 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_PERIOD_WDT2POW18 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW18 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW18 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW18 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_PERIOD_WDT2POW17 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW17 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW17 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW17 Setting */
#define MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_PERIOD_WDT2POW16 Value */
#define MXC_S_WDT_CTRL_RST_PERIOD_WDT2POW16 (MXC_V_WDT_CTRL_RST_PERIOD_WDT2POW16 << MXC_F_WDT_CTRL_RST_PERIOD_POS) /**< CTRL_RST_PERIOD_WDT2POW16 Setting */
#define MXC_F_WDT_CTRL_WDT_EN_POS 8 /**< CTRL_WDT_EN Position */
#define MXC_F_WDT_CTRL_WDT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_EN_POS)) /**< CTRL_WDT_EN Mask */
#define MXC_V_WDT_CTRL_WDT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_WDT_EN_DIS Value */
#define MXC_S_WDT_CTRL_WDT_EN_DIS (MXC_V_WDT_CTRL_WDT_EN_DIS << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_DIS Setting */
#define MXC_V_WDT_CTRL_WDT_EN_EN ((uint32_t)0x1UL) /**< CTRL_WDT_EN_EN Value */
#define MXC_S_WDT_CTRL_WDT_EN_EN (MXC_V_WDT_CTRL_WDT_EN_EN << MXC_F_WDT_CTRL_WDT_EN_POS) /**< CTRL_WDT_EN_EN Setting */
#define MXC_F_WDT_CTRL_INT_FLAG_POS 9 /**< CTRL_INT_FLAG Position */
#define MXC_F_WDT_CTRL_INT_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_FLAG_POS)) /**< CTRL_INT_FLAG Mask */
#define MXC_V_WDT_CTRL_INT_FLAG_INACTIVE ((uint32_t)0x0UL) /**< CTRL_INT_FLAG_INACTIVE Value */
#define MXC_S_WDT_CTRL_INT_FLAG_INACTIVE (MXC_V_WDT_CTRL_INT_FLAG_INACTIVE << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_INACTIVE Setting */
#define MXC_V_WDT_CTRL_INT_FLAG_PENDING ((uint32_t)0x1UL) /**< CTRL_INT_FLAG_PENDING Value */
#define MXC_S_WDT_CTRL_INT_FLAG_PENDING (MXC_V_WDT_CTRL_INT_FLAG_PENDING << MXC_F_WDT_CTRL_INT_FLAG_POS) /**< CTRL_INT_FLAG_PENDING Setting */
#define MXC_F_WDT_CTRL_INT_EN_POS 10 /**< CTRL_INT_EN Position */
#define MXC_F_WDT_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */
#define MXC_V_WDT_CTRL_INT_EN_DIS ((uint32_t)0x0UL) /**< CTRL_INT_EN_DIS Value */
#define MXC_S_WDT_CTRL_INT_EN_DIS (MXC_V_WDT_CTRL_INT_EN_DIS << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_DIS Setting */
#define MXC_V_WDT_CTRL_INT_EN_EN ((uint32_t)0x1UL) /**< CTRL_INT_EN_EN Value */
#define MXC_S_WDT_CTRL_INT_EN_EN (MXC_V_WDT_CTRL_INT_EN_EN << MXC_F_WDT_CTRL_INT_EN_POS) /**< CTRL_INT_EN_EN Setting */
#define MXC_F_WDT_CTRL_RST_EN_POS 11 /**< CTRL_RST_EN Position */
#define MXC_F_WDT_CTRL_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EN_POS)) /**< CTRL_RST_EN Mask */
#define MXC_V_WDT_CTRL_RST_EN_DIS ((uint32_t)0x0UL) /**< CTRL_RST_EN_DIS Value */
#define MXC_S_WDT_CTRL_RST_EN_DIS (MXC_V_WDT_CTRL_RST_EN_DIS << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_DIS Setting */
#define MXC_V_WDT_CTRL_RST_EN_EN ((uint32_t)0x1UL) /**< CTRL_RST_EN_EN Value */
#define MXC_S_WDT_CTRL_RST_EN_EN (MXC_V_WDT_CTRL_RST_EN_EN << MXC_F_WDT_CTRL_RST_EN_POS) /**< CTRL_RST_EN_EN Setting */
#define MXC_F_WDT_CTRL_RST_FLAG_POS 31 /**< CTRL_RST_FLAG Position */
#define MXC_F_WDT_CTRL_RST_FLAG ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_FLAG_POS)) /**< CTRL_RST_FLAG Mask */
#define MXC_V_WDT_CTRL_RST_FLAG_NOEVENT ((uint32_t)0x0UL) /**< CTRL_RST_FLAG_NOEVENT Value */
#define MXC_S_WDT_CTRL_RST_FLAG_NOEVENT (MXC_V_WDT_CTRL_RST_FLAG_NOEVENT << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_NOEVENT Setting */
#define MXC_V_WDT_CTRL_RST_FLAG_OCCURRED ((uint32_t)0x1UL) /**< CTRL_RST_FLAG_OCCURRED Value */
#define MXC_S_WDT_CTRL_RST_FLAG_OCCURRED (MXC_V_WDT_CTRL_RST_FLAG_OCCURRED << MXC_F_WDT_CTRL_RST_FLAG_POS) /**< CTRL_RST_FLAG_OCCURRED Setting */
/**@} end of group WDT_CTRL_Register */
/**
* @ingroup wdt_registers
* @defgroup WDT_RST WDT_RST
* @brief Watchdog Timer Reset Register.
* @{
*/
#define MXC_F_WDT_RST_WDT_RST_POS 0 /**< RST_WDT_RST Position */
#define MXC_F_WDT_RST_WDT_RST ((uint32_t)(0xFFUL << MXC_F_WDT_RST_WDT_RST_POS)) /**< RST_WDT_RST Mask */
#define MXC_V_WDT_RST_WDT_RST_SEQ0 ((uint32_t)0xA5UL) /**< RST_WDT_RST_SEQ0 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ0 (MXC_V_WDT_RST_WDT_RST_SEQ0 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ0 Setting */
#define MXC_V_WDT_RST_WDT_RST_SEQ1 ((uint32_t)0x5AUL) /**< RST_WDT_RST_SEQ1 Value */
#define MXC_S_WDT_RST_WDT_RST_SEQ1 (MXC_V_WDT_RST_WDT_RST_SEQ1 << MXC_F_WDT_RST_WDT_RST_POS) /**< RST_WDT_RST_SEQ1 Setting */
/**@} end of group WDT_RST_Register */
#ifdef __cplusplus
}
#endif
#endif /* _WDT_REGS_H_ */

0
bsp/maxim/libraries/CMSIS/startup_max32660.s → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/ARM/startup_max32660.s
View File

391
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/gcc.mk Normal file
View File

@ -0,0 +1,391 @@
################################################################################
# Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included
# in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
# OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
# OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
# OTHER DEALINGS IN THE SOFTWARE.
#
# Except as contained in this notice, the name of Maxim Integrated
# Products, Inc. shall not be used except as stated in the Maxim Integrated
# Products, Inc. Branding Policy.
#
# The mere transfer of this software does not imply any licenses
# of trade secrets, proprietary technology, copyrights, patents,
# trademarks, maskwork rights, or any other form of intellectual
# property whatsoever. Maxim Integrated Products, Inc. retains all
# ownership rights.
#
# $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
# $Revision: 40072 $
#
###############################################################################
# The build directory
ifeq "$(BUILD_DIR)" ""
BUILD_DIR=$(CURDIR)/build
endif
# Create output object file names
SRCS_NOPATH := $(foreach NAME,$(SRCS),$(basename $(notdir $(NAME))).c)
OBJS_NOPATH := $(SRCS_NOPATH:.c=.o)
OBJS := $(OBJS_NOPATH:%.o=$(BUILD_DIR)/%.o)
################################################################################
# Goals
# The default goal, which causes the example to be built.
.DEFAULT_GOAL :=
.PHONY: all
all: mkbuildir
all: ${BUILD_DIR}/${PROJECT}.elf
# Goal to build for release without debug
.PHONY: release
release: mkbuildir
release: ${BUILD_DIR}/${PROJECT}.elf
release: ${BUILD_DIR}/${PROJECT}.srec
release: ${BUILD_DIR}/${PROJECT}.hex
release: ${BUILD_DIR}/${PROJECT}.bin
release: ${BUILD_DIR}/${PROJECT}.dasm
# The goal to build as a library
.PHONY: lib
lib: mkbuildir
lib: ${BUILD_DIR}/${PROJECT}.a
# The goal to create the target directory.
.PHONY: mkbuildir
mkbuildir:
@mkdir -p ${BUILD_DIR}
# The goal to clean out all the build products.
.PHONY: clean
clean:
@rm -rf ${BUILD_DIR} ${wildcard *~}
${BUILD_DIR}/${PROJECT}.elf: ${LIBS} ${OBJS} ${LINKERFILE}
${BUILD_DIR}/${PROJECT}.a: ${OBJS}
# Create a goal to exercise the library build dependencies
.PHONY: FORCE
FORCE:
# Include the automatically generated dependency files.
ifneq (${MAKECMDGOALS},clean)
-include ${wildcard ${BUILD_DIR}/*.d} __dummy__
endif
################################################################################
# Get the operating system name. If this is Cygwin, the .d files will be
# munged to convert c: into /cygdrive/c so that "make" will be happy with the
# auto-generated dependencies. Also if this is Cygwin, file paths for ARM GCC
# will be converted from /cygdrive/c to C:.
################################################################################
ifneq ($(findstring CYGWIN, ${shell uname -s}), )
CYGWIN=True
endif
# Get the prefix for the tools to use.
ifeq "$(TOOL_DIR)" ""
PREFIX=arm-none-eabi
else
PREFIX=$(TOOL_DIR)/arm-none-eabi
endif
# The command for calling the compiler.
CC=${PREFIX}-gcc
CXX=${PREFIX}-g++
# Discover if we are using GCC > 4.8.0
GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \> 4)
ifeq "$(GCCVERSIONGTEQ4)" "0"
GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f1 -d.` \>= 4)
ifeq "$(GCCVERSIONGTEQ4)" "1"
GCCVERSIONGTEQ4 := $(shell expr `gcc -dumpversion | cut -f2 -d.` \>= 8)
endif
endif
# The flags passed to the assembler.
AFLAGS=-mthumb \
-mcpu=cortex-m4 \
-MD
ifneq "$(HEAP_SIZE)" ""
AFLAGS+=-D__HEAP_SIZE=$(HEAP_SIZE)
endif
ifneq "$(STACK_SIZE)" ""
AFLAGS+=-D__STACK_SIZE=$(STACK_SIZE)
endif
AFLAGS+=$(PROJ_AFLAGS)
ifeq "$(MXC_OPTIMIZE_CFLAGS)" ""
# Default is optimize for size
MXC_OPTIMIZE_CFLAGS = -Os
endif
# The flags passed to the compiler.
# fno-isolate-erroneous-paths-dereference disables the check for pointers with the value of 0
# add this below when arm-none-eabi-gcc version is past 4.8 -fno-isolate-erroneous-paths-dereference \
CFLAGS=-mthumb \
-mcpu=cortex-m4 \
-mfloat-abi=hard \
-mfpu=fpv4-sp-d16 \
-Wa,-mimplicit-it=thumb \
$(MXC_OPTIMIZE_CFLAGS) \
-fsingle-precision-constant \
-ffunction-sections \
-fdata-sections \
-MD \
-Wall \
-Wdouble-promotion \
-Wno-format \
-c
# The flags passed to the C++ compiler.
CXXFLAGS= \
-mthumb \
-mcpu=cortex-m4 \
-mfloat-abi=hard \
-mfpu=fpv4-sp-d16 \
-Wa,-mimplicit-it=thumb \
$(MXC_OPTIMIZE_CFLAGS) \
-ffunction-sections \
-fdata-sections \
-MD \
-Wall \
-Wno-format \
-fno-rtti \
-fno-exceptions \
-std=c++11 \
-c
# On GCC version > 4.8.0 use the -fno-isolate-erroneous-paths-dereference flag
ifeq "$(GCCVERSIONGTEQ4)" "1"
CFLAGS += -fno-isolate-erroneous-paths-dereference
endif
ifneq "$(TARGET)" ""
# Turn TARGET into a number for use within source files (e.g. MAX32650 -> 32650)
CFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]')
CXXFLAGS+=-DTARGET=$(shell echo $(TARGET) | tr -d '[:alpha:]')
endif
ifneq "$(TARGET_REV)" ""
CFLAGS+=-DTARGET_REV=$(TARGET_REV)
CXXFLAGS+=-DTARGET_REV=$(TARGET_REV)
endif
# Exclude debug for 'release' builds
ifneq (${MAKECMDGOALS},release)
ifneq (${DEBUG},0)
CFLAGS+=-g3 -ggdb -DDEBUG
endif
endif
CFLAGS+=$(PROJ_CFLAGS)
CXXFLAGS+=$(PROJ_CFLAGS)
# The command for calling the library archiver.
AR=${PREFIX}-ar
# The command for calling the linker.
LD=${PREFIX}-gcc
# The flags passed to the linker.
LDFLAGS=-mthumb \
-mcpu=cortex-m4 \
-mfloat-abi=hard \
-mfpu=fpv4-sp-d16 \
-Xlinker --gc-sections \
-Xlinker -Map -Xlinker ${BUILD_DIR}/$(PROJECT).map
LDFLAGS+=$(PROJ_LDFLAGS)
# Include math library
STD_LIBS=-lc -lm
# Determine if any C++ files are in the project sources, and add libraries as appropriate
ifneq "$(findstring cpp, ${SRCS})" ""
STD_LIBS+=-lsupc++ -lstdc++
endif
# Finally, resolve any newlib system calls with libnosys
STD_LIBS+=-lnosys
PROJ_LIBS:=$(addprefix -l, $(PROJ_LIBS))
# The command for extracting images from the linked executables.
OBJCOPY=${PREFIX}-objcopy
OBJDUMP=${PREFIX}-objdump
ifeq "$(CYGWIN)" "True"
fixpath=$(shell echo $(1) | sed -r 's/\/cygdrive\/([A-Na-n])/\U\1:/g' )
else
fixpath=$(1)
endif
# Add the include file paths to AFLAGS and CFLAGS.
AFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
CFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
CXXFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
LDFLAGS+=${patsubst %,-L%,$(call fixpath,$(LIBPATH))}
################################################################################
# The rule for building the object file from each C source file.
${BUILD_DIR}/%.o: %.c
@if [ 'x${ECLIPSE}' != x ]; \
then \
echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \
elif [ 'x${VERBOSE}' != x ]; \
then \
echo ${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}); \
else \
echo " CC ${<}"; \
fi
@${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<})
ifeq "$(CYGWIN)" "True"
@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
endif
# The rule to build an object file from a C++ source file
${BUILD_DIR}/%.o: %.cpp
@if [ 'x${ECLIPSE}' != x ]; \
then \
echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}) | sed 's/-I\/\(.\)\//-I\1:\//g' ; \
elif [ 'x${VERBOSE}' != x ]; \
then \
echo ${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<}); \
else \
echo " CXX ${<}"; \
fi
@${CXX} ${CXXFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<})
ifeq "$(CYGWIN)" "True"
@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
endif
# The rule for building the object file from each assembly source file.
${BUILD_DIR}/%.o: %.S
@if [ 'x${VERBOSE}' = x ]; \
then \
echo " AS ${<}"; \
else \
echo ${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<}); \
fi
@${CC} ${AFLAGS} -o $(call fixpath,${@}) -c $(call fixpath,${<})
ifeq "$(CYGWIN)" "True"
@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
endif
# The rule for creating an object library.
${BUILD_DIR}/%.a:
@if [ 'x${VERBOSE}' = x ]; \
then \
echo " AR ${@}"; \
else \
echo ${AR} -cr $(call fixpath,${@}) $(call fixpath,${^}); \
fi
@${AR} -cr $(call fixpath,${@}) $(call fixpath,${^})
# The rule for linking the application.
${BUILD_DIR}/%.elf:
@if [ 'x${VERBOSE}' = x ]; \
then \
echo " LD ${@} ${LNK_SCP}"; \
else \
echo ${LD} -T $(call fixpath,${LINKERFILE}) \
--entry ${ENTRY} \
$(call fixpath,${LDFLAGS}) \
-o $(call fixpath,${@}) \
$(call fixpath,$(filter %.o, ${^})) \
-Xlinker --start-group \
$(call fixpath,$(filter %.a, ${^})) \
${PROJ_LIBS} \
${STD_LIBS} \
-Xlinker --end-group; \
fi; \
${LD} -T $(call fixpath,${LINKERFILE}) \
--entry ${ENTRY} \
$(call fixpath,${LDFLAGS}) \
-o $(call fixpath,${@}) \
$(call fixpath,$(filter %.o, ${^})) \
-Xlinker --start-group \
$(call fixpath,$(filter %.a, ${^})) \
${PROJ_LIBS} \
${STD_LIBS} \
-Xlinker --end-group
# Create S-Record output file
%.srec: %.elf
@if [ 'x${VERBOSE}' = x ]; \
then \
echo "Creating ${@}"; \
else \
echo ${OBJCOPY} -O srec $(call fixpath,${<}) $(call fixpath,${@}); \
fi
@$(OBJCOPY) -O srec $< $(call fixpath,${@})
# Create Intex Hex output file
%.hex: %.elf
@if [ 'x${VERBOSE}' = x ]; \
then \
echo "Creating ${@}"; \
else \
echo ${OBJCOPY} -O ihex $(call fixpath,${<}) $(call fixpath,${@}); \
fi
@$(OBJCOPY) -O ihex $< $(call fixpath,${@})
# Create binary output file
%.bin: %.elf
@if [ 'x${VERBOSE}' = x ]; \
then \
echo "Creating ${@}"; \
else \
echo ${OBJCOPY} -O binary $(call fixpath,${<}) $(call fixpath,${@}); \
fi
@$(OBJCOPY) -O binary $< $(call fixpath,${@})
# Create disassembly file
%.dasm: %.elf
@if [ 'x${VERBOSE}' = x ]; \
then \
echo "Creating ${@}"; \
else \
echo $(OBJDUMP) -S $(call fixpath,${<}) $(call fixpath,${@}); \
fi
@$(OBJDUMP) -S $< > $(call fixpath,${@})
################################################################################
.PHONY: debug
debug:
@echo CYGWIN = ${CYGWIN}
@echo
@echo BUILD_DIR = ${BUILD_DIR}
@echo
@echo SRCS = ${SRCS}
@echo
@echo SRCS_NOPATH = ${SRCS_NOPATH}
@echo
@echo OBJS_NOPATH = ${OBJS_NOPATH}
@echo
@echo OBJS = ${OBJS}
@echo
@echo LIBS = ${LIBS}
@echo
@echo VPATH = ${VPATH}
@echo
@echo IPATH = ${IPATH}

131
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.ld Normal file
View File

@ -0,0 +1,131 @@
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
MEMORY {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 256K
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
}
SECTIONS {
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*) /* program code */
*(.rodata*) /* read-only data: "const" */
KEEP(*(.init))
KEEP(*(.fini))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > FLASH
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > FLASH
.data :
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
} > SRAM AT>FLASH
__load_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM
.heap (COPY):
{
. = ALIGN(4);
*(.heap*)
__HeapLimit = ABSOLUTE(__StackLimit);
} > SRAM
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}

68
bsp/maxim/libraries/MAX32660PeriphDriver/periphdriver.mk → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660.mk
View File

@ -34,44 +34,50 @@
#
###############################################################################
################################################################################
# This file can be included in a project makefile to build the library for the
# project.
################################################################################
ifeq "$(PERIPH_DRIVER_DIR)" ""
$(error "PERIPH_DRIVER_DIR must be specified")
ifeq "$(CMSIS_ROOT)" ""
$(error CMSIS_ROOT must be specified)
endif
# Specify the build directory if not defined by the project
# The build directory
ifeq "$(BUILD_DIR)" ""
PERIPH_DRIVER_BUILD_DIR=$(CURDIR)/build/PeriphDriver
else
PERIPH_DRIVER_BUILD_DIR=$(BUILD_DIR)/PeriphDriver
BUILD_DIR=$(CURDIR)/build
endif
# Export paths needed by the peripheral driver makefile. Since the makefile to
# build the library will execute in a different directory, paths must be
# specified absolutely
PERIPH_DRIVER_BUILD_DIR := ${abspath ${PERIPH_DRIVER_BUILD_DIR}}
export TOOL_DIR := ${abspath ${TOOL_DIR}}
export CMSIS_ROOT := ${abspath ${CMSIS_ROOT}}
ifeq "$(STARTUPFILE)" ""
STARTUPFILE=startup_max32660.S
endif
# Export other variables needed by the peripheral driver makefile
export TARGET
export COMPILER
export TARGET_MAKEFILE
export PROJ_CFLAGS
export PROJ_LDFLAGS
export MXC_OPTIMIZE_CFLAGS
ifeq "$(LINKERFILE)" ""
LINKERFILE=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/max32660.ld
endif
# Add to library list
LIBS += ${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a
ifeq "$(ENTRY)" ""
ENTRY=Reset_Handler
endif
# Add to include directory list
IPATH += ${PERIPH_DRIVER_DIR}/Include
# Default TARGET_REVISION
# "A1" in ASCII
ifeq "$(TARGET_REV)" ""
TARGET_REV=0x4131
endif
# Add rule to build the Driver Library
${PERIPH_DRIVER_BUILD_DIR}/PeriphDriver.a: FORCE
$(MAKE) -C ${PERIPH_DRIVER_DIR} lib BUILD_DIR=${PERIPH_DRIVER_BUILD_DIR}
# Add target specific CMSIS source files
ifneq (${MAKECMDGOALS},lib)
SRCS += ${STARTUPFILE}
SRCS += heap.c
SRCS += system_max32660.c
endif
# Add target specific CMSIS source directories
VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC
VPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source
# Add target specific CMSIS include directories
IPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Include
IPATH+=$(CMSIS_ROOT)/Include
# Add directory with linker include file
LIBPATH+=$(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC
# Include the rules and goals for building
include $(CMSIS_ROOT)/Device/Maxim/MAX32660/Source/GCC/gcc.mk

131
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator.ld Normal file
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@ -0,0 +1,131 @@
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
MEMORY {
FLASH (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
}
SECTIONS {
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*) /* program code */
*(.rodata*) /* read-only data: "const" */
KEEP(*(.init))
KEEP(*(.fini))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > FLASH
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > FLASH
.data :
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
} > SRAM AT>FLASH
__load_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM
.heap (COPY):
{
. = ALIGN(4);
*(.heap*)
__HeapLimit = ABSOLUTE(__StackLimit);
} > SRAM
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}

132
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_emulator_ram.ld Normal file
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@ -0,0 +1,132 @@
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
MEMORY {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
}
SECTIONS {
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*) /* program code */
*(.rodata*) /* read-only data: "const" */
KEEP(*(.init))
KEEP(*(.fini))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > SRAM
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > SRAM
.data :
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
*(.flashprog*) /* Flash program */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
} > SRAM AT>SRAM
__load_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM
.heap (COPY):
{
. = ALIGN(4);
*(.heap*)
__HeapLimit = ABSOLUTE(__StackLimit);
} > SRAM
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}

132
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/GCC/max32660_ram.ld Normal file
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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
MEMORY {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
}
SECTIONS {
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*) /* program code */
*(.rodata*) /* read-only data: "const" */
*(.flashprog*) /* Flash program */
KEEP(*(.init))
KEEP(*(.fini))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > SRAM
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > SRAM
.data :
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
} > SRAM AT>SRAM
__load_data = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM
.heap (COPY):
{
. = ALIGN(4);
*(.heap*)
__HeapLimit = ABSOLUTE(__StackLimit);
} > SRAM
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}

271
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@ -0,0 +1,271 @@
/*******************************************************************************
* Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
MEMORY {
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256kB "FLASH" */
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000
}
OUTPUT_FORMAT ("elf32-littlearm")
ENTRY(Reset_Handler)
EXTERN(__start_c main __stack __section_end_heap)
SECTIONS {
/* SRAM start/stop addresses used during startup (PreInit(), preinit.S) to initialize ECCEN register
* and initial Error correcting state. (SEC-DED) */
__sram_ecc_initialize_start = ORIGIN(SRAM);
__sram_ecc_initialize_stop = (ORIGIN(SRAM) + LENGTH(SRAM));
.text : ALIGN(0x100)
{
_text = .;
__section_load_nvic = .;
KEEP(*(.isr_vector))
__section_load_nvic_end = .;
KEEP(*startup*(.text))
*(.text*) /* program code */
*(.flashprog*) /* Flash program */
KEEP(*(.init))
KEEP(*(.fini))
*(.rodata*) /* read-only data: "const" */
KEEP(*(.iota_rom_params))
/* C++ Exception handling */
KEEP(*(.eh_frame*))
_etext = .;
} > FLASH
__section_nvic_size = __section_load_nvic_end - __section_load_nvic;
__section_nvic_start = ORIGIN(SRAM);
__section_nvic_end = __section_nvic_start + __section_nvic_size;
/* it's used for C++ exception handling */
/* we need to keep this to avoid overlapping */
.ARM.exidx :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > FLASH
.data __section_nvic_end : ALIGN(0x10)
{
_data = ALIGN(., 4);
*(.data*) /*read-write initialized data: initialized global variable*/
*(.spix_config*) /* SPIX configuration functions need to be run from SRAM */
/* These array sections are used by __libc_init_array to call static C++ constructors */
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
_edata = ALIGN(., 4);
__section_end_data = .;
} > SRAM AT>FLASH
__load_data = LOADADDR(.data);
/** Info block/OTP reserved area */
__virtual_otp_size = 0x400;
__virtual_end_otp = ORIGIN(FLASH) + LENGTH(FLASH);
__virtual_start_otp = __virtual_end_otp - __virtual_otp_size;
/** Free area to program application */
__virtual_start_iota = ALIGN(__load_data,0x10);
__virtual_end_iota = __virtual_start_otp;
__virtual_iota_size = __virtual_end_iota - __virtual_start_iota;
/** Work buffer */
.iota_work __virtual_start_iota :
{
. += __virtual_iota_size;
}
/** OTP area */
.iota_otp __virtual_start_otp :
{
. += __virtual_otp_size;
}
.bss :
{
. = ALIGN(4);
_bss = .;
*(.bss*) /*read-write zero initialized data: uninitialzed global variable*/
*(COMMON)
_ebss = ALIGN(., 4);
} > SRAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
/* Stack and Heap */
.heap (NOLOAD) : ALIGN(0x80)
{
__section_start_heap = .;
*(.heap*)
__section_end_heap = .;
} > SRAM
__section_start_heap_va = __section_start_heap;
__section_end_heap_va = __section_start_heap_va + SIZEOF(.heap);
.stack __section_end_heap : ALIGN(0x80)
{
__section_start_stack = .;
*(.stack*)
_stack = .;
__section_end_stack = .;
} > SRAM
__stack_va = __stack;
PROVIDE(__stack = _stack);
/* ======================================================================== */
/** RAM for STP and SCP **/
__section_protocol_ram_end = (ORIGIN(SRAM) + LENGTH(SRAM));
__region_end_ram = (ORIGIN(SRAM) + LENGTH(SRAM));
/** Cryptography work buffer */
.iota_work.sh __section_end_stack : ALIGN(0x10)
{
KEEP(*(.iota_work.sh))
} >SRAM=0
__iota_work_sh_start = LOADADDR(.iota_work.sh);
__iota_work_sh_end = LOADADDR(.iota_work.sh) + SIZEOF(.iota_work.sh);
__iota_work_sh_size = SIZEOF(.iota_work.sh);
/** Configuration Management work buffer */
.iota_work.cm __iota_work_sh_end : ALIGN(0x10)
{
KEEP(*(.iota_work.cm))
} >SRAM=0
__iota_work_cm_start = LOADADDR(.iota_work.cm);
__iota_work_cm_end = LOADADDR(.iota_work.cm) + SIZEOF(.iota_work.cm);
__iota_work_cm_size = SIZEOF(.iota_work.cm);
/** RCE Signature check work buffer */
.iota_work.rce __iota_work_cm_end : ALIGN(0x10)
{
KEEP(*(.iota_work.rce))
} >SRAM=0
__iota_work_rce_start = LOADADDR(.iota_work.rce);
__iota_work_rce_end = LOADADDR(.iota_work.rce) + SIZEOF(.iota_work.rce);
__iota_work_rce_size = SIZEOF(.iota_work.rce);
/* ======================================================================== */
/** STP Application, SCP Applet memory areas */
.protocol_ram.stack __iota_work_rce_end : ALIGN(0x10)
{
__section_protocol_start = .;
/** Stack dedicated to STP/SCP application matter if needed */
__section_start_stp_stack = .;
KEEP(*(.protocol_ram.stack))
/* . += __stack_size_stp;*/
__stack_stp = .;
} >SRAM
__section_end_stp_stack = .;
.protocol_ram.bss __section_end_stp_stack : ALIGN(0x10)
{
*stp_*(.bss .bss.* .gnu.linkonce.b.*)
} >SRAM
__section_start_bss_stp = LOADADDR(.protocol_ram.bss);
__section_end_bss_stp = LOADADDR(.protocol_ram.bss) + SIZEOF(.protocol_ram.bss);
__section_bss_stp_size = SIZEOF(.protocol_ram.bss);
.protocol_ram __section_end_bss_stp : ALIGN(0x10)
{
/** Code part */
KEEP(*stp_*(.data .data.* .gnu.linkonce.d.*))
KEEP(*(.protocol_ram))
} >SRAM
__section_protocol_end = ALIGN(0x10);
__scp_applet_area_size = __section_protocol_ram_end - __section_protocol_end;
/** Lasting free internal SRAM space */
.iota_scp_applet __section_protocol_end : ALIGN(0x10)
{
__scp_applet_start = .;
. += __scp_applet_area_size;
__scp_applet_end = .;
} >SRAM
__section_scp_start = LOADADDR(.protocol_ram);
__section_scp_stop = LOADADDR(.iota_scp_applet) + SIZEOF(.iota_scp_applet);
__section_bss_size_stp = __section_end_bss_stp - __section_start_bss_stp;
__section_stp_size = SIZEOF(.protocol_ram.stack) + SIZEOF(.protocol_ram.bss) + SIZEOF(.protocol_ram);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack")
}

314
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/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000C00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Device-specific Interrupts */
.long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */
.long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */
.long RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */
.long RTC_IRQHandler /* 0x13 0x004C 19: RTC */
.long RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */
.long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */
.long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */
.long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */
.long RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */
.long RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */
.long RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */
.long RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */
.long RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */
.long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */
.long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */
.long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */
.long SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */
.long SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */
.long RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */
.long RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */
.long RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */
.long RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */
.long RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */
.long FLC_IRQHandler /* 0x27 0x009C 39: FLC */
.long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */
.long RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */
.long RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */
.long RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */
.long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */
.long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */
.long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */
.long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */
.long RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */
.long RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */
.long RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */
.long RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */
.long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */
.long RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */
.long RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */
.long RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */
.long RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */
.long RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */
.long RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */
.long RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */
.long RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */
.long RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */
.long RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */
.long RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */
.long RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */
.long RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */
.long RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */
.long RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */
.long RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */
.long RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */
.long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =__StackTop
mov sp, r0
/* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */
ldr r0, =PreInit
blx r0
cbnz r0, .SKIPRAMINIT
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __load_data: Where data sections are saved.
* _data /_edata: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__load_data
ldr r2, =_data
ldr r3, =_edata
#if 0
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
.LC0:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .LC0
#else
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#endif
/*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* _bss : start of BSS section. Must align to 4
* _ebss : end of BSS section. Must align to 4
*/
ldr r1, =_bss
ldr r2, =_ebss
movs r0, 0
.LC2:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .LC2
.SKIPRAMINIT:
/* Perform system initialization after RAM initialization */
ldr r0, =SystemInit
blx r0
/* This must be called to walk the constructor array for static C++ objects */
/* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */
/* where X is {preinit, init, fini} */
ldr r0, =__libc_init_array
blx r0
/* Transfer control to users main program */
ldr r0, =main
blx r0
.SPIN:
/* spin if main ever returns. */
bl .SPIN
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
/* SysTick_Handler is defined in mxc_delay.c */
def_irq_handler Default_Handler
/* Device-specific Interrupts */
def_irq_handler PF_IRQHandler /* 0x10 0x0040 16: Power Fail */
def_irq_handler WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */
def_irq_handler RSV00_IRQHandler /* 0x12 0x0048 18: RSV00 */
def_irq_handler RTC_IRQHandler /* 0x13 0x004C 19: RTC */
def_irq_handler RSV1_IRQHandler /* 0x14 0x0050 20: RSV1 */
def_irq_handler TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */
def_irq_handler TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */
def_irq_handler TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */
def_irq_handler RSV02_IRQHandler /* 0x18 0x0060 24: RSV02 */
def_irq_handler RSV03_IRQHandler /* 0x19 0x0064 25: RSV03 */
def_irq_handler RSV04_IRQHandler /* 0x1A 0x0068 26: RSV04 */
def_irq_handler RSV05_IRQHandler /* 0x1B 0x006C 27: RSV05 */
def_irq_handler RSV06_IRQHandler /* 0x1C 0x0070 28: RSV06 */
def_irq_handler I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */
def_irq_handler UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */
def_irq_handler UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */
def_irq_handler SPI0_IRQHandler /* 0x20 0x0080 32: SPIY17 */
def_irq_handler SPI1_IRQHandler /* 0x21 0x0084 33: SPIMSS */
def_irq_handler RSV07_IRQHandler /* 0x22 0x0088 34: RSV07 */
def_irq_handler RSV08_IRQHandler /* 0x23 0x008C 35: RSV08 */
def_irq_handler RSV09_IRQHandler /* 0x24 0x0090 36: RSV09 */
def_irq_handler RSV10_IRQHandler /* 0x25 0x0094 37: RSV10 */
def_irq_handler RSV11_IRQHandler /* 0x26 0x0098 38: RSV11 */
def_irq_handler FLC_IRQHandler /* 0x27 0x009C 39: FLC */
def_irq_handler GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */
def_irq_handler RSV12_IRQHandler /* 0x29 0x00A4 41: RSV12 */
def_irq_handler RSV13_IRQHandler /* 0x2A 0x00A8 42: RSV13 */
def_irq_handler RSV14_IRQHandler /* 0x2B 0x00AC 43: RSV14 */
def_irq_handler DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */
def_irq_handler DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */
def_irq_handler DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */
def_irq_handler DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */
def_irq_handler RSV15_IRQHandler /* 0x30 0x00C0 48: RSV15 */
def_irq_handler RSV16_IRQHandler /* 0x31 0x00C4 49: RSV16 */
def_irq_handler RSV17_IRQHandler /* 0x32 0x00C8 50: RSV17 */
def_irq_handler RSV18_IRQHandler /* 0x33 0x00CC 51: RSV18 */
def_irq_handler I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */
def_irq_handler RSV19_IRQHandler /* 0x35 0x00D4 53: RSV19 */
def_irq_handler RSV20_IRQHandler /* 0x36 0x00D8 54: RSV20 */
def_irq_handler RSV21_IRQHandler /* 0x37 0x00DC 55: RSV21 */
def_irq_handler RSV22_IRQHandler /* 0x38 0x00E0 56: RSV22 */
def_irq_handler RSV23_IRQHandler /* 0x39 0x00E4 57: RSV23 */
def_irq_handler RSV24_IRQHandler /* 0x3A 0x00E8 58: RSV24 */
def_irq_handler RSV25_IRQHandler /* 0x3B 0x00EC 59: RSV25 */
def_irq_handler RSV26_IRQHandler /* 0x3C 0x00F0 60: RSV26 */
def_irq_handler RSV27_IRQHandler /* 0x3D 0x00F4 61: RSV27 */
def_irq_handler RSV28_IRQHandler /* 0x3E 0x00F8 62: RSV28 */
def_irq_handler RSV29_IRQHandler /* 0x3F 0x00FC 63: RSV29 */
def_irq_handler RSV30_IRQHandler /* 0x40 0x0100 64: RSV30 */
def_irq_handler RSV31_IRQHandler /* 0x41 0x0104 65: RSV31 */
def_irq_handler RSV32_IRQHandler /* 0x42 0x0108 66: RSV32 */
def_irq_handler RSV33_IRQHandler /* 0x43 0x010C 67: RSV33 */
def_irq_handler RSV34_IRQHandler /* 0x44 0x0110 68: RSV34 */
def_irq_handler RSV35_IRQHandler /* 0x45 0x0114 69: RSV35 */
def_irq_handler GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */
.end

79
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/**************************************************
*
* Part two of the system initialization code, contains C-level
* initialization, thumb-2 only variant.
*
* Copyright 2006 IAR Systems. All rights reserved.
*
* $Revision: 36818 $
*
**************************************************/
; --------------------------------------------------
; Module ?cmain, C-level initialization.
;
SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
SECTION .text:CODE:NOROOT(2)
PUBLIC __cmain
;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
PUBLIC ?main
EXTWEAK __iar_data_init3
EXTWEAK __iar_argc_argv
EXTERN __low_level_init
EXTERN __call_ctors
EXTERN SystemInit
EXTERN main
EXTERN exit
THUMB
__cmain:
?main:
; Initialize segments.
; __segment_init and __low_level_init are assumed to use the same
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
FUNCALL __cmain, __low_level_init
bl __low_level_init
cmp r0,#0
beq ?l1
FUNCALL __cmain, __iar_data_init3
bl __iar_data_init3
?l1:
REQUIRE ?l3
SECTION .text:CODE:NOROOT(2)
PUBLIC _main
PUBLIC _call_main
THUMB
__iar_init$$done: ; Copy initialization is done
?l3:
_call_main:
; Static Initialization is complete. Call the SystemInit function to
; set up the device and system.
FUNCALL __cmain, SystemInit
BL SystemInit
MOVS r0,#0 ; No parameters
FUNCALL __cmain, __iar_argc_argv
BL __iar_argc_argv ; Maybe setup command line
FUNCALL __cmain, main
BL main
_main:
FUNCALL __cmain, exit
BL exit
END

50
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/* *************************************************
*
* This module contains the function `__low_level_init', a function
* that is called before the `main' function of the program. Normally
* low-level initializations - such as setting the prefered interrupt
* level or setting the watchdog - can be performed here.
*
* Note that this function is called before the data segments are
* initialized, this means that this function cannot rely on the
* values of global or static variables.
*
* When this function returns zero, the startup code will inhibit the
* initialization of the data segments. The result is faster startup,
* the drawback is that neither global nor static data will be
* initialized.
*
* Copyright 1999-2004 IAR Systems. All rights reserved.
*
* $Revision: 36818 $
*
************************************************* */
#ifdef __cplusplus
extern "C" {
#endif
extern int PreInit(void);
#pragma language=extended
__interwork int __low_level_init(void);
__interwork int __low_level_init(void)
{
/*====================================*/
/* Initialize hardware. */
/* AND */
/* Choose if segment initialization */
/* should be done or not. */
/* Return: 0 to omit seg_init */
/* 1 to run seg_init */
/*====================================*/
return !PreInit(); // See system_max32660.c
}
#pragma language=default
#ifdef __cplusplus
}
#endif

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;*******************************************************************************
;* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
;*
;* Permission is hereby granted, free of charge, to any person obtaining a
;* copy of this software and associated documentation files (the "Software"),
;* to deal in the Software without restriction, including without limitation
;* the rights to use, copy, modify, merge, publish, distribute, sublicense,
;* and/or sell copies of the Software, and to permit persons to whom the
;* Software is furnished to do so, subject to the following conditions:
;*
;* The above copyright notice and this permission notice shall be included
;* in all copies or substantial portions of the Software.
;*
;* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
;* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
;* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
;* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
;* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
;* OTHER DEALINGS IN THE SOFTWARE.
;*
;* Except as contained in this notice, the name of Maxim Integrated
;* Products, Inc. shall not be used except as stated in the Maxim Integrated
;* Products, Inc. Branding Policy.
;*
;* The mere transfer of this software does not imply any licenses
;* of trade secrets, proprietary technology, copyrights, patents,
;* trademarks, maskwork rights, or any other form of intellectual
;* property whatsoever. Maxim Integrated Products, Inc. retains all
;* ownership rights.
;*
;* Description : MAX32660 device vector table for IAR EWARM toolchain.
;* - Sets the initial SP
;* - Sets the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address, all set as PUBWEAK. User may override any ISR
;* defined as PUBWEAK.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
; EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __isr_vector
PUBLIC __vector_table_modify
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
__isr_vector
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_modify
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; MAX32660 Device-specific Interrupts
DCD PF_IRQHandler ; /* 0x10 0x0040 16: Power Fail */
DCD WDT0_IRQHandler ; /* 0x11 0x0044 17: Watchdog 0 */
DCD RSV00_IRQHandler ; /* 0x12 0x0048 18: RSV00 */
DCD RTC_IRQHandler ; /* 0x13 0x004C 19: RTC */
DCD RSV1_IRQHandler ; /* 0x14 0x0050 20: RSV1 */
DCD TMR0_IRQHandler ; /* 0x15 0x0054 21: Timer 0 */
DCD TMR1_IRQHandler ; /* 0x16 0x0058 22: Timer 1 */
DCD TMR2_IRQHandler ; /* 0x17 0x005C 23: Timer 2 */
DCD RSV02_IRQHandler ; /* 0x18 0x0060 24: RSV02 */
DCD RSV03_IRQHandler ; /* 0x19 0x0064 25: RSV03 */
DCD RSV04_IRQHandler ; /* 0x1A 0x0068 26: RSV04 */
DCD RSV05_IRQHandler ; /* 0x1B 0x006C 27: RSV05 */
DCD RSV06_IRQHandler ; /* 0x1C 0x0070 28: RSV06 */
DCD I2C0_IRQHandler ; /* 0x1D 0x0074 29: I2C0 */
DCD UART0_IRQHandler ; /* 0x1E 0x0078 30: UART 0 */
DCD UART1_IRQHandler ; /* 0x1F 0x007C 31: UART 1 */
DCD SPI0_IRQHandler ; /* 0x20 0x0080 32: SPI0 */
DCD SPI1_IRQHandler ; /* 0x21 0x0084 33: SPI1 */
DCD RSV07_IRQHandler ; /* 0x22 0x0088 34: RSV07 */
DCD RSV08_IRQHandler ; /* 0x23 0x008C 35: RSV08 */
DCD RSV09_IRQHandler ; /* 0x24 0x0090 36: RSV09 */
DCD RSV10_IRQHandler ; /* 0x25 0x0094 37: RSV10 */
DCD RSV11_IRQHandler ; /* 0x26 0x0098 38: RSV11 */
DCD FLC_IRQHandler ; /* 0x27 0x009C 39: FLC */
DCD GPIO0_IRQHandler ; /* 0x28 0x00A0 40: GPIO0 */
DCD RSV12_IRQHandler ; /* 0x29 0x00A4 41: RSV12 */
DCD RSV13_IRQHandler ; /* 0x2A 0x00A8 42: RSV13 */
DCD RSV14_IRQHandler ; /* 0x2B 0x00AC 43: RSV14 */
DCD DMA0_IRQHandler ; /* 0x2C 0x00B0 44: DMA0 */
DCD DMA1_IRQHandler ; /* 0x2D 0x00B4 45: DMA1 */
DCD DMA2_IRQHandler ; /* 0x2E 0x00B8 46: DMA2 */
DCD DMA3_IRQHandler ; /* 0x2F 0x00BC 47: DMA3 */
DCD RSV15_IRQHandler ; /* 0x30 0x00C0 48: RSV15 */
DCD RSV16_IRQHandler ; /* 0x31 0x00C4 49: RSV16 */
DCD RSV17_IRQHandler ; /* 0x32 0x00C8 50: RSV17 */
DCD RSV18_IRQHandler ; /* 0x33 0x00CC 51: RSV18 */
DCD I2C1_IRQHandler ; /* 0x34 0x00D0 52: I2C1 */
DCD RSV19_IRQHandler ; /* 0x35 0x00D4 53: RSV19 */
DCD RSV20_IRQHandler ; /* 0x36 0x00D8 54: RSV20 */
DCD RSV21_IRQHandler ; /* 0x37 0x00DC 55: RSV21 */
DCD RSV22_IRQHandler ; /* 0x38 0x00E0 56: RSV22 */
DCD RSV23_IRQHandler ; /* 0x39 0x00E4 57: RSV23 */
DCD RSV24_IRQHandler ; /* 0x3A 0x00E8 58: RSV24 */
DCD RSV25_IRQHandler ; /* 0x3B 0x00EC 59: RSV25 */
DCD RSV26_IRQHandler ; /* 0x3C 0x00F0 60: RSV26 */
DCD RSV27_IRQHandler ; /* 0x3D 0x00F4 61: RSV27 */
DCD RSV28_IRQHandler ; /* 0x3E 0x00F8 62: RSV28 */
DCD RSV29_IRQHandler ; /* 0x3F 0x00FC 63: RSV29 */
DCD RSV30_IRQHandler ; /* 0x40 0x0100 64: RSV30 */
DCD RSV31_IRQHandler ; /* 0x41 0x0104 65: RSV31 */
DCD RSV32_IRQHandler ; /* 0x42 0x0108 66: RSV32 */
DCD RSV33_IRQHandler ; /* 0x43 0x010C 67: RSV33 */
DCD RSV34_IRQHandler ; /* 0x44 0x0110 68: RSV34 */
DCD RSV35_IRQHandler ; /* 0x45 0x0114 69: RSV35 */
DCD GPIOWAKE_IRQHandler ; /* 0x46 0x0118 70: GPIO Wakeup */
; Continue this pattern when vectors are eventually assigned by hardware
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; IAR: PreInit is called from low_level_init.c
; IAR: SystemInit is called from cmain.s
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
; SysTick Handler is defined in mxc_delay.c
; PUBWEAK SysTick_Handler
; SECTION .text:CODE:REORDER:NOROOT(1)
; SysTick_Handler
; B SysTick_Handler
PUBWEAK PF_IRQHandler ; /* 0x10 0x0040 16: Power Fail */
SECTION .text:CODE:REORDER:NOROOT(1)
PF_IRQHandler
B PF_IRQHandler
PUBWEAK WDT0_IRQHandler ; /* 0x11 0x0044 17: Watchdog 0 */
SECTION .text:CODE:REORDER:NOROOT(1)
WDT0_IRQHandler
B WDT0_IRQHandler
PUBWEAK RSV00_IRQHandler ; /* 0x12 0x0048 18: RSV00 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV00_IRQHandler
B RSV00_IRQHandler
PUBWEAK RTC_IRQHandler ; /* 0x13 0x004C 19: RTC */
SECTION .text:CODE:REORDER:NOROOT(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK RSV1_IRQHandler ; /* 0x14 0x0050 20: RSV1 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV1_IRQHandler
B RSV1_IRQHandler
PUBWEAK TMR0_IRQHandler ; /* 0x15 0x0054 21: Timer 0 */
SECTION .text:CODE:REORDER:NOROOT(1)
TMR0_IRQHandler
B TMR0_IRQHandler
PUBWEAK TMR1_IRQHandler ; /* 0x16 0x0058 22: Timer 1 */
SECTION .text:CODE:REORDER:NOROOT(1)
TMR1_IRQHandler
B TMR1_IRQHandler
PUBWEAK TMR2_IRQHandler ; /* 0x17 0x005C 23: Timer 2 */
SECTION .text:CODE:REORDER:NOROOT(1)
TMR2_IRQHandler
B TMR2_IRQHandler
PUBWEAK RSV02_IRQHandler ; /* 0x18 0x0060 24: RSV02 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV02_IRQHandler
B RSV02_IRQHandler
PUBWEAK RSV03_IRQHandler ; /* 0x19 0x0064 25: RSV03 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV03_IRQHandler
B RSV03_IRQHandler
PUBWEAK RSV04_IRQHandler ; /* 0x1A 0x0068 26: RSV04 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV04_IRQHandler
B RSV04_IRQHandler
PUBWEAK RSV05_IRQHandler ; /* 0x1B 0x006C 27: RSV05 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV05_IRQHandler
B RSV05_IRQHandler
PUBWEAK RSV06_IRQHandler ; /* 0x1C 0x0070 28: RSV06 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV06_IRQHandler
B RSV06_IRQHandler
PUBWEAK I2C0_IRQHandler ; /* 0x1D 0x0074 29: I2C0 */
SECTION .text:CODE:REORDER:NOROOT(1)
I2C0_IRQHandler
B I2C0_IRQHandler
PUBWEAK UART0_IRQHandler ; /* 0x1E 0x0078 30: UART 0 */
SECTION .text:CODE:REORDER:NOROOT(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK UART1_IRQHandler ; /* 0x1F 0x007C 31: UART 1 */
SECTION .text:CODE:REORDER:NOROOT(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK SPI0_IRQHandler ; /* 0x20 0x0080 32: SPI0 */
SECTION .text:CODE:REORDER:NOROOT(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler ; /* 0x21 0x0084 33: SPI1 */
SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK RSV07_IRQHandler ; /* 0x22 0x0088 34: RSV07 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV07_IRQHandler
B RSV07_IRQHandler
PUBWEAK RSV08_IRQHandler ; /* 0x23 0x008C 35: RSV08 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV08_IRQHandler
B RSV08_IRQHandler
PUBWEAK RSV09_IRQHandler ; /* 0x24 0x0090 36: RSV09 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV09_IRQHandler
B RSV09_IRQHandler
PUBWEAK RSV10_IRQHandler ; /* 0x25 0x0094 37: RSV10 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV10_IRQHandler
B RSV10_IRQHandler
PUBWEAK RSV11_IRQHandler ; /* 0x26 0x0098 38: RSV11 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV11_IRQHandler
B RSV11_IRQHandler
PUBWEAK FLC_IRQHandler ; /* 0x27 0x009C 39: FLC */
SECTION .text:CODE:REORDER:NOROOT(1)
FLC_IRQHandler
B FLC_IRQHandler
PUBWEAK GPIO0_IRQHandler ; /* 0x28 0x00A0 40: GPIO0 */
SECTION .text:CODE:REORDER:NOROOT(1)
GPIO0_IRQHandler
B GPIO0_IRQHandler
PUBWEAK RSV12_IRQHandler ; /* 0x29 0x00A4 41: RSV12 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV12_IRQHandler
B RSV12_IRQHandler
PUBWEAK RSV13_IRQHandler ; /* 0x2A 0x00A8 42: RSV13 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV13_IRQHandler
B RSV13_IRQHandler
PUBWEAK RSV14_IRQHandler ; /* 0x2B 0x00AC 43: RSV14 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV14_IRQHandler
B RSV14_IRQHandler
PUBWEAK DMA0_IRQHandler ; /* 0x2C 0x00B0 44: DMA0 */
SECTION .text:CODE:REORDER:NOROOT(1)
DMA0_IRQHandler
B DMA0_IRQHandler
PUBWEAK DMA1_IRQHandler ; /* 0x2D 0x00B4 45: DMA1 */
SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_IRQHandler
B DMA1_IRQHandler
PUBWEAK DMA2_IRQHandler ; /* 0x2E 0x00B8 46: DMA2 */
SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_IRQHandler
B DMA2_IRQHandler
PUBWEAK DMA3_IRQHandler ; /* 0x2F 0x00BC 47: DMA3 */
SECTION .text:CODE:REORDER:NOROOT(1)
DMA3_IRQHandler
B DMA3_IRQHandler
PUBWEAK RSV15_IRQHandler ; /* 0x30 0x00C0 48: RSV15 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV15_IRQHandler
B RSV15_IRQHandler
PUBWEAK RSV16_IRQHandler ; /* 0x31 0x00C4 49: RSV16 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV16_IRQHandler
B RSV16_IRQHandler
PUBWEAK RSV17_IRQHandler ; /* 0x32 0x00C8 50: RSV17 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV17_IRQHandler
B RSV17_IRQHandler
PUBWEAK RSV18_IRQHandler ; /* 0x33 0x00CC 51: RSV18 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV18_IRQHandler
B RSV18_IRQHandler
PUBWEAK I2C1_IRQHandler ; /* 0x34 0x00D0 52: I2C1 */
SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK RSV19_IRQHandler ; /* 0x35 0x00D4 53: RSV19 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV19_IRQHandler
B RSV19_IRQHandler
PUBWEAK RSV20_IRQHandler ; /* 0x36 0x00D8 54: RSV20 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV20_IRQHandler
B RSV20_IRQHandler
PUBWEAK RSV21_IRQHandler ; /* 0x37 0x00DC 55: RSV21 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV21_IRQHandler
B RSV21_IRQHandler
PUBWEAK RSV22_IRQHandler ; /* 0x38 0x00E0 56: RSV22 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV22_IRQHandler
B RSV22_IRQHandler
PUBWEAK RSV23_IRQHandler ; /* 0x39 0x00E4 57: RSV23 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV23_IRQHandler
B RSV23_IRQHandler
PUBWEAK RSV24_IRQHandler ; /* 0x3A 0x00E8 58: RSV24 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV24_IRQHandler
B RSV24_IRQHandler
PUBWEAK RSV25_IRQHandler ; /* 0x3B 0x00EC 59: RSV25 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV25_IRQHandler
B RSV25_IRQHandler
PUBWEAK RSV26_IRQHandler ; /* 0x3C 0x00F0 60: RSV26 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV26_IRQHandler
B RSV26_IRQHandler
PUBWEAK RSV27_IRQHandler ; /* 0x3D 0x00F4 61: RSV27 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV27_IRQHandler
B RSV27_IRQHandler
PUBWEAK RSV28_IRQHandler ; /* 0x3E 0x00F8 62: RSV28 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV28_IRQHandler
B RSV28_IRQHandler
PUBWEAK RSV29_IRQHandler ; /* 0x3F 0x00FC 63: RSV29 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV29_IRQHandler
B RSV29_IRQHandler
PUBWEAK RSV30_IRQHandler ; /* 0x40 0x0100 64: RSV30 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV30_IRQHandler
B RSV30_IRQHandler
PUBWEAK RSV31_IRQHandler ; /* 0x41 0x0104 65: RSV31 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV31_IRQHandler
B RSV31_IRQHandler
PUBWEAK RSV32_IRQHandler ; /* 0x42 0x0108 66: RSV32 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV32_IRQHandler
B RSV32_IRQHandler
PUBWEAK RSV33_IRQHandler ; /* 0x43 0x010C 67: RSV33 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV33_IRQHandler
B RSV33_IRQHandler
PUBWEAK RSV34_IRQHandler ; /* 0x44 0x0110 68: RSV34 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV34_IRQHandler
B RSV34_IRQHandler
PUBWEAK RSV35_IRQHandler ; /* 0x45 0x0114 69: RSV35 */
SECTION .text:CODE:REORDER:NOROOT(1)
RSV35_IRQHandler
B RSV35_IRQHandler
PUBWEAK GPIOWAKE_IRQHandler ; /* 0x46 0x0118 70: GPIO Wakeup */
SECTION .text:CODE:REORDER:NOROOT(1)
GPIOWAKE_IRQHandler
B GPIOWAKE_IRQHandler
END

77
bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/heap.c Normal file
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@ -0,0 +1,77 @@
/**
* @file heap.c
* @brief System level setup help
*/
/*******************************************************************************
* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of Maxim Integrated
* Products, Inc. shall not be used except as stated in the Maxim Integrated
* Products, Inc. Branding Policy.
*
* The mere transfer of this software does not imply any licenses
* of trade secrets, proprietary technology, copyrights, patents,
* trademarks, maskwork rights, or any other form of intellectual
* property whatsoever. Maxim Integrated Products, Inc. retains all
* ownership rights.
*
* $Date: 2018-12-18 15:37:22 -0600 (Tue, 18 Dec 2018) $
* $Revision: 40072 $
*
******************************************************************************/
/* **** Includes **** */
#include <stdint.h>
#include <errno.h>
#include <unistd.h>
/**
* @brief sbrk
* @detail Increase program data space
* @detail Malloc and related functions depend on this
*/
/* **** declarations **** */
static char *heap_end = 0;
extern unsigned int __HeapBase;
extern unsigned int __HeapLimit;
/* **** functions **** */
caddr_t _sbrk(int incr)
{
char *prev_heap_end;
if (heap_end == 0) {
heap_end = (caddr_t)&__HeapBase;
}
prev_heap_end = heap_end;
if ((unsigned int)(heap_end + incr) > (unsigned int)&__HeapLimit) {
errno = ENOMEM;
return (caddr_t) -1;
}
heap_end += incr;
return (caddr_t) prev_heap_end;
}

0
bsp/maxim/libraries/CMSIS/system_max32660.c → bsp/maxim/libraries/MAX32660PeriphDriver/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
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50
bsp/maxim/libraries/MAX32660PeriphDriver/SConscript Normal file
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split('''
CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c
Source/gpio.c
Source/lp.c
Source/tmr.c
Source/tmr_utils.c
Source/rtc.c
Source/icc.c
Source/mxc_lock.c
Source/mxc_assert.c
Source/mxc_delay.c
Source/mxc_pins.c
Source/mxc_sys.c
Source/nvic_table.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['Source/uart.c']
if GetDepend(['RT_USING_I2C']):
src += ['Source/i2c.c']
if GetDepend(['RT_USING_SPI']):
src += ['Source/spi.c']
if GetDepend(['RT_USING_RTC']):
src += ['Source/rtc.c']
if GetDepend(['RT_USING_WDT']):
src += ['Source/wdt.c']
path = [cwd + '/CMSIS/Device/Maxim/MAX32660/Include',
cwd + '/CMSIS/Core/Include',
cwd + '/Include']
CPPDEFINES = ['TARGET=32660']
CPPDEFINES += ['TARGET_REV=0x4131']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')