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[bsp/phytium] add phytium bsp to support e2000 bootup with smp (#6566) 

add phytium board (E2000) bsp
support usart
support SMP with demo
This commit is contained in:
zhugengyu 2022-11-10 22:22:48 +08:00 committed by GitHub
parent 5370d4da50
commit 1537544f6a
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# PHYTIUM BSP 说明
## 简介
本文档为基于 RT-THREAD 的 Phytium 系列 CPU 相关 BSP 说明。
本文的主要内容如下:
- BSP 简介
- 移植支持情况
- 如何在 Ubuntu/Windows 环境下使用此 BSP
- 如何进行编译与实验
- 维护人信息
- 注意事项
## BSP简介
- 飞腾芯片产品具有谱系全、性能高、生态完善、自主化程度高等特点，目前主要包括高性能服务器CPU（飞腾腾云S系列）、高效能桌面CPU（飞腾腾锐D系列）、高端嵌入式CPU（飞腾腾珑E系列）和飞腾套片四大系列，为从端到云的各型设备提供核心算力支撑。
- 本BSP目前支持飞腾腾锐D系列、飞腾腾珑E系列 相关CPU,基于 Phytium-Standalone-SDK 进行开发。开发者能够使用
- 本BSP 支持Phytium系列CPU 工作在 aarch32/aarch64 两种执行状态 ，开发者能够根据自己的应用场景灵活选择CPU 工作状态。
## 移植支持情况
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| UART | 支持 | uart1 打印输出|
| **芯片** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| E2000D | 支持 | 支持SMP |
| E2000Q | 支持 | 支持SMP |
| E2000S | 支持 | |
## 如何在Ubuntu/Windows 环境下使用此BSP
### Ubuntu 环境
1. 根据 [Linux x86_64 SDK安装方法](https://gitee.com/phytium_embedded/phytium-standalone-sdk/blob/release/doc/reference/usr/install_linux_x86_64.md) 中1.1 - 1.2 节中介绍，先安装 SDK 编译环境
2. 参考[RT-Thread/env](https://github.com/RT-Thread/env) 中Tutorial 在ubuntu 环境下安装 env 环境
3. 在编译环境下执行 ```source ~/.env/env.sh```
4. 以aarch32 执行状态为例，```cd bsp/phytium/aarch32```
### Windows 环境
1. 根据[Windows 10 SDK安装方法](https://gitee.com/phytium_embedded/phytium-standalone-sdk/blob/release/doc/reference/usr/install_windows.md)，安装 SDK 编译环境，编辑新建 Windows 环境变量 AARCH32_CROSS_PATH 和 AARCH64_CROSS_PATH
2. 参考[RT-Thread/env](https://github.com/RT-Thread/env) 中Tutorial 在 Windows 环境下解压 env 压缩包
3. 以aarch32 执行状态为例，```cd bsp/phytium/aarch32```
4. 使用 export_project.py 导出 BSP 工程到其他目录进行开发
5. 使用 RT-Studio 导入 BSP 工程进行开发
## 如何进行编译与实验
### 编译说明
- [AARCH32](./aarch32/README.md)
- [AARCH64](./aarch64/README.md)
### 烧写及执行
#### Ubuntu 环境配置 tftp 服务
- 在开发环境`host`侧安装`tftp`服务
```
sudo apt-get install tftp-hpa tftpd-hpa
sudo apt-get install xinetd
```
- 新建 tftboot 目录, 以`/mnt/d/tftboot`为例, 此目录应与项目编译脚本makefile中的USR_BOOT_DIR一致, 并确保 tftboot 目录有执行权限`chmod 777 /**/tftboot`
- 配置主机 tftpboot 服务, 新建并配置文件`/etc/xinetd.d/tftp`
```
# /etc/xinetd.d/tftp
server tftp
{
socket_type = dgram
protocol = udp
wait = yes
user = root
server = /usr/sbin/in.tftpd
server_args = -s /mnt/d/tftboot
disable = no
per_source = 11
cps = 100 2
flags = IPv4
}
```
- 启动主机`tftp`服务，生成默认配置
```
$ sudo service tftpd-hpa start
```
- 修改主机`tftp`配置，指向`tftboot`目录
修改/etc/default/tftpd-hpa
```
$ sudo nano /etc/default/tftpd-hpa
# /etc/default/tftpd-hpa
TFTP_USERNAME="tftp"
TFTP_DIRECTORY="/mnt/d/tftboot"
TFTP_ADDRESS=":69"
TFTP_OPTIONS="-l -c -s"
```
- 重启主机`tftp`服务
```
$ sudo service tftpd-hpa restart
```
- 测试主机`tftp`服务的可用性
> 登录`tftp`服务，获取`tftboot`目录下的一个文件
```
$ tftp 192.168.4.50
tftp> get test1234
tftp> q
```
#### Windows环境下配置 tftp 服务
- 下载Tftpd64 工具 ，并安装Tftpd64 工具
![输入图片说明](./figures/tftp32_srv.png)
- 之后每次使用前，进入Windows服务，手动将一下服务打开
![输入图片说明](./figures/config_tftp32.png)
#### 利用uboot 上tftp 服务加载镜像
- 进入`u-boot`界面，输入如下指令，配置开发板ip，`host`侧ip和网关地址
```
setenv ipaddr 192.168.4.20
setenv serverip 192.168.4.50
setenv gatewayip 192.168.4.1
```
- 将编译好的elf 或者bin 文件拷贝至Tftpd64所设置文件夹下
- 随后烧录的文件到开发板，输入以下指令
```
tftpboot 0x90100000 rtthread.elf
bootelf -p 0x90100000
```
### 运行结果
![运行结果](./figures/result.png)
## 维护人信息
- huanghe: huanghe@phytium.com.cn
- zhugengyu: zhugengyu@phytium.com.cn

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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_SYSTEM_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_A=y
# CONFIG_RT_SMP_AUTO_BOOT is not set
# CONFIG_RT_USING_GIC_V2 is not set
CONFIG_RT_USING_GIC_V3=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_LIBHYDROGEN is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
# CONFIG_PKG_USING_RTT_RUST is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
#
# Board extended module Drivers
#
CONFIG_PHYTIUM_ARCH_AARCH32=y
#
# Standalone Setting
#
CONFIG_TARGET_ARMV8_AARCH32=y
CONFIG_USE_AARCH64_L1_TO_AARCH32=y
#
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
#
# Components Configuration
#
# CONFIG_USE_SPI is not set
# CONFIG_USE_QSPI is not set
CONFIG_USE_GIC=y
CONFIG_ENABLE_GICV3=y
CONFIG_USE_SERIAL=y
#
# Usart Configuration
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
# CONFIG_USE_USB is not set
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
# CONFIG_USE_IPC is not set
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
CONFIG_INTERRUPT_ROLE_MASTER=y
# CONFIG_INTERRUPT_ROLE_SLAVE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set

54
bsp/phytium/aarch32/Kconfig Normal file
View File

@ -0,0 +1,54 @@
mainmenu "RT-Thread Project Configuration"
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config BSP_DIR
string
option env="BSP_ROOT"
default "../."
config STANDALONE_DIR
string
option env="STANDALONE_DIR"
default ".././libraries/standalone"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$BSP_DIR/libraries/drivers/Kconfig"
config PHYTIUM_ARCH_AARCH32
bool
select ARCH_ARM_CORTEX_A
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_GIC_V3
select TARGET_ARMV8_AARCH32
select USE_AARCH64_L1_TO_AARCH32
default y
menu "Standalone Setting"
config TARGET_ARMV8_AARCH32
bool "Armv8 Aarch32"
default y
config USE_AARCH64_L1_TO_AARCH32
bool
prompt "Use Aarch64 L1 to Aarch32 code"
default y
help
Use the Aarch64 to Aarch32 mode function
source "$STANDALONE_DIR/board/Kconfig"
source "$STANDALONE_DIR/drivers/Kconfig"
source "$STANDALONE_DIR/common/Kconfig"
endmenu

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# AARCH32 工作模式使用
- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
## 1. 如何选择芯片
- Windows Env 环境下
```shell
menuconfig
```
- Linux 环境下
```shell
scons --menuconfig
```
开发者通过以下选择进行配置
```
Standalone Setting > Board Configuration > Chip
```
![](./figures/chip_select.png)
![](./figures/phytium_cpu_select.png)
## 2. 如何选择驱动
```shell
scons --menuconfig
```
开发者通过以下选项进行驱动的使能
```
Hardware Drivers > On-chip Peripheral Drivers
```
![](./figures/select_driver.png)
## 3. 开启SDK中内部调试信息
```shell
scons --menuconfig
```
开发者通过以下选项进行调试信息等级的设置
![](./figures/select_debug_info.png)
## 4. 编译程序
```shell
scons -c
scons
```
- 完成编译之后目录下将会生成以下几个文件
```
rtthread_a32.bin
rtthread_a32.elf
rtthread_a32.map
```
## 5. 打包导出工程源代码
- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
```
python ./export_project.py -n=phytium-a32 -o=D:/proj/rt-thread-e2000/phytium-a32
```
![](./figures/export_project.png)
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
```
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config STANDALONE_DIR
string
option env="STANDALONE_DIR"
default "libraries/standalone"
```
- 输入 menuconfig 和 scons 完成编译
## 6. 将工程导入 RT-Studio
- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 设置 BSP 工程的交叉编译链后进行后续开发
![](./figures/import_project.png)

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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

58
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import os
import sys
import rtconfig
IS_EXPORTED = False
# setup RT-Thread Root Path
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.getcwd() + '/../../..'
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
if RTT_ROOT == 'rt-thread':
IS_EXPORTED = True # if kenrel and bsp has been exported by export_project.py
# setup Phytium BSP Root Path
if IS_EXPORTED:
BSP_ROOT = '.'
else:
BSP_ROOT = RTT_ROOT + '/bsp/phytium'
TARGET = 'rtthread_a32.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('BSP_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
if not IS_EXPORTED: # if project is not exported, libraries and board need to manually add
# include libraries
objs.extend(SConscript(os.path.join(BSP_ROOT + '/libraries', 'SConscript')))
# include board
objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#ifdef RT_USING_SMP
struct rt_thread test_core[RT_CPUS_NR];
static char *core_thread_name[8] =
{
"core0_test",
"core1_test",
"core2_test",
"core3_test",
"core4_test",
"core5_test",
"core6_test",
"core7_test"
};
static rt_uint8_t core_stack[RT_CPUS_NR][1024];
static void demo_core_thread(void *parameter)
{
rt_base_t level;
while (1)
{
/* code */
level = rt_cpus_lock();
rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
rt_cpus_unlock(level);
rt_thread_mdelay(2000000);
}
}
void demo_core(void)
{
rt_ubase_t i;
rt_ubase_t cpu_id = 0;
for (i = 0; i < RT_CPUS_NR; i++)
{
cpu_id = i;
rt_thread_init(&test_core[i],
core_thread_name[i],
demo_core_thread,
RT_NULL,
&core_stack[i],
1024,
20,
32);
rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
rt_thread_startup(&test_core[i]);
}
}
#endif
int main(void)
{
#ifdef RT_USING_SMP
demo_core();
#endif
return RT_EOK;
}

10
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from building import *
cwd = GetCurrentDir()
src = Glob('*.S') + Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('AARCH32-BOOT', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
.global _boot
.set FPEXC_EN, 0x40000000 /* FPU enable bit, (1 << 30) */
.org 0
.text
.section .boot,"ax"
/* switch from aarch64-el2 to aarch32-el1 */
_boot:
Startup_Aarch32:
.long 0xd5384240 /* mrs x0, currentel */
.long 0xd342fc00 /* lsr x0, x0, #2 */
.long 0x92400400 /* and x0, x0, #0x3 */
.long 0xf1000c1f /* cmp x0, #0x3 */
.long 0x540003a1 /* b.ne 1d0080c4 <el2_mode> */
el3_mode:
.long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */
.long 0xb2400c00 /* orr x0, x0, #0xf */
.long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */
.long 0xd5033fdf /* isb */
.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */
.long 0xb2400c00 /* orr x0, x0, #0xf */
.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */
.long 0xd5033fdf /* isb */
.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */
.long 0xb2400000 /* orr x0, x0, #0x1 */
.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */
.long 0xd5033fdf /* isb */
.long 0xd2803620 /* mov x0, #0x1b1 */
.long 0xd51e1100 /* msr scr_el3, x0 */
.long 0xd2867fe0 /* mov x0, #0x33ff */
.long 0xd51c1140 /* msr cptr_el2, x0 */
.long 0xd2810000 /* mov x0, #0x800 */
.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */
.long 0xd5181000 /* msr sctlr_el1, x0 */
.long 0x910003e0 /* mov x0, sp */
.long 0xd51c4100 /* msr sp_el1, x0 */
.long 0xd53ec000 /* mrs x0, vbar_el3 */
.long 0xd518c000 /* msr vbar_el1, x0 */
.long 0xd2803a60 /* mov x0, #0x1d3 */
.long 0xd51e4000 /* msr spsr_el3, x0 */
.long 0x10000500 /* adr x0, 1d008158 <el1_mode> */
.long 0xd51e4020 /* msr elr_el3, x0 */
.long 0xd69f03e0 /* eret */
el2_mode:
.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */
.long 0xb2400c00 /* orr x0, x0, #0xf */
.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */
.long 0xd5033fdf /* isb */
.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */
.long 0xb2400000 /* orr x0, x0, #0x1 */
.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */
.long 0xd5033fdf /* isb */
.long 0xd53ce100 /* mrs x0, cnthctl_el2 */
.long 0xb2400400 /* orr x0, x0, #0x3 */
.long 0xd51ce100 /* msr cnthctl_el2, x0 */
.long 0xd51ce07f /* msr cntvoff_el2, xzr */
.long 0xd5380000 /* mrs x0, midr_el1 */
.long 0xd53800a1 /* mrs x1, mpidr_el1 */
.long 0xd51c0000 /* msr vpidr_el2, x0 */
.long 0xd51c00a1 /* msr vmpidr_el2, x1 */
.long 0xd2867fe0 /* mov x0, #0x33ff */
.long 0xd51c1140 /* msr cptr_el2, x0 */
.long 0xd51c117f /* msr hstr_el2, xzr */
.long 0xd2a00600 /* mov x0, #0x300000 */
.long 0xd5181040 /* msr cpacr_el1, x0 */
.long 0xd2800000 /* mov x0, #0x0 */
.long 0xb2630000 /* orr x0, x0, #0x20000000 */
.long 0xd51c1100 /* msr hcr_el2, x0 */
.long 0xd53c1100 /* mrs x0, hcr_el2 */
.long 0xd2810000 /* mov x0, #0x800 */
.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */
.long 0xd5181000 /* msr sctlr_el1, x0 */
.long 0x910003e0 /* mov x0, sp */
.long 0xd51c4100 /* msr sp_el1, x0 */
.long 0xd53cc000 /* mrs x0, vbar_el2 */
.long 0xd518c000 /* msr vbar_el1, x0 */
.long 0xd2803a60 /* mov x0, #0x1d3 */
.long 0xd51c4000 /* msr spsr_el2, x0 */
.long 0x10000060 /* adr x0, 1d008158 <el1_mode> */
.long 0xd51c4020 /* msr elr_el2, x0 */
.long 0xd69f03e0 /* eret */
el1_mode:
mov r0, #0
mov r1, #0
mov r2, #0
mov r3, #0
mov r4, #0
mov r5, #0
mov r6, #0
mov r7, #0
mov r8, #0
mov r9, #0
mov r10, #0
mov r11, #0
mov r12, #0
mcr p15, 0, r0, c1, c0, 0 /* reset control register */
isb
/* enable vfp, therefore f_prink workable */
vmrs r1, FPEXC /* read the exception register */
orr r1,r1, #FPEXC_EN /* set VFP enable bit, leave the others in orig state */
vmsr FPEXC, r1 /* write back the exception register */
bl system_vectors /* jump to libcpu/arm/cortex-a/vector_gcc.S */

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import os
import shutil
import argparse
parser = argparse.ArgumentParser()
parser.description='please enter two parameters <project-name> and <export-path> ...'
parser.add_argument("-n", "--name", help="project name", type=str, default="phytium-a32")
parser.add_argument("-o", "--output", help="export path", type=str, default="./phytium-a32")
args = parser.parse_args()
print('=== Exporting Phytium BSP for RT-Studio ====')
board_src_path = os.path.abspath(r'../board')
librs_src_path = os.path.abspath(r'../libraries')
board_dst_path = os.path.abspath(r'./board')
librs_dst_path = os.path.abspath(r'./libraries')
print(' Copying BSP board from {} to {}'.format(board_src_path, board_dst_path))
print(' Copying BSP libraries from {} to {}'.format(librs_src_path, librs_dst_path))
if os.path.exists(board_dst_path):
shutil.rmtree(board_dst_path)
if os.path.exists(librs_dst_path):
shutil.rmtree(librs_dst_path)
shutil.copytree(board_src_path, board_dst_path)
shutil.copytree(librs_src_path, librs_dst_path)
os.system('scons --dist-ide --project-name={} --project-path={}'.format(args.name, args.output))
if os.path.exists(board_dst_path):
shutil.rmtree(board_dst_path)
if os.path.exists(librs_dst_path):
shutil.rmtree(librs_dst_path)

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116
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_boot)
SECTIONS
{
. = 0x80100000;
.text :
{
*(.boot)
. = ALIGN(64);
*(.vectors)
*(.text)
*(.text.*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
/* section information for initialization */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
} =0
__text_end = .;
__rodata_start = .;
.rodata : { *(.rodata) *(.rodata.*) }
__rodata_end = .;
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16 * 1024);
.l1_page_table :
{
__l1_page_table_start = .;
. += 16K;
}
. = ALIGN(8);
__data_start = .;
.data :
{
*(.data)
*(.data.*)
}
__data_end = .;
. = ALIGN(8);
__bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
}
. = ALIGN(4);
__bss_end = .;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += 0x400;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
_end = .;
}

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define SYSTEM_THREAD_STACK_SIZE 256
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_A
#define RT_USING_GIC_V3
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* Kendryte SDK */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define PHYTIUM_ARCH_AARCH32
/* Standalone Setting */
#define TARGET_ARMV8_AARCH32
#define USE_AARCH64_L1_TO_AARCH32
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_GIC
#define ENABLE_GICV3
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#define USE_DEFAULT_INTERRUPT_CONFIG
#define INTERRUPT_ROLE_MASTER
#endif

68
bsp/phytium/aarch32/rtconfig.py Normal file
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import os
import rtconfig
# toolchains options
ARCH='arm'
CPU='cortex-a'
CROSS_TOOL='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# only support GNU GCC compiler.
PLATFORM = 'gcc'
EXEC_PATH = r'/usr/lib/arm-none-eabi/bin'
if os.getenv('AARCH32_CROSS_PATH'):
EXEC_PATH = os.getenv('AARCH32_CROSS_PATH')
print('EXEC_PATH = {}'.format(EXEC_PATH))
else:
print('AARCH32_CROSS_PATH not found')
BUILD = 'debug'
LIBPATH = EXEC_PATH + r'/../lib'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
DEVICE = ' -g -DGUEST -ffreestanding -Wextra -g -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -march=armv8-a -fdiagnostics-color=always'
# CFLAGS = DEVICE + ' -Wall'
CFLAGS = DEVICE
AFLAGS = ' -c'+ DEVICE + ' -fsingle-precision-constant -fno-builtin -x assembler-with-cpp -D__ASSEMBLY__'
LINK_SCRIPT = 'link.lds'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors'+\
' -T %s' % LINK_SCRIPT
CPATH = ''
LPATH = LIBPATH
# generate debug info in all cases
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -g -gdwarf-2'
if BUILD == 'debug':
CFLAGS += ' -O0'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' +\
SIZE + ' $TARGET \n'

75
bsp/phytium/aarch32/sdkconfig.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: sdkconfig.h
* Date: 2022-10-13 15:53:46
* LastEditTime: 2022-10-13 15:53:46
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
#ifndef SDK_CONFIG_H__
#define SDK_CONFIG_H__
#include "rtconfig.h"
/* arch */
#if defined(TARGET_ARMV8_AARCH32)
#define CONFIG_TARGET_ARMV8_AARCH32
#endif
#if defined(USE_AARCH64_L1_TO_AARCH32)
#define CONFIG_USE_AARCH64_L1_TO_AARCH32
#endif
/* board */
/* E2000 */
#if defined(TARGET_E2000)
#define CONFIG_TARGET_E2000
#endif
/* debug */
#ifdef LOG_VERBOS
#define CONFIG_LOG_VERBOS
#endif
#ifdef LOG_ERROR
#define CONFIG_LOG_ERROR
#endif
#ifdef LOG_WARN
#define CONFIG_LOG_WARN
#endif
#ifdef LOG_INFO
#define CONFIG_LOG_INFO
#endif
#ifdef LOG_DEBUG
#define CONFIG_LOG_DEBUG
#endif
#ifdef BOOTUP_DEBUG_PRINTS
#define CONFIG_BOOTUP_DEBUG_PRINTS
#endif
#endif

922
bsp/phytium/aarch64/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=4
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
#
# kservice optimization
#
CONFIG_RT_KSERVICE_USING_STDLIB=y
# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_KPRINTF_USING_LONGLONG=y
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_CPU_64BIT=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARMV8=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
CONFIG_RT_USING_MSH=y
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_FAL is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# C/C++ and POSIX layer
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LWIP is not set
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_IOTSHARP_SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_LIBHYDROGEN is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
#
# JSON: JavaScript Object Notation, a lightweight data-interchange format
#
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
#
# CONFIG_PKG_USING_SIMPLE_XML is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
# CONFIG_PKG_USING_RTT_RUST is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_GUIENGINE is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_CHERRYUSB is not set
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# project laboratory
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_HEATSHRINK is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers
#
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_RT_USING_UART1=y
# CONFIG_RT_USING_UART0 is not set
#
# Board extended module Drivers
#
CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GICV3=y
CONFIG_PHYTIUM_ARCH_AARCH64=y
#
# Standalone Setting
#
CONFIG_TARGET_ARMV8_AARCH64=y
#
# Board Configuration
#
# CONFIG_TARGET_F2000_4 is not set
# CONFIG_TARGET_D2000 is not set
CONFIG_TARGET_E2000Q=y
# CONFIG_TARGET_E2000D is not set
# CONFIG_TARGET_E2000S is not set
CONFIG_TARGET_E2000=y
CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
#
# Components Configuration
#
# CONFIG_USE_SPI is not set
# CONFIG_USE_QSPI is not set
# CONFIG_USE_GIC is not set
CONFIG_USE_SERIAL=y
#
# Usart Configuration
#
CONFIG_ENABLE_Pl011_UART=y
# CONFIG_USE_GPIO is not set
# CONFIG_USE_ETH is not set
# CONFIG_USE_CAN is not set
# CONFIG_USE_I2C is not set
# CONFIG_USE_TIMER is not set
# CONFIG_USE_MIO is not set
# CONFIG_USE_SDMMC is not set
# CONFIG_USE_PCIE is not set
# CONFIG_USE_WDT is not set
# CONFIG_USE_DMA is not set
# CONFIG_USE_NAND is not set
# CONFIG_USE_RTC is not set
# CONFIG_USE_SATA is not set
# CONFIG_USE_USB is not set
# CONFIG_USE_ADC is not set
# CONFIG_USE_PWM is not set
# CONFIG_USE_IPC is not set
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_NONE is not set
# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_BOOTUP_DEBUG_PRINTS is not set

55
bsp/phytium/aarch64/Kconfig Normal file
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@ -0,0 +1,55 @@
mainmenu "RT-Thread Project Configuration"
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config BSP_DIR
string
option env="BSP_ROOT"
default "../."
config STANDALONE_DIR
string
option env="STANDALONE_DIR"
default ".././libraries/standalone"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "$BSP_DIR/libraries/drivers/Kconfig"
config BSP_USING_GIC
bool
default y
config BSP_USING_GICV3
bool
default y
config PHYTIUM_ARCH_AARCH64
bool
select ARCH_ARMV8
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select ARCH_CPU_64BIT
select TARGET_ARMV8_AARCH64
default y
menu "Standalone Setting"
config TARGET_ARMV8_AARCH64
bool "Armv8 Aarch64"
default y
source "$STANDALONE_DIR/board/Kconfig"
source "$STANDALONE_DIR/drivers/Kconfig"
source "$STANDALONE_DIR/common/Kconfig"
endmenu

121
bsp/phytium/aarch64/README.md Normal file
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<!--
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: README.md
* Date: 2022-10-17 15:16:12
* LastEditTime: 2022-10-17 15:16:12
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
-->
# AARCH64 工作模式使用
- 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
## 1. 如何选择芯片
```shell
scons --menuconfig
```
开发者通过以下选择进行配置
```
Standalone Setting > Board Configuration > Chip
```
![](./figures/chip_select.png)
![](./figures/phytium_cpu_select.png)
## 2. 如何选择驱动
```shell
scons --menuconfig
```
开发者通过以下选项进行驱动的使能
```
Hardware Drivers Config > On-chip Peripheral Drivers
```
![](./figures/select_driver.png)
## 3. 开启SDK中内部调试信息
```shell
scons --menuconfig
```
开发者通过以下选项进行调试信息等级的设置
![](./figures/select_debug_info.png)
## 4. 编译程序
```shell
scons -c
scons
```
- 完成编译之后目录下将会生成以下几个文件
```
rtthread_a64.bin
rtthread_a64.elf
rtthread_a64.map
```
## 5. 打包导出工程源代码
- 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
```
python ./export_project.py -n=phytium-a64 -o=D:/proj/rt-thread-e2000/phytium-a64
```
![](./figures/export_project.png)
- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
> env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
```
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config STANDALONE_DIR
string
option env="STANDALONE_DIR"
default "libraries/standalone"
```
- 输入 menuconfig 和 scons 完成编译
## 6. 将工程导入 RT-Studio
- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
- 设置 BSP 工程的交叉编译链后进行后续开发
![](./figures/import_project.png)

15
bsp/phytium/aarch64/SConscript Normal file
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@ -0,0 +1,15 @@
# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

58
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import os
import sys
import rtconfig
IS_EXPORTED = False
# setup RT-Thread Root Path
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.getcwd() + '/../../..'
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
if RTT_ROOT == 'rt-thread':
IS_EXPORTED = True # if kenrel and bsp has been exported by export_project.py
# setup Phytium BSP Root Path
if IS_EXPORTED:
BSP_ROOT = '.'
else:
BSP_ROOT = RTT_ROOT + '/bsp/phytium'
TARGET = 'rtthread_a64.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('BSP_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
if not IS_EXPORTED: # if project is not exported, libraries and board need to manually add
# include libraries
objs.extend(SConscript(os.path.join(BSP_ROOT + '/libraries', 'SConscript')))
# include board
objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)

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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#ifdef RT_USING_SMP
struct rt_thread test_core[RT_CPUS_NR];
static char *core_thread_name[8] =
{
"core0_test",
"core1_test",
"core2_test",
"core3_test",
"core4_test",
"core5_test",
"core6_test",
"core7_test"
};
static rt_uint8_t core_stack[RT_CPUS_NR][1024];
static void demo_core_thread(void *parameter)
{
rt_base_t level;
while (1)
{
/* code */
level = rt_cpus_lock();
rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
rt_cpus_unlock(level);
rt_thread_mdelay(2000000);
}
}
void demo_core(void)
{
rt_ubase_t i;
rt_ubase_t cpu_id = 0;
for (i = 0; i < RT_CPUS_NR; i++)
{
cpu_id = i;
rt_thread_init(&test_core[i],
core_thread_name[i],
demo_core_thread,
RT_NULL,
&core_stack[i],
1024,
20,
32);
rt_thread_control(&test_core[i], RT_THREAD_CTRL_BIND_CPU, (void *)cpu_id);
rt_thread_startup(&test_core[i]);
}
}
#endif
int main(void)
{
#ifdef RT_USING_SMP
demo_core();
#endif
return RT_EOK;
}

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import os
import shutil
import argparse
parser = argparse.ArgumentParser()
parser.description='please enter two parameters <project-name> and <export-path> ...'
parser.add_argument("-n", "--name", help="project name", type=str, default="phytium-a64")
parser.add_argument("-o", "--output", help="export path", type=str, default="./phytium-a64")
args = parser.parse_args()
print('=== Exporting Phytium BSP for RT-Studio ====')
board_src_path = os.path.abspath(r'../board')
librs_src_path = os.path.abspath(r'../libraries')
board_dst_path = os.path.abspath(r'./board')
librs_dst_path = os.path.abspath(r'./libraries')
print(' Copying BSP board from {} to {}'.format(board_src_path, board_dst_path))
print(' Copying BSP libraries from {} to {}'.format(librs_src_path, librs_dst_path))
if os.path.exists(board_dst_path):
shutil.rmtree(board_dst_path)
if os.path.exists(librs_dst_path):
shutil.rmtree(librs_dst_path)
shutil.copytree(board_src_path, board_dst_path)
shutil.copytree(librs_src_path, librs_dst_path)
os.system('scons --dist-ide --project-name={} --project-path={}'.format(args.name, args.output))
if os.path.exists(board_dst_path):
shutil.rmtree(board_dst_path)
if os.path.exists(librs_dst_path):
shutil.rmtree(librs_dst_path)

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* 2017-5-30 bernard first version
*/
/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
SECTIONS
{
. = 0x80100000;
. = ALIGN(4096);
.text :
{
KEEP(*(.text.entrypoint)) /* The entry point */
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
*(COMMON)
/* section information for finsh shell */
. = ALIGN(16);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(16);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(16);
/* section information for initial. */
. = ALIGN(16);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(16);
. = ALIGN(16);
_etext = .;
}
. = ALIGN(4);
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(16);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(16);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(16);
.ctors :
{
PROVIDE(__ctors_start__ = .);
/* new GCC version uses .init_array */
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__ctors_end__ = .);
}
. = ALIGN(4);
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(16);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
. = ALIGN(32);
PROVIDE(__bss_end = .);
}
. = ALIGN(4);
.heap :
{
PROVIDE(__heap_start = .);
. = ALIGN(8);
PROVIDE(end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
__bss_size = SIZEOF(.bss);

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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 4
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 4096
#define SYSTEM_THREAD_STACK_SIZE 4096
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 4096
/* kservice optimization */
#define RT_KSERVICE_USING_STDLIB
#define RT_KPRINTF_USING_LONGLONG
#define RT_DEBUG
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define ARCH_CPU_64BIT
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 4096
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* Kendryte SDK */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_UART
#define RT_USING_UART1
/* Board extended module Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Board Configuration */
#define TARGET_E2000Q
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
/* Components Configuration */
#define USE_SERIAL
/* Usart Configuration */
#define ENABLE_Pl011_UART
#define LOG_ERROR
#endif

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import os
# toolchains options
ARCH ='aarch64'
CPU ='cortex-a'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'
if os.getenv('AARCH64_CROSS_PATH'):
EXEC_PATH = os.getenv('AARCH64_CROSS_PATH')
print('EXEC_PATH = {}'.format(EXEC_PATH))
else:
print('AARCH64_CROSS_PATH not found')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds -fdiagnostics-color=always'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.dis\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'

71
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: sdkconfig.h
* Date: 2022-10-09 15:04:36
* LastEditTime: 2022-10-09 15:04:37
* Description: This file is for
*
* Modify History:
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------
*/
#ifndef SDK_CONFIG_H__
#define SDK_CONFIG_H__
#include "rtconfig.h"
/* board */
/* E2000 */
#if defined(TARGET_E2000)
#define CONFIG_TARGET_E2000
#endif
#if defined(TARGET_E2000Q)
#define CONFIG_TARGET_E2000Q
#endif
#if defined(TARGET_ARMV8_AARCH64)
#define CONFIG_TARGET_ARMV8_AARCH64
#endif
/* debug */
#ifdef LOG_VERBOS
#define CONFIG_LOG_VERBOS
#endif
#ifdef LOG_ERROR
#define CONFIG_LOG_ERROR
#endif
#ifdef LOG_WARN
#define CONFIG_LOG_WARN
#endif
#ifdef LOG_INFO
#define CONFIG_LOG_INFO
#endif
#ifdef LOG_DEBUG
#define CONFIG_LOG_DEBUG
#endif
#ifdef BOOTUP_DEBUG_PRINTS
#define CONFIG_BOOTUP_DEBUG_PRINTS
#endif
#endif

25
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from building import *
cwd = GetCurrentDir()
src = Glob('*.S')
src += Glob('*.c')
if GetDepend(['TARGET_E2000']):
if GetDepend(['TARGET_E2000Q']):
src += Glob(cwd + '/e2000/q/parameters.c')
elif GetDepend(['TARGET_E2000D']):
src += Glob(cwd + '/e2000/d/parameters.c')
elif GetDepend(['TARGET_E2000S']):
src += Glob(cwd + '/e2000/s/parameters.c')
if GetDepend(['TARGET_F2000_4']):
src += Glob(cwd + '/d2000/parameters.c')
if GetDepend(['TARGET_D2000']):
src += Glob(cwd + '/ft2004/parameters.c')
CPPPATH = [cwd]
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-10-26 zhugengyu support aarch64
*
*/
#include "rtconfig.h"
#include <rthw.h>
#include <rtthread.h>
#include <mmu.h>
#include <gicv3.h>
#if defined(TARGET_ARMV8_AARCH64)
#include <psci.h>
#include <gtimer.h>
#include <cpuport.h>
#else
#include "fgeneric_timer.h" /* for aarch32 */
#endif
#include <interrupt.h>
#include <board.h>
#include "fdebug.h"
#include "fprintk.h"
#include "fearly_uart.h"
#include "fcpu_info.h"
#include "fpsci.h"
#define LOG_DEBUG_TAG "BOARD"
#define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
#define BSP_LOG_WARN(format, ...) FT_DEBUG_PRINT_W(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
#define BSP_LOG_INFO(format, ...) FT_DEBUG_PRINT_I(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
#define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
/* mmu config */
struct mem_desc platform_mem_desc[] =
#if defined(TARGET_E2000)
{
{
0x00U,
0x00U + 0x40000000U,
0x00U,
DEVICE_MEM
},
{
0x40000000U,
0x40000000U + 0x10000000U,
0x40000000U,
DEVICE_MEM
},
{
0x50000000U,
0x50000000U + 0x30000000U,
0x50000000U,
DEVICE_MEM
},
{
0x80000000U,
0xffffffffU,
0x80000000U,
NORMAL_MEM
},
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
{
{
0x80000000,
0xFFFFFFFF,
0x80000000,
DDR_MEM
},
{
0, //< QSPI
0x1FFFFFFF,
0,
DEVICE_MEM
},
{
0x20000000, //<! LPC
0x27FFFFFF,
0x20000000,
DEVICE_MEM
},
{
FT_DEV_BASE_ADDR, //<! Device register
FT_DEV_END_ADDR,
FT_DEV_BASE_ADDR,
DEVICE_MEM
},
{
0x30000000, //<! debug
0x39FFFFFF,
0x30000000,
DEVICE_MEM
},
{
0x3A000000, //<! Internal register space in the on-chip network
0x3AFFFFFF,
0x3A000000,
DEVICE_MEM
},
{
FT_PCI_CONFIG_BASEADDR,
FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
FT_PCI_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_IO_CONFIG_BASEADDR,
FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
FT_PCI_IO_CONFIG_BASEADDR,
DEVICE_MEM
},
{
FT_PCI_MEM32_BASEADDR,
FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
FT_PCI_MEM32_BASEADDR,
DEVICE_MEM
}
#if defined(TARGET_ARMV8_AARCH64)
{
0x1000000000,
0x1000000000 + 0x1000000000,
0x1000000000,
DEVICE_MEM
},
{
0x2000000000,
0x2000000000 + 0x2000000000,
0x2000000000,
NORMAL_MEM
},
#endif
};
#endif
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
/* aarch64 use kernel gtimer */
void idle_wfi(void)
{
asm volatile("wfi");
}
#else /* AARCH32 */
static rt_uint32_t timerStep;
void rt_hw_timer_isr(int vector, void *parameter)
{
GenericTimerCompare(timerStep);
rt_tick_increase();
}
int rt_hw_timer_init(void)
{
rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
timerStep = GenericTimerFrequecy();
timerStep /= RT_TICK_PER_SECOND;
GenericTimerCompare(timerStep);
GenericTimerInterruptEnable();
GenericTimerStart();
return 0;
}
INIT_BOARD_EXPORT(rt_hw_timer_init);
#endif
#ifdef RT_USING_SMP
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
#endif
/**
* This function will initialize hardware board
*/
void rt_hw_board_init(void)
{
/* mmu init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
rt_hw_mmu_init();
#endif
/* interrupt init */
#if defined(TARGET_ARMV8_AARCH64)
f_printk("aarch64 interrupt init \r\n");
#else
f_printk("aarch32 interrupt init \r\n");
extern int rt_hw_cpu_id(void);
u32 cpu_id, cpu_offset = 0;
GetCpuId(&cpu_id);
f_printk("cpu_id is %d \r\n", cpu_id);
#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
#endif
f_printk("cpu_offset is %d \r\n", cpu_offset);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
#if defined(TARGET_E2000Q)
#if RT_CPUS_NR == 2
f_printk("arm_gic_redist_address_set is 2 \r\n");
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + GICV3_RD_OFFSET, 3);
#endif
#else
#if RT_CPUS_NR == 2
f_printk("arm_gic_redist_address_set is 2 \r\n");
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
#elif RT_CPUS_NR == 3
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
#elif RT_CPUS_NR == 4
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
#endif
#endif
#endif
rt_hw_interrupt_init();
/* gtimer init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_gtimer_init();
#endif
/* compoent init */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
/* shell init */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* init memory pool */
#ifdef RT_USING_HEAP
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
#endif
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
static void ft_reset(void)
{
PsciCpuReset();
}
MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
/*@}*/

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "fparameters.h"
#include "phytium_cpu.h"
#if defined(__CC_ARM)
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif defined(__GNUC__)
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void *)(0x80000000 + 1024 * 1024 * 1024)
void rt_hw_board_init(void);
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "fcpu_info.h"
#include "fparameters.h"
/**
* @name: GetCpuMaskToAffval
* @msg: Convert information in cpu_mask to cluster_ID and target_list
* @param {u32} *cpu_mask is each bit of cpu_mask represents a selected CPU, for example, 0x3 represents core0 and CORE1 .
* @param {u32} *cluster_id is information about the cluster in which core resides ,format is
* |--------[bit31-24]-------[bit23-16]-------------[bit15-8]-----------[bit7-0]
* |--------Affinity level3-----Affinity level2-----Affinity level1-----Affinity level0
* @param {u32} *target_list is core mask in cluster
* @return {u32} 0 indicates that the conversion was not successful , 1 indicates that the conversion was successful
*/
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
{
return 0;
}
*target_list = 0;
*cluster_id = 0;
if (*cpu_mask & 0x3)
{
if ((*cpu_mask & 0x3) == 0x3)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x1))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0x3;
}
else if (*cpu_mask & 0xc)
{
*cluster_id = 0x100;
if ((*cpu_mask & 0xc) == 0xc)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x4))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0xc;
}
else if (*cpu_mask & 0x30)
{
*cluster_id = 0x200;
if ((*cpu_mask & 0x30) == 0x30)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x10))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0x30;
}
else if (*cpu_mask & 0xc0)
{
*cluster_id = 0x300;
if ((*cpu_mask & 0xc0) == 0xc0)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x40))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0xc0;
}
else
{
*cpu_mask = 0;
return 0;
}
return 1;
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "fcpu_info.h"
#include "fparameters.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
{
return 0;
}
*target_list = 0;
*cluster_id = 0;
if (*cpu_mask & 0x3)
{
*cluster_id = 0x200;
if ((*cpu_mask & 0x3) == 0x3)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x1))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0x3; /* clear all mask */
}
else
{
*cpu_mask = 0;
return 0;
}
return 1;
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "fcpu_info.h"
#include "fparameters.h"
/**
* @name: GetCpuMaskToAffval
* @msg: 参考 GetCpuMaskToAffval 进行参数的重新定义 ，两个小核心定义的id 为0，1 ，两个大核的id 为 2，3
* @return {*}
* @note:
* @param {u32} *cpu_mask
* @param {u32} *cluster_id
* @param {u32} *target_list
*/
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
{
return 0;
}
*target_list = 0;
*cluster_id = 0;
if (*cpu_mask & 0x4)
{
*target_list = 1;
*cpu_mask &= ~0x4;
}
else if (*cpu_mask & 0x8)
{
*cluster_id = 0x100;
*target_list = 1;
*cpu_mask &= ~0x8;
}
else if (*cpu_mask & 0x3)
{
*cluster_id = 0x200;
if ((*cpu_mask & 0x3) == 0x3)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x4))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0x3;
}
else
{
*cpu_mask = 0;
return 0;
}
return 1;
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "fcpu_info.h"
#include "fparameters.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
{
return 0;
}
*target_list = 0;
*cluster_id = 0;
if (*cpu_mask & 0x1)
{
*target_list = 1;
*cluster_id = 0x200;
*cpu_mask &= ~0x1;
}
else
{
*cpu_mask = 0;
return 0;
}
return 1;
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "fcpu_info.h"
#include "fparameters.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{
if (*cpu_mask == 0)
{
return 0;
}
*target_list = 0;
*cluster_id = 0;
if (*cpu_mask & 0x3)
{
if ((*cpu_mask & 0x3) == 0x3)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x1))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0x3;
}
else if (*cpu_mask & 0xc)
{
*cluster_id = 0x100;
if ((*cpu_mask & 0xc) == 0xc)
{
*target_list = 3;
}
else if ((*cpu_mask & 0x4))
{
*target_list = 1;
}
else
{
*target_list = 2;
}
*cpu_mask &= ~0xc;
}
else
{
*cpu_mask = 0;
return 0;
}
return 1;
}

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "rtconfig.h"
#include <rtthread.h>
#include "gicv3.h"
#include "fparameters.h"
#include "fcpu_info.h"
#include "phytium_cpu.h"
int phytium_cpu_id_mapping(int cpu_id)
{
#if defined(TARGET_E2000Q)
switch (cpu_id)
{
case 0:
return 2;
case 1:
return 3;
case 2:
return 0;
case 3:
return 1;
default:
RT_ASSERT(0);
return 0;
break;
}
#else
return (int)cpu_id;
#endif
}
#if defined(TARGET_ARMV8_AARCH64)
int phytium_cpu_id(void)
{
FError ret;
u32 cpu_id;
ret = GetCpuId(&cpu_id);
if (ret != ERR_SUCCESS)
{
RT_ASSERT(0);
}
return phytium_cpu_id_mapping(cpu_id);
};
#else
int rt_hw_cpu_id(void)
{
FError ret;
u32 cpu_id;
ret = GetCpuId(&cpu_id);
if (ret != ERR_SUCCESS)
{
RT_ASSERT(0);
}
return phytium_cpu_id_mapping(cpu_id);
};
rt_uint64_t get_main_cpu_affval(void)
{
#if defined(TARGET_E2000Q)
return CORE2_AFF;
#else
return CORE0_AFF;
#endif
}
extern u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list);
rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list)
{
return GetCpuMaskToAffval(cpu_mask, cluster_id, target_list);
}
#ifdef RT_USING_SMP
void send_core_isg(void)
{
for (rt_size_t i = 0; i <= 0xf; i++)
{
/* code */
rt_kprintf("i %x \r\n", i);
arm_gic_send_affinity_sgi(0, 0, i, 0);
rt_thread_mdelay(100);
}
}
MSH_CMD_EXPORT(send_core_isg, send_core_isg);
#endif
#endif

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#ifndef __PHYTIUM_CPU_H__
#define __PHYTIUM_CPU_H__
#include <rthw.h>
#include <rtthread.h>
#include "fparameters.h"
#define ARM_GIC_MAX_NR 1
#define MAX_HANDLERS 160
#define GIC_IRQ_START 0
#define GIC_ACK_INTID_MASK 0x000003ff
rt_uint64_t get_main_cpu_affval(void);
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
return GICV3_DISTRIBUTOR_BASEADDRESS;
}
#if defined(TARGET_ARMV8_AARCH64)
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_redist_base(void)
{
extern int phytium_cpu_id(void);
s32 cpu_offset = 0;
#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
#endif
#if defined(TARGET_E2000Q)
u32 cpu_id = 0;
cpu_id = phytium_cpu_id();
switch (cpu_id)
{
case 0:
case 1:
cpu_offset = 2;
break;
case 2:
case 3:
cpu_offset = -2;
default:
break;
}
#endif
rt_kprintf("offset is %x\n", cpu_offset);
return (GICV3_RD_BASEADDRESS + (cpu_offset) * GICV3_RD_OFFSET);
}
rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
{
return 0U; /* unused in gicv3 */
}
#endif
int phytium_cpu_id_mapping(int cpu_id);
#endif // !

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
* 2022-10-26 zhugengyu support aarch64
*
*/
#include <rtthread.h>
#include "board.h"
#include <gicv3.h>
#include "rtconfig.h"
#include "phytium_cpu.h"
#if defined(TARGET_ARMV8_AARCH64)
#include "cpuport.h"
#include "gtimer.h"
#include "mmu.h"
#endif
#ifdef RT_USING_SMP
#include <interrupt.h>
#if defined(TARGET_ARMV8_AARCH64)
#include "psci.h"
#endif
#include "fpsci.h"
rt_uint64_t rt_cpu_mpidr_early[] =
{
#if defined(TARGET_E2000D)
[0] = 0x80000200,
[1] = 0x80000201,
#elif defined(TARGET_E2000Q)
[0] = 0x80000200,
[1] = 0x80000201,
[2] = 0x80000000,
[3] = 0x80000100,
#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
[0] = 0x80000000,
[1] = 0x80000001,
[2] = 0x80000100,
[3] = 0x80000101,
#if defined(TARGET_D2000)
[4] = 0x80000200,
[5] = 0x80000201,
[6] = 0x80000300,
[7] = 0x80000301,
#endif
#endif
};
extern int rt_hw_timer_init(void);
extern void secondary_cpu_start(void);
void rt_hw_secondary_cpu_up(void)
{
rt_uint32_t i;
rt_uint32_t cpu_mask = 0;
rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
for (i = 1; i < RT_CPUS_NR; i++)
{
cpu_mask = 1 << phytium_cpu_id_mapping(i);
/* code */
PsciCpuOn(cpu_mask, (uintptr)secondary_cpu_start);
#if defined(TARGET_ARMV8_AARCH64)
__DSB();
#else
__asm__ volatile("dsb" ::: "memory");
#endif
}
}
void secondary_cpu_c_start(void)
{
/* mmu init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_mmu_init();
#endif
/* spin lock init */
rt_hw_spin_lock(&_cpus_lock);
/* interrupt init */
#if defined(TARGET_ARMV8_AARCH64)
arm_gic_cpu_init(0, platform_get_gic_cpu_base());
arm_gic_redist_init(0, platform_get_gic_redist_base());
#else
arm_gic_cpu_init(0);
arm_gic_redist_init(0);
#endif
/* vector init */
rt_hw_vector_init();
/* gtimer init */
#if defined(TARGET_ARMV8_AARCH64)
rt_hw_gtimer_local_enable();
#else
rt_hw_timer_init();
#endif
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
/* start scheduler */
rt_kprintf("\rcall cpu %d on success\n", rt_hw_cpu_id());
rt_hw_secondary_cpu_idle_exec();
rt_system_scheduler_start();
}
void rt_hw_secondary_cpu_idle_exec(void)
{
#if defined(TARGET_ARMV8_AARCH64)
__WFE();
#else
asm volatile("wfe" ::
: "memory", "cc");
#endif
}
#endif

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import os
from building import *
objs = []
cwd = GetCurrentDir()
STANDALONE_DIR = cwd + '/standalone'
# common source
src = Glob(STANDALONE_DIR+'/common/*.c')
path = [STANDALONE_DIR + '/common']
# arch
path += [STANDALONE_DIR + '/arch/common']
if GetDepend(['TARGET_ARMV8_AARCH32']):
src += Glob(STANDALONE_DIR+'/arch/armv8/aarch32/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch32/gcc/*.S')
path += [STANDALONE_DIR + '/arch/armv8/aarch32']
elif GetDepend(['TARGET_ARMV8_AARCH64']):
src += Glob(STANDALONE_DIR+'/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch64/gcc/*.S')
path += [STANDALONE_DIR + '/arch/armv8/aarch64']
# board
src += Glob(STANDALONE_DIR+'/board/common/*.c') + Glob(STANDALONE_DIR+'/board/common/*.S')
path += [STANDALONE_DIR + '/board/common']
if GetDepend(['TARGET_F2000_4']):
src += Glob(STANDALONE_DIR+'/board/ft2004/*.c')
path += [STANDALONE_DIR + '/board/ft2004']
if GetDepend(['TARGET_E2000']):
src += Glob(STANDALONE_DIR+'/board/e2000/*.c')
path += [STANDALONE_DIR + '/board/e2000']
if GetDepend(['TARGET_E2000Q']):
src += Glob(STANDALONE_DIR+'/board/e2000/q/*.c')
path += [STANDALONE_DIR + '/board/e2000/q']
if GetDepend(['TARGET_E2000D']):
src += Glob(STANDALONE_DIR+'/board/e2000/d/*.c')
path += [STANDALONE_DIR + '/board/e2000/d']
if GetDepend(['ARGET_E2000S']):
src += Glob(STANDALONE_DIR+'/board/e2000/s/*.c')
path += [STANDALONE_DIR + '/board/e2000/s']
if GetDepend(['TARGET_D2000']):
src += Glob(STANDALONE_DIR+'/board/d2000/*.c')
path += [STANDALONE_DIR + '/board/d2000']
# driver
## serial
if GetDepend(['ENABLE_Pl011_UART']):
src += Glob(STANDALONE_DIR+'/drivers/serial/fpl011/*.c')
path += [STANDALONE_DIR + '/drivers/serial/fpl011']
## gicv3
if GetDepend(['ENABLE_GICV3']):
src += Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.c') + Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.S')
path += [STANDALONE_DIR + '/drivers/gic/fgic']
# phytium ports rt-thread drivers
PORT_DRV_DIR = cwd + '/drivers'
src += Glob(PORT_DRV_DIR + '/*.S')
src += Glob(PORT_DRV_DIR + '/*.c')
ASFLAGS = ''
group = DefineGroup('FT_DRIVER', src, depend=[
''], CPPPATH=path, ASFLAGS = ASFLAGS)
Return('group')

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menu "Hardware Drivers"
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select USE_SERIAL # sdk serial component
select ENABLE_Pl011_UART # select sdk pl011 driver
select RT_USING_SERIAL
if BSP_USING_UART
config RT_USING_UART1
bool "Enable UART1"
default y
config RT_USING_UART0
bool "Enable UART0"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#include "board.h"
#include "drv_usart.h"
#include "interrupt.h"
#include "fpl011.h"
#include "rtconfig.h"
#include "fprintk.h"
#ifdef RT_USING_SERIAL
extern u32 FUart_GetInterruptMask(FPl011 *uart_ptr);
static void Ft_Os_Uart_Callback(void *Args, u32 Event, u32 EventData);
static void rt_hw_uart_isr(int irqno, void *param)
{
FPl011InterruptHandler(irqno, param);
}
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct drv_usart *uart = RT_NULL;
FPl011 *uart_hw = RT_NULL;
u32 intr_mask;
FPl011Config config;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct drv_usart, serial);
uart_hw = uart->handle;
config = *(const FPl011Config *)FPl011LookupConfig(uart->config.uart_instance);
RT_ASSERT(FPl011CfgInitialize(uart_hw, &config) == FT_SUCCESS);
FPl011SetHandler(uart_hw, Ft_Os_Uart_Callback, serial);
FPl011SetRxFifoThreadhold(uart_hw, FPL011IFLS_RXIFLSEL_1_4);
FPl011SetTxFifoThreadHold(uart_hw, FPL011IFLS_TXIFLSEL_1_2);
//<! 打开接收中断
intr_mask = uart->config.isr_event_mask;
FPl011SetInterruptMask(uart_hw, intr_mask);
FPl011SetOptions(uart_hw, FPL011_OPTION_UARTEN | FPL011_OPTION_RXEN | FPL011_OPTION_TXEN | FPL011_OPTION_FIFOEN);
rt_hw_interrupt_set_priority(uart_hw->config.irq_num, uart->config.isr_priority);
rt_hw_interrupt_install(uart_hw->config.irq_num, rt_hw_uart_isr, uart_hw, "uart");
rt_hw_interrupt_umask(uart_hw->config.irq_num);
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct drv_usart *uart = RT_NULL;
FPl011 *uart_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct drv_usart, serial);
uart_ptr = uart->handle;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
rt_hw_interrupt_mask(uart_ptr->config.irq_num);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
rt_hw_interrupt_umask(uart_ptr->config.irq_num);
break;
}
return RT_EOK;
}
static void Ft_Os_Uart_Callback(void *Args, u32 Event, u32 EventData)
{
struct rt_serial_device *serial = (struct rt_serial_device *)Args;
if (FPL011_EVENT_RECV_DATA == Event || FPL011_EVENT_RECV_TOUT == Event)
{
if (serial->serial_rx)
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
else if (FPL011_EVENT_RECV_ERROR == Event)
{
}
else if (FPL011_EVENT_SENT_DATA == Event)
{
}
else if (FPL011_EVENT_PARE_FRAME_BRKE == Event)
{
}
else if (FPL011_EVENT_RECV_ORERR == Event)
{
}
if (FPL011_EVENT_SENT_DATA == Event)
{
}
else
{
}
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct drv_usart *uart = RT_NULL;
FPl011 *uart_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct drv_usart, serial);
uart_ptr = uart->handle;
FPl011SendByte(uart_ptr->config.base_address, c);
return 1;
}
u8 FPl011RecvByteNoBlocking(u32 addr)
{
u32 recieved_byte;
while (FUART_ISRECEIVEDATA(addr))
{
return 0xff;
}
recieved_byte = FUART_READREG32(addr, FPL011DR_OFFSET);
return recieved_byte;
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch;
struct drv_usart *uart = RT_NULL;
FPl011 *uart_ptr = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct drv_usart, serial);
uart_ptr = uart->handle;
ch = FPl011RecvByteNoBlocking(uart_ptr->config.base_address);
if (ch == 0xff)
{
ch = -1;
rt_kprintf("") ;
}
else
{
//
}
return ch;
}
static const struct rt_uart_ops _uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
NULL
};
#define RT_USING_UART0
#define RT_USING_UART1
#ifdef RT_USING_UART0
static FPl011 Ft_Uart0;
static struct drv_usart _RtUart0;
#endif
#ifdef RT_USING_UART1
static FPl011 Ft_Uart1;
static struct drv_usart _RtUart1;
#endif
int rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
config.bufsz = RT_SERIAL_RB_BUFSZ;
_RtUart0.serial.ops = &_uart_ops;
_RtUart0.serial.config = config;
// Ft_Uart0.config.instance_id = FUART0_ID;
_RtUart0.handle = &Ft_Uart0;
_RtUart0.config.uart_instance = FUART0_ID;
_RtUart0.config.isr_priority = 0xd0;
_RtUart0.config.isr_event_mask = (RTOS_UART_ISR_OEIM_MASK | RTOS_UART_ISR_BEIM_MASK | RTOS_UART_ISR_PEIM_MASK | RTOS_UART_ISR_FEIM_MASK | RTOS_UART_ISR_RTIM_MASK | RTOS_UART_ISR_RXIM_MASK);
_RtUart0.config.uart_baudrate = 115200;
rt_hw_serial_register(&_RtUart0.serial, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&_RtUart0);
#endif
#ifdef RT_USING_UART1
config.bufsz = RT_SERIAL_RB_BUFSZ;
_RtUart1.serial.ops = &_uart_ops;
_RtUart1.serial.config = config;
// Ft_Uart1.config.instance_id = FUART1_ID;
_RtUart1.handle = &Ft_Uart1;
_RtUart1.config.uart_instance = FUART1_ID;
_RtUart1.config.isr_priority = 0xd0;
_RtUart1.config.isr_event_mask = (RTOS_UART_ISR_OEIM_MASK | RTOS_UART_ISR_BEIM_MASK | RTOS_UART_ISR_PEIM_MASK | RTOS_UART_ISR_FEIM_MASK | RTOS_UART_ISR_RTIM_MASK | RTOS_UART_ISR_RXIM_MASK);
_RtUart1.config.uart_baudrate = 115200;
rt_hw_serial_register(&_RtUart1.serial, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&_RtUart1);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
#endif /* RT_USING_SERIAL */

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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Email: opensource_embedded@phytium.com.cn
*
* Change Logs:
* Date Author Notes
* 2022-10-26 huanghe first commit
*
*/
#ifndef __DRV_USART_H__
#define __DRV_USART_H__
#include <rtthread.h>
#include "rtdevice.h"
#include "fpl011.h"
#include "fpl011_hw.h"
#define RTOS_UART_ISR_OEIM_MASK FPL011IMSC_OEIM /* Overrun error interrupt mask. */
#define RTOS_UART_ISR_BEIM_MASK FPL011IMSC_BEIM /* Break error interrupt mask */
#define RTOS_UART_ISR_PEIM_MASK FPL011IMSC_PEIM /* Parity error interrupt mask. */
#define RTOS_UART_ISR_FEIM_MASK FPL011IMSC_FEIM /* Framing error interrupt mask. */
#define RTOS_UART_ISR_RTIM_MASK FPL011IMSC_RTIM /* Receive timeout interrupt mask. */
#define RTOS_UART_ISR_TXIM_MASK FPL011IMSC_TXIM /* Transmit interrupt mask. */
#define RTOS_UART_ISR_RXIM_MASK FPL011IMSC_RXIM /* Receive interrupt mask. */
typedef struct
{
u32 uart_instance; /* select uart global object */
u32 isr_priority; /* irq Priority */
u32 isr_event_mask; /* followed by RTOS_UART_ISR_XX */
u32 uart_baudrate;
} FtFreertosUartConfig;
struct drv_usart
{
FPl011 *handle;
FtFreertosUartConfig config;
struct rt_serial_device serial;
};
#endif // !

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Phytium Public License 1.0 (PPL-1.0)
UNLESS IT HAS ITS OWN COPYRIGHT/LICENSE EMBEDDED IN ITS BODY, EACH FILE IS SUBJECT TO THE FOLLOWING LICENSE TERMS
Copyright (C) 2022, Phytium Technology Co., Ltd.
All Rights Reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that
the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
the following disclaimer in the documentation and/or other materials provided with the distribution.
3. If the name of phytium or the names of its contributors are needed to endorse or promote products
derived from this software ,Prior written permission should be required.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

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# Phytium-Standalone-SDK
**v0.3.1** [ReleaseNote](./doc/ChangeLog.md)
## 1. 项目概要
### 1.1 基本介绍
本项目发布了 Phytium 系列 CPU 的 嵌入式软件开发工具包，包括板级支持包、第三方开源中间件、交叉编译构建工具、及其 Baremetal 参考例程，在支持多平台裸机应用开发的基础上，能够为多种RTOS提供外设驱动和配置构建工具。
![LetterShell](./doc/fig/letter_shell.png)
### 1.2 系统架构
本项目的整体设计如下所示，自下而上可以分为平台层、组件层、框架层和应用层。
![Framework](./doc/design/system_2.png)
- 平台层（Platform）在整个软件框架中位于最底层，提供了基本数据结构类型定义、驱动参数标定、硬件平台耦合的寄存器自检、板级启动、CPU 内存虚拟等功能
- 组件层（Component）在整个软件框架中位于中间位置，向下依赖于平台层提供的参数配置与内存方案，向上提供应用开发与模块测试的支持
- 框架层（Framework）为开发主机提供了开发环境，支持SDK安装，应用工程配置和二进制文件构建及烧录等工具。
- 应用层（Application）提供了应用开发模板和例程，帮助开发者迅速熟悉SDK的使用，进行不同类型的应用程序开发
### 1.3. 源代码结构
```
.
├── Kconfig --> 配置定义
├── LICENSE --> 版权声明
├── README.md --> 使用说明
├── arch
│   └── armv8 --> 架构相关
├── baremetal
│   └── example --> 裸机例程
├── board
│   ├── d2000
│   ├── e2000
│   └── ft2004 --> 平台相关
├── common
│   ├── fprintf.c
│   ├── fprintf.h
│   ├── fsleep.c
│   └── fsleep.h --> 通用方法
├── configs
│   ├── ft2004_aarch32_defconfig
│   └── ft2004_aarch64_defconfig --> 各平台默认配置
├── doc
│   ├── ChangeLog.md --> 修改记录
│   └── reference --> 接口说明文档
├── drivers
│   ├── can
│   ├── dma
│   └── watchdog --> 外设驱动
├── install.py --> 安装脚本
├── lib
│   ├── Kconfiglib
│   ├── lib.mk
│   ├── libc
│   └── nostdlib --> 依赖库
├── make
│   ├── build_baremetal.mk
│   ├── buildinfo.mk
│   ├── complier.mk
│   └── preconfig.mk --> 编译脚本和链接脚本
├── requirements.txt --> python环境依赖组件
├── scripts
├── standalone.mk
├── third-party
│   └── letter-shell-3.1 --> 第三方库
├── tools
```
---
## 2. 快速入门
- 目前支持在Windows和Linux上使用SDK，支持在x86_64和ARM AARCH64设备上完成交叉编译
![windows](./doc/fig/windows.png)![linux](./doc/fig/linux.png)![输入图片说明](./doc/fig/kylin.png)
- 参考[Windows10 快速入门](./doc/reference/usr/install_windows.md), [Linux x86_64 快速入门](./doc/reference/usr/install_linux_x86_64.md)
- 参考[使用说明](./doc/reference/usr/usage.md), 新建Phytium Standalone SDK的应用工程，与开发板建立连接
- 参考[例程](./baremetal/example)，开始使用SDK
---
## 3. 硬件参考
### 3.1 FT2000-4
FT-2000/4 是一款面向桌面应用的高性能通用 4 核处理器。每 2 个核构成 1 个处理器核簇（Cluster），并共享 L2 Cache。主要技术特征如下：
- 兼容 ARM v8 64 位指令系统，兼容 32 位指令
- 支持单精度、双精度浮点运算指令
- 支持 ASIMD 处理指令
- 集成 2 个 DDR4 通道，可对 DDR 存储数据进行实时加密
- 集成 34 Lane PCIE3.0 接口：2 个 X16（每个可拆分成 2 个 X8），2 个 X1
- 集成 2 个 GMAC，RGMII 接口，支持 10/100/1000 自适应
- 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
- 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
- 集成 SM2、SM3、SM4 模块
- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通 用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成温度传感器
### 3.2 D2000
D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个核构成 1 个处理器核簇（Cluster），并共享 L2 Cache。存储系统包含 Cache 子系统和 DDR，I/O 系统包含 PCIe、高速 IO 子系统、千兆位以太网 GMAC 和低速 IO 子系统，主要技术特征如下，
- 兼容 ARM v8 64 位指令系统，兼容 32 位指令
- 支持单精度、双精度浮点运算指令
- 支持 ASIMD 处理指令
- 集成 2 个 DDR 通道，支持 DDR4 和 LPDDR4，可对 DDR 存储数据进行实时加密
- 集成 34 Lane PCIE3.0 接口：2 个 X16（每个可拆分成 2 个 X8），2 个 X1
- 集成 2 个 GMAC，RGMII 接口，支持 10/100/1000 自适应
- 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
- 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
- 集成 SM2、SM3、SM4、SM9 模块
- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
- 集成 2 个温度传感器
### 3.3 E2000D
- E2000D 1个cluster有2个cpu，共两核。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 支持单精度、双精度浮点运算指令
- L1有32KB，L2有256KB
- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
- 集成4 Lane PCIE3.0 接口（4X1）
- 集成网络接口4x1000M SGMII，1路支持RGMII/RMII，支持1路TSN
- 集成2个USB2.0(OTG)接口
- 集成1个HDAudio，支持音频输出;2路DP显示接口
- 集成2路SATA3.0模块
- 集成常用低速接口：WDT，DMAC，QSPI，PWM，Nand，SD/SDIO/eMMC ，SPI_M，UART，I2C，MIO，CAN， LPC_M_S，GPIO，LBC，Timer
### 3.4 E2000S
- E2000S 1个cluster有1个cpu，单核结构。主要技术特征如下：
- 兼容ARM v8 64 位指令系统，兼容32 位指令
- 支持单精度、双精度浮点运算指令
- L1有32KB，L2有256KB
- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
- 集成2 Lane PCIE3.0 接口（2X1）
- 集成网络接口2x1000M SGMII/RGMII/RMII，支持2路NCSI
- 集成2个USB2.0(OTG)接口
- 集成1个HDAudio，支持音频输出;2路DP显示接口
- 集成JPEG Encoder模块
- 集成常用低速接口：WDT，DMAC，PWM，QSPI，SD/SDIO/eMMC，SPI_M，UART，I2C，MIO，I3C，PMBUS， LPC_M_S，GPIO，oneWire，Timer
## 4 外设驱动支持情况
| Hardware Interface | Platform Supported | Platform Developing | Component |
| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
| Generic Intrrupt Controller v3 | FT2000/4<br>E2000<br>D2000 | | gic/fgic |
| Generic Timer | FT2000/4<br>E2000<br>D2000 | | generic_timer |
| UART (PrimeCell PL011) | FT2000/4<br>E2000<br>D2000 | | usart/pl011_uart |
| 10/100/1000MB-ETHERNET | FT2000/4<br>E2000<br>D2000 | | eth/fgmac<br>eth/fxmac |
| ADC | E2000 | | adc/fadc |
| CAN | FT2000/4<br>E2000<br>D2000 | | can/fcan |
| DDMA | | E2000 | dma/fddma |
| GDMA | E2000 | | dma/gdma |
| GPIO | FT2000/4<br>E2000<br>D2000 | | gpio/fgpio |
| I2C | FT2000/4<br>E2000<br>D2000 | | i2c/fi2c |
| QSPI (Nor Flash) | FT2000/4<br>E2000<br>D2000 | | qspi/fqspi |
| SPI | FT2000/4<br>E2000<br>D2000 | | spi/fspim |
| TIMER & TACHO | E2000 | | timer/ftimer_tacho |
| MIO | E2000 | | mio/fmio |
| SDMMC | | FT2000/4<br>D2000 | mmc/fsdmmc |
| SDIO | E2000 | | mmc/fsdio |
| PCIE | FT2000/4<br>D2000<br>E2000 | | pcie/fpcie |
| NAND | E2000 | | nand/fnand |
| RTC | FT2000/4<br>D2000 | | rtc/frtc |
| SATA | FT2000/4<br>D2000<br>E2000 | | sata/fsata |
| USB-PCI | | FT2000/4<br>E2000<br>D2000 | usb/fxhci |
| PWM | E2000 | | pwm/fpwm |
| WDT | FT2000/4<br>D2000<br>E2000 | | watchdog/fwdt |
| Third-Party | Platform Supported | Platform Developing | Component |
| ------------------------------ | -------------------------- | --------------------------- | ------------------------- |
| LWIP 2.1.2 | FT2000/4<br>D2000<br>E2000 | | lwip-2.1.2 |
| Letter shell 3.1 | FT2000/4<br>D2000<br>E2000 | | letter-shell-3.1 |
| Sdmmc | FT2000/4<br>D2000 | | sdmmc |
| Sfud 1.1.0 | FT2000/4<br>D2000<br>E2000 | | sfud-1.1.0 |
| Backtrace | FT2000/4<br>D2000<br>E2000 | | backtrace |
| Tlsf | FT2000/4<br>D2000<br>E2000 | | tlsf-3.1.0 |
| Fatfs (RAM/Sd/SATA) | FT2000/4<br>D2000<br>E2000 | | fatfs-0.1.3 |
| Ymodem | FT2000/4<br>D2000<br>E2000 | | |
| OpenAMP | FT2000/4<br>D2000<br>E2000 | | openamp |
| LittleFS-2.4.2 | | FT2000/4<br>E2000<br>D2000 | littlefs-2.4.2 |
| SPIFFS-0.3.7 | FT2000/4<br>D2000<br>E2000 | | spiffs-0.3.7 |
---
## 5. API指南
### 5.1 DRIVERS
#### 5.1.1 [FI2C](./doc/reference/driver/fi2c.md)
#### 5.1.2 [FPL011](./doc/reference/driver/fpl011.md)
#### 5.1.3 [FRTC](./doc/reference/driver/frtc.md)
#### 5.1.4 [FWDT](./doc/reference/driver/fwdt.md)
#### 5.1.5 [FSPIM](./doc/reference/driver/fspim.md)
#### 5.1.6 [FQSPI](./doc/reference/driver/fqspi.md)
#### 5.1.7 [FSDMMC](./doc/reference/driver/fsdmmc.md)
#### 5.1.8 [FSATA](./doc/reference/driver/fsata.md)
#### 5.1.9 [FPCIE](./doc/reference/driver/fpcie.md)
#### 5.1.10 [FUSB](./doc/reference/driver/fusb.md)
#### 5.1.11 [FGPIO](./doc/reference/driver/fgpio.md)
#### 5.1.12 [FGIC](./doc/reference/driver/fgic.md)
#### 5.1.13 [FDDMA](./doc/reference/driver/fddma.md)
#### 5.1.14 [FCAN](./doc/reference/driver/fcan.md)
#### 5.1.15 [FADC](./doc/reference/driver/fadc.md)
#### 5.1.16 [FPWM](./doc/reference/driver/fpwm.md)
#### 5.1.17 [FSDIO](./doc/reference/driver/fsdio.md)
### 5.2 MEMORY
#### 5.2.1 [FMEMORY_POOL](./doc/reference/sdk/fmemory_pool.md)
### 5.3 CPU
#### 5.3.1 [MMU](./doc/reference/processor/mmu.md)
#### 5.3.2 [FPINCTRL](./doc/reference/sdk/fpinctrl.md)
#### 5.3.2 [INTERRUPT](./doc/reference/processor/interrupt.md)
---
## 6. 贡献方法
请联系飞腾嵌入式软件部
huanghe@phytium.com.cn
zhugengyu@phytium.com.cn
wangxiaodong1030@phytium.com.cn
liushengming1118@phytium.com.cn
---
## 6. 相关资源
- ARM Architecture Reference Manual
- ARM Cortex-A Series Programmer’s Guide
- Programmer Guide for ARMv8-A
- ARM System Developers Guide Designing and Optimizing System Software
- FT-2000／4 软件编程手册-V1.4
- D2000 软件编程手册-V1.0
- Bare-metal programming for ARM —— A hands-on guide
- Using the GNU Compiler Collection
- Using ld, The GNU Linker
- Using as, The GNU Assembler
- Armv8-A memory model guide
---
## 7. 许可协议
Phytium Public License 1.0 (PPL-1.0)

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: faarch32.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:28:37
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 Huanghe 2021/7/3 init
* 1.1 Wangxiaodong 2021/9/24 modify sys_icc_bpr_set and sys_icc_bpr_get
*/
#ifndef BSP_AARCH32_ASM_H
#define BSP_AARCH32_ASM_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#define __ASM __asm
#define __STATIC_INLINE static inline
#define __STRINGIFY(x) #x
/* C语言实现MCR指令 */
#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \
__ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
: \
: "r"(src) \
: "memory");
/* C语言实现MRC指令 */
#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \
( \
{ \
u32 __dst; \
__ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
: "=r"(__dst)::"memory"); \
__dst; \
})
/* C语言实现MRRC指令 */
#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) ( \
{ \
__asm__ __volatile__( \
"MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \
"%0,%1," __STRINGIFY(c##CRm) \
: "=r"(dst_1), "=r"(dst_2)); \
})
/**
* @name: aarch32_cntp_ctl_get
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void)
{
/* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m) 1(opcode2) */
return __MRC(15, 0, 14, 2, 1);
}
/**
* @name: aarch32_cntp_tlb_get
* @msg:
* @return {*}
* @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void)
{
return __MRC(15, 0, 0, 2, 0);
}
/**
* @name: aarch32_cntp_ctl_set
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal)
{
/* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m) 1(opcode2) */
__MCR(15, 0, regVal, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntfrq_get
* @msg: This register is provided so that software can discover the frequency of the system counter.
* @return {__STATIC_INLINEu32}: frequency of the system counter
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void)
{
return __MRC(15, 0, 14, 0, 0);
}
/**
* @name: aarch32_cntpct_get
* @msg: get the 64-bit physical count value
* @return {*}
* @param {__STATIC_INLINE u64} aarch32_cntpct_get
*/
__attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get()
{
u64 cnt = 0;
u32 cnt_low = 0, cnt_high = 0;
__MRRC(15, 0, cnt_low, cnt_high, 14);
cnt = (u64)cnt_high << 32 | cnt_low;
return cnt;
}
/**
* @name: aarch32_cntp_tval_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 0);
}
/**
* @name: aarch32_sctrl_get
* @msg: read the register that control system
*/
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get()
{
return __MRC(15, 0, 1, 0, 0);
}
/**
* @name: aarch32_sctrl_set
* @msg: read the register that control system
*/
#define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */
__attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal)
{
__MCR(15, 0, RegVal, 1, 0, 0);
}
/**********************************************/
__attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void)
{
return __MRC(15, 0, 12, 0, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar)
{
__MCR(15, 0, vbar, 12, 0, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 6);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void)
{
return __MRC(15, 0, 12, 12, 6);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 7);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void)
{
return __MRC(15, 0, 12, 12, 7);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 4);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void)
{
return __MRC(15, 0, 12, 12, 4);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void)
{
return __MRC(15, 0, 12, 8, 2);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 3);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void)
{
return __MRC(15, 0, 12, 12, 3);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void)
{
return __MRC(15, 0, 12, 12, 2);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value)
{
__MCR(15, 0, value, 12, 8, 1);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 1);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value)
{
__MCR(15, 0, value, 4, 6, 0);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void)
{
return __MRC(15, 0, 4, 6, 0);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void)
{
return __MRC(15, 0, 12, 12, 0);
}
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value)
{
__MCR(15, 0, value, 12, 12, 5);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void)
{
return __MRC(15, 0, 12, 12, 5);
}
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void)
{
return __MRC(15, 0, 12, 11, 3);
}
/* Generic Timer registers */
/**
* @name: arm_aarch32_cntfrq_get
* @msg: This register is provided so that software can discover the frequency of the system counter.
* @return {__STATIC_INLINEu32}: frequency of the system counter
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void)
{
return __MRC(15, 0, 14, 0, 0);
}
/* arm_aarch32_cnttimer_set */
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 2);
}
/**
* @name: arm_aarch32_cnthv_tval_get
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
* @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void)
{
return __MRC(15, 0, 14, 3, 0);
}
/**
* @name: arm_aarch32_cnthv_ctl_set
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
* @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 3, 1);
}
/**
* @name: arm_aarch32_cnthv_ctl_get
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer.
* @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit.
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void)
{
return __MRC(15, 0, 14, 3, 1);
}
/**
* @name: arm_aarch32_cnthv_tval_set
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 3, 0);
}
/**
* @name: arm_aarch32_cntvct_get
* @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF.
* @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value.
*/
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void)
{
/* "r0" --- low,
"r1" --- hi
*/
u32 low;
u32 hi;
__asm__ volatile(
".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */
"mov %0, r0 \n"
"mov %1, r1 \n"
: "=&r"(low), "=&r"(hi));
return (((u64)hi) << 32) | low;
}
/* physical */
/**
* @name: arm_aarch32_cntp_tval_get
* @msg: Read the register that holds the timer value for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void)
{
return __MRC(15, 0, 14, 2, 0);
}
/**
* @name: arm_aarch32_cntp_tval_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 0);
}
/**
* @name: arm_aarch32_cntp_ctl_set
* @msg: write the register that control register for the EL1 physical timer.
* @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
*/
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue)
{
__MCR(15, 0, RegValue, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntp_ctl_get
* @msg: Read the register that control register for the EL1 physical timer.
* @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
*/
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void)
{
return __MRC(15, 0, 14, 2, 1);
}
/**
* @name: arm_aarch32_cntpct_get
* @msg: Read the register that holds the 64-bit physical count value.
* @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value.
*/
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void)
{
/* "r0" --- low,
"r1" --- hi
*/
u32 low;
u32 hi;
__asm__ volatile(
".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */
"mov %0, r0 \n"
"mov %1, r1 \n"
: "=&r"(low), "=&r"(hi));
return (((u64)hi) << 32) | low;
}
#define INTERRUPT_DISABLE() \
__asm volatile("CPSID i" :: \
: "memory"); \
__asm volatile("DSB"); \
__asm volatile("ISB");
#define INTERRUPT_ENABLE() \
__asm volatile("CPSIE i" :: \
: "memory"); \
__asm volatile("DSB"); \
__asm volatile("ISB");
#ifdef __cplusplus
}
#endif
#endif // !

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: generic_timer.c
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:07
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fparameters.h"
#include "fgeneric_timer.h"
#include "faarch32.h"
#include "sdkconfig.h"
#ifndef SDK_CONFIG_H__
#warning "Please include sdkconfig.h"
#endif
#ifdef CONFIG_USE_SYS_TICK
#include "fassert.h"
#include "finterrupt.h"
static volatile u32 genericTick;
static GenericTimerTickHandler usr_tick_handler = NULL;
#endif
#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0)
#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1)
void GenericTimerStart(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
{
ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerStop(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
{
ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerInterruptEnable(void)
{
u32 ctrl = aarch32_cntp_ctl_get();
if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)
{
ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
void GenericTimerInterruptDisable(void)
{
u64 ctrl = aarch32_cntp_ctl_get();
if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK))
{
ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK;
aarch32_cntp_ctl_set(ctrl);
}
}
u32 GenericTimerFrequecy(void)
{
u32 rate = aarch32_cntfrq_get();
return (rate != 0) ? rate : 1000000;
}
u64 GenericTimerRead(void)
{
return aarch32_cntpct_get();
}
void GenericTimerCompare(u32 interval)
{
aarch32_cntp_tval_set(interval);
}
#ifdef CONFIG_USE_SYS_TICK
static void GenericTimerClearTickIntr(u32 tickRateHz)
{
GenericTimerCompare(GenericTimerFrequecy() / tickRateHz);
}
static void GenericTimerTickIntrHandler(s32 vector, void *param)
{
u32 tickRateHz = (u32)param;
(void)vector;
genericTick++; /* tick */
GenericTimerClearTickIntr(tickRateHz); /* clear tick intrrupt */
if (usr_tick_handler) /* execute user handler */
usr_tick_handler();
}
#endif
void GenericTimerSetupSystick(u32 tickRateHz, GenericTimerTickHandler tickHandler, u32 intrPrority)
{
#ifdef CONFIG_USE_SYS_TICK
u32 cntFrq;
/* disable timer and get system frequency */
GenericTimerStop();
cntFrq = GenericTimerFrequecy();
/* set tick rate */
GenericTimerCompare(cntFrq / tickRateHz);
GenericTimerInterruptEnable();
/* set generic timer intrrupt */
InterruptSetPriority(GENERIC_TIMER_NS_IRQ_NUM, intrPrority);
/* install tick handler */
usr_tick_handler = tickHandler;
InterruptInstall(GENERIC_TIMER_NS_IRQ_NUM, GenericTimerTickIntrHandler,
(void *)tickRateHz, "GenericTimerTick");
/* enable intrrupt */
InterruptUmask(GENERIC_TIMER_NS_IRQ_NUM);
GenericTimerStart();
#endif
}
u32 GenericGetTick(void)
{
#ifdef CONFIG_USE_SYS_TICK
return genericTick;
#else
return 0xffU;
#endif
}

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fgeneric_timer.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:13
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H
#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
typedef void (* GenericTimerTickHandler)();
void GenericTimerStart(void);
void GenericTimerStop(void);
void GenericTimerInterruptEnable(void);
void GenericTimerInterruptDisable(void);
u32 GenericTimerFrequecy(void);
u64 GenericTimerRead(void);
void GenericTimerCompare(u32 interval);
void GenericTimerSetupSystick(u32 tickRateHz, GenericTimerTickHandler tickHandler, u32 intrPrority);
u32 GenericGetTick(void);
#ifdef __cplusplus
}
#endif
#endif // !

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bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: psci.c
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:35
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fpsci.h"
#include "fsmc.h"
#include "fcpu_info.h"
#include "ferror_code.h"
#include "fparameters.h"
#include "ftypes.h"
#define PSCI_CPUON_NUM 0x84000003
#define PSCI_RESET_NUM 0x84000009
/**
* @name: FPsci_CpuOn
* @msg: Power up a core
* @in param cpu_id_mask: cpu id mask
* @in param bootaddr: a 32-bit entry point physical address (or IPA).
* @return FError
*/
FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr)
{
FError ret ;
u64 cluster = 0;
FSmc_Data_t input = {0};
FSmc_Data_t output = {0};
input.function_identifier = PSCI_CPUON_NUM;
ret = GetCpuAffinityByMask(cpu_id_mask, &cluster);
if (ret != ERR_SUCCESS)
{
return ret;
}
input.a1 = cluster;
input.a2 = (u32)(bootaddr & 0xFFFFFFFF);
FSmcCall(&input, &output);
__asm__ volatile("NOP");
return ERR_SUCCESS;
}
void PsciCpuReset(void)
{
FSmc_Data_t input = {0};
FSmc_Data_t output = {0};
input.function_identifier = PSCI_RESET_NUM;
FSmcCall(&input, &output);
__asm__ volatile("NOP");
while (1)
;
}

43
bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fpsci.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:40
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H
#define BSP_ARCH_ARMV8_AARCH32_PSCI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#include "ferror_code.h"
FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr);
void PsciCpuReset(void);
#ifdef __cplusplus
}
#endif
#endif // !

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bsp/phytium/libraries/standalone/arch/armv8/aarch32/fsmc.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fsmc.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:30:49
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H
#define BSP_ARCH_ARMV8_AARCH32_SMC_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
typedef struct
{
/* data */
u32 function_identifier;
u32 a1;
u32 a2;
u32 a3;
u32 a4;
u32 a5;
u32 a6;
} FSmc_Data_t;
void FSmcCall(FSmc_Data_t *Input, FSmc_Data_t *Output);
#ifdef __cplusplus
}
#endif
#endif // !FT_SMC_H

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bsp/phytium/libraries/standalone/arch/armv8/aarch32/gcc/fsmccc_call.S Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: smccc-call.S
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:28:10
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
/*******************************************************************************
*
* FSmcCall - initiate SMC call
*
* This routine initiates SMC call which traps the processor into Monitor Mode.
* The ARM SMC Call Convetion defines that up to eight registers can be exchanged
* during an SMC call. The input parameter contains eight INT32 valeus which are
* to be passed in the SMC call; similarily the output parameter also contains
* eight INT32 values which are returned from the SMC call.
*
* \NOMANUAL
*
* RETURNS: OK
*
* void FSmcCall
* (
* FSmc_Data_t * input, /@ r0 - input register values @/
* FSmc_Data_t * output /@ r1 - output register values @/
* )
*/
.arm
.align 4
.globl FSmcCall
FSmcCall:
STMDB sp!, {r0-r7} /* save clobbered registers to stack */
ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */
ldmia r12, {r0-r7} /* save input argument to r0-r7 */
smc #0
ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */
stmia r12, {r0-r7} /* get output argument from r0-r7 */
ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */
bx lr
.size FSmcCall, .- FSmcCall

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bsp/phytium/libraries/standalone/arch/armv8/aarch64/farm_smccc.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: farm_smccc.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:32:15
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef __LINUX_ARM_SMCCC_H
#define __LINUX_ARM_SMCCC_H
/*
* This file provides common defines for ARM SMC Calling Convention as
* specified in
* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
*/
#define ARM_SMCCC_STD_CALL 0
#define ARM_SMCCC_FAST_CALL 1
#define ARM_SMCCC_TYPE_SHIFT 31
#define ARM_SMCCC_SMC_32 0
#define ARM_SMCCC_SMC_64 1
#define ARM_SMCCC_CALL_CONV_SHIFT 30
#define ARM_SMCCC_OWNER_MASK 0x3F
#define ARM_SMCCC_OWNER_SHIFT 24
#define ARM_SMCCC_FUNC_MASK 0xFFFF
#define ARM_SMCCC_IS_FAST_CALL(smc_val) \
((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
#define ARM_SMCCC_IS_64(smc_val) \
((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK)
#define ARM_SMCCC_OWNER_NUM(smc_val) \
(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)
#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
(((type) << ARM_SMCCC_TYPE_SHIFT) | \
((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
(((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
((func_num)&ARM_SMCCC_FUNC_MASK))
#define ARM_SMCCC_OWNER_ARCH 0
#define ARM_SMCCC_OWNER_CPU 1
#define ARM_SMCCC_OWNER_SIP 2
#define ARM_SMCCC_OWNER_OEM 3
#define ARM_SMCCC_OWNER_STANDARD 4
#define ARM_SMCCC_OWNER_TRUSTED_APP 48
#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49
#define ARM_SMCCC_OWNER_TRUSTED_OS 50
#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63
#define ARM_SMCCC_QUIRK_NONE 0
#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
#ifndef __ASSEMBLY__
#include <stdio.h>
/**
* struct arm_smccc_res - Result from SMC/HVC call
* @a0-a3 result values from registers 0 to 3
*/
struct arm_smccc_res
{
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
};
/**
* struct arm_smccc_quirk - Contains quirk information
* @id: quirk identification
* @state: quirk specific information
* @a6: Qualcomm quirk entry for returning post-smc call contents of a6
*/
struct arm_smccc_quirk
{
int id;
union
{
unsigned long a6;
} state;
};
/**
* __arm_smccc_smc() - make SMC calls
* @a0-a7: arguments passed in registers 0 to 7
* @res: result values from registers 0 to 3
* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
*
* This function is used to make SMC calls following SMC Calling Convention.
* The content of the supplied param are copied to registers 0 to 7 prior
* to the SMC instruction. The return values are updated with the content
* from register 0 to 3 on return from the SMC instruction. An optional
* quirk structure provides vendor specific behavior.
*/
void __arm_smccc_smc(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3, unsigned long a4,
unsigned long a5, unsigned long a6, unsigned long a7,
struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
#endif /*__ASSEMBLY__*/
#endif /*__LINUX_ARM_SMCCC_H*/

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bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: psci.c
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:33:51
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fpsci.h"
#include "farm_smccc.h"
#include "ftypes.h"
#include "fcpu_info.h"
#include "ferror_code.h"
FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr)
{
FError ret ;
u64 cluster = 0;
ret = GetCpuAffinityByMask(cpu_id_mask, &cluster);
if (ret != ERR_SUCCESS)
{
printf("GetCpuAffinity is failed \r\n") ;
return ret ;
}
arm_smccc_smc(0xc4000003, cluster, bootaddr, 0, 0, 0, 0, 0, 0);
return ERR_SUCCESS ;
}
void PsciCpuReset(void)
{
struct arm_smccc_res res;
arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
}

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bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fpsci.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:34:06
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_ARCH_AARMV8_AARCH64_PSCI_H
#define BSP_ARCH_AARMV8_AARCH64_PSCI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#include "ferror_code.h"
void PsciCpuReset(void);
FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr);
#ifdef __cplusplus
}
#endif
#endif // !BSP_ARCH_AARMV8_AARCH64_PSCI_H

49
bsp/phytium/libraries/standalone/arch/armv8/aarch64/gcc/fsmccc_call.S Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: smccc-call.S
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:31:23
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
.macro SMCCC instr
\instr #0
ldr x4, [sp]
stp x0, x1, [x4, #0]
stp x2, x3, [x4, #16]
ldr x4, [sp, #8]
cbz x4, 1f /* no quirk structure */
ldr x9, [x4, #0]
cmp x9, #1
b.ne 1f
str x6, [x4, 4]
1: ret
.endm SMCCC instr
/*
* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
* unsigned long a3, unsigned long a4, unsigned long a5,
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
* struct arm_smccc_quirk *quirk)
*/
.globl __arm_smccc_smc
.type __arm_smccc_smc, "function"
.cfi_startproc
__arm_smccc_smc:
SMCCC smc
.cfi_endproc

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bsp/phytium/libraries/standalone/arch/common/fkernel.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: kernel.h
* Date: 2022-02-10 14:53:41
* LastEditTime: 2022-02-17 17:35:07
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef KERNEL_H
#define KERNEL_H
#ifdef __ASSEMBLY__
#define _AC(X, Y) X
#define _AT(T, X) X
#else
#define __AC(X, Y) (X##Y)
#define _AC(X, Y) __AC(X, Y)
#define _AT(T, X) ((T)(X))
#endif
#define _UL(x) (_AC(x, UL))
#define _ULL(x) (_AC(x, ULL))
#define _BITUL(x) (_UL(1) << (x))
#define _BITULL(x) (_ULL(1) << (x))
#define UL(x) (_UL(x))
#define ULL(x) (_ULL(x))
#define min(x, y) ( \
{ \
typeof(x) _min1 = (x); \
typeof(y) _min2 = (y); \
(void)(&_min1 == &_min2); \
_min1 < _min2 ? _min1 : _min2; \
})
#define max(x, y) ( \
{ \
typeof(x) _max1 = (x); \
typeof(y) _max2 = (y); \
(void)(&_max1 == &_max2); \
_max1 > _max2 ? _max1 : _max2; \
})
#define min3(x, y, z) min((typeof(x))min(x, y), z)
#define max3(x, y, z) max((typeof(x))max(x, y), z)
/**
* clamp - return a value clamped to a given range with strict typechecking
* @val: current value
* @lo: lowest allowable value
* @hi: highest allowable value
*
* This macro does strict typechecking of @lo/@hi to make sure they are of the
* same type as @val. See the unnecessary pointer comparisons.
*/
#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
/**
* do_div - returns 2 values: calculate remainder and update new dividend
* @n: uint64_t dividend (will be updated)
* @base: uint32_t divisor
*
* Summary:
* ``uint32_t remainder = n % base;``
* ``n = n / base;``
*
* Return: (uint32_t)remainder
*
* NOTE: macro parameter @n is evaluated multiple times,
* beware of side effects!
*/
#define do_div(n, base) ( \
{ \
uint32_t __base = (base); \
uint32_t __rem; \
__rem = ((uint64_t)(n)) % __base; \
(n) = ((uint64_t)(n)) / __base; \
__rem; \
})
/* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */
#define roundup(x, y) ( \
{ \
const typeof(y) __y = y; \
((x + (__y - 1)) / __y) * __y; \
})
#define rounddown(x, y) ( \
{ \
typeof(x) __x = (x); \
__x - (__x % (y)); \
})
#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
#if defined(__aarch64__)
#define BITS_PER_LONG 64
#else
#define BITS_PER_LONG 32
#endif
#ifndef BITS_PER_LONG_LONG
#define BITS_PER_LONG_LONG 64
#endif
#define BIT(nr) (1ULL << (nr))
#define BIT_ULL(nr) (1ULL << (nr))
#define BIT_MASK(nr) (BIT(nr) - 1UL)
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG))
#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG)
#define BITS_PER_BYTE 8
#define DIV_ROUND_DOWN_ULL(ll, d) \
({ unsigned long long _tmp = (ll); do_div(_tmp, d); _tmp; })
#define DIV_ROUND_UP_ULL(ll, d) DIV_ROUND_DOWN_ULL((ll) + (d) - 1, (d))
#if BITS_PER_LONG == 32
#define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d)
#else
#define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP(ll,d)
#endif
/*
* Create a contiguous bitmask starting at bit position @l and ending at
* position @h. For example
* GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000.
*/
#define GENMASK(h, l) \
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
#define GENMASK_ULL(h, l) \
(((~0ULL) - (1ULL << (l)) + 1) & \
(~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
#define SZ_1 0x00000001
#define SZ_2 0x00000002
#define SZ_4 0x00000004
#define SZ_8 0x00000008
#define SZ_16 0x00000010
#define SZ_32 0x00000020
#define SZ_64 0x00000040
#define SZ_128 0x00000080
#define SZ_256 0x00000100
#define SZ_512 0x00000200
#define SZ_1K 0x00000400
#define SZ_2K 0x00000800
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_32K 0x00008000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define SZ_2G 0x80000000
#define SZ_3G 0xC0000000
#define SZ_4G 0x100000000ULL
#define SZ_8G 0x200000000ULL
#define NANO_TO_MICRO 1000
#define NANO_TO_KILO 1000000
/**
* UPPER_32_BITS - return bits 32-63 of a number
* @n: the number we're accessing
*
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
* the "right shift count >= width of type" warning when that quantity is
* 32-bits.
* Note that do not input signed int 'n'
*/
#define UPPER_32_BITS(n) ((uint32_t)(((n) >> 16) >> 16))
/**
* LOWER_32_BITS - return bits 0-31 of a number
* @n: the number we're accessing
* Note that do not input signed int 'n'
*/
#define LOWER_32_BITS(n) ((uint32_t)((n)&0xffffffff))
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a)-1)) == 0)
#ifndef __aligned
#define __aligned(x) __attribute__((__aligned__(x)))
#endif
/**
* CONTAINER_OF - return the member address of ptr, if the type of ptr is the
* struct type.
*/
#define CONTAINER_OF(ptr, type, member) \
((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#endif
/* set 32-bit register [a:b] as x, where a is high bit, b is low bit, x is setting/getting value */
#define GET_REG32_BITS(x, a, b) (u32)((((u32)(x)) & GENMASK(a, b)) >> b)
#define SET_REG32_BITS(x, a, b) (u32)((((u32)(x)) << b) & GENMASK(a, b))
/* Integer alignment down */
#define PALIGN_DOWN(x,align) (x & ~(align-1))
/* Integer alignment up */
#define PALIGN_UP(x,align) ((x + (align-1)) & ~(align-1))
#endif

50
bsp/phytium/libraries/standalone/board/Kconfig Normal file
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menu "Board Configuration"
choice BUILD_TARGET_CHIP_TYPE
prompt "Chip"
default TARGET_E2000Q
help
Select chip type for build
config TARGET_F2000_4
bool "FT2000-4"
config TARGET_D2000
bool "D2000"
config TARGET_E2000Q
bool "E2000Q"
select TARGET_E2000
config TARGET_E2000D
bool "E2000D"
select TARGET_E2000
config TARGET_E2000S
bool "E2000S"
select TARGET_E2000
endchoice # BUILD_TARGET_CHIP_TYPE
# an invisible config to define common code of E2000 Q/D/S
config TARGET_E2000
bool
default y if TARGET_E2000Q || TARGET_E2000D || TARGET_E2000S
choice DEBUG_PRINT_UART
prompt "Select Debug uart instance"
default DEFAULT_DEBUG_PRINT_UART1
help
Select arch for build
config DEFAULT_DEBUG_PRINT_UART1
bool "Use uart1"
config DEFAULT_DEBUG_PRINT_UART0
bool "Use uart0"
config DEFAULT_DEBUG_PRINT_UART2
bool "Use uart2"
endchoice # DEBUG_PRINT_UART
endmenu

63
bsp/phytium/libraries/standalone/board/common/fcpu_asm.S Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: _cpu_asm.S
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:57:55
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "sdkconfig.h"
#ifdef CONFIG_TARGET_ARMV8_AARCH64
// ------------------------------------------------------------
.global GetAffinity
//uint32_t GetAffinity(void);
.type GetAffinity, @function
GetAffinity:
MRS x0, MPIDR_EL1
RET
.global ArchSpinLock;
.text;
ArchSpinLock:
mov w2, #1
sevl
1:
wfe
ldaxr w1, [x0]
cbnz w1, 1b
stxr w1, w2, [x0]
cbnz w1, 1b
ret
.global ArchSpinUnlock;
.text;
ArchSpinUnlock:
stlr xzr, [x0]
ret
#else
.globl GetAffinity
GetAffinity:
mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register
bx lr
#endif

264
bsp/phytium/libraries/standalone/board/common/fcpu_info.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: cpu_info.c
* Date: 2022-03-08 19:37:19
* LastEditTime: 2022-03-15 11:18:14
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fcpu_info.h"
#include "ferror_code.h"
#include "fparameters.h"
#include "fprintk.h"
FError GetCpuId(u32 *cpu_id_p)
{
u32 affinity = GetAffinity();
FError ret = ERR_SUCCESS ;
switch (affinity & 0xfff)
{
#ifdef CORE0_AFF
case CORE0_AFF:
*cpu_id_p = 0 ;
break;
#endif
#ifdef CORE1_AFF
case CORE1_AFF:
*cpu_id_p = 1 ;
break;
#endif
#ifdef CORE2_AFF
case CORE2_AFF:
*cpu_id_p = 2;
break;
#endif
#ifdef CORE3_AFF
case CORE3_AFF:
*cpu_id_p = 3 ;
break;
#endif
#ifdef CORE4_AFF
case CORE4_AFF:
*cpu_id_p = 4 ;
break;
#endif
#ifdef CORE5_AFF
case CORE5_AFF:
*cpu_id_p = 5 ;
break;
#endif
#ifdef CORE6_AFF
case CORE6_AFF:
*cpu_id_p = 6 ;
break;
#endif
#ifdef CORE7_AFF
case CORE7_AFF:
*cpu_id_p = 7 ;
break;
#endif
default:
ret = ERR_GENERAL ;
break;
}
return ret;
}
/**
* @name: GetCpuAffinityByMask
* @msg: Determine the cluster information using the CPU ID
* @param {u32} cpu_id cpu id mask .for example : 1 is core0 ,2 is core1 .....
* @param {u64} *affinity_level_p cluster information , format is:
* |--------[bit31-24]-------[bit23-16]-------------[bit15-8]--------[bit7-0]
* |--------Affinity level3-----Affinity level2-----Affinity level1---Affinity level0
* @return {*} ERR_SUCCESS is ok
*/
FError GetCpuAffinityByMask(u32 cpu_id_mask, u64 *affinity_level_p)
{
FError ret = ERR_SUCCESS ;
switch (cpu_id_mask)
{
#ifdef CORE0_AFF
case (1<<0):
*affinity_level_p = CORE0_AFF;
break ;
#endif
#ifdef CORE1_AFF
case (1<<1):
*affinity_level_p = CORE1_AFF;
break ;
#endif
#ifdef CORE2_AFF
case (1<<2):
*affinity_level_p = CORE2_AFF;
break ;
#endif
#ifdef CORE3_AFF
case (1<<3):
*affinity_level_p = CORE3_AFF;
break ;
#endif
#ifdef CORE4_AFF
case (1<<4):
*affinity_level_p = CORE4_AFF;
break ;
#endif
#ifdef CORE5_AFF
case (1<<5):
*affinity_level_p = CORE5_AFF;
break ;
#endif
#ifdef CORE6_AFF
case (1<<6):
*affinity_level_p = CORE6_AFF;
break ;
#endif
#ifdef CORE7_AFF
case (1<<7):
*affinity_level_p = CORE7_AFF;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
}
return ret;
}
/**
* @name: GetCpuAffinity
* @msg: Determine the cluster information using the CPU ID
* @param {u32} cpu_id cpu id .for example : 0 is core0 ,1 is core1 .....
* @param {u64} *affinity_level_p cluster information , format is:
* |--------[bit31-24]-------[bit23-16]-------------[bit15-8]--------[bit7-0]
* |--------Affinity level3-----Affinity level2-----Affinity level1---Affinity level0
* @return {*} ERR_SUCCESS is ok
*/
FError GetCpuAffinity(u32 cpu_id, u64 *affinity_level_p)
{
FError ret = ERR_SUCCESS ;
switch (cpu_id)
{
#ifdef CORE0_AFF
case (0):
*affinity_level_p = CORE0_AFF;
break ;
#endif
#ifdef CORE1_AFF
case (1):
*affinity_level_p = CORE1_AFF;
break ;
#endif
#ifdef CORE2_AFF
case (2):
*affinity_level_p = CORE2_AFF;
break ;
#endif
#ifdef CORE3_AFF
case (3):
*affinity_level_p = CORE3_AFF;
break ;
#endif
#ifdef CORE4_AFF
case (4):
*affinity_level_p = CORE4_AFF;
break ;
#endif
#ifdef CORE5_AFF
case (5):
*affinity_level_p = CORE5_AFF;
break ;
#endif
#ifdef CORE6_AFF
case (6):
*affinity_level_p = CORE6_AFF;
break ;
#endif
#ifdef CORE7_AFF
case (7):
*affinity_level_p = CORE7_AFF;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
}
return ret;
}
/**
* @name: UseAffinityGetCpuId
* @msg: Get the core value from affinity level
* @param {u64} affinity_level is cpu affinity level value
* @param {u32*} cpu_id_p is pointer to get cpu id value
* @return {*} ERR_SUCCESS is ok , ERR_GENERAL is fail
*/
FError UseAffinityGetCpuId(u64 affinity_level, u32 *cpu_id_p)
{
FError ret = ERR_SUCCESS ;
switch (affinity_level)
{
#ifdef CORE0_AFF
case CORE0_AFF:
*cpu_id_p = 0;
break ;
#endif
#ifdef CORE1_AFF
case CORE1_AFF:
*cpu_id_p = 1;
break ;
#endif
#ifdef CORE2_AFF
case CORE2_AFF:
*cpu_id_p = 2;
break ;
#endif
#ifdef CORE3_AFF
case CORE3_AFF:
*cpu_id_p = 3;
break ;
#endif
#ifdef CORE4_AFF
case CORE4_AFF:
*cpu_id_p = 4;
break ;
#endif
#ifdef CORE5_AFF
case CORE5_AFF:
*cpu_id_p = 5;
break ;
#endif
#ifdef CORE6_AFF
case CORE6_AFF:
*cpu_id_p = 6;
break ;
#endif
#ifdef CORE7_AFF
case CORE7_AFF:
*cpu_id_p = 7;
break ;
#endif
default:
ret = ERR_GENERAL;
break;
}
return ret;
}

44
bsp/phytium/libraries/standalone/board/common/fcpu_info.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fcpu_info.h
* Date: 2022-03-08 19:37:19
* LastEditTime: 2022-03-15 11:18:07
* Description:  This file is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BOARD_COMMON_CPU_INFO_H
#define BOARD_COMMON_CPU_INFO_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
#include "ferror_code.h"
u32 GetAffinity(void);
FError GetCpuId(u32 *cpu_id_p);
FError GetCpuAffinity(u32 cpu_id, u64 *cluster_value_p);
FError GetCpuAffinityByMask(u32 cpu_id, u64 *affinity_level_p);
FError UseAffinityGetCpuId(u64 affinity_level, u32 *cpu_id_p);
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list);
#ifdef __cplusplus
}
#endif
#endif // !

34
bsp/phytium/libraries/standalone/board/common/fsmp.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fsmp.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 17:58:18
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_BOARD_COMMON_SMP_H
#define BSP_BOARD_COMMON_SMP_H
#include "ftypes.h"
void SpinLockInit(unsigned long global_addr);
void SpinLock(void);
void SpinUnlock(void);
#endif // DEBUG

269
bsp/phytium/libraries/standalone/board/e2000/d/fiopad.h Normal file
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#ifndef BOARD_E2000D_FIOPAD_H
#define BOARD_E2000D_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

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bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c Normal file
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@ -0,0 +1,562 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fdebug.h"
#include "fpinctrl.h"
#include "fassert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
}
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_3 == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
break;
case 8: /* gpio 3-a-8 */
FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
break;
case 9: /* gpio 3-a-9 */
FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetCanMux
* @msg: set iopad mux for can
* @return {*}
* @param {u32} can_id, instance id of can
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN_INSTANCE_0)
{
/* mio0 */
FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN_INSTANCE_1)
{
/* mio1 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetQspiMux
* @msg: set iopad mux for qspi
* @return {*}
* @param {u32} qspi_id, id of qspi instance
* @param {u32} cs_id, id of qspi cs
*/
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI_INSTANCE_0)
{
/* add sck, io0-io3 iopad multiplex */
}
if (cs_id == FQSPI_CS_0)
{
FPinSetFunc(FIOPAD_AR51, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_1)
{
FPinSetFunc(FIOPAD_AR45, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_2)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC5);
}
else if (cs_id == FQSPI_CS_3)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC5);
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetPwmMux
* @msg: set iopad mux for pwm
* @return {*}
* @param {u32} pwm_id, id of pwm instance
* @param {u32} pwm_channel, channel of pwm instance
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_INSTANCE_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM_INSTANCE_0:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM_INSTANCE_1:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM_INSTANCE_2:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM_INSTANCE_3:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM_INSTANCE_4:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM_INSTANCE_5:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM_INSTANCE_6:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM_INSTANCE_7:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
/**
* @name: FIOPadSetAdcMux
* @msg: set iopad mux for adc
* @return {*}
* @param {u32} adc_id, id of adc instance
* @param {u32} adc_channel, id of adc channel
*/
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC_INSTANCE_0)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else if (adc_id == FADC_INSTANCE_1)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_G43, FPIN_FUNC7); /* adc1-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_J43, FPIN_FUNC7); /* adc1-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc1-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N45, FPIN_FUNC7); /* adc1-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L47, FPIN_FUNC7); /* adc1-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_L45, FPIN_FUNC7); /* adc1-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
{
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BOARD_E2000D_PARAMTERERS_H
#define BOARD_E2000D_PARAMTERERS_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fparameters_comm.h"
/************************** Constant Definitions *****************************/
#define CORE0_AFF 0x200U
#define CORE1_AFF 0x201U
#define FT_CPUS_NR 2U
/* GIC offset */
#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

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bsp/phytium/libraries/standalone/board/e2000/fearly_uart.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: early_uart.c
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 17:59:26
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
/***************************** Include Files *********************************/
#include "fkernel.h"
#include "fio.h"
#include "fparameters.h"
#include "fearly_uart.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
void OutByte(s8 byte)
{
/* wait until tx fifo is not full */
while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_TXFF) == EARLY_UART_TXFF)
{
}
FtOut32(EARLY_UART_UARTDR, (((u32)byte) & EARLY_UART_DATA_MASK));
}
char GetByte(void)
{
/* wait until rx fifo is not empty */
while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_RXFE) == EARLY_UART_RXFE)
{
}
return (char)(EARLY_UART_DATA_MASK & FtIn32(EARLY_UART_UARTDR));
}

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bsp/phytium/libraries/standalone/board/e2000/fearly_uart.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fearly_uart.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:16
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 rtos 2022/6/25 init commit
*/
#ifndef BOARD_E2000_EARLY_UART_H
#define BOARD_E2000_EARLY_UART_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
#include "fio.h"
#include "fparameters.h"
#include "sdkconfig.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
#if defined(CONFIG_DEFAULT_DEBUG_PRINT_UART2)
#define EARLY_UART_BASE FUART2_BASE_ADDR
#define EARLY_UART_IRQ_NUM FUART2_IRQ_NUM
#elif defined(CONFIG_DEFAULT_DEBUG_PRINT_UART0)
#define EARLY_UART_BASE FUART0_BASE_ADDR
#define EARLY_UART_IRQ_NUM FUART0_IRQ_NUM
#else
#define EARLY_UART_BASE FUART1_BASE_ADDR
#define EARLY_UART_IRQ_NUM FUART1_IRQ_NUM
#endif
#define EARLY_UART_UARTDR (EARLY_UART_BASE + 0x0) /* UART 数据寄存器地址 */
#define EARLY_UART_UARTFR (EARLY_UART_BASE + 0x18) /* UART 状态寄存器地址 */
#define EARLY_UART_UARTCR (EARLY_UART_BASE + 0x30)
#define EARLY_UART_UARTCR_UARTEN BIT(0)
#define EARLY_UART_UARTCR_TXE BIT(8)
#define EARLY_UART_UARTCR_RXE BIT(9)
#define EARLY_UART_UARTCR_INIT (EARLY_UART_UARTCR_UARTEN | EARLY_UART_UARTCR_TXE | \
EARLY_UART_UARTCR_RXE)
#define EARLY_UART_UARTIMSC (EARLY_UART_BASE + 0x38)
#define EARLY_UART_UARTIMSC_RXIM BIT(4)
#define EARLY_UART_UARTIMSC_RTIM BIT(6)
#define EARLY_UART_UARTMIS (EARLY_UART_BASE + 0x40)
#define EARLY_UART_UARTICR (EARLY_UART_BASE + 0x44)
#define EARLY_UART_TXFF BIT(5) /* 发送 FIFO 已满标志位 */
#define EARLY_UART_RXFE BIT(4) /* 接收 FIFO 为空标志位 */
#define EARLY_UART_DATA_MASK GENMASK(7, 0)
#define EARLY_UART_RXI_MASK BIT(4)
#define STDOUT_BASEADDRESS
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
void OutByte(s8 byte);
char GetByte(void);
#ifdef __cplusplus
}
#endif
#endif

572
bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_comm.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fparameters.h"
#include "fio.h"
#include "fkernel.h"
#include "fassert.h"
#include "fdebug.h"
#include "stdio.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/** @name IO PAD Control Register
*/
#define FIOPAD_X_REG0_BEG_OFFSET 0x0 /* 上下拉/驱动能力/复用功能配置 */
#define FIOPAD_X_REG0_END_OFFSET 0x24c
#define FIOPAD_X_REG1_BEG_OFFSET 0x1024 /* 输入/输出延时配置 */
#define FIOPAD_X_REG1_END_OFFSET 0x124c
/** @name X_reg0 Register
*/
#define FIOPAD_X_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */
#define FIOPAD_X_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8)
#define FIOPAD_X_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8)
#define FIOPAD_X_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */
#define FIOPAD_X_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4)
#define FIOPAD_X_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4)
#define FIOPAD_X_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */
#define FIOPAD_X_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0)
#define FIOPAD_X_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0)
/** @name X_reg1 Register
*/
#define FIOPAD_X_REG1_OUT_DELAY_EN BIT(8)
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK GENMASK(11, 9)
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */
#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 11, 9)
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK GENMASK(14, 12)
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */
#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 14, 12)
#define FIOPAD_X_REG1_IN_DELAY_EN BIT(0)
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK GENMASK(3, 1)
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */
#define FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 3, 1)
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK GENMASK(6, 4)
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */
#define FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 6, 4)
#define FIOPAD_DELAY_MAX 15
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
static inline u32 FIOPadRead(FPinIndex pin)
{
return FtIn32(FIOPAD_BASE_ADDR + pin.reg_off);
}
static inline void FIOPadWrite(FPinIndex pin, u32 reg_val)
{
FtOut32(FIOPAD_BASE_ADDR + pin.reg_off, reg_val);
return;
}
#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_X_REG0_END_OFFSET >= pin.reg_off), "invalid reg0 offset @0x%x\r\n", (pin.reg_off))
#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d\r\n", (func))
#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d\r\n", (pull))
#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FPIN_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive))
#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_X_REG1_BEG_OFFSET <= pin.reg_off) && (FIOPAD_X_REG1_END_OFFSET >= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off))
#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
#define FIOPAD_DEBUG_TAG "FIOPAD"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/**
* @name: FPinGetFunc
* @msg: 获取IO引脚当前的复用功能
* @return {FPinFunc} 当前的复用功能
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
FPinFunc FPinGetFunc(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 func = FIOPAD_X_REG0_FUNC_GET(FIOPadRead(pin));
FIOPAD_ASSERT_FUNC(func);
return (FPinFunc)func;
}
/**
* @name: FPinSetFunc
* @msg: 设置IO引脚复用功能
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinFunc} func IO复用功能
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
void FPinSetFunc(const FPinIndex pin, FPinFunc func)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_FUNC(func);
u32 reg_val = FIOPadRead(pin);
u32 test_val = 0;
reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
FIOPadWrite(pin, reg_val);
test_val = FIOPadRead(pin);
if (reg_val != test_val)
{
FIOPAD_ERROR("ERROR: FIOPad write is failed ,pin is %x\n, 0x%x != 0x%x",
pin.reg_off, reg_val, test_val);
}
return;
}
/**
* @name: FPinGetDrive
* @msg: 获取IO引脚的驱动能力
* @return {FPinDrive} 引脚的当前的驱动能力
* @param {FPinIndex} pin IO引脚索引
*/
FPinDrive FPinGetDrive(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 drive = FIOPAD_X_REG0_DRIVE_GET(FIOPadRead(pin));
FIOPAD_ASSERT_DRIVE(drive);
return (FPinDrive)drive;
}
/**
* @name: FPinSetDrive
* @msg: 设置IO引脚的驱动能力
* @return {*}
* @param {FPinIndex} pin, IO引脚索引
* @param {FPinDrive} drive, 引脚驱动能力设置
*/
void FPinSetDrive(const FPinIndex pin, FPinDrive drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_DRIVE(drive);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
FIOPadWrite(pin, reg_val);
return;
}
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (func)
{
*func = FIOPAD_X_REG0_FUNC_GET(reg_val);
}
if (pull)
{
*pull = FIOPAD_X_REG0_PULL_GET(reg_val);
}
if (drive)
{
*pull = FIOPAD_X_REG0_DRIVE_GET(reg_val);
}
return;
}
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_FUNC_MASK;
reg_val |= FIOPAD_X_REG0_FUNC_SET(func);
reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK;
reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive);
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetPull
* @msg: 获取IO引脚当前的上下拉设置
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值
*/
FPinPull FPinGetPull(const FPinIndex pin)
{
FIOPAD_ASSERT_REG0_OFF(pin);
u32 pull = FIOPAD_X_REG0_PULL_GET(FIOPadRead(pin));
FIOPAD_ASSERT_PULL(pull);
return (FPinPull)pull;
}
/**
* @name: FPinSetPull
* @msg: 设置IO引脚当前的上下拉
* @return {*}
* @param {FPinIndex} pin IO引脚索引
* @param {FPinPull} pull 上下拉设置
*/
void FPinSetPull(const FPinIndex pin, FPinPull pull)
{
FIOPAD_ASSERT_REG0_OFF(pin);
FIOPAD_ASSERT_PULL(pull);
u32 reg_val = FIOPadRead(pin);
reg_val &= ~FIOPAD_X_REG0_PULL_MASK;
reg_val |= FIOPAD_X_REG0_PULL_SET(pull);
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetDelay
* @msg: 获取IO引脚当前的延时设置
* @return {FPinDelay} 当前的延时设置
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
*/
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
{
FIOPAD_ASSERT_REG1_OFF(pin);
const u32 reg_val = FIOPadRead(pin);
u8 delay = 0;
if (FPIN_OUTPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
}
else
{
FASSERT(0);
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
}
else
{
FASSERT(0);
}
}
else
{
FASSERT(0);
}
FIOPAD_ASSERT_DELAY(delay);
return (FPinDelay)delay;
}
/**
* @name: FPinGetDelayEn
* @msg: 获取IO引脚当前的延时使能标志位
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
*/
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
{
FIOPAD_ASSERT_REG1_OFF(pin);
const u32 reg_val = FIOPadRead(pin);
boolean enabled = FALSE;
if (FPIN_OUTPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
enabled = TRUE;
else
enabled = FALSE;
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
enabled = TRUE;
else
enabled = FALSE;
}
else
{
FASSERT(0);
}
return enabled;
}
/**
* @name: FPinSetDelay
* @msg: 设置IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {FPinDelayType} type 精调/粗调延时
* @param {FPinDelay} delay 延时设置
*/
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
{
FIOPAD_ASSERT_REG1_OFF(pin);
FIOPAD_ASSERT_DELAY(delay);
u32 reg_val = FIOPadRead(pin);
if (FPIN_OUTPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delay);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(delay);
}
else
{
FASSERT(0);
}
}
else if (FPIN_INPUT_DELAY == dir)
{
if (FPIN_DELAY_FINE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delay);
}
else if (FPIN_DELAY_COARSE_TUNING == type)
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(delay);
}
else
{
FASSERT(0);
}
}
else
{
FASSERT(0);
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinSetDelayEn
* @msg: 使能/去使能IO引脚延时
* @return {*}
* @param {FPinIndex} pin IO引脚延时设置索引
* @param {FPinDelayDir} dir 输入/输出延时
* @param {boolean} enable TRUE: 使能, FALSE: 去使能
*/
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (FPIN_OUTPUT_DELAY == dir)
{
if (enable)
reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
else
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
}
else if (FPIN_INPUT_DELAY == dir)
{
if (enable)
reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
else
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
}
else
{
FASSERT(0);
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinSetDelayConfig
* @msg: Update and enable common IO pin delay config
* @return {NONE}
* @param {FPinIndex} pin, IO pin index
* @param {FPinDelayIOType} in_out_type, Select the input and output types ，
* @param {FPinDelay} roungh_delay, delay rough setting
* @param {FPinDelay} delicate_delay, delay delicate setting
* @param {boolean} enable, enable delay
*/
void FPinSetDelayConfig(const FPinIndex pin, FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay, boolean enable)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (in_out_type == FPIN_DELAY_IN_TYPE)
{
reg_val = FIOPadRead(pin);
/* update delicate input delay */
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delicate_delay);
/* update rough input delay */
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(roungh_delay);
/* enable input delay */
if (enable)
{
reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
}
}
else
{
/* update delicate output delay */
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delicate_delay);
/* update rough output delay */
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK;
reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(roungh_delay);
/* enable output delay */
if (enable)
{
reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
}
else
{
reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
}
}
FIOPadWrite(pin, reg_val);
return;
}
/**
* @name: FPinGetDelayConfig
* @msg: Get current common IO pin delay config
* @return {NONE}
* @param {FPinIndex} pin, IO pin index
* @param {FPinDelay} *in_roungh_delay, input delay rough setting (输入粗调)
* @param {FPinDelay} *in_delicate_delay, input delay delicate setting (输入精调)
* @param {FPinDelay} *out_roungh_delay, output delay rough setting (输出粗调)
* @param {FPinDelay} *out_delicate_delay, output delay delicate setting (输出精调)
*/
void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay,
FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay)
{
FIOPAD_ASSERT_REG1_OFF(pin);
u32 reg_val = FIOPadRead(pin);
if (out_delicate_delay)
{
*out_delicate_delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val);
}
if (out_roungh_delay)
{
*out_roungh_delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val);
}
if (in_delicate_delay)
{
*in_delicate_delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val);
}
if (in_roungh_delay)
{
*in_roungh_delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val);
}
return;
}
/**
* @name: FIOPadDumpPadFunc
* @msg: print information of all iopad
* @return {*}
*/
void FIOPadDumpPadFunc(void)
{
uintptr beg_off = FIOPAD_0_FUNC_OFFSET;
uintptr end_off = FIOPAD_147_FUNC_OFFSET;
uintptr off;
FPinIndex pin;
const char *pull_state[FPIN_NUM_OF_PULL] = {"none", "down", "up"};
FIOPAD_DEBUG("Pad Func Info...");
for (off = beg_off; off <= end_off; off += 4U)
{
pin.reg_off = off;
FIOPAD_DEBUG(" [0x%x] func: %d, ds: %d, pull: %s ",
pin.reg_off,
FPinGetFunc(pin),
FPinGetDrive(pin),
pull_state[FPinGetPull(pin)]);
}
}

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bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h Normal file
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#ifndef BOARD_E2000_FIOPAD_COMMON_H
#define BOARD_E2000_FIOPAD_COMMON_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_INDEX(offset) \
{ \
/* reg_off */ (offset), \
/* reg_bit */ (0) \
}
/*****************************************************************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_0_FUNC_OFFSET 0x0000U
#define FIOPAD_2_FUNC_OFFSET 0x0004U
#define FIOPAD_3_FUNC_OFFSET 0x0008U
#define FIOPAD_4_FUNC_OFFSET 0x000CU
#define FIOPAD_5_FUNC_OFFSET 0x0010U
#define FIOPAD_6_FUNC_OFFSET 0x0014U
#define FIOPAD_7_FUNC_OFFSET 0x0018U
#define FIOPAD_8_FUNC_OFFSET 0x001CU
#define FIOPAD_9_FUNC_OFFSET 0x0020U
#define FIOPAD_10_FUNC_OFFSET 0x0024U
#define FIOPAD_11_FUNC_OFFSET 0x0028U
#define FIOPAD_12_FUNC_OFFSET 0x002CU
#define FIOPAD_13_FUNC_OFFSET 0x0030U
#define FIOPAD_14_FUNC_OFFSET 0x0034U
#define FIOPAD_15_FUNC_OFFSET 0x0038U
#define FIOPAD_16_FUNC_OFFSET 0x003CU
#define FIOPAD_17_FUNC_OFFSET 0x0040U
#define FIOPAD_18_FUNC_OFFSET 0x0044U
#define FIOPAD_19_FUNC_OFFSET 0x0048U
#define FIOPAD_20_FUNC_OFFSET 0x004CU
#define FIOPAD_21_FUNC_OFFSET 0x0050U
#define FIOPAD_22_FUNC_OFFSET 0x0054U
#define FIOPAD_23_FUNC_OFFSET 0x0058U
#define FIOPAD_24_FUNC_OFFSET 0x005CU
#define FIOPAD_25_FUNC_OFFSET 0x0060U
#define FIOPAD_26_FUNC_OFFSET 0x0064U
#define FIOPAD_27_FUNC_OFFSET 0x0068U
#define FIOPAD_28_FUNC_OFFSET 0x006CU
#define FIOPAD_31_FUNC_OFFSET 0x0070U
#define FIOPAD_32_FUNC_OFFSET 0x0074U
#define FIOPAD_33_FUNC_OFFSET 0x0078U
#define FIOPAD_34_FUNC_OFFSET 0x007CU
#define FIOPAD_35_FUNC_OFFSET 0x0080U
#define FIOPAD_36_FUNC_OFFSET 0x0084U
#define FIOPAD_37_FUNC_OFFSET 0x0088U
#define FIOPAD_38_FUNC_OFFSET 0x008CU
#define FIOPAD_39_FUNC_OFFSET 0x0090U
#define FIOPAD_40_FUNC_OFFSET 0x0094U
#define FIOPAD_41_FUNC_OFFSET 0x0098U
#define FIOPAD_42_FUNC_OFFSET 0x009CU
#define FIOPAD_43_FUNC_OFFSET 0x00A0U
#define FIOPAD_44_FUNC_OFFSET 0x00A4U
#define FIOPAD_45_FUNC_OFFSET 0x00A8U
#define FIOPAD_46_FUNC_OFFSET 0x00ACU
#define FIOPAD_47_FUNC_OFFSET 0x00B0U
#define FIOPAD_48_FUNC_OFFSET 0x00B4U
#define FIOPAD_49_FUNC_OFFSET 0x00B8U
#define FIOPAD_50_FUNC_OFFSET 0x00BCU
#define FIOPAD_51_FUNC_OFFSET 0x00C0U
#define FIOPAD_52_FUNC_OFFSET 0x00C4U
#define FIOPAD_53_FUNC_OFFSET 0x00C8U
#define FIOPAD_54_FUNC_OFFSET 0x00CCU
#define FIOPAD_55_FUNC_OFFSET 0x00D0U
#define FIOPAD_56_FUNC_OFFSET 0x00D4U
#define FIOPAD_57_FUNC_OFFSET 0x00D8U
#define FIOPAD_58_FUNC_OFFSET 0x00DCU
#define FIOPAD_59_FUNC_OFFSET 0x00E0U
#define FIOPAD_60_FUNC_OFFSET 0x00E4U
#define FIOPAD_61_FUNC_OFFSET 0x00E8U
#define FIOPAD_62_FUNC_OFFSET 0x00ECU
#define FIOPAD_63_FUNC_OFFSET 0x00F0U
#define FIOPAD_64_FUNC_OFFSET 0x00F4U
#define FIOPAD_65_FUNC_OFFSET 0x00F8U
#define FIOPAD_66_FUNC_OFFSET 0x00FCU
#define FIOPAD_67_FUNC_OFFSET 0x0100U
#define FIOPAD_68_FUNC_OFFSET 0x0104U
#define FIOPAD_148_FUNC_OFFSET 0x0108U
#define FIOPAD_69_FUNC_OFFSET 0x010CU
#define FIOPAD_70_FUNC_OFFSET 0x0110U
#define FIOPAD_71_FUNC_OFFSET 0x0114U
#define FIOPAD_72_FUNC_OFFSET 0x0118U
#define FIOPAD_73_FUNC_OFFSET 0x011CU
#define FIOPAD_74_FUNC_OFFSET 0x0120U
#define FIOPAD_75_FUNC_OFFSET 0x0124U
#define FIOPAD_76_FUNC_OFFSET 0x0128U
#define FIOPAD_77_FUNC_OFFSET 0x012CU
#define FIOPAD_78_FUNC_OFFSET 0x0130U
#define FIOPAD_79_FUNC_OFFSET 0x0134U
#define FIOPAD_80_FUNC_OFFSET 0x0138U
#define FIOPAD_81_FUNC_OFFSET 0x013CU
#define FIOPAD_82_FUNC_OFFSET 0x0140U
#define FIOPAD_83_FUNC_OFFSET 0x0144U
#define FIOPAD_84_FUNC_OFFSET 0x0148U
#define FIOPAD_85_FUNC_OFFSET 0x014CU
#define FIOPAD_86_FUNC_OFFSET 0x0150U
#define FIOPAD_87_FUNC_OFFSET 0x0154U
#define FIOPAD_88_FUNC_OFFSET 0x0158U
#define FIOPAD_89_FUNC_OFFSET 0x015CU
#define FIOPAD_90_FUNC_OFFSET 0x0160U
#define FIOPAD_91_FUNC_OFFSET 0x0164U
#define FIOPAD_92_FUNC_OFFSET 0x0168U
#define FIOPAD_93_FUNC_OFFSET 0x016CU
#define FIOPAD_94_FUNC_OFFSET 0x0170U
#define FIOPAD_95_FUNC_OFFSET 0x0174U
#define FIOPAD_96_FUNC_OFFSET 0x0178U
#define FIOPAD_97_FUNC_OFFSET 0x017CU
#define FIOPAD_98_FUNC_OFFSET 0x0180U
#define FIOPAD_29_FUNC_OFFSET 0x0184U
#define FIOPAD_30_FUNC_OFFSET 0x0188U
#define FIOPAD_99_FUNC_OFFSET 0x018CU
#define FIOPAD_100_FUNC_OFFSET 0x0190U
#define FIOPAD_101_FUNC_OFFSET 0x0194U
#define FIOPAD_102_FUNC_OFFSET 0x0198U
#define FIOPAD_103_FUNC_OFFSET 0x019CU
#define FIOPAD_104_FUNC_OFFSET 0x01A0U
#define FIOPAD_105_FUNC_OFFSET 0x01A4U
#define FIOPAD_106_FUNC_OFFSET 0x01A8U
#define FIOPAD_107_FUNC_OFFSET 0x01ACU
#define FIOPAD_108_FUNC_OFFSET 0x01B0U
#define FIOPAD_109_FUNC_OFFSET 0x01B4U
#define FIOPAD_110_FUNC_OFFSET 0x01B8U
#define FIOPAD_111_FUNC_OFFSET 0x01BCU
#define FIOPAD_112_FUNC_OFFSET 0x01C0U
#define FIOPAD_113_FUNC_OFFSET 0x01C4U
#define FIOPAD_114_FUNC_OFFSET 0x01C8U
#define FIOPAD_115_FUNC_OFFSET 0x01CCU
#define FIOPAD_116_FUNC_OFFSET 0x01D0U
#define FIOPAD_117_FUNC_OFFSET 0x01D4U
#define FIOPAD_118_FUNC_OFFSET 0x01D8U
#define FIOPAD_119_FUNC_OFFSET 0x01DCU
#define FIOPAD_120_FUNC_OFFSET 0x01E0U
#define FIOPAD_121_FUNC_OFFSET 0x01E4U
#define FIOPAD_122_FUNC_OFFSET 0x01E8U
#define FIOPAD_123_FUNC_OFFSET 0x01ECU
#define FIOPAD_124_FUNC_OFFSET 0x01F0U
#define FIOPAD_125_FUNC_OFFSET 0x01F4U
#define FIOPAD_126_FUNC_OFFSET 0x01F8U
#define FIOPAD_127_FUNC_OFFSET 0x01FCU
#define FIOPAD_128_FUNC_OFFSET 0x0200U
#define FIOPAD_129_FUNC_OFFSET 0x0204U
#define FIOPAD_130_FUNC_OFFSET 0x0208U
#define FIOPAD_131_FUNC_OFFSET 0x020CU
#define FIOPAD_132_FUNC_OFFSET 0x0210U
#define FIOPAD_133_FUNC_OFFSET 0x0214U
#define FIOPAD_134_FUNC_OFFSET 0x0218U
#define FIOPAD_135_FUNC_OFFSET 0x021CU
#define FIOPAD_136_FUNC_OFFSET 0x0220U
#define FIOPAD_137_FUNC_OFFSET 0x0224U
#define FIOPAD_138_FUNC_OFFSET 0x0228U
#define FIOPAD_139_FUNC_OFFSET 0x022CU
#define FIOPAD_140_FUNC_OFFSET 0x0230U
#define FIOPAD_141_FUNC_OFFSET 0x0234U
#define FIOPAD_142_FUNC_OFFSET 0x0238U
#define FIOPAD_143_FUNC_OFFSET 0x023CU
#define FIOPAD_144_FUNC_OFFSET 0x0240U
#define FIOPAD_145_FUNC_OFFSET 0x0244U
#define FIOPAD_146_FUNC_OFFSET 0x0248U
#define FIOPAD_147_FUNC_OFFSET 0x024CU
/* register offset of iopad delay */
#define FIOPAD_10_DELAY_OFFSET 0x1024U
#define FIOPAD_11_DELAY_OFFSET 0x1028U
#define FIOPAD_12_DELAY_OFFSET 0x102CU
#define FIOPAD_13_DELAY_OFFSET 0x1030U
#define FIOPAD_14_DELAY_OFFSET 0x1034U
#define FIOPAD_23_DELAY_OFFSET 0x1058U
#define FIOPAD_24_DELAY_OFFSET 0x105CU
#define FIOPAD_25_DELAY_OFFSET 0x1060U
#define FIOPAD_26_DELAY_OFFSET 0x1064U
#define FIOPAD_32_DELAY_OFFSET 0x1074U
#define FIOPAD_33_DELAY_OFFSET 0x1078U
#define FIOPAD_34_DELAY_OFFSET 0x107CU
#define FIOPAD_35_DELAY_OFFSET 0x1080U
#define FIOPAD_55_DELAY_OFFSET 0x10D0U
#define FIOPAD_56_DELAY_OFFSET 0x10D4U
#define FIOPAD_57_DELAY_OFFSET 0x10D8U
#define FIOPAD_58_DELAY_OFFSET 0x10DCU
#define FIOPAD_59_DELAY_OFFSET 0x10E0U
#define FIOPAD_60_DELAY_OFFSET 0x10E4U
#define FIOPAD_61_DELAY_OFFSET 0x10E8U
#define FIOPAD_62_DELAY_OFFSET 0x10ECU
#define FIOPAD_63_DELAY_OFFSET 0x10F0U
#define FIOPAD_64_DELAY_OFFSET 0x10F4U
#define FIOPAD_65_DELAY_OFFSET 0x10F8U
#define FIOPAD_66_DELAY_OFFSET 0x10FCU
#define FIOPAD_67_DELAY_OFFSET 0x1100U
#define FIOPAD_68_DELAY_OFFSET 0x1104U
#define FIOPAD_148_DELAY_OFFSET 0x1108U
#define FIOPAD_69_DELAY_OFFSET 0x110CU
#define FIOPAD_70_DELAY_OFFSET 0x1110U
#define FIOPAD_71_DELAY_OFFSET 0x1114U
#define FIOPAD_72_DELAY_OFFSET 0x1118U
#define FIOPAD_73_DELAY_OFFSET 0x111CU
#define FIOPAD_74_DELAY_OFFSET 0x1120U
#define FIOPAD_75_DELAY_OFFSET 0x1124U
#define FIOPAD_76_DELAY_OFFSET 0x1128U
#define FIOPAD_77_DELAY_OFFSET 0x112CU
#define FIOPAD_78_DELAY_OFFSET 0x1130U
#define FIOPAD_80_DELAY_OFFSET 0x1138U
#define FIOPAD_81_DELAY_OFFSET 0x113CU
#define FIOPAD_82_DELAY_OFFSET 0x1140U
#define FIOPAD_83_DELAY_OFFSET 0x1144U
#define FIOPAD_84_DELAY_OFFSET 0x1148U
#define FIOPAD_85_DELAY_OFFSET 0x114CU
#define FIOPAD_86_DELAY_OFFSET 0x1150U
#define FIOPAD_87_DELAY_OFFSET 0x1154U
#define FIOPAD_88_DELAY_OFFSET 0x1158U
#define FIOPAD_89_DELAY_OFFSET 0x115CU
#define FIOPAD_90_DELAY_OFFSET 0x1160U
#define FIOPAD_92_DELAY_OFFSET 0x1168U
#define FIOPAD_93_DELAY_OFFSET 0x116CU
#define FIOPAD_94_DELAY_OFFSET 0x1170U
#define FIOPAD_95_DELAY_OFFSET 0x1174U
#define FIOPAD_96_DELAY_OFFSET 0x1178U
#define FIOPAD_97_DELAY_OFFSET 0x117CU
#define FIOPAD_98_DELAY_OFFSET 0x1180U
#define FIOPAD_99_DELAY_OFFSET 0x118CU
#define FIOPAD_100_DELAY_OFFSET 0x1190U
#define FIOPAD_101_DELAY_OFFSET 0x1194U
#define FIOPAD_102_DELAY_OFFSET 0x1198U
#define FIOPAD_103_DELAY_OFFSET 0x119CU
#define FIOPAD_104_DELAY_OFFSET 0x11A0U
#define FIOPAD_105_DELAY_OFFSET 0x11A4U
#define FIOPAD_106_DELAY_OFFSET 0x11A8U
#define FIOPAD_107_DELAY_OFFSET 0x11ACU
#define FIOPAD_108_DELAY_OFFSET 0x11B0U
#define FIOPAD_109_DELAY_OFFSET 0x11B4U
#define FIOPAD_110_DELAY_OFFSET 0x11B8U
#define FIOPAD_111_DELAY_OFFSET 0x11BCU
#define FIOPAD_112_DELAY_OFFSET 0x11C0U
#define FIOPAD_115_DELAY_OFFSET 0x11CCU
#define FIOPAD_116_DELAY_OFFSET 0x11D0U
#define FIOPAD_117_DELAY_OFFSET 0x11D4U
#define FIOPAD_118_DELAY_OFFSET 0x11D8U
#define FIOPAD_119_DELAY_OFFSET 0x11DCU
#define FIOPAD_120_DELAY_OFFSET 0x11E0U
#define FIOPAD_121_DELAY_OFFSET 0x11E4U
#define FIOPAD_122_DELAY_OFFSET 0x11E8U
#define FIOPAD_123_DELAY_OFFSET 0x11ECU
#define FIOPAD_124_DELAY_OFFSET 0x11F0U
#define FIOPAD_125_DELAY_OFFSET 0x11F4U
#define FIOPAD_126_DELAY_OFFSET 0x11F8U
#define FIOPAD_127_DELAY_OFFSET 0x11FCU
#define FIOPAD_128_DELAY_OFFSET 0x1200U
#define FIOPAD_136_DELAY_OFFSET 0x1220U
#define FIOPAD_137_DELAY_OFFSET 0x1224U
#define FIOPAD_138_DELAY_OFFSET 0x1228U
#define FIOPAD_139_DELAY_OFFSET 0x122CU
#define FIOPAD_140_DELAY_OFFSET 0x1230U
#define FIOPAD_141_DELAY_OFFSET 0x1234U
#define FIOPAD_142_DELAY_OFFSET 0x1238U
#define FIOPAD_143_DELAY_OFFSET 0x123CU
#define FIOPAD_144_DELAY_OFFSET 0x1240U
#define FIOPAD_145_DELAY_OFFSET 0x1244U
#define FIOPAD_146_DELAY_OFFSET 0x1248U
#define FIOPAD_147_DELAY_OFFSET 0x124CU
/************************** Function Prototypes ******************************/
/* set iopad mux for spim */
void FIOPadSetSpimMux(u32 spim_id);
/* set iopad mux for gpio */
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id);
/* set iopad mux for mio */
void FIOPadSetMioMux(u32 mio_id);
/* print information of all iopad */
void FIOPadDumpPadFunc(void);
/* set iopad mux for can */
void FIOPadSetCanMux(u32 can_id);
/* set iopad mux for qspi */
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id);
/* set iopad mux for pwm */
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel);
/* set iopad mux for adc */
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel);
/* set iopad mux for tacho*/
void FIOPadSetTachoMux(u32 pwm_in_id);
/* set iopad mux for uart*/
void FIOPadSetUartMux(u32 uart_id);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters_comm.h
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-17 18:01:11
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BOARD_E2000_PARAMTERERS_COMMON_H
#define BOARD_E2000_PARAMTERERS_COMMON_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
/************************** Constant Definitions *****************************/
/* CACHE */
#define CACHE_LINE_ADDR_MASK 0x3FU
#define CACHE_LINE 64U
/* DEVICE Register Address */
#define FT_DEV_BASE_ADDR 0x28000000U
#define FT_DEV_END_ADDR 0x2FFFFFFFU
/* PCI */
#define FT_PCIE_NUM 1
#define FT_PCIE0_ID 0
#define FT_PCIE0_MISC_IRQ_NUM 40
#define FT_PCIE_CFG_MAX_NUM_OF_BUS 256
#define FT_PCIE_CFG_MAX_NUM_OF_DEV 32
#define FT_PCIE_CFG_MAX_NUM_OF_FUN 8
#define FT_PCI_CONFIG_BASEADDR 0x40000000U
#define FT_PCI_CONFIG_REG_LENGTH 0x10000000U
#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000U
#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000U
#define FT_PCI_MEM32_BASEADDR 0x58000000U
#define FT_PCI_MEM32_REG_LENGTH 0x27FFFFFFU
#define FT_PCI_MEM64_BASEADDR 0x1000000000U
#define FT_PCI_MEM64_REG_LENGTH 0x1000000000U
#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000U
#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000U
#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000U
#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000U
#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000U
#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000U
#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000U
#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000U
#define FT_PCI_INTA_IRQ_NUM 36
#define FT_PCI_INTB_IRQ_NUM 37
#define FT_PCI_INTC_IRQ_NUM 38
#define FT_PCI_INTD_IRQ_NUM 39
#define FT_PCI_NEED_SKIP 0
#define FT_PCI_INTX_PEU0_STAT 0x29100000U
#define FT_PCI_INTX_PEU1_STAT 0x29101000U
#define FT_PCI_INTX_EU0_C0_CONTROL 0x29000184U
#define FT_PCI_INTX_EU0_C1_CONTROL 0x29010184U
#define FT_PCI_INTX_EU0_C2_CONTROL 0x29020184U
#define FT_PCI_INTX_EU1_C0_CONTROL 0x29030184U
#define FT_PCI_INTX_EU1_C1_CONTROL 0x29040184U
#define FT_PCI_INTX_EU1_C2_CONTROL 0x29050184U
#define FT_PCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
#define FT_PCI_INTX_SATA_NUM 2 /* Total number of controllers */
/* platform ahci host */
#define PLAT_AHCI_HOST_MAX_COUNT 5
#define AHCI_BASE_0 0
#define AHCI_BASE_1 0
#define AHCI_BASE_2 0
#define AHCI_BASE_3 0
#define AHCI_BASE_4 0
#define AHCI_IRQ_0 0
#define AHCI_IRQ_1 0
#define AHCI_IRQ_2 0
#define AHCI_IRQ_3 0
#define AHCI_IRQ_4 0
/* sata controller */
#define FSATA0_BASEADDR 0x31A40000U
#define FSATA1_BASEADDR 0x32014000U
#define FSATA0_IRQNUM 74
#define FSATA1_IRQNUM 75
#if !defined(__ASSEMBLER__)
typedef enum
{
FSATA_INSTANCE_0 = 0,
FSATA_INSTANCE_1 = 1,
FSATA_INSTANCE_NUM
} FSataInstance;
#endif
/* Generic Timer */
#define GENERIC_TIMER_CLK_FREQ_MHZ 48U
#define GENERIC_TIMER_NS_IRQ_NUM 30U
#define GENERIC_TIMER_NS_CLK_FREQ 2000000U
#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ
/* UART */
#define FUART_NUM 4U
#define FUART_REG_LENGTH 0x18000U
#define FUART0_ID 0U
#define FUART0_IRQ_NUM (85 + 30)
#define FUART0_BASE_ADDR 0x2800c000U
#define FUART0_CLK_FREQ_HZ 100000000U
#define FUART1_ID 1U
#define FUART1_IRQ_NUM (86 + 30)
#define FUART1_BASE_ADDR 0x2800d000U
#define FUART1_CLK_FREQ_HZ 100000000U
#define FUART2_ID 2U
#define FUART2_IRQ_NUM (87 + 30)
#define FUART2_BASE_ADDR 0x2800e000U
#define FUART2_CLK_FREQ_HZ 100000000U
#define FUART3_BASE_ADDR 0x2800f000U
#define FUART3_ID 3U
#define FUART3_IRQ_NUM (88 + 30)
#define FUART3_CLK_FREQ_HZ 100000000U
#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
/****** GIC v3 *****/
#define FT_GICV3_INSTANCES_NUM 1U
#define GICV3_REG_LENGTH 0x00009000U
/*
* The maximum priority value that can be used in the GIC.
*/
#define GICV3_MAX_INTR_PRIO_VAL 240U
#define GICV3_INTR_PRIO_MASK 0x000000f0U
#define ARM_GIC_NR_IRQS 160U
#define ARM_GIC_IRQ_START 0U
#define FGIC_NUM 1U
#define ARM_GIC_IPI_COUNT 16U /* MPCore IPI count */
#define SGI_INT_MAX 16U
#define SPI_START_INT_NUM 32U /* SPI start at ID32 */
#define PPI_START_INT_NUM 16U /* PPI start at ID16 */
#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */
#define GICV3_BASEADDRESS 0x30800000U
#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
#define GICV3_RD_OFFSET (2U << 16)
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
/* GPIO */
#define FGPIO_ID_0 0U
#define FGPIO_ID_1 1U
#define FGPIO_ID_2 2U
#define FGPIO_WITH_PIN_IRQ 2U /* max id of gpio assign irq for each pin */
#define FGPIO_ID_3 3U
#define FGPIO_ID_4 4U
#define FGPIO_ID_5 5U
#define FGPIO_NUM 6U
#define FGPIO_0_BASE_ADDR 0x28034000U
#define FGPIO_1_BASE_ADDR 0x28035000U
#define FGPIO_2_BASE_ADDR 0x28036000U
#define FGPIO_3_BASE_ADDR 0x28037000U
#define FGPIO_4_BASE_ADDR 0x28038000U
#define FGPIO_5_BASE_ADDR 0x28039000U
#define FGPIO_CTRL_PIN_NUM 16U
#define FGPIO_PIN_IRQ_BASE 140U
#define FGPIO_PIN_IRQ_NUM_GET(id, pin) (FGPIO_PIN_IRQ_BASE + FGPIO_CTRL_PIN_NUM * (id) + (pin))
#define FGPIO_3_IRQ_NUM 188U
#define FGPIO_4_IRQ_NUM 189U
#define FGPIO_5_IRQ_NUM 190U
#define FGPIO_PIN_IRQ_TOTAL 51U
/* SPI */
#define FSPI0_BASE 0x2803A000U
#define FSPI1_BASE 0x2803B000U
#define FSPI2_BASE 0x2803C000U
#define FSPI3_BASE 0x2803D000U
#define FSPI0_ID 0U
#define FSPI1_ID 1U
#define FSPI2_ID 2U
#define FSPI3_ID 3U
#define FSPI0_IRQ_NUM 191U
#define FSPI1_IRQ_NUM 192U
#define FSPI2_IRQ_NUM 193U
#define FSPI3_IRQ_NUM 194U
#define FSPI_FREQ 50000000U
#define FSPI_DEVICE_NUM 4U
/* XMAC */
#define FT_XMAC_NUM 4U
#define FT_XMAC0_ID 0U
#define FT_XMAC1_ID 1U
#define FT_XMAC2_ID 2U
#define FT_XMAC3_ID 3U
#define FT_XMAC0_BASEADDRESS 0x3200C000U
#define FT_XMAC1_BASEADDRESS 0x3200E000U
#define FT_XMAC2_BASEADDRESS 0x32010000U
#define FT_XMAC3_BASEADDRESS 0x32012000U
#define FT_XMAC0_MODE_SEL_BASEADDRESS 0x3200DC00U
#define FT_XMAC0_LOOPBACK_SEL_BASEADDRESS 0x3200DC04U
#define FT_XMAC1_MODE_SEL_BASEADDRESS 0x3200FC00U
#define FT_XMAC1_LOOPBACK_SEL_BASEADDRESS 0x3200FC04U
#define FT_XMAC2_MODE_SEL_BASEADDRESS 0x32011C00U
#define FT_XMAC2_LOOPBACK_SEL_BASEADDRESS 0x32011C04U
#define FT_XMAC3_MODE_SEL_BASEADDRESS 0x32013C00U
#define FT_XMAC3_LOOPBACK_SEL_BASEADDRESS 0x32013C04U
#define FT_XMAC0_PCLK 50000000U
#define FT_XMAC1_PCLK 50000000U
#define FT_XMAC2_PCLK 50000000U
#define FT_XMAC3_PCLK 50000000U
#define FT_XMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
#define FT_XMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
#define FT_XMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
#define FT_XMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
#define FT_XMAC_QUEUE_MAX_NUM 16U
#define FT_XMAC0_QUEUE0_IRQ_NUM (57U + 30U)
#define FT_XMAC0_QUEUE1_IRQ_NUM (58U + 30U)
#define FT_XMAC0_QUEUE2_IRQ_NUM (59U + 30U)
#define FT_XMAC0_QUEUE3_IRQ_NUM (60U + 30U)
#define FT_XMAC0_QUEUE4_IRQ_NUM (30U + 30U)
#define FT_XMAC0_QUEUE5_IRQ_NUM (31U + 30U)
#define FT_XMAC0_QUEUE6_IRQ_NUM (32U + 30U)
#define FT_XMAC0_QUEUE7_IRQ_NUM (33U + 30U)
#define FT_XMAC1_QUEUE0_IRQ_NUM (61U + 30U)
#define FT_XMAC1_QUEUE1_IRQ_NUM (62U + 30U)
#define FT_XMAC1_QUEUE2_IRQ_NUM (63U + 30U)
#define FT_XMAC1_QUEUE3_IRQ_NUM (64U + 30U)
#define FT_XMAC2_QUEUE0_IRQ_NUM (66U + 30U)
#define FT_XMAC2_QUEUE1_IRQ_NUM (67U + 30U)
#define FT_XMAC2_QUEUE2_IRQ_NUM (68U + 30U)
#define FT_XMAC2_QUEUE3_IRQ_NUM (69U + 30U)
#define FT_XMAC3_QUEUE0_IRQ_NUM (70U + 30U)
#define FT_XMAC3_QUEUE1_IRQ_NUM (71U + 30U)
#define FT_XMAC3_QUEUE2_IRQ_NUM (72U + 30U)
#define FT_XMAC3_QUEUE3_IRQ_NUM (73U + 30U)
#define FT_XMAC_PHY_MAX_NUM 32U
/* QSPI */
#define FQSPI_BASEADDR 0x028008000U
#if !defined(__ASSEMBLER__)
typedef enum
{
FQSPI_INSTANCE_0 = 0,
FQSPI_INSTANCE_NUM
} FQspiInstance;
/* FQSPI cs 0_3, chip number */
typedef enum
{
FQSPI_CS_0 = 0,
FQSPI_CS_1 = 1,
FQSPI_CS_2 = 2,
FQSPI_CS_3 = 3,
FQSPI_CS_NUM
} FQspiChipCS;
#endif
#define FQSPI_MEM_START_ADDR 0x0U
#define FQSPI_MEM_END_ADDR 0x0FFFFFFFU /* 256MB */
#define FQSPI_MEM_START_ADDR_64 0x100000000U
#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */
/* TIMER and TACHO */
#define TIMER_NUM 38U
#define TACHO_NUM 16U
#define TIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
#define TIMER_TICK_PERIOD_NS 20U /* 20ns */
#define TIMER_TACHO_IRQ_ID(n) (226U + (n))
#define TIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
#if !defined(__ASSEMBLER__)
typedef enum
{
TACHO_INSTANCE_0 = 0,
TACHO_INSTANCE_1 = 1,
TACHO_INSTANCE_2 = 2,
TACHO_INSTANCE_3 = 3,
TACHO_INSTANCE_4 = 4,
TACHO_INSTANCE_5 = 5,
TACHO_INSTANCE_6 = 6,
TACHO_INSTANCE_7 = 7,
TACHO_INSTANCE_8 = 8,
TACHO_INSTANCE_9 = 9,
TACHO_INSTANCE_10 = 10,
TACHO_INSTANCE_11 = 11,
TACHO_INSTANCE_12 = 12,
TACHO_INSTANCE_13 = 13,
TACHO_INSTANCE_14 = 14,
TACHO_INSTANCE_15 = 15,
TACHO_INSTANCE_NUM
} TachoInstance;
#endif
/* GDMA */
#define FGDMA0_ID 0U
#define FGDMA0_BASE_ADDR 0x32B34000U
#define FGDMA0_IRQ_NUM 266U
#define FGDMA_INSTANCE_NUM 1U
/* CANFD */
#define FCAN_REF_CLOCK 200000000U
#define FCAN0_BASEADDR 0x2800A000U
#define FCAN1_BASEADDR 0x2800B000U
#define FCAN0_IRQNUM 113U
#define FCAN1_IRQNUM 114U
#if !defined(__ASSEMBLER__)
typedef enum
{
FCAN_INSTANCE_0 = 0,
FCAN_INSTANCE_1 = 1,
FCAN_INSTANCE_NUM
} FCanInstance;
#endif
/* WDT */
#if !defined(__ASSEMBLER__)
typedef enum
{
FWDT_INSTANCE_0 = 0,
FWDT_INSTANCE_1,
FWDT_INSTANCE_NUM
} FWdtInstance;
#endif
#define FWDT0_REFRESH_BASE 0x28040000U
#define FWDT0_CONTROL_BASE 0x28041000U
#define FWDT1_REFRESH_BASE 0x28042000U
#define FWDT1_CONTROL_BASE 0x28043000U
#define FWDT0_INTR_IRQ 196U
#define FWDT1_INTR_IRQ 197U
#define FWDT_CLK 48000000U /* 48MHz */
/*MIO*/
#define FMIO_NUM 16
#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n))
#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000
#define FMIO_IRQ_NUM(n) (124+n)
#define MIO_REF_CLK_HZ 50000000 /* 50MHz */
#if !defined(__ASSEMBLER__)
typedef enum
{
MIO_INSTANCE_0 = 0,
MIO_INSTANCE_1,
MIO_INSTANCE_2,
MIO_INSTANCE_3,
MIO_INSTANCE_4,
MIO_INSTANCE_5,
MIO_INSTANCE_6,
MIO_INSTANCE_7,
MIO_INSTANCE_8,
MIO_INSTANCE_9,
MIO_INSTANCE_10,
MIO_INSTANCE_11,
MIO_INSTANCE_12,
MIO_INSTANCE_13,
MIO_INSTANCE_14,
MIO_INSTANCE_15,
MIO_INSTANCE_NUM
} MioInstance;
#endif
#if !defined(__ASSEMBLER__)
/*I2C0 -> PMBUS0
* I2C1 -> PMBUS1
* I2C2 -> SMBUS0
*/
typedef enum
{
I2C_INSTANCE_0 = 0,
I2C_INSTANCE_1,
I2C_INSTANCE_2,
I2C_INSTANCE_NUM
} I2cInstance;
#endif
#define I2C_0_BASEADDR 0x28011000
#define I2C_1_BASEADDR 0x28012000
#define I2C_2_BASEADDR 0x28013000
#define I2C_0_INTR_IRQ 121
#define I2C_1_INTR_IRQ 122
#define I2C_2_INTR_IRQ 123
#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
/* SDIO */
#if !defined(__ASSEMBLER__)
enum
{
FSDIO_HOST_INSTANCE_0 = 0,
FSDIO_HOST_INSTANCE_1,
FSDIO_HOST_INSTANCE_NUM
};
#endif
#define FSDIO_HOST_0_BASE_ADDR 0x28000000U
#define FSDIO_HOST_1_BASE_ADDR 0x28001000U
#define FSDIO_HOST_0_IRQ_NUM 104U
#define FSDIO_HOST_1_IRQ_NUM 105U
#define FSDIO_CLK_RATE_HZ (1200000000UL) /* 1.2GHz */
/* NAND */
#define FNAND_NUM 1U
#define FNAND_INSTANCE0 0U
#define FNAND_BASEADDRESS 0x28002000U
#define FNAND_IRQ_NUM (106U)
#define FNAND_CONNECT_MAX_NUM 1U
#define FIOPAD_BASE_ADDR 0x32B30000U
/* DDMA */
#define FDDMA0_ID 0U
#define FDDMA0_BASE_ADDR 0x28003000U
#define FDDMA0_IRQ_NUM 107U
#define FDDMA1_ID 1U
#define FDDMA1_BASE_ADDR 0x28004000U
#define FDDMA1_IRQ_NUM 108U
#define FDDMA_INSTANCE_NUM 2U
#define FDDMA0_UART0_TX_SLAVE_ID 2U /* uart0 tx slave-id */
#define FDDMA0_UART1_TX_SLAVE_ID 3U /* uart1 tx slave-id */
#define FDDMA0_UART2_TX_SLAVE_ID 4U /* uart2 tx slave-id */
#define FDDMA0_UART3_TX_SLAVE_ID 5U /* uart3 tx slave-id */
#define FDDMA0_SPIM0_TX_SLAVE_ID 6U /* spi0 tx slave-id */
#define FDDMA0_SPIM1_TX_SLAVE_ID 7U /* spi1 tx slave-id */
#define FDDMA0_SPIM2_TX_SLAVE_ID 8U /* spi2 tx slave-id */
#define FDDMA0_SPIM3_TX_SLAVE_ID 9U /* spi3 tx slave-id */
#define FDDMA0_UART0_RX_SLAVE_ID 15U /* uart0 rx slave-id */
#define FDDMA0_UART1_RX_SLAVE_ID 16U /* uart1 rx slave-id */
#define FDDMA0_UART2_RX_SLAVE_ID 17U /* uart2 rx slave-id */
#define FDDMA0_UART3_RX_SLAVE_ID 18U /* uart3 rx slave-id */
#define FDDMA0_SPIM0_RX_SLAVE_ID 19U /* spi0 rx slave-id */
#define FDDMA0_SPIM1_RX_SLAVE_ID 20U /* spi1 rx slave-id */
#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */
#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */
#define FDDMA_MIN_SLAVE_ID 0U
#define FDDMA_MAX_SLAVE_ID 31U
/* ADC */
#if !defined(__ASSEMBLER__)
typedef enum
{
FADC_INSTANCE_0 = 0,
FADC_INSTANCE_1,
FADC_INSTANCE_NUM
} FAdcInstance;
typedef enum
{
FADC_CHANNEL_0 = 0,
FADC_CHANNEL_1 = 1,
FADC_CHANNEL_2,
FADC_CHANNEL_3,
FADC_CHANNEL_4,
FADC_CHANNEL_5,
FADC_CHANNEL_6,
FADC_CHANNEL_7,
FADC_CHANNEL_NUM
} FAdcChannel;
#endif
#define FADC0_CONTROL_BASE 0x2807B000U
#define FADC1_CONTROL_BASE 0x2807C000U
#define FADC0_INTR_IRQ 264U
#define FADC1_INTR_IRQ 265U
/* PWM */
#if !defined(__ASSEMBLER__)
typedef enum
{
FPWM_INSTANCE_0 = 0,
FPWM_INSTANCE_1,
FPWM_INSTANCE_2,
FPWM_INSTANCE_3,
FPWM_INSTANCE_4,
FPWM_INSTANCE_5,
FPWM_INSTANCE_6,
FPWM_INSTANCE_7,
FPWM_INSTANCE_NUM
} FPwmInstance;
typedef enum
{
FPWM_CHANNEL_0 = 0,
FPWM_CHANNEL_1,
FPWM_CHANNEL_NUM
} FPwmChannel;
#endif
#define FPWM_CONTROL_BASE 0x2804A000U
#define FPWM_CLK 50000000U /* 50MHz */
#define FPWM0_INTR_IRQ 205U
#define FPWM1_INTR_IRQ 206U
#define FPWM2_INTR_IRQ 207U
#define FPWM3_INTR_IRQ 208U
#define FPWM4_INTR_IRQ 209U
#define FPWM5_INTR_IRQ 210U
#define FPWM6_INTR_IRQ 211U
#define FPWM7_INTR_IRQ 212U
#define FPWM8_INTR_IRQ 213U
#define FPWM9_INTR_IRQ 214U
#define FPWM10_INTR_IRQ 215U
#define FPWM11_INTR_IRQ 216U
#define FPWM12_INTR_IRQ 217U
#define FPWM13_INTR_IRQ 218U
#define FPWM14_INTR_IRQ 219U
#define FPWM15_INTR_IRQ 220U
/* Semaphore */
#define FSEMA0_ID 0U
#define FSEMA0_BASE_ADDR 0x32B36000U
#define FSEMA_INSTANCE_NUM 1U
/* LSD Config */
#define FLSD_CONFIG_BASE 0x2807E000U
#define FLSD_NAND_MMCSD_HADDR 0xC0U
#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U
/* USB3 */
#define FUSB3_ID_0 0U
#define FUSB3_ID_1 1U
#define FUSB3_NUM 2U
#define FUSB3_XHCI_OFFSET 0x8000U
#define FUSB3_0_BASE_ADDR 0x31A00000U
#define FUSB3_1_BASE_ADDR 0x31A20000U
#define FUSB3_0_IRQ_NUM 48U
#define FUSB3_1_IRQ_NUM 49U
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

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#ifndef BOARD_E2000Q_FIOPAD_H
#define BOARD_E2000Q_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN59 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL53 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN51 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW57 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW59 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN57 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL59 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ59 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ57 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG59 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG57 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE59 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC59 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC57 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR49 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR59 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU59 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR57 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R57 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R59 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U59 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W59 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U57 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C37 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A49 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C49 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A51 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C31 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL47 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN49 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG49 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE53 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W53 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G59 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J59 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L57 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C59 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E59 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J57 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L59 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N59 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C57 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E57 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N33 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N43 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L31 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E29 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G29 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N27 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G41 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L43 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C43 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E41 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E35 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G35 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L37 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R51 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R49 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E47 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G47 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J47 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L49 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N53 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

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bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c Normal file
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@ -0,0 +1,619 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fdebug.h"
#include "fpinctrl.h"
#include "fassert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI0_ID == spim_id)
{
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
FPinGetFunc(FIOPAD_U53));
FPinSetFunc(FIOPAD_W55, FPIN_FUNC2); /* sclk */
FPinSetFunc(FIOPAD_W53, FPIN_FUNC2); /* txd */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC2); /* rxd */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC2); /* csn0 */
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55),
FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55),
FPinGetFunc(FIOPAD_U53));
}
else if (FSPI1_ID == spim_id)
{
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
FPinGetFunc(FIOPAD_J29));
FPinSetFunc(FIOPAD_N43, FPIN_FUNC4); /* sclk */
FPinSetFunc(FIOPAD_L31, FPIN_FUNC4); /* txd */
FPinSetFunc(FIOPAD_J31, FPIN_FUNC4); /* rxd */
FPinSetFunc(FIOPAD_J29, FPIN_FUNC4); /* csn0 */
FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43),
FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31),
FPinGetFunc(FIOPAD_J29));
}
else if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A33, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC0); /* csn0 */
}
else if (FSPI3_ID == spim_id)
{
FPinSetFunc(FIOPAD_AC55, FPIN_FUNC2); /* sclk */
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC2); /* txd */
FPinSetFunc(FIOPAD_AE51, FPIN_FUNC2); /* rxd */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC2); /* csn0 */
}
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_2 == gpio_id)
{
switch (pin_id)
{
case 11: /* gpio 2-a-11 */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
break;
case 12: /* gpio 2-a-12 */
FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
break;
case 13: /* gpio 2-a-13 */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
break;
case 14: /* gpio 2-a-14 */
FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
break;
case 15: /* gpio 2-a-15 */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
break;
}
}
else if (FGPIO_ID_3 == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
break;
default:
break;
}
}
else if (FGPIO_ID_4 == gpio_id)
{
switch (pin_id)
{
case 5: /* gpio 4-a-5 */
FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
break;
case 9: /* gpio 4-a-9 */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetCanMux
* @msg: set iopad mux for can
* @return {*}
* @param {u32} can_id, instance id of can
*/
void FIOPadSetCanMux(u32 can_id)
{
if (can_id == FCAN_INSTANCE_0)
{
/* mio0 */
FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */
}
else if (can_id == FCAN_INSTANCE_1)
{
/* mio1 */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetQspiMux
* @msg: set iopad mux for qspi
* @return {*}
* @param {u32} qspi_id, id of qspi instance
* @param {u32} cs_id, id of qspi cs
*/
void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
{
if (qspi_id == FQSPI_INSTANCE_0)
{
/* add sck, io0-io3 iopad multiplex */
}
if (cs_id == FQSPI_CS_0)
{
FPinSetFunc(FIOPAD_AR55, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_1)
{
FPinSetFunc(FIOPAD_AR49, FPIN_FUNC0);
}
else if (cs_id == FQSPI_CS_2)
{
FPinSetFunc(FIOPAD_C37, FPIN_FUNC5);
}
else if (cs_id == FQSPI_CS_3)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5);
}
else
{
FIOPAD_ERROR("can id is error.\r\n");
}
}
/**
* @name: FIOPadSetPwmMux
* @msg: set iopad mux for pwm
* @return {*}
* @param {u32} pwm_id, id of pwm instance
* @param {u32} pwm_channel, channel of pwm instance
*/
void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
{
FASSERT(pwm_id < FPWM_INSTANCE_NUM);
FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
switch (pwm_id)
{
case FPWM_INSTANCE_0:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
}
break;
case FPWM_INSTANCE_1:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
}
break;
case FPWM_INSTANCE_2:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
}
break;
case FPWM_INSTANCE_3:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
}
break;
case FPWM_INSTANCE_4:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
}
break;
case FPWM_INSTANCE_5:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
}
break;
case FPWM_INSTANCE_6:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
}
break;
case FPWM_INSTANCE_7:
if (pwm_channel == 0)
{
FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
}
if (pwm_channel == 1)
{
FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
}
break;
default:
FIOPAD_ERROR("pwm id is error.\r\n");
break;
}
}
/**
* @name: FIOPadSetAdcMux
* @msg: set iopad mux for adc
* @return {*}
* @param {u32} adc_id, id of adc instance
* @param {u32} adc_channel, id of adc channel
*/
void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
{
if (adc_id == FADC_INSTANCE_0)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else if (adc_id == FADC_INSTANCE_1)
{
switch (adc_channel)
{
case FADC_CHANNEL_0:
FPinSetFunc(FIOPAD_G47, FPIN_FUNC7); /* adc1-0: func 7 */
break;
case FADC_CHANNEL_1:
FPinSetFunc(FIOPAD_J47, FPIN_FUNC7); /* adc1-1: func 7 */
break;
case FADC_CHANNEL_2:
FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-2: func 7 */
break;
case FADC_CHANNEL_3:
FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-3: func 7 */
break;
case FADC_CHANNEL_4:
FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc1-4: func 7 */
break;
case FADC_CHANNEL_5:
FPinSetFunc(FIOPAD_L49, FPIN_FUNC7); /* adc1-5: func 7 */
break;
case FADC_CHANNEL_6:
FPinSetFunc(FIOPAD_N53, FPIN_FUNC7); /* adc1-6: func 7 */
break;
case FADC_CHANNEL_7:
FPinSetFunc(FIOPAD_J53, FPIN_FUNC7); /* adc1-7: func 7 */
break;
default:
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
break;
}
}
else
{
FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
break;
default:
break;
}
}

50
bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BOARD_E2000Q_PARAMTERERS_H
#define BOARD_E2000Q_PARAMTERERS_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fparameters_comm.h"
/************************** Constant Definitions *****************************/
#define CORE0_AFF 0x000U
#define CORE1_AFF 0x100U
#define CORE2_AFF 0x200U
#define CORE3_AFF 0x201U
#define FT_CPUS_NR 4U
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

270
bsp/phytium/libraries/standalone/board/e2000/s/fiopad.h Normal file
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#ifndef BOARD_E2000Q_FIOPAD_H
#define BOARD_E2000Q_FIOPAD_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fiopad_comm.h"
/************************** Constant Definitions *****************************/
/* register offset of iopad function / pull / driver strength */
#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET)
#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET)
#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET)
#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET)
#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET)
#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET)
#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET)
#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET)
#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET)
#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET)
#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET)
#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET)
#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET)
#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET)
#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET)
#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET)
#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET)
#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET)
#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET)
#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET)
#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET)
#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET)
#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET)
#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET)
#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET)
#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET)
#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET)
#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET)
#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET)
#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET)
#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET)
#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET)
#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET)
#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET)
#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET)
#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET)
#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET)
#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET)
#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET)
#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET)
#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET)
#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET)
#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET)
#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET)
#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET)
#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET)
#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET)
#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET)
#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET)
#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET)
#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET)
#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET)
#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET)
#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET)
#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET)
#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET)
#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET)
#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET)
#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET)
#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET)
#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET)
#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET)
#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET)
#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET)
#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET)
#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET)
#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET)
#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET)
#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET)
#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET)
#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET)
#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET)
#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET)
#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET)
#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET)
#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET)
#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET)
#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET)
#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET)
#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET)
#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET)
#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET)
#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET)
#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET)
#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET)
#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET)
#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET)
#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET)
#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET)
#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET)
#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET)
#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET)
#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET)
#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET)
#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET)
#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET)
#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET)
#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET)
#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET)
#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET)
#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET)
#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET)
#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET)
#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET)
#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET)
#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET)
#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET)
#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET)
#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET)
#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET)
#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET)
#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET)
#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET)
#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET)
#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET)
#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET)
#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET)
#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET)
#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET)
#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET)
#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET)
#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET)
#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET)
#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET)
#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET)
#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET)
#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET)
#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET)
#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET)
#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET)
#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET)
#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET)
#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET)
#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET)
#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET)
#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET)
#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET)
#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET)
#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET)
#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET)
#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET)
#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET)
/* register offset of iopad delay */
#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET)
#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET)
#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET)
#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET)
#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET)
#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET)
#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET)
#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET)
#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET)
#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET)
#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET)
#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET)
#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET)
#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET)
#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET)
#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET)
#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET)
#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET)
#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET)
#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET)
#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET)
#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET)
#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET)
#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET)
#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET)
#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET)
#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET)
#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET)
#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET)
#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET)
#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET)
#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET)
#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET)
#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET)
#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET)
#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET)
#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET)
#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET)
#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET)
#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET)
#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET)
#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET)
#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET)
#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET)
#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET)
#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET)
#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET)
#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET)
#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET)
#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET)
#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET)
#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET)
#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET)
#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET)
#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET)
#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET)
#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET)
#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET)
#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET)
#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET)
#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET)
#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET)
#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET)
#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET)
#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET)
#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET)
#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET)
#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET)
#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET)
#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET)
#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET)
#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET)
#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET)
#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET)
#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET)
#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET)
#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET)
#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET)
#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET)
#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET)
#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET)
#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET)
#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET)
#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET)
#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET)
#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET)
#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET)
#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET)
#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET)
#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET)
#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET)
#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET)
#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET)
#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET)
#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET)
#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET)
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

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bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c Normal file
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@ -0,0 +1,291 @@
/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fiopad_config.c
* Date: 2022-02-10 14:53:42
* LastEditTime: 2022-02-18 08:25:29
* Description:  This files is for io-pad function definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021/11/5 init commit
* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
*/
/***************************** Include Files *********************************/
#include "fiopad.h"
#include "fparameters.h"
#include "fpinctrl.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
* @name: FIOPadSetSpimMux
* @msg: set iopad mux for spim
* @return {*}
* @param {u32} spim_id, instance id of spi
*/
void FIOPadSetSpimMux(u32 spim_id)
{
if (FSPI2_ID == spim_id)
{
FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
}
}
/**
* @name: FIOPadSetGpioMux
* @msg: set iopad mux for gpio
* @return {*}
* @param {u32} gpio_id, instance id of gpio
* @param {u32} pin_id, index of pin
*/
void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
{
if (FGPIO_ID_3 == gpio_id)
{
switch (pin_id)
{
case 3: /* gpio 3-a-3 */
FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
break;
case 4: /* gpio 3-a-4 */
FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
break;
case 5: /* gpio 3-a-5 */
FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
break;
case 6: /* gpio 3-a-6 */
FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
break;
default:
break;
}
}
}
/**
* @name: FIOPadSetMioMux
* @msg: set iopad mux for mio
* @return {*}
* @param {u32} mio_id, instance id of i2c
*/
void FIOPadSetMioMux(u32 mio_id)
{
switch (mio_id)
{
case MIO_INSTANCE_0:
{
FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_1:
{
FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_2:
{
FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_3:
{
FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_4:
{
FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_5:
{
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_6:
{
FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_7:
{
FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_8:
{
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_9:
{
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
}
break;
case MIO_INSTANCE_10:
{
FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
}
break;
case MIO_INSTANCE_11:
{
FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_12:
{
FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
}
break;
case MIO_INSTANCE_13:
{
FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_14:
{
FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
}
break;
case MIO_INSTANCE_15:
{
FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
}
break;
default:
break;
}
}
/**
* @name: FIOPadSetTachoMux
* @msg: set iopad mux for pwm_in
* @return {*}
* @param {u32} pwm_in_id, instance id of tacho
*/
void FIOPadSetTachoMux(u32 pwm_in_id)
{
switch (pwm_in_id)
{
case TACHO_INSTANCE_0:
FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_1:
FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_2:
FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_3:
FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
break;
case TACHO_INSTANCE_4:
FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
break;
case TACHO_INSTANCE_5:
FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
break;
case TACHO_INSTANCE_6:
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
break;
case TACHO_INSTANCE_7:
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
break;
case TACHO_INSTANCE_8:
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
break;
case TACHO_INSTANCE_9:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
break;
case TACHO_INSTANCE_10:
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_11:
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
break;
case TACHO_INSTANCE_12:
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
break;
case TACHO_INSTANCE_13:
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
break;
case TACHO_INSTANCE_14:
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
break;
case TACHO_INSTANCE_15:
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
break;
default:
break;
}
}
/**
* @name: FIOPadSetUartMux
* @msg: set iopad mux for uart
* @return {*}
* @param {u32} uart_id, instance id of uart
*/
void FIOPadSetUartMux(u32 uart_id)
{
switch (uart_id)
{
case FUART0_ID:
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
break;
case FUART1_ID:
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
break;
case FUART2_ID:
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
break;
case FUART3_ID:
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
break;
default:
break;
}
}

53
bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fparameters.h
* Date: 2022-02-11 13:33:28
* LastEditTime: 2022-02-17 18:00:50
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BOARD_E2000S_PARAMTERERS_H
#define BOARD_E2000S_PARAMTERERS_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fparameters_comm.h"
/************************** Constant Definitions *****************************/
#define CORE0_AFF 0x200U
#define FT_CPUS_NR 1U
/* GIC offset */
#define FT_GIC_REDISTRUBUTIOR_OFFSET 2
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif

64
bsp/phytium/libraries/standalone/common/Kconfig Normal file
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choice DEBUG_LOG_LEVEL
prompt "Debug Log Level"
default LOG_ERROR
help
VERBOS: Print bigger chunks of debugging information
DEBUG: Print extra information for debugging
INFO: Print necessary information messages
WARN: Print error conditions from which recovery measures have been taken
ERROR: Print critical errors, software module can not recover on its own
config LOG_VERBOS
bool "VERBOS"
config LOG_DEBUG
bool "DEBUG"
config LOG_INFO
bool "INFO"
config LOG_WARN
bool "WARN"
config LOG_ERROR
bool "ERROR"
config LOG_NONE
bool "NONE"
endchoice # DEBUG_LOG_LEVEL
config USE_DEFAULT_INTERRUPT_CONFIG
bool
prompt "Use default interrupt configuration"
default y
help
"If this option is not selected, core0 is used as the main core by default and all interrupt driver modules are initialized. Non-0 core initializes only the necessary interrupt driver modules. If this option is selected, the developer needs to initiate each module independently "
if USE_DEFAULT_INTERRUPT_CONFIG
choice INTERRUPT_ROLE_SELECT
prompt "Interrupt role select"
default INTERRUPT_ROLE_MASTER
help
"Select Interrupt role"
config INTERRUPT_ROLE_MASTER
bool "use master role"
config INTERRUPT_ROLE_SLAVE
bool "use slave role"
endchoice # INTERRUPT_ROLE_SELECT
endif
config LOG_EXTRA_INFO
bool "Debug Log with Extra Info"
default n
help
Print debug information with source file name and source code line num.
config BOOTUP_DEBUG_PRINTS
bool
prompt "Bootup debug"
default n
help
Enable Bootup debug printing

118
bsp/phytium/libraries/standalone/common/fassert.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: ft_assert.c
* Date: 2021-04-07 09:53:07
* LastEditTime: 2022-02-17 18:04:28
* Description:  This files is for assertion implmentation
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021.4 init commit
* 1.1 zhugengyu 2022.3 re-define assert macro
*/
/***************************** Include Files *********************************/
#include "ftypes.h"
#include "fassert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
typedef struct
{
u32 status; /* 当前断言状态 */
FAssertCB cb; /* 断言回调函数 */
} FAssertInfo; /* 断言实例类型 */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static void FAssertCallback(const char *file, s32 line, int ret);
/************************** Variable Definitions *****************************/
static FAssertInfo assert_info =
{
.status = FASSERT_NONE,
.cb = FAssertCallback
}; /* 断言实例 */
/*****************************************************************************/
/**
* @name: FAssertSetStatus
* @msg: 设置断言状态
* @return {*}
* @param {FAssertStatus} status, 断言状态
*/
void FAssertSetStatus(FAssertStatus status)
{
assert_info.status = status;
}
/**
* @name: FAssertGetStatus
* @msg: 获取当前断言状态
* @return {FAssertStatus} 当前断言状态
*/
FAssertStatus FAssertGetStatus(void)
{
return assert_info.status;
}
/**
* @name: FAssertCallback
* @msg: 默认的断言回调函数
* @return {*}
* @param {char} *file, 断言发生的源文件
* @param {s32} line, 断言发生的源文件行号
* @param {int} ret, 保留给Non-block断言使用
*/
static void FAssertCallback(const char *file, s32 line, int ret)
{
f_printk("Assert Error at %s : %ld \r\n", file, line);
}
/**
* @name: FAssertSetCB
* @msg: 设置断言回调函数
* @return {*}
* @param {FAssertCB} cb, 断言回调函数
*/
void FAssertSetCB(FAssertCB cb)
{
if (NULL != cb)
assert_info.cb = cb;
}
/**
* @name: FAssert
* @msg: 断言实现
* @return {*}
* @param {char} *file, 断言发生的源文件
* @param {s32} line, 断言发生的源文件行号
* @param {int} code, 断言发生的退出码，保留给Non-block断言使用
*/
void FAssert(const char *file, s32 line, int code)
{
if (NULL != assert_info.cb)
{
/* 如果要实现Non-block断言，需要在回调中返回 */
assert_info.cb(file, line, code);
}
while (TRUE)
{
;
}
}

102
bsp/phytium/libraries/standalone/common/fassert.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fassert.h
* Date: 2021-04-07 09:53:07
* LastEditTime: 2022-02-17 18:04:35
* Description:  This files is for assertion defintion
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 huanghe 2021.4 init commit
* 1.1 zhugengyu 2022.3 re-define assert macro
*/
#ifndef FT_ASSERT_H
#define FT_ASSERT_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "fprintk.h"
#include "ferror_code.h"
#include "ftypes.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
typedef enum
{
FASSERT_NONE = 0,
FASSERT_OCCURRED
} FAssertStatus; /* 断言状态 */
/* 断言处理回调函数 */
typedef void (*FAssertCB)(const char *file, s32 line, int ret);
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FASSERT_MSG(expression, fmt, ...) \
{ \
if (expression) \
{ \
FAssertSetStatus(FASSERT_NONE); \
} \
else \
{ \
FAssertSetStatus(FASSERT_OCCURRED); \
f_printk(fmt, ##__VA_ARGS__); \
FAssert(__FILE__, __LINE__, 0xff); \
} \
}
#define FASSERT(expression)\
{ \
if (expression) \
{ \
FAssertSetStatus(FASSERT_NONE); \
} \
else \
{ \
FAssertSetStatus(FASSERT_OCCURRED); \
FAssert(__FILE__, __LINE__, 0xff); \
} \
}
/* 检查静态断言状态 */
#define FASSERT_STATIC(expression) \
extern int assert_static[(expression) ? 1 : -1]
/************************** Function Prototypes ******************************/
/* 设置断言状态 */
void FAssertSetStatus(FAssertStatus status);
/* 获取当前断言状态 */
FAssertStatus FAssertGetStatus(void);
/* 设置断言回调函数 */
void FAssertSetCB(FAssertCB cb);
/* 断言实现 */
void FAssert(const char *file, s32 line, int code);
#ifdef __cplusplus
}
#endif
#endif // !

106
bsp/phytium/libraries/standalone/common/fdebug.c Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: ft_debug.c
* Date: 2021-04-25 16:44:23
* LastEditTime: 2022-02-17 18:04:50
* Description:  This files is for
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#include "fdebug.h"
#include "fprintf.h"
#include "stdio.h"
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
void FtDumpHexByte(const u8 *ptr, u32 buflen)
{
u8 *buf = (u8 *)ptr;
fsize_t i, j;
for (i = 0; i < buflen; i += 16)
{
printf("%p: ", ptr + i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
printf("%02X ", buf[i + j]);
else
printf(" ");
printf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
printf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
printf("\r\n");
}
}
void FtDumpHexByteDebug(const u8 *ptr, u32 buflen)
{
u8 *buf = (u8 *)ptr;
fsize_t i, j;
for (i = 0; i < buflen; i += 16)
{
f_printf("%x: ", ptr + i);
for (j = 0; j < 16; j++)
if (i + j < buflen)
f_printf("%x ", buf[i + j]);
else
f_printf(" ");
f_printf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
f_printf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
f_printf("\r\n");
}
}
void FtDumpHexWord(const u32 *ptr, u32 buflen)
{
u32 *buf = (u32 *)ptr;
u8 *char_data = (u8 *)ptr;
fsize_t i, j;
buflen = buflen / 4;
for (i = 0; i < buflen; i += 4)
{
printf("%p: ", ptr + i);
for (j = 0; j < 4; j++)
{
if (i + j < buflen)
{
printf("%lx ", buf[i + j]);
}
else
{
printf(" ");
}
}
printf(" ");
for (j = 0; j < 16; j++)
if (i + j < buflen)
printf("%c", (char)(__is_print(char_data[i + j]) ? char_data[i + j] : '.'));
printf("\r\n");
}
}

127
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fdebug.h
* Date: 2021-04-07 09:53:07
* LastEditTime: 2022-02-17 18:04:58
* Description:  This files is for debug functions
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef BSP_COMMON_FT_DEBUG_H
#define BSP_COMMON_FT_DEBUG_H
#include <stdio.h>
#include "sdkconfig.h"
#include "ftypes.h"
typedef enum
{
FT_LOG_NONE, /* No log output */
FT_LOG_ERROR, /* Critical errors, software module can not recover on its own */
FT_LOG_WARN, /* Error conditions from which recovery measures have been taken */
FT_LOG_INFO, /* Information messages which describe normal flow of events */
FT_LOG_DEBUG, /* Extra information which is not necessary for normal use (values, pointers, sizes, etc). */
FT_LOG_VERBOSE /* Bigger chunks of debugging information, or frequent messages which can potentially flood the output. */
} ft_log_level_t;
#define LOG_COLOR_BLACK "30"
#define LOG_COLOR_RED "31"
#define LOG_COLOR_GREEN "32"
#define LOG_COLOR_BROWN "33"
#define LOG_COLOR_BLUE "34"
#define LOG_COLOR_PURPLE "35"
#define LOG_COLOR_CYAN "36"
#define LOG_COLOR(COLOR) "\033[0;" COLOR "m"
#define LOG_BOLD(COLOR) "\033[1;" COLOR "m"
#define LOG_RESET_COLOR "\033[0m"
#define LOG_COLOR_E LOG_COLOR(LOG_COLOR_RED)
#define LOG_COLOR_W LOG_COLOR(LOG_COLOR_BROWN)
#define LOG_COLOR_I LOG_COLOR(LOG_COLOR_GREEN)
#define LOG_COLOR_D LOG_COLOR(LOG_COLOR_CYAN)
#define LOG_COLOR_V LOG_COLOR(LOG_COLOR_PURPLE)
/* select debug log level */
#ifdef CONFIG_LOG_VERBOS
#define LOG_LOCAL_LEVEL FT_LOG_VERBOSE
#endif
#ifdef CONFIG_LOG_ERROR
#define LOG_LOCAL_LEVEL FT_LOG_ERROR
#endif
#ifdef CONFIG_LOG_WARN
#define LOG_LOCAL_LEVEL FT_LOG_WARN
#endif
#ifdef CONFIG_LOG_INFO
#define LOG_LOCAL_LEVEL FT_LOG_INFO
#endif
#ifdef CONFIG_LOG_DEBUG
#define LOG_LOCAL_LEVEL FT_LOG_DEBUG
#endif
#define LOG_FORMAT(letter, format) LOG_COLOR_##letter " %s: " format LOG_RESET_COLOR "\r\n"
#define PORT_KPRINTF printf
#ifndef CONFIG_LOG_EXTRA_INFO
#define LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) \
do \
{ \
if (LOG_LOCAL_LEVEL < log_level) \
break; \
PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \
} while (0)
#else
#include <string.h>
#define __FILENAME__ (strrchr(__FILE__, '/') ? (strrchr(__FILE__, '/') + 1):__FILE__)
/* print debug information with source file name and source code line num. */
#define LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) \
do \
{ \
if (LOG_LOCAL_LEVEL < log_level) \
break; \
PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format" @%s:%d"), tag, ##__VA_ARGS__, __FILENAME__, __LINE__); \
} while (0)
#endif
#define EARLY_LOGE(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_ERROR, E, ##__VA_ARGS__)
#define EARLY_LOGI(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_INFO, I, ##__VA_ARGS__)
#define EARLY_LOGD(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_DEBUG, D, ##__VA_ARGS__)
#define EARLY_LOGW(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_WARN, W, ##__VA_ARGS__)
#define EARLY_LOGV(tag, format, ...) LOG_EARLY_IMPL(tag, format, FT_LOG_VERBOSE, W, ##__VA_ARGS__)
/* do not compile log if define CONFIG_LOG_NONE */
#ifndef CONFIG_LOG_NONE
#define FT_DEBUG_PRINT_I(TAG, format, ...) EARLY_LOGI(TAG, format, ##__VA_ARGS__)
#define FT_DEBUG_PRINT_E(TAG, format, ...) EARLY_LOGE(TAG, format, ##__VA_ARGS__)
#define FT_DEBUG_PRINT_D(TAG, format, ...) EARLY_LOGD(TAG, format, ##__VA_ARGS__)
#define FT_DEBUG_PRINT_W(TAG, format, ...) EARLY_LOGW(TAG, format, ##__VA_ARGS__)
#define FT_DEBUG_PRINT_V(TAG, format, ...) EARLY_LOGV(TAG, format, ##__VA_ARGS__)
#else
#define FT_DEBUG_PRINT_I(TAG, format, ...)
#define FT_DEBUG_PRINT_E(TAG, format, ...)
#define FT_DEBUG_PRINT_D(TAG, format, ...)
#define FT_DEBUG_PRINT_W(TAG, format, ...)
#define FT_DEBUG_PRINT_V(TAG, format, ...)
#endif
#define FT_RAW_PRINTF(format, ...) PORT_KPRINTF(format, ##__VA_ARGS__)
void FtDumpHexWord(const u32 *ptr, u32 buflen);
void FtDumpHexByte(const u8 *ptr, u32 buflen);
#endif // !

106
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: ferror_code.h
* Date: 2021-04-07 09:53:30
* LastEditTime: 2022-02-17 18:05:27
* Description:  This files is for error code functions
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef _FT_ERROR_CODE_H
#define _FT_ERROR_CODE_H
#include "ftypes.h"
typedef u32 FError;
#define FT_SUCCESS 0
/* 系统错误码模块定义 */
typedef enum
{
ErrorModGeneral = 0,
ErrModBsp,
ErrModAssert,
ErrModPort,
StatusModBsp,
ErrModMaxMask = 255,
} FtErrorCodeModuleMask;
/* COMMON组件的错误码子模块定义 */
typedef enum
{
ErrCommGeneral = 0,
ErrCommMemp,
ErrInterrupt,
} FtErrCodeCommMask;
/* BSP模块的错误子模块定义 */
typedef enum
{
ErrBspGeneral = 0,
ErrBspClk,
ErrBspRtc,
ErrBspTimer,
ErrBspUart,
ErrBspGpio,
ErrBspSpi,
ErrBspEth,
ErrBspCan,
ErrPcie,
ErrBspQSpi,
ErrBspMio,
ErrBspI2c,
ErrBspMmc,
ErrBspWdt,
ErrGic,
ErrGdma,
ErrNand,
ErrIoMux,
ErrBspSata,
ErrUsb,
ErrEthPhy,
ErrDdma,
ErrBspAdc,
ErrBspPwm,
ErrSema,
ErrBspModMaxMask = 255
} FtErrCodeBspMask;
#define FT_ERRCODE_SYS_MODULE_OFFSET (u32)24
#define FT_ERRCODE_SUB_MODULE_OFFSET (u32)16
#define FT_ERRCODE_SYS_MODULE_MASK ((u32)0xff << FT_ERRCODE_SYS_MODULE_OFFSET) /* bit 24 .. 31 */
#define FT_ERRCODE_SUB_MODULE_MASK ((u32)0xff << FT_ERRCODE_SUB_MODULE_OFFSET) /* bit 16 .. 23 */
#define FT_ERRCODE_TAIL_VALUE_MASK ((u32)0xffff) /* bit 1 .. 15 */
/* Offset error code */
#define FT_ERRCODE_OFFSET(code, offset, mask) \
(((code) << (offset)) & (mask))
/* Assembly error code */
#define FT_MAKE_ERRCODE(sys_mode, sub_mode, tail) \
((FT_ERRCODE_OFFSET((u32)sys_mode, FT_ERRCODE_SYS_MODULE_OFFSET, FT_ERRCODE_SYS_MODULE_MASK)) | \
(FT_ERRCODE_OFFSET((u32)sub_mode, FT_ERRCODE_SUB_MODULE_OFFSET, FT_ERRCODE_SUB_MODULE_MASK)) | \
((u32)tail & FT_ERRCODE_TAIL_VALUE_MASK))
#define FT_CODE_ERR FT_MAKE_ERRCODE
#define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */
#define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */
#endif

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bsp/phytium/libraries/standalone/common/fio.h Normal file
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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fio.h
* Date: 2021-04-07 09:53:07
* LastEditTime: 2022-02-18 08:24:01
* Description:  This files is for general reigster io functions
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
*/
#ifndef FT_IO_H
#define FT_IO_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "ftypes.h"
static _INLINE u8 FtIn8(uintptr addr)
{
return *(volatile u8 *)addr;
}
static _INLINE u16 FtIn16(uintptr addr)
{
return *(volatile u16 *)addr;
}
static _INLINE u32 FtIn32(uintptr addr)
{
return *(volatile u32 *)addr;
}
static _INLINE u64 FtIn64(uintptr addr)
{
return *(volatile u64 *)addr;
}
static _INLINE void FtOut8(uintptr addr, u8 value)
{
volatile u8 *local_addr = (volatile u8 *)addr;
*local_addr = value;
}
static _INLINE void FtOut16(uintptr addr, u16 value)
{
volatile u16 *local_addr = (volatile u16 *)addr;
*local_addr = value;
}
static _INLINE void FtOut32(uintptr addr, u32 value)
{
volatile u32 *local_addr = (volatile u32 *)addr;
*local_addr = value;
}
static _INLINE void FtOut64(uintptr addr, u64 value)
{
volatile u64 *local_addr = (volatile u64 *)addr;
*local_addr = value;
}
static _INLINE void FtSetBit32(uintptr addr, u32 value)
{
volatile u32 last_value;
last_value = FtIn32(addr);
last_value |= value;
FtOut32(addr, last_value);
}
static _INLINE void FtClearBit32(uintptr addr, u32 value)
{
volatile u32 last_value;
last_value = FtIn32(addr);
last_value &= ~value;
FtOut32(addr, last_value);
}
static _INLINE void FtToggleBit32(uintptr addr, u32 toggle_pos)
{
volatile u32 value;
value = FtIn32(addr);
value ^= (1 << toggle_pos);
FtOut32(addr, value);
}
static _INLINE u16 FtEndianSwap16(u16 data)
{
return (u16)(((data & 0xFF00U) >> 8U) | ((data & 0x00FFU) << 8U));
}
#define FT_WRITE32(_reg, _val) (*(volatile uint32_t *)&_reg = _val)
#define FT_READ32(_reg) (*(volatile uint32_t *)&_reg)
#ifdef __cplusplus
}
#endif
#endif // !

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/*
* Copyright : (C) 2022 Phytium Information Technology, Inc.
* All Rights Reserved.
*
* This program is OPEN SOURCE software: you can redistribute it and/or modify it
* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
* either version 1.0 of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the Phytium Public License for more details.
*
*
* FilePath: fpinctrl.h
* Date: 2022-03-28 14:16:09
* LastEditTime: 2022-03-28 14:16:10
* Description:  This files is for IO pin ctrl API definition
*
* Modify History:
* Ver   Who        Date         Changes
* ----- ------     --------    --------------------------------------
* 1.0 zhugengyu 2022/3/28 init commit
*/
#ifndef COMMON_FPINCTRL_H
#define COMMON_FPINCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
/***************************** Include Files *********************************/
#include "ftypes.h"
#include "sdkconfig.h"
#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
#ifndef FPIN_IO_CTRL
#define FPIN_IO_CTRL
#endif
#endif
#if defined(CONFIG_TARGET_E2000)
#ifndef FPIN_IO_PAD
#define FPIN_IO_PAD
#endif
#endif
#if defined(FPIN_IO_CTRL)
#include "fioctrl.h"
#endif
#if defined(FPIN_IO_PAD)
#include "fiopad.h"
#endif
/**************************** Type Definitions *******************************/
typedef enum
{
FPIN_FUNC0 = 0b000,
FPIN_FUNC1,
FPIN_FUNC2,
FPIN_FUNC3 = 0b011,
#if defined(FPIN_IO_PAD) /* E2000 support more pin func */
FPIN_FUNC4,
FPIN_FUNC5,
FPIN_FUNC6,
FPIN_FUNC7 = 0b111,
#endif
FPIN_NUM_OF_FUNC
} FPinFunc; /* 引脚复用功能配置, func0为默认功能 */
#if defined(FPIN_IO_PAD) /* Only support driver strength config in E2000 */
typedef enum
{
FPIN_DRV0 = 0b0000,
FPIN_DRV1,
FPIN_DRV2,
FPIN_DRV3,
FPIN_DRV4,
FPIN_DRV5,
FPIN_DRV6,
FPIN_DRV7,
FPIN_DRV8,
FPIN_DRV9,
FPIN_DRV10,
FPIN_DRV11,
FPIN_DRV12,
FPIN_DRV13,
FPIN_DRV14,
FPIN_DRV15 = 0b1111,
FPIN_NUM_OF_DRIVE
} FPinDrive; /* 引脚驱动能力配置 */
#endif
typedef enum
{
FPIN_PULL_NONE = 0b00,
FPIN_PULL_DOWN = 0b01,
FPIN_PULL_UP = 0b10,
FPIN_NUM_OF_PULL
} FPinPull; /* 引脚上下拉配置 */
typedef enum
{
FPIN_OUTPUT_DELAY = 0, /* 延时设置方向为输出 */
FPIN_INPUT_DELAY, /* 延时设置方向为输入 */
FPIN_NUM_OF_DELAY_DIR
} FPinDelayDir; /* 引脚延时配置方向 */
typedef enum
{
FPIN_DELAY_COARSE_TUNING = 0, /* 延迟粗调档位 */
FPIN_DELAY_FINE_TUNING, /* 延迟精调档位 */
FPIN_NUM_OF_DELAY_TYPE
} FPinDelayType; /* 引脚延时配置类型 */
typedef enum
{
FPIN_DELAY_NONE = 0,
FPIN_DELAY_1,
FPIN_DELAY_2,
FPIN_DELAY_3,
FPIN_DELAY_4,
FPIN_DELAY_5,
FPIN_DELAY_6,
FPIN_DELAY_7,
FPIN_NUM_OF_DELAY
} FPinDelay;
typedef enum
{
FPIN_DELAY_IN_TYPE = 0, /* input delay */
FPIN_DELAY_OUT_TYPE = 1, /* output delay */
} FPinDelayIOType;
typedef struct
{
u32 reg_off; /* 引脚配置寄存器偏移量 */
u32 reg_bit; /* 引脚配置起始位 */
} FPinIndex; /* 引脚索引 */
/************************** Variable Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define FPIN_NULL {0xffffffff, 0}
/************************** Function Prototypes ******************************/
/* 获取IO引脚当前的复用功能 */
FPinFunc FPinGetFunc(const FPinIndex pin);
/* 设置IO引脚复用功能 */
void FPinSetFunc(const FPinIndex pin, FPinFunc func);
/* 获取IO引脚当前的上下拉设置 */
FPinPull FPinGetPull(const FPinIndex pin);
/* 设置IO引脚的上下拉 */
void FPinSetPull(const FPinIndex pin, FPinPull pull);
#if defined(FPIN_IO_PAD)
/* 获取IO引脚的驱动能力 */
FPinDrive FPinGetDrive(const FPinIndex pin);
/* 设置IO引脚的驱动能力 */
void FPinSetDrive(const FPinIndex pin, FPinDrive drive);
/* 获取IO引脚的复用、上下拉和驱动能力设置 */
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive);
/* 设置IO引脚的复用、上下拉和驱动能力 */
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive);
#else
/* 获取IO引脚的复用、上下拉和驱动能力设置 */
void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull);
/* 设置IO引脚的复用、上下拉和驱动能力 */
void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull);
#endif
/* 获取IO引脚当前的单项延时设置 */
FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type);
/* 检查IO引脚延时是否使能 */
boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir);
/* 设置IO引脚单项延时 */
void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay);
/* 使能或去使能IO引脚延时 */
void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable);
/* Update and enable common IO pin delay config */
void FPinSetDelayConfig(const FPinIndex pin, FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay, boolean enable);
/* Get current common IO pin delay config */
void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay,
FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay);
#ifdef __cplusplus
}
#endif
#endif

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