bsp: enable KERNEL_REMAP for cvitek platform

Changes:

- board.c: add static assert for KERNEL_VADDR_START to check if it's valid
- board.h: updated deafult KERNEL_VADDR_START for standard version
- config bsp for v5.2.0 smart requirements
- kconfig: update bsp Kconfig for remap kernel

Signed-off-by: Shell <smokewood@qq.com>
Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9229
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>

bsp/cvitek/cv18xx_risc-v/.config

@@ -17,7 +17,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
-# CONFIG_RT_USING_HOOKLIST is not set
+CONFIG_RT_USING_HOOKLIST=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=8192
@@ -25,7 +25,7 @@ CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192
 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set
-# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
+CONFIG_RT_USING_CPU_USAGE_TRACER=y
 
 #
 # kservice optimization
@@ -83,7 +83,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_DEVICE_OPS=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 # CONFIG_RT_USING_THREADSAFE_PRINTF is not set
-# CONFIG_RT_USING_SCHED_THREAD_CTX is not set
+CONFIG_RT_USING_SCHED_THREAD_CTX=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
@@ -771,6 +771,8 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # STM32 HAL & SDK Drivers
 #
+# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set
+# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set
 # CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set
 # CONFIG_PKG_USING_STM32WB55_SDK is not set
@@ -1333,3 +1335,5 @@ CONFIG_SOC_TYPE_SG2002=y
 # CONFIG_BOARD_TYPE_MILKV_DUO_SPINOR is not set
 CONFIG_BOARD_TYPE_MILKV_DUO256M=y
 # CONFIG_BOARD_TYPE_MILKV_DUO256M_SPINOR is not set
+CONFIG_BSP_ROOTFS_TYPE_ROMFS=y
+# CONFIG_BSP_ROOTFS_TYPE_CROMFS is not set

bsp/cvitek/cv18xx_risc-v/Kconfig

@@ -20,6 +20,7 @@ config BSP_USING_CV18XX
     select RT_USING_CACHE
     select ARCH_MM_MMU
     select RT_USING_DEVICE_OPS
+    select ARCH_REMAP_KERNEL if RT_USING_SMART
     default y
 
 config C906_PLIC_PHY_ADDR

bsp/cvitek/cv18xx_risc-v/SConstruct

@@ -34,6 +34,10 @@ else:
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 
+if GetDepend('RT_USING_SMART'):
+    # use smart link.lds
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
+
 # include libraries
 objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
 

bsp/cvitek/cv18xx_risc-v/board/board.c

@@ -20,13 +20,15 @@
 #include "page.h"
 #include "lwp_arch.h"
 
+/* respect to boot loader, must be 0xFFFFFFC000200000 */
+RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xFFFFFFC000200000);
+
 rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END};
 
 extern size_t MMUTable[];
 
 struct mem_desc platform_mem_desc[] = {
     {KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM},
-    {0x1000, ((KERNEL_VADDR_START - 1) & 0xfffff000) - 1, (rt_size_t)ARCH_MAP_FAILED, DEVICE_MEM},
 };
 
 #define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]))

bsp/cvitek/cv18xx_risc-v/board/board.h

@@ -19,11 +19,11 @@ extern unsigned int __bss_start;
 extern unsigned int __bss_end;
 
 #ifndef RT_USING_SMART
-#define KERNEL_VADDR_START 0x0
+#define KERNEL_VADDR_START 0x80200000
 #endif
 
 #define RT_HW_HEAP_BEGIN ((void *)&__bss_end)
-#define RT_HW_HEAP_END   ((void *)(RT_HW_HEAP_BEGIN + 16 * 1024 * 1024))
+#define RT_HW_HEAP_END   ((void *)(KERNEL_VADDR_START + 16 * 1024 * 1024))
 #define RT_HW_PAGE_START RT_HW_HEAP_END
 #define RT_HW_PAGE_END   ((void *)(KERNEL_VADDR_START + 32 * 1024 * 1024))
 

bsp/cvitek/cv18xx_risc-v/link_smart.lds

@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/12/12     bernard      The first version
+ */
+
+INCLUDE "link_stacksize.lds"
+
+OUTPUT_ARCH( "riscv" )
+
+/*
+ * Memory layout:
+ * 0x10200000 - 0x10201000: Bootloader
+ * 0x10201000 - 0x10A00000: Kernel
+ * 0x10A00000 - 0x11200000: Heap
+ */
+
+MEMORY
+{
+   SRAM : ORIGIN = 0xFFFFFFC000200000, LENGTH = 64M
+}
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0xFFFFFFC000200000 ;
+
+    /* __STACKSIZE__ = 4096; */
+    __text_start = .;
+    .start :
+    {
+        *(.start);
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .text :
+    {
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(8);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(8);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(8);
+
+        /* section information for initial. */
+        . = ALIGN(8);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(8);
+
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        . = ALIGN(8);
+        _etext = .;
+    } > SRAM
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    } > SRAM
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
+
+    . = ALIGN(8);
+    __text_end = .;
+    __text_size = __text_end - __text_start;
+
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+
+        *(.data1)
+        *(.data1.*)
+
+        . = ALIGN(8);
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.sdata)
+        *(.sdata.*)
+    } > SRAM
+
+    . = ALIGN(8);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    } > SRAM
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE(__dtors_end__ = .);
+    } > SRAM
+
+    /* stack for dual core */
+    .stack :
+    {
+        . = ALIGN(64);
+        __stack_start__ = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu0 = .;
+
+        . += __STACKSIZE__;
+        __stack_cpu1 = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .osdebug :
+    {
+        _osdebug_start = .;
+        . += 87K;
+        _osdebug_end = .;
+    } > SRAM
+
+    . = ALIGN(8);
+
+    .sbss :
+    {
+    __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    } > SRAM
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+    __bss_end = .;
+    } > SRAM
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/cvitek/cv18xx_risc-v/rtconfig.h

@@ -11,12 +11,14 @@
 #define RT_TICK_PER_SECOND 1000
 #define RT_USING_HOOK
 #define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_HOOKLIST
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 8192
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 8192
+#define RT_USING_CPU_USAGE_TRACER
 
 /* kservice optimization */
 
@@ -51,6 +53,7 @@
 /* end of Memory Management */
 #define RT_USING_DEVICE
 #define RT_USING_DEVICE_OPS
+#define RT_USING_SCHED_THREAD_CTX
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart0"
@@ -456,5 +459,6 @@
 #define __STACKSIZE__ 8192
 #define SOC_TYPE_SG2002
 #define BOARD_TYPE_MILKV_DUO256M
+#define BSP_ROOTFS_TYPE_ROMFS
 
 #endif