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AT32UC3B: Implement initial GPIO driver and app test function (#8164)

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Raman 2023-10-23 11:30:07 +05:30 committed by GitHub
parent 9afd38455d
commit 144e662f42
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 134 additions and 8 deletions
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11
bsp/avr32uc3b0/SConscript
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@ -2,7 +2,16 @@ import rtconfig
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c', 'drv_uart.c']
src_bsp = ['application.c', 'startup.c', 'board.c']
if GetDepend(['RT_USING_PIN']):
src_bsp += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SERIAL_V2']):
src_bsp += ['drv_uart_v2.c']
else:
src_bsp += ['drv_uart.c']
src = File(src_bsp)
CPPPATH = [RTT_ROOT + '/bsp/avr32uc3b0']

21
bsp/avr32uc3b0/application.c
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@ -1,27 +1,33 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
* Date Author Notes
* 2010-03-30 Kyle First version
* 2023-10-20 Raman Gopalan Access GPIO using RT's pin abstractions
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "compiler.h"
#include "gpio.h"
#define USER_LED_1 AVR32_PIN_PA08
#define USER_LED_2 AVR32_PIN_PA07
char thread_led1_stack[1024];
struct rt_thread thread_led1;
static void rt_thread_entry_led1(void* parameter)
{
rt_pin_mode(USER_LED_1, PIN_MODE_OUTPUT);
while (1)
{
gpio_tgl_gpio_pin(AVR32_PIN_PA08);
rt_pin_write(USER_LED_1, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
gpio_tgl_gpio_pin(AVR32_PIN_PA08);
rt_pin_write(USER_LED_1, 0);
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
@ -30,12 +36,13 @@ char thread_led2_stack[1024];
struct rt_thread thread_led2;
void rt_thread_entry_led2(void* parameter)
{
rt_pin_mode(USER_LED_2, PIN_MODE_OUTPUT);
while (1)
{
gpio_tgl_gpio_pin(AVR32_PIN_PA07);
rt_pin_write(USER_LED_2, 1);
rt_thread_delay(RT_TICK_PER_SECOND);
gpio_tgl_gpio_pin(AVR32_PIN_PA07);
rt_pin_write(USER_LED_2, 0);
rt_thread_delay(RT_TICK_PER_SECOND);
}
}

6
bsp/avr32uc3b0/board.c
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@ -7,6 +7,7 @@
* Date Author Notes
* 2010-03-30 Kyle First version
* 2023-10-13 Raman Gopalan Move UART specific code sections into the drv_uart files
* 2023-10-20 Raman Gopalan Initialize GPIO sub-system
*/
#include <rtthread.h>
@ -16,6 +17,7 @@
#include "usart.h"
#include "intc.h"
#include "drv_uart.h"
#include "drv_gpio.h"
/**
* System tick interrupt handler.
@ -72,6 +74,10 @@ void rt_hw_board_init(void)
rt_hw_uart_init();
#endif
#ifdef RT_USING_PIN
rt_hw_gpio_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif

84
bsp/avr32uc3b0/drv_gpio.c Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-18 Raman Gopalan Initial version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "gpio.h"
#include <rtdbg.h>
#ifdef RT_USING_PIN
static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
/* Pointer to the register set for this GPIO port */
volatile avr32_gpio_port_t *gpio_regs = &AVR32_GPIO.port[pin >> 5];
/* Decide based on required mode */
switch (mode)
{
case PIN_MODE_OUTPUT:
gpio_regs->oders = 1 << (pin & 0x1F); /* Enable output driver */
gpio_regs->gpers = 1 << (pin & 0x1F); /* Make GPIO control this pin */
break;
case PIN_MODE_INPUT:
gpio_regs->oderc = 1 << (pin & 0x1F);
gpio_regs->gpers = 1 << (pin & 0x1F);
break;
case PIN_MODE_INPUT_PULLUP:
gpio_regs->puers = 1 << (pin & 0x1F);
break;
case PIN_MODE_INPUT_PULLDOWN:
LOG_W("Pull-down enable register not defined for AT32UC3B.");
break;
case PIN_MODE_OUTPUT_OD:
LOG_W("The open-drain mode is not synthesized on the current AVR32 products.");
break;
}
}
static void at32uc3b0_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
if (value == PIN_HIGH)
{
gpio_set_gpio_pin(pin);
}
else
{
gpio_clr_gpio_pin(pin);
}
}
static rt_int8_t at32uc3b0_pin_read(struct rt_device *device, rt_base_t pin)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW);
}
static const struct rt_pin_ops ops =
{
at32uc3b0_pin_mode,
at32uc3b0_pin_write,
at32uc3b0_pin_read,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
int rt_hw_gpio_init(void)
{
rt_device_pin_register("gpio", &ops, RT_NULL);
return 0;
}
#endif /* RT_USING_PIN */

20
bsp/avr32uc3b0/drv_gpio.h Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-18 Raman Gopalan Initial version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtconfig.h>
#ifdef RT_USING_PIN
int rt_hw_gpio_init(void);
#endif
#endif /* __DRV_GPIO_H__ */