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[libcpu/arm]SECTION=>RT_SECTION(与catch2中SECTION冲突)

This commit is contained in:
liruncong 2021-02-09 23:25:34 +08:00
parent f5ede64c83
commit 12d5ca60c5
2 changed files with 4 additions and 4 deletions
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6
libcpu/arm/realview-a8-vmm/interrupt.c
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@ -26,9 +26,9 @@ extern volatile rt_uint8_t rt_interrupt_nest;
struct rt_irq_desc isr_table[MAX_HANDLERS];
/* Those varibles will be accessed in ISR, so we need to share them. */
rt_uint32_t rt_interrupt_from_thread SECTION(".bss.share.int");
rt_uint32_t rt_interrupt_to_thread SECTION(".bss.share.int");
rt_uint32_t rt_thread_switch_interrupt_flag SECTION(".bss.share.int");
rt_uint32_t rt_interrupt_from_thread RT_SECTION(".bss.share.int");
rt_uint32_t rt_interrupt_to_thread RT_SECTION(".bss.share.int");
rt_uint32_t rt_thread_switch_interrupt_flag RT_SECTION(".bss.share.int");
const unsigned int VECTOR_BASE = 0x00;
extern void rt_cpu_vector_set_base(unsigned int addr);

2
libcpu/arm/zynq7000/mmu.c
View File

@ -109,7 +109,7 @@ void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
/* level1 page table, each entry for 1MB memory. */
/* MMUTable is the name used by codes of Xilinx */
volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024)));
volatile unsigned long MMUTable[4*1024] RT_SECTION("mmu_tbl") __attribute__((aligned(16*1024)));
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart,