mips/loongson_1b: format code
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0ee101ccb0
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11fb9060e0
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@ -30,7 +30,7 @@ void rt_interrupt_dispatch(void *ptreg);
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void rt_hw_timer_handler();
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void rt_hw_timer_handler();
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static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
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static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
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= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
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= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
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/**
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/**
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* @addtogroup Loongson LS1B
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* @addtogroup Loongson LS1B
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@ -40,7 +40,7 @@ static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
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static void rt_hw_interrupt_handler(int vector, void *param)
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static void rt_hw_interrupt_handler(int vector, void *param)
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{
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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}
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}
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/**
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/**
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@ -48,26 +48,26 @@ static void rt_hw_interrupt_handler(int vector, void *param)
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*/
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*/
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void rt_hw_interrupt_init(void)
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void rt_hw_interrupt_init(void)
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{
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{
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rt_int32_t idx;
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rt_int32_t idx;
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/* pci active low */
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/* pci active low */
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ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
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ls1b_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
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/* make all interrupts level triggered */
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/* make all interrupts level triggered */
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(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
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(ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
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/* mask all interrupts */
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/* mask all interrupts */
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(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
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(ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
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rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
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rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
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for (idx = 0; idx < MAX_INTR; idx ++)
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for (idx = 0; idx < MAX_INTR; idx ++)
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{
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{
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irq_handle_table[idx].handler = rt_hw_interrupt_handler;
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irq_handle_table[idx].handler = rt_hw_interrupt_handler;
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}
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}
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/* init interrupt nest, and context in thread sp */
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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rt_thread_switch_interrupt_flag = 0;
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}
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}
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/**
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/**
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@ -76,8 +76,8 @@ void rt_hw_interrupt_init(void)
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*/
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*/
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void rt_hw_interrupt_mask(int vector)
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void rt_hw_interrupt_mask(int vector)
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{
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{
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/* mask interrupt */
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/* mask interrupt */
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(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
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(ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
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}
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}
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/**
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/**
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@ -86,7 +86,7 @@ void rt_hw_interrupt_mask(int vector)
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*/
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*/
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void rt_hw_interrupt_umask(int vector)
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void rt_hw_interrupt_umask(int vector)
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{
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{
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(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
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(ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
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}
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}
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/**
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/**
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@ -100,8 +100,8 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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{
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{
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rt_isr_handler_t old_handler = RT_NULL;
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector >= 0 && vector < MAX_INTR)
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if (vector >= 0 && vector < MAX_INTR)
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{
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{
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old_handler = irq_handle_table[vector].handler;
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old_handler = irq_handle_table[vector].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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#ifdef RT_USING_INTERRUPT_INFO
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@ -118,71 +118,71 @@ void rt_interrupt_dispatch(void *ptreg)
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{
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{
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int irq;
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int irq;
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void *param;
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void *param;
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rt_isr_handler_t irq_func;
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rt_isr_handler_t irq_func;
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static rt_uint32_t status = 0;
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static rt_uint32_t status = 0;
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rt_uint32_t c0_status;
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rt_uint32_t c0_status;
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rt_uint32_t c0_cause;
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rt_uint32_t c0_cause;
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volatile rt_uint32_t cause_im;
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volatile rt_uint32_t cause_im;
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volatile rt_uint32_t status_im;
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volatile rt_uint32_t status_im;
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rt_uint32_t pending_im;
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rt_uint32_t pending_im;
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/* check os timer */
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/* check os timer */
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c0_status = read_c0_status();
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c0_status = read_c0_status();
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c0_cause = read_c0_cause();
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c0_cause = read_c0_cause();
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cause_im = c0_cause & ST0_IM;
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cause_im = c0_cause & ST0_IM;
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status_im = c0_status & ST0_IM;
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status_im = c0_status & ST0_IM;
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pending_im = cause_im & status_im;
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pending_im = cause_im & status_im;
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if (pending_im & CAUSEF_IP7)
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if (pending_im & CAUSEF_IP7)
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{
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{
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rt_hw_timer_handler();
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rt_hw_timer_handler();
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}
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}
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if (pending_im & CAUSEF_IP2)
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if (pending_im & CAUSEF_IP2)
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{
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{
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/* the hardware interrupt */
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/* the hardware interrupt */
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status = ls1b_hw0_icregs->int_isr;
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status = ls1b_hw0_icregs->int_isr;
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if (!status)
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if (!status)
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return;
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return;
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for (irq = MAX_INTR; irq > 0; --irq)
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for (irq = MAX_INTR; irq > 0; --irq)
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{
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{
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if ((status & (1 << irq)))
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if ((status & (1 << irq)))
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{
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{
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status &= ~(1 << irq);
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status &= ~(1 << irq);
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irq_func = irq_handle_table[irq].handler;
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irq_func = irq_handle_table[irq].handler;
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param = irq_handle_table[irq].param;
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param = irq_handle_table[irq].param;
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/* do interrupt */
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/* do interrupt */
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irq_func(irq, param);
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irq_func(irq, param);
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#ifdef RT_USING_INTERRUPT_INFO
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#ifdef RT_USING_INTERRUPT_INFO
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irq_handle_table[irq].counter++;
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irq_handle_table[irq].counter++;
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#endif /* RT_USING_INTERRUPT_INFO */
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#endif /* RT_USING_INTERRUPT_INFO */
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/* ack interrupt */
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/* ack interrupt */
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ls1b_hw0_icregs->int_clr |= (1 << irq);
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ls1b_hw0_icregs->int_clr |= (1 << irq);
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}
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}
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}
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}
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}
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}
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else if (pending_im & CAUSEF_IP3)
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else if (pending_im & CAUSEF_IP3)
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{
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{
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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}
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}
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else if (pending_im & CAUSEF_IP4)
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else if (pending_im & CAUSEF_IP4)
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{
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{
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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}
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}
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else if (pending_im & CAUSEF_IP5)
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else if (pending_im & CAUSEF_IP5)
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{
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{
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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}
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}
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else if (pending_im & CAUSEF_IP6)
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else if (pending_im & CAUSEF_IP6)
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{
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{
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
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}
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}
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}
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}
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/*@}*/
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/*@}*/
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