diff --git a/bsp/stm32l476-nucleo/.config b/bsp/stm32l476-nucleo/.config new file mode 100644 index 0000000000..96ce350fc4 --- /dev/null +++ b/bsp/stm32l476-nucleo/.config @@ -0,0 +1,184 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_DEBUG=y +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_DEBUG_INIT=0 +CONFIG_RT_DEBUG_THREAD=0 +CONFIG_RT_USING_HOOK=y +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +# CONFIG_RT_USING_MODULE is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +# CONFIG_RT_USING_USER_MAIN is not set + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +# CONFIG_RT_USING_LIBC is not set +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network stack +# + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# RT-Thread UI Engine +# +# CONFIG_RT_USING_GUIENGINE is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread online packages +# + +# +# system packages +# +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_SQLITE is not set + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_EZXML is not set + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_MARVELLWIFI is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set + +# +# language packages +# +# CONFIG_PKG_USING_JERRYSCRIPT is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_FASTLZ is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_RT_USING_UART2=y diff --git a/bsp/stm32l476-nucleo/Kconfig b/bsp/stm32l476-nucleo/Kconfig new file mode 100644 index 0000000000..a58fcdda75 --- /dev/null +++ b/bsp/stm32l476-nucleo/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default: "rt-thread" + +# you can change the RTT_ROOT default: "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/KConfig" +source "$PKGS_DIR/KConfig" +source "$BSP_DIR/drivers/Kconfig" diff --git a/bsp/stm32l476-nucleo/SConstruct b/bsp/stm32l476-nucleo/SConstruct index ac3196e370..1a32356531 100644 --- a/bsp/stm32l476-nucleo/SConstruct +++ b/bsp/stm32l476-nucleo/SConstruct @@ -15,7 +15,7 @@ except: print RTT_ROOT exit(-1) -TARGET = 'rtthread-stm32f42x.' + rtconfig.TARGET_EXT +TARGET = 'rtthread-stm32l476.' + rtconfig.TARGET_EXT env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, diff --git a/bsp/stm32l476-nucleo/applications/application.c b/bsp/stm32l476-nucleo/applications/application.c index c9300df630..2ccb6cbb01 100644 --- a/bsp/stm32l476-nucleo/applications/application.c +++ b/bsp/stm32l476-nucleo/applications/application.c @@ -1,16 +1,25 @@ /* * File : application.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes - * 2009-01-05 Bernard the first version - * 2014-04-27 Bernard make code cleanup. + * 2017-11-20 tanek first implementation */ #include @@ -44,8 +53,8 @@ #include #endif -//rt_module_t module_ptr; -#define DATA_PATH "/Data" +extern void rt_hw_userled_init(void); + void rt_init_thread_entry(void* parameter) { /* initialization RT-Thread Components */ @@ -53,6 +62,8 @@ void rt_init_thread_entry(void* parameter) rt_components_init(); #endif + rt_hw_userled_init(); + } int rt_application_init() { @@ -65,8 +76,6 @@ int rt_application_init() if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; } diff --git a/bsp/stm32l476-nucleo/applications/startup.c b/bsp/stm32l476-nucleo/applications/startup.c index 39dec62b61..03e5b04be8 100644 --- a/bsp/stm32l476-nucleo/applications/startup.c +++ b/bsp/stm32l476-nucleo/applications/startup.c @@ -1,11 +1,21 @@ /* * File : startup.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes diff --git a/bsp/stm32l476-nucleo/applications/userled.c b/bsp/stm32l476-nucleo/applications/userled.c new file mode 100644 index 0000000000..b2440dd241 --- /dev/null +++ b/bsp/stm32l476-nucleo/applications/userled.c @@ -0,0 +1,104 @@ +/* + * File : userled.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2012-09-20 heyuanjie first version + * 2012-09-29 lgnq re-fromat the coding style + */ + +#include +#include "drv_led.h" + +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +#include +#endif + +static rt_thread_t tid; + +/** + * This function is the entry of the led thread + * + * @param param parameter of the led thread + */ +static void rt_userled_thread_init(void *param) +{ + led_init(); + + led_set(1); + + /* leds blink */ + while (1) + { + led_set(0); + rt_thread_delay(RT_TICK_PER_SECOND / 100); + led_clear(0); + rt_thread_delay(RT_TICK_PER_SECOND); + } +} + +/** + * This function will create and start a led thread + */ +void rt_hw_userled_init(void) +{ + tid = rt_thread_create("userled", + rt_userled_thread_init, + RT_NULL, + 512, + 8, + 1); + if (tid != RT_NULL) + rt_thread_startup(tid); +} + +void rt_hw_userled_cleanup(void) +{ + rt_enter_critical(); + + led_clear(0); + + if (tid != RT_NULL && tid->stat != RT_THREAD_CLOSE) + { + rt_kprintf("delete led thread success\n"); + rt_thread_delete(tid); + } + else + { + rt_kprintf("delete led thread faild\n"); + if (tid == RT_NULL) + rt_kprintf("tid is null\n"); + else + rt_kprintf("tid stat is %d\n", tid->stat); + } + + rt_exit_critical(); +} +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +MSH_CMD_EXPORT_ALIAS(rt_hw_userled_cleanup, led_cleanup, delete led task); +#endif + + +void rt_hw_userled_input(void) +{ + led_deinit(); +} +#if defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) +MSH_CMD_EXPORT_ALIAS(rt_hw_userled_input, led_as_input, delete led task); +#endif diff --git a/bsp/stm32l476-nucleo/drivers/Kconfig b/bsp/stm32l476-nucleo/drivers/Kconfig new file mode 100644 index 0000000000..f47537e041 --- /dev/null +++ b/bsp/stm32l476-nucleo/drivers/Kconfig @@ -0,0 +1,7 @@ +config RT_USING_UART2 + bool "Enable UART2" + default y + +config RT_USING_PIN + bool "Enable PIN" + default y \ No newline at end of file diff --git a/bsp/stm32l476-nucleo/drivers/SConscript b/bsp/stm32l476-nucleo/drivers/SConscript index c9e2f91b91..2a38670853 100644 --- a/bsp/stm32l476-nucleo/drivers/SConscript +++ b/bsp/stm32l476-nucleo/drivers/SConscript @@ -8,6 +8,8 @@ cwd = os.path.join(str(Dir('#')), 'drivers') src = Split(""" board.c usart.c +drv_led.c +gpio.c """) CPPPATH = [cwd] diff --git a/bsp/stm32l476-nucleo/drivers/board.c b/bsp/stm32l476-nucleo/drivers/board.c index e35a4d1f46..8aa7b6dd45 100644 --- a/bsp/stm32l476-nucleo/drivers/board.c +++ b/bsp/stm32l476-nucleo/drivers/board.c @@ -1,11 +1,21 @@ /* * File : board.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 RT-Thread Develop Team + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes @@ -143,15 +153,13 @@ void rt_hw_board_init() SystemClock_Config(); - stm32_hw_usart_init(); -#ifdef RT_USING_CONSOLE - rt_console_set_device(CONSOLE_DEVICE); -#endif - #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif +#ifdef RT_USING_CONSOLE + rt_console_set_device(CONSOLE_DEVICE); +#endif } /*@}*/ diff --git a/bsp/stm32l476-nucleo/drivers/board.h b/bsp/stm32l476-nucleo/drivers/board.h index 910218e5d7..a335eb85dd 100644 --- a/bsp/stm32l476-nucleo/drivers/board.h +++ b/bsp/stm32l476-nucleo/drivers/board.h @@ -1,11 +1,21 @@ /* * File : board.h * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes @@ -56,6 +66,12 @@ void rt_hw_board_init(void); #define CONSOLE_DEVICE "uart2" #elif STM32_CONSOLE_USART == 3 #define CONSOLE_DEVICE "uart3" +#elif STM32_CONSOLE_USART == 4 +#define CONSOLE_DEVICE "uart4" +#elif STM32_CONSOLE_USART == 5 +#define CONSOLE_DEVICE "uart5" +#elif STM32_CONSOLE_USART == 6 +#define CONSOLE_DEVICE "lpuart1" #endif #define FINSH_DEVICE_NAME CONSOLE_DEVICE diff --git a/bsp/stm32l476-nucleo/drivers/drv_led.c b/bsp/stm32l476-nucleo/drivers/drv_led.c new file mode 100644 index 0000000000..29be9d700b --- /dev/null +++ b/bsp/stm32l476-nucleo/drivers/drv_led.c @@ -0,0 +1,125 @@ +/* + * File : drv_led.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + */ + +#include "board.h" +#include "drv_led.h" +#include + +//the pin number can be find in :goip.c pins[]. +//in nucleo-l476rg board,the green led is attached to PA5 which the number is 21. +#define LED 21 + +/** + * This function light up LED + * + * @param led LED number (6) + */ +void led_set(int led) +{ + if (led == 0) + { + rt_pin_write(LED, 1); + } +} + +/** + * This function return LED status, on or off + * + * @param led LED number (0-1) + */ +int led_get(int led) +{ + int ret = 0; + + if (led == 0) + { + ret = rt_pin_read(LED); + } + + return ret; +} + +/** + * This function turn off LED + * + * @param led LED number (0-1) + */ +void led_clear(int led) +{ + if (led == 0) + { + rt_pin_write(LED, 0); + } +} + +/** + * This function toggle LED, switch from on to off or vice versa + * + * @param led LED number (0-1) + */ +void led_toggle(int led) +{ + int ret = 0; + + ret = rt_pin_read(LED); + + if(ret==1) + { + ret=0; + } + else if(ret==0) + { + ret=1; + } + + if (led == 0) + { + rt_pin_write(LED, ret); + } +} + +/** + * This function light up LEDs according value of 2 least significat bits + * + * @param value Bit pattern + */ +void led_value(int value) +{ + rt_pin_write(LED, value); +} + +/** + * This function initialize LED interface + */ +void led_init(void) +{ + rt_pin_mode(LED, PIN_MODE_OUTPUT); +} + +/** + * This function initialize LED interface + */ +void led_deinit(void) +{ + rt_pin_mode(LED, PIN_MODE_INPUT); +} diff --git a/bsp/stm32l476-nucleo/drivers/drv_led.h b/bsp/stm32l476-nucleo/drivers/drv_led.h new file mode 100644 index 0000000000..c47075e9e5 --- /dev/null +++ b/bsp/stm32l476-nucleo/drivers/drv_led.h @@ -0,0 +1,43 @@ +/* + * File : drv_led.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + */ + +#ifndef __DRV_LED_H__ +#define __DRV_LED_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +void led_init(void); +void led_set(int led); +int led_get(int led); +void led_clear(int led); +void led_toggle(int led); +void led_value(int value); +void led_deinit(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/stm32l476-nucleo/drivers/gpio.c b/bsp/stm32l476-nucleo/drivers/gpio.c new file mode 100644 index 0000000000..64e8caa73a --- /dev/null +++ b/bsp/stm32l476-nucleo/drivers/gpio.c @@ -0,0 +1,867 @@ +/* + * File : gpio.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Change Logs: + * Date Author Notes + * 2017-11-20 DQL the first version + */ + +#include +#include +#include + +#ifdef RT_USING_PIN + +#define STM32L476_PIN_NUMBERS 64 //[48, 64, 100, 144 ] + +#define __STM32_PIN(index, gpio, gpio_index) \ + { \ + index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_PIN_##gpio_index \ + } +#define __STM32_PIN_DEFAULT \ + { \ + -1, 0, 0, 0 \ + } +static void GPIOA_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOA_CLK_ENABLE + __HAL_RCC_GPIOA_CLK_ENABLE(); +#endif +} +static void GPIOB_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOB_CLK_ENABLE + __HAL_RCC_GPIOB_CLK_ENABLE(); +#endif +} +static void GPIOC_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOC_CLK_ENABLE + __HAL_RCC_GPIOC_CLK_ENABLE(); +#endif +} +#if (STM32L476_PIN_NUMBERS !=48) + +static void GPIOD_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOD_CLK_ENABLE + __HAL_RCC_GPIOD_CLK_ENABLE(); +#endif +} +#if (STM32L476_PIN_NUMBERS !=64) +static void GPIOE_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOE_CLK_ENABLE + __HAL_RCC_GPIOE_CLK_ENABLE(); +#endif +} +static void GPIOF_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOF_CLK_ENABLE + __HAL_RCC_GPIOF_CLK_ENABLE(); +#endif +} +static void GPIOG_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOG_CLK_ENABLE + __HAL_RCC_GPIOG_CLK_ENABLE(); +#endif +} +static void GPIOH_CLK_ENABLE(void) +{ +#ifdef __HAL_RCC_GPIOH_CLK_ENABLE + __HAL_RCC_GPIOH_CLK_ENABLE(); +#endif +} +#endif +#endif +/* STM32 GPIO driver */ +struct pin_index +{ + int index; + void (*rcc)(void); + GPIO_TypeDef *gpio; + uint32_t pin; +}; + +static const struct pin_index pins[] = + { +#if (STM32L476_PIN_NUMBERS == 48) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, C, 13), + __STM32_PIN(3, C, 14), + __STM32_PIN(4, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(10, A, 0), + __STM32_PIN(11, A, 1), + __STM32_PIN(12, A, 2), + __STM32_PIN(13, A, 3), + __STM32_PIN(14, A, 4), + __STM32_PIN(15, A, 5), + __STM32_PIN(16, A, 6), + __STM32_PIN(17, A, 7), + __STM32_PIN(18, B, 0), + __STM32_PIN(19, B, 1), + __STM32_PIN(20, B, 2), + __STM32_PIN(21, B, 10), + __STM32_PIN(22, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(25, B, 12), + __STM32_PIN(26, B, 13), + __STM32_PIN(27, B, 14), + __STM32_PIN(28, B, 15), + __STM32_PIN(29, A, 8), + __STM32_PIN(30, A, 9), + __STM32_PIN(31, A, 10), + __STM32_PIN(32, A, 11), + __STM32_PIN(33, A, 12), + __STM32_PIN(34, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(37, A, 14), + __STM32_PIN(38, A, 15), + __STM32_PIN(39, B, 3), + __STM32_PIN(40, B, 4), + __STM32_PIN(41, B, 5), + __STM32_PIN(42, B, 6), + __STM32_PIN(43, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(45, B, 8), + __STM32_PIN(46, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + +#endif +#if (STM32L476_PIN_NUMBERS == 64) + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(2, C, 13), + __STM32_PIN(3, C, 14), + __STM32_PIN(4, C, 15), + __STM32_PIN(5, D, 0), + __STM32_PIN(6, D, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN(8, C, 0), + __STM32_PIN(9, C, 1), + __STM32_PIN(10, C, 2), + __STM32_PIN(11, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(14, A, 0), + __STM32_PIN(15, A, 1), + __STM32_PIN(16, A, 2), + __STM32_PIN(17, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(20, A, 4), + __STM32_PIN(21, A, 5), + __STM32_PIN(22, A, 6), + __STM32_PIN(23, A, 7), + __STM32_PIN(24, C, 4), + __STM32_PIN(25, C, 5), + __STM32_PIN(26, B, 0), + __STM32_PIN(27, B, 1), + __STM32_PIN(28, B, 2), + __STM32_PIN(29, B, 10), + __STM32_PIN(30, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(33, B, 12), + __STM32_PIN(34, B, 13), + __STM32_PIN(35, B, 14), + __STM32_PIN(36, B, 15), + __STM32_PIN(37, C, 6), + __STM32_PIN(38, C, 7), + __STM32_PIN(39, C, 8), + __STM32_PIN(40, C, 9), + __STM32_PIN(41, A, 8), + __STM32_PIN(42, A, 9), + __STM32_PIN(43, A, 10), + __STM32_PIN(44, A, 11), + __STM32_PIN(45, A, 12), + __STM32_PIN(46, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(49, A, 14), + __STM32_PIN(50, A, 15), + __STM32_PIN(51, C, 10), + __STM32_PIN(52, C, 11), + __STM32_PIN(53, C, 12), + __STM32_PIN(54, D, 2), + __STM32_PIN(55, B, 3), + __STM32_PIN(56, B, 4), + __STM32_PIN(57, B, 5), + __STM32_PIN(58, B, 6), + __STM32_PIN(59, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(61, B, 8), + __STM32_PIN(62, B, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32L476_PIN_NUMBERS == 100) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, C, 13), + __STM32_PIN(8, C, 14), + __STM32_PIN(9, C, 15), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(15, C, 0), + __STM32_PIN(16, C, 1), + __STM32_PIN(17, C, 2), + __STM32_PIN(18, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(23, A, 0), + __STM32_PIN(24, A, 1), + __STM32_PIN(25, A, 2), + __STM32_PIN(26, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(29, A, 4), + __STM32_PIN(30, A, 5), + __STM32_PIN(31, A, 6), + __STM32_PIN(32, A, 7), + __STM32_PIN(33, C, 4), + __STM32_PIN(34, C, 5), + __STM32_PIN(35, B, 0), + __STM32_PIN(36, B, 1), + __STM32_PIN(37, B, 2), + __STM32_PIN(38, E, 7), + __STM32_PIN(39, E, 8), + __STM32_PIN(40, E, 9), + __STM32_PIN(41, E, 10), + __STM32_PIN(42, E, 11), + __STM32_PIN(43, E, 12), + __STM32_PIN(44, E, 13), + __STM32_PIN(45, E, 14), + __STM32_PIN(46, E, 15), + __STM32_PIN(47, B, 10), + __STM32_PIN(48, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(51, B, 12), + __STM32_PIN(52, B, 13), + __STM32_PIN(53, B, 14), + __STM32_PIN(54, B, 15), + __STM32_PIN(55, D, 8), + __STM32_PIN(56, D, 9), + __STM32_PIN(57, D, 10), + __STM32_PIN(58, D, 11), + __STM32_PIN(59, D, 12), + __STM32_PIN(60, D, 13), + __STM32_PIN(61, D, 14), + __STM32_PIN(62, D, 15), + __STM32_PIN(63, C, 6), + __STM32_PIN(64, C, 7), + __STM32_PIN(65, C, 8), + __STM32_PIN(66, C, 9), + __STM32_PIN(67, A, 8), + __STM32_PIN(68, A, 9), + __STM32_PIN(69, A, 10), + __STM32_PIN(70, A, 11), + __STM32_PIN(71, A, 12), + __STM32_PIN(72, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(76, A, 14), + __STM32_PIN(77, A, 15), + __STM32_PIN(78, C, 10), + __STM32_PIN(79, C, 11), + __STM32_PIN(80, C, 12), + __STM32_PIN(81, D, 0), + __STM32_PIN(82, D, 1), + __STM32_PIN(83, D, 2), + __STM32_PIN(84, D, 3), + __STM32_PIN(85, D, 4), + __STM32_PIN(86, D, 5), + __STM32_PIN(87, D, 6), + __STM32_PIN(88, D, 7), + __STM32_PIN(89, B, 3), + __STM32_PIN(90, B, 4), + __STM32_PIN(91, B, 5), + __STM32_PIN(92, B, 6), + __STM32_PIN(93, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(95, B, 8), + __STM32_PIN(96, B, 9), + __STM32_PIN(97, E, 0), + __STM32_PIN(98, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +#if (STM32L476_PIN_NUMBERS == 144) + __STM32_PIN_DEFAULT, + __STM32_PIN(1, E, 2), + __STM32_PIN(2, E, 3), + __STM32_PIN(3, E, 4), + __STM32_PIN(4, E, 5), + __STM32_PIN(5, E, 6), + __STM32_PIN_DEFAULT, + __STM32_PIN(7, C, 13), + __STM32_PIN(8, C, 14), + __STM32_PIN(9, C, 15), + + __STM32_PIN(10, F, 0), + __STM32_PIN(11, F, 1), + __STM32_PIN(12, F, 2), + __STM32_PIN(13, F, 3), + __STM32_PIN(14, F, 4), + __STM32_PIN(15, F, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(18, F, 6), + __STM32_PIN(19, F, 7), + __STM32_PIN(20, F, 8), + __STM32_PIN(21, F, 9), + __STM32_PIN(22, F, 10), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(26, C, 0), + __STM32_PIN(27, C, 1), + __STM32_PIN(28, C, 2), + __STM32_PIN(29, C, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(34, A, 0), + __STM32_PIN(35, A, 1), + __STM32_PIN(36, A, 2), + __STM32_PIN(37, A, 3), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(40, A, 4), + __STM32_PIN(41, A, 5), + __STM32_PIN(42, A, 6), + __STM32_PIN(43, A, 7), + __STM32_PIN(44, C, 4), + __STM32_PIN(45, C, 5), + __STM32_PIN(46, B, 0), + __STM32_PIN(47, B, 1), + __STM32_PIN(48, B, 2), + __STM32_PIN(49, F, 11), + __STM32_PIN(50, F, 12), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(53, F, 13), + __STM32_PIN(54, F, 14), + __STM32_PIN(55, F, 15), + __STM32_PIN(56, G, 0), + __STM32_PIN(57, G, 1), + __STM32_PIN(58, E, 7), + __STM32_PIN(59, E, 8), + __STM32_PIN(60, E, 9), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(63, E, 10), + __STM32_PIN(64, E, 11), + __STM32_PIN(65, E, 12), + __STM32_PIN(66, E, 13), + __STM32_PIN(67, E, 14), + __STM32_PIN(68, E, 15), + __STM32_PIN(69, B, 10), + __STM32_PIN(70, B, 11), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(73, B, 12), + __STM32_PIN(74, B, 13), + __STM32_PIN(75, B, 14), + __STM32_PIN(76, B, 15), + __STM32_PIN(77, D, 8), + __STM32_PIN(78, D, 9), + __STM32_PIN(79, D, 10), + __STM32_PIN(80, D, 11), + __STM32_PIN(81, D, 12), + __STM32_PIN(82, D, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(85, D, 14), + __STM32_PIN(86, D, 15), + __STM32_PIN(87, G, 2), + __STM32_PIN(88, G, 3), + __STM32_PIN(89, G, 4), + __STM32_PIN(90, G, 5), + __STM32_PIN(91, G, 6), + __STM32_PIN(92, G, 7), + __STM32_PIN(93, G, 8), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(96, C, 6), + __STM32_PIN(97, C, 7), + __STM32_PIN(98, C, 8), + __STM32_PIN(99, C, 9), + __STM32_PIN(100, A, 8), + __STM32_PIN(101, A, 9), + __STM32_PIN(102, A, 10), + __STM32_PIN(103, A, 11), + __STM32_PIN(104, A, 12), + __STM32_PIN(105, A, 13), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(109, A, 14), + __STM32_PIN(110, A, 15), + __STM32_PIN(111, C, 10), + __STM32_PIN(112, C, 11), + __STM32_PIN(113, C, 12), + __STM32_PIN(114, D, 0), + __STM32_PIN(115, D, 1), + __STM32_PIN(116, D, 2), + __STM32_PIN(117, D, 3), + __STM32_PIN(118, D, 4), + __STM32_PIN(119, D, 5), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(122, D, 6), + __STM32_PIN(123, D, 7), + __STM32_PIN(124, G, 9), + __STM32_PIN(125, G, 10), + __STM32_PIN(126, G, 11), + __STM32_PIN(127, G, 12), + __STM32_PIN(128, G, 13), + __STM32_PIN(129, G, 14), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, + __STM32_PIN(132, G, 15), + __STM32_PIN(133, B, 3), + __STM32_PIN(134, B, 4), + __STM32_PIN(135, B, 5), + __STM32_PIN(136, B, 6), + __STM32_PIN(137, B, 7), + __STM32_PIN_DEFAULT, + __STM32_PIN(139, B, 8), + __STM32_PIN(140, B, 9), + __STM32_PIN(141, E, 0), + __STM32_PIN(142, E, 1), + __STM32_PIN_DEFAULT, + __STM32_PIN_DEFAULT, +#endif +}; + +struct pin_irq_map +{ + rt_uint16_t pinbit; + IRQn_Type irqno; +}; +static const struct pin_irq_map pin_irq_map[] = + { + {GPIO_PIN_0, EXTI0_IRQn}, + {GPIO_PIN_1, EXTI1_IRQn}, + {GPIO_PIN_2, EXTI2_IRQn}, + {GPIO_PIN_3, EXTI3_IRQn}, + {GPIO_PIN_4, EXTI4_IRQn}, + {GPIO_PIN_5, EXTI9_5_IRQn}, + {GPIO_PIN_6, EXTI9_5_IRQn}, + {GPIO_PIN_7, EXTI9_5_IRQn}, + {GPIO_PIN_8, EXTI9_5_IRQn}, + {GPIO_PIN_9, EXTI9_5_IRQn}, + {GPIO_PIN_10, EXTI15_10_IRQn}, + {GPIO_PIN_11, EXTI15_10_IRQn}, + {GPIO_PIN_12, EXTI15_10_IRQn}, + {GPIO_PIN_13, EXTI15_10_IRQn}, + {GPIO_PIN_14, EXTI15_10_IRQn}, + {GPIO_PIN_15, EXTI15_10_IRQn}, +}; +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = + { + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +const struct pin_index *get_pin(uint8_t pin) +{ + const struct pin_index *index; + + if (pin < ITEM_NUM(pins)) + { + index = &pins[pin]; + if (index->index == -1) + index = RT_NULL; + } + else + { + index = RT_NULL; + } + + return index; +}; + +void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + const struct pin_index *index; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value); +} + +int stm32_pin_read(rt_device_t dev, rt_base_t pin) +{ + int value; + const struct pin_index *index; + + value = PIN_LOW; + + index = get_pin(pin); + if (index == RT_NULL) + { + return value; + } + + value = HAL_GPIO_ReadPin(index->gpio, index->pin); + + return value; +} + +void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + const struct pin_index *index; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return; + } + + /* GPIO Periph clock enable */ + index->rcc(); + + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + + if (mode == PIN_MODE_OUTPUT) + { + /* output setting */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT) + { + /* input setting: not pull. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + /* input setting: pull up. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + } + + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); +} +rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) +{ + int i; + for (i = 0; i < 32; i++) + { + if ((0x01 << i) == bit) + { + return i; + } + } + return -1; +} +rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) +{ + rt_int32_t mapindex = bit2bitno(pinbit); + if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map)) + { + return RT_NULL; + } + return &pin_irq_map[mapindex]; +}; +rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + const struct pin_index *index; + rt_base_t level; + rt_int32_t irqindex = -1; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} +rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + const struct pin_index *index; + const struct pin_irq_map *irqmap; + rt_base_t level; + rt_int32_t irqindex = -1; + GPIO_InitTypeDef GPIO_InitStruct; + + index = get_pin(pin); + if (index == RT_NULL) + { + return RT_ENOSYS; + } + if (enabled == PIN_IRQ_ENABLE) + { + irqindex = bit2bitno(index->pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + irqmap = &pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ + index->rcc(); + /* Configure GPIO_InitStructure */ + GPIO_InitStruct.Pin = index->pin; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + break; + case PIN_IRQ_MODE_FALLING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; + break; + } + HAL_GPIO_Init(index->gpio, &GPIO_InitStruct); + HAL_NVIC_SetPriority(irqmap->irqno, 5, 0); + HAL_NVIC_EnableIRQ(irqmap->irqno); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + irqmap = get_pin_irq_map(index->pin); + if (irqmap == RT_NULL) + { + return RT_ENOSYS; + } + HAL_NVIC_DisableIRQ(irqmap->irqno); + } + else + { + return RT_ENOSYS; + } + + return RT_EOK; +} +const static struct rt_pin_ops _stm32_pin_ops = +{ + stm32_pin_mode, + stm32_pin_write, + stm32_pin_read, + stm32_pin_attach_irq, + stm32_pin_dettach_irq, + stm32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + int result; + + result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); + return result; +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +rt_inline void pin_irq_hdr(int irqno) +{ + if (pin_irq_hdr_tab[irqno].hdr) + { + pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args); + } +} + +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + pin_irq_hdr(bit2bitno(GPIO_Pin)); +} + +void EXTI0_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0); + rt_interrupt_leave(); +} +void EXTI1_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1); + rt_interrupt_leave(); +} +void EXTI2_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2); + rt_interrupt_leave(); +} +void EXTI3_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3); + rt_interrupt_leave(); +} +void EXTI4_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); + rt_interrupt_leave(); +} +void EXTI9_5_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9); + rt_interrupt_leave(); +} +void EXTI15_10_IRQHandler(void) +{ + rt_interrupt_enter(); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14); + HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15); + rt_interrupt_leave(); +} + +#endif diff --git a/bsp/stm32l476-nucleo/drivers/gpio.h b/bsp/stm32l476-nucleo/drivers/gpio.h new file mode 100644 index 0000000000..b10a315df1 --- /dev/null +++ b/bsp/stm32l476-nucleo/drivers/gpio.h @@ -0,0 +1,30 @@ +/* + * File : gpio.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-01-05 Bernard the first version + */ +#ifndef GPIO_H__ +#define GPIO_H__ + + +struct stm32_hw_pin_userdata +{ + int pin; + uint32_t mode; +}; + +#define PIN_USERDATA_END {-1,0} + +extern struct stm32_hw_pin_userdata stm32_pins[]; + +int rt_hw_pin_init(void); + +#endif diff --git a/bsp/stm32l476-nucleo/drivers/usart.c b/bsp/stm32l476-nucleo/drivers/usart.c index 07b9313924..4fa5ff5306 100644 --- a/bsp/stm32l476-nucleo/drivers/usart.c +++ b/bsp/stm32l476-nucleo/drivers/usart.c @@ -1,19 +1,25 @@ /* * File : usart.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team + * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * * Change Logs: * Date Author Notes * 2009-01-05 Bernard the first version - * 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode - * 2012-02-08 aozima update for F4. - * 2012-07-28 aozima update for ART board. - * 2016-05-28 armink add DMA Rx mode */ #include @@ -87,6 +93,19 @@ #define USART5_RX_AF GPIO_AF7_USART5 #endif +#ifdef RT_USING_LPUART1 +#define LPUART1_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define LPUART1_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() + +/* Definition for LPUART1 Pins */ +#define LPUART1_TX_PIN GPIO_PIN_0 +#define LPUART1_TX_GPIO_PORT GPIOC +#define LPUART1_TX_AF GPIO_AF8_LPUART1 +#define LPUART1_RX_PIN GPIO_PIN_1 +#define LPUART1_RX_GPIO_PORT GPIOC +#define LPUART1_RX_AF GPIO_AF8_LPUART1 +#endif + /* STM32 uart driver */ struct stm32_uart { @@ -96,90 +115,104 @@ struct stm32_uart static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg) { - struct stm32_uart *uart; + struct stm32_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); - uart = (struct stm32_uart *)serial->parent.user_data; + uart = (struct stm32_uart *)serial->parent.user_data; - uart->UartHandle.Init.BaudRate = cfg->baud_rate; - uart->UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - uart->UartHandle.Init.Mode = UART_MODE_TX_RX; - uart->UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; + uart->UartHandle.Init.BaudRate = cfg->baud_rate; + uart->UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; + uart->UartHandle.Init.Mode = UART_MODE_TX_RX; + uart->UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; - switch (cfg->data_bits) - { - case DATA_BITS_8: - uart->UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - break; - case DATA_BITS_9: - uart->UartHandle.Init.WordLength = UART_WORDLENGTH_9B; - break; - default: - uart->UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - break; - } - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->UartHandle.Init.StopBits = UART_STOPBITS_1; - break; - case STOP_BITS_2: - uart->UartHandle.Init.StopBits = UART_STOPBITS_2; - break; - default: - uart->UartHandle.Init.StopBits = UART_STOPBITS_1; - break; - } - switch (cfg->parity) - { - case PARITY_NONE: - uart->UartHandle.Init.Parity = UART_PARITY_NONE; - break; - case PARITY_ODD: - uart->UartHandle.Init.Parity = UART_PARITY_ODD; - break; - case PARITY_EVEN: - uart->UartHandle.Init.Parity = UART_PARITY_EVEN; - break; - default: - uart->UartHandle.Init.Parity = UART_PARITY_NONE; - break; - } + switch (cfg->data_bits) + { + case DATA_BITS_8: + uart->UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + break; + case DATA_BITS_9: + uart->UartHandle.Init.WordLength = UART_WORDLENGTH_9B; + break; + default: + uart->UartHandle.Init.WordLength = UART_WORDLENGTH_8B; + break; + } + + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->UartHandle.Init.StopBits = UART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->UartHandle.Init.StopBits = UART_STOPBITS_2; + break; + default: + uart->UartHandle.Init.StopBits = UART_STOPBITS_1; + break; + } + + switch (cfg->parity) + { + case PARITY_NONE: + uart->UartHandle.Init.Parity = UART_PARITY_NONE; + break; + case PARITY_ODD: + uart->UartHandle.Init.Parity = UART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->UartHandle.Init.Parity = UART_PARITY_EVEN; + break; + default: + uart->UartHandle.Init.Parity = UART_PARITY_NONE; + break; + } + + if (HAL_UART_Init(&uart->UartHandle) != HAL_OK) + { + return RT_ERROR; + } - if (HAL_UART_Init(&uart->UartHandle) != HAL_OK) - { - return RT_ERROR; - } - - return RT_EOK; + if (uart->UartHandle.Instance == LPUART1) + { + static UART_WakeUpTypeDef WakeUpSelection; + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_READDATA_NONEMPTY; + + if (HAL_UARTEx_StopModeWakeUpSourceConfig(&uart->UartHandle, WakeUpSelection)!= HAL_OK) + { + return RT_ERROR; + } + HAL_UARTEx_EnableStopMode(&uart->UartHandle); + } + + return RT_EOK; } static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg) { - struct stm32_uart *uart; + struct stm32_uart *uart; - RT_ASSERT(serial != RT_NULL); - uart = (struct stm32_uart *)serial->parent.user_data; + RT_ASSERT(serial != RT_NULL); + uart = (struct stm32_uart *)serial->parent.user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - NVIC_DisableIRQ(uart->irq); - /* disable interrupt */ - __HAL_UART_DISABLE_IT(&uart->UartHandle, UART_IT_RXNE); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - NVIC_EnableIRQ(uart->irq); - /* enable interrupt */ - __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_RXNE); - break; - } + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + /* disable rx irq */ + NVIC_DisableIRQ(uart->irq); + /* disable interrupt */ + __HAL_UART_DISABLE_IT(&uart->UartHandle, UART_IT_RXNE); + break; + case RT_DEVICE_CTRL_SET_INT: + /* enable rx irq */ + NVIC_EnableIRQ(uart->irq); + /* enable interrupt */ + __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_RXNE); + break; + } - return RT_EOK; + return RT_EOK; } static int stm32_putc(struct rt_serial_device *serial, char c) @@ -213,7 +246,8 @@ static int stm32_getc(struct rt_serial_device *serial) * * @param serial serial device */ -static void uart_isr(struct rt_serial_device *serial) { +static void uart_isr(struct rt_serial_device *serial) +{ struct stm32_uart *uart = (struct stm32_uart *) serial->parent.user_data; RT_ASSERT(uart != RT_NULL); @@ -400,6 +434,38 @@ void HAL_UART_MspInit(UART_HandleTypeDef *huart) HAL_NVIC_EnableIRQ(USART5_IRQn); } #endif + +#if defined(RT_USING_LPUART1) + if (huart->Instance == LPUART1) + { + /*##-1- Enable peripherals and GPIO Clocks #################################*/ + /* Enable GPIO TX/RX clock */ + LPUART1_TX_GPIO_CLK_ENABLE(); + LPUART1_RX_GPIO_CLK_ENABLE(); + + /* Enable USARTx clock */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + + /*##-2- Configure peripheral GPIO ##########################################*/ + /* UART TX GPIO pin configuration */ + GPIO_InitStruct.Pin = LPUART1_TX_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; + GPIO_InitStruct.Alternate = LPUART1_TX_AF; + + HAL_GPIO_Init(LPUART1_TX_GPIO_PORT, &GPIO_InitStruct); + + /* UART RX GPIO pin configuration */ + GPIO_InitStruct.Pin = LPUART1_RX_PIN; + GPIO_InitStruct.Alternate = LPUART1_RX_AF; + + HAL_GPIO_Init(LPUART1_RX_GPIO_PORT, &GPIO_InitStruct); + + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 1); + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + } +#endif } /** @@ -496,6 +562,23 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) HAL_NVIC_DisableIRQ(USART5_IRQn); } #endif + +#if defined(RT_USING_LPUART1) + if (huart->Instance == LPUART1) + { + /*##-1- Reset peripherals ##################################################*/ + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + + /*##-2- Disable peripherals and GPIO Clocks #################################*/ + /* Configure UART Tx as alternate function */ + HAL_GPIO_DeInit(LPUART1_TX_GPIO_PORT, LPUART1_TX_PIN); + /* Configure UART Rx as alternate function */ + HAL_GPIO_DeInit(LPUART1_RX_GPIO_PORT, LPUART1_RX_PIN); + + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + } +#endif } @@ -608,7 +691,7 @@ void UART5_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - (&serial5); + uart_isr(&serial5); /* leave interrupt */ rt_interrupt_leave(); @@ -616,6 +699,28 @@ void UART5_IRQHandler(void) #endif /* RT_USING_UART5 */ +#if defined(RT_USING_LPUART1) +/* UART5 device driver structure */ +struct stm32_uart lpuart1 = +{ + {LPUART1}, + LPUART1_IRQn, +}; +struct rt_serial_device serial6; + +void LPUART1_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&serial6); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#endif /* RT_USING_LPUART1 */ + int stm32_hw_usart_init(void) { struct stm32_uart *uart; @@ -690,6 +795,23 @@ int stm32_hw_usart_init(void) RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart); #endif /* RT_USING_UART5 */ + +#ifdef RT_USING_LPUART1 + uart = &lpuart1; + uart->UartHandle.Instance = LPUART1; + + + serial6.ops = &stm32_uart_ops; + serial6.config = config; + + serial6.config.baud_rate = BAUD_RATE_4800; + + /* register UART5 device */ + rt_hw_serial_register(&serial6, + "lpuart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); +#endif /* RT_USING_LPUART1 */ return 0; } INIT_BOARD_EXPORT(stm32_hw_usart_init); diff --git a/bsp/stm32l476-nucleo/project.uvprojx b/bsp/stm32l476-nucleo/project.uvprojx index b275bb1a28..b99771dc40 100644 --- a/bsp/stm32l476-nucleo/project.uvprojx +++ b/bsp/stm32l476-nucleo/project.uvprojx @@ -1,42 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread_stm32l4xx 0x4 ARM-ADS - 5060422::V5.06 update 4 (build 422)::ARMCC + 5060528::V5.06 update 5 (build 528)::ARMCC + 0 STM32L476RGTx STMicroelectronics - Keil.STM32L4xx_DFP.1.4.0 + Keil.STM32L4xx_DFP.2.0.0 http://www.keil.com/pack IRAM(0x20000000,0x00018000) IRAM2(0x10000000,0x00008000) IROM(0x08000000,0x00100000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32L476RGTx$Flash\STM32L4xx_1024.FLM)) 0 $$Device:STM32L476RGTx$Device\Include\stm32l4xx.h - - - - - - - - - + + + + + + + + + $$Device:STM32L476RGTx$SVD\STM32L4x6.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -100,8 +104,8 @@ 0 0 3 - - + + 1 @@ -134,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M4" - + 0 0 0 @@ -303,7 +307,7 @@ 0x8000 - + 1 @@ -329,9 +333,9 @@ 0 0 - - USE_HAL_DRIVER, STM32L476xx, USE_STM32L4XX_NUCLEO, STM32F429xx - + + STM32L4x6, USE_HAL_DRIVER, STM32L476xx, USE_STM32L4XX_NUCLEO + applications;.;drivers;Libraries\STM32L4xx_HAL_Driver\Inc;Libraries\CMSIS\Device\ST\STM32L4xx\Include;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m4;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh @@ -347,10 +351,10 @@ 0 0 - - - - + + + + @@ -362,13 +366,13 @@ 0 0x08000000 0x20000000 - - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -381,13 +385,16 @@ 1 applications\application.c - - startup.c 1 applications\startup.c + + userled.c + 1 + applications\userled.c + @@ -398,13 +405,21 @@ 1 drivers\board.c - - usart.c 1 drivers\usart.c + + drv_led.c + 1 + drivers\drv_led.c + + + gpio.c + 1 + drivers\gpio.c + @@ -415,610 +430,436 @@ 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal.c - - stm32l4xx_hal_adc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc.c - - stm32l4xx_hal_adc_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_adc_ex.c - - stm32l4xx_hal_can.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_can.c - - stm32l4xx_hal_comp.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_comp.c - - stm32l4xx_hal_cortex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cortex.c - - stm32l4xx_hal_crc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc.c - - stm32l4xx_hal_crc_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_crc_ex.c - - stm32l4xx_hal_cryp.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp.c - - stm32l4xx_hal_cryp_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_cryp_ex.c - - stm32l4xx_hal_dac.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac.c - - stm32l4xx_hal_dac_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dac_ex.c - - stm32l4xx_hal_dcmi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dcmi.c - - stm32l4xx_hal_dfsdm.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dfsdm.c - - stm32l4xx_hal_dma.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma.c - - stm32l4xx_hal_dma2d.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_dma2d.c - - stm32l4xx_hal_firewall.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_firewall.c - - stm32l4xx_hal_flash.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash.c - - stm32l4xx_hal_flash_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ex.c - - stm32l4xx_hal_flash_ramfunc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_flash_ramfunc.c - - stm32l4xx_hal_gpio.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_gpio.c - - stm32l4xx_hal_hash.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash.c - - stm32l4xx_hal_hash_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hash_ex.c - - stm32l4xx_hal_hcd.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_hcd.c - - stm32l4xx_hal_i2c.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c.c - - stm32l4xx_hal_i2c_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_i2c_ex.c - - stm32l4xx_hal_irda.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_irda.c - - stm32l4xx_hal_iwdg.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_iwdg.c - - stm32l4xx_hal_lcd.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lcd.c - - stm32l4xx_hal_lptim.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_lptim.c - - stm32l4xx_hal_msp_template.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_msp_template.c - - stm32l4xx_hal_nand.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nand.c - - stm32l4xx_hal_nor.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_nor.c - - stm32l4xx_hal_opamp.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp.c - - stm32l4xx_hal_opamp_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_opamp_ex.c - - stm32l4xx_hal_pcd.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd.c - - stm32l4xx_hal_pcd_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pcd_ex.c - - stm32l4xx_hal_pwr.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr.c - - stm32l4xx_hal_pwr_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_pwr_ex.c - - stm32l4xx_hal_qspi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_qspi.c - - stm32l4xx_hal_rcc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc.c - - stm32l4xx_hal_rcc_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rcc_ex.c - - stm32l4xx_hal_rng.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rng.c - - stm32l4xx_hal_rtc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc.c - - stm32l4xx_hal_rtc_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_rtc_ex.c - - stm32l4xx_hal_sai.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sai.c - - stm32l4xx_hal_sd.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sd.c - - stm32l4xx_hal_smartcard.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard.c - - stm32l4xx_hal_smartcard_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smartcard_ex.c - - stm32l4xx_hal_smbus.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_smbus.c - - stm32l4xx_hal_spi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi.c - - stm32l4xx_hal_spi_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_spi_ex.c - - stm32l4xx_hal_sram.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_sram.c - - stm32l4xx_hal_swpmi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_swpmi.c - - stm32l4xx_hal_tim.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim.c - - stm32l4xx_hal_tim_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tim_ex.c - - stm32l4xx_hal_tsc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_tsc.c - - stm32l4xx_hal_uart.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart.c - - stm32l4xx_hal_uart_ex.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_uart_ex.c - - stm32l4xx_hal_usart.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_usart.c - - stm32l4xx_hal_wwdg.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_hal_wwdg.c - - stm32l4xx_ll_adc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_adc.c - - stm32l4xx_ll_comp.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_comp.c - - stm32l4xx_ll_crc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crc.c - - stm32l4xx_ll_crs.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_crs.c - - stm32l4xx_ll_dac.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dac.c - - stm32l4xx_ll_dma.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma.c - - stm32l4xx_ll_dma2d.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_dma2d.c - - stm32l4xx_ll_exti.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_exti.c - - stm32l4xx_ll_fmc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_fmc.c - - stm32l4xx_ll_gpio.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_gpio.c - - stm32l4xx_ll_i2c.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_i2c.c - - stm32l4xx_ll_lptim.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lptim.c - - stm32l4xx_ll_lpuart.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_lpuart.c - - stm32l4xx_ll_opamp.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_opamp.c - - stm32l4xx_ll_pwr.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_pwr.c - - stm32l4xx_ll_rcc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rcc.c - - stm32l4xx_ll_rng.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rng.c - - stm32l4xx_ll_rtc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_rtc.c - - stm32l4xx_ll_sdmmc.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_sdmmc.c - - stm32l4xx_ll_spi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_spi.c - - stm32l4xx_ll_swpmi.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_swpmi.c - - stm32l4xx_ll_tim.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_tim.c - - stm32l4xx_ll_usart.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usart.c - - stm32l4xx_ll_usb.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_usb.c - - stm32l4xx_ll_utils.c 1 Libraries\STM32L4xx_HAL_Driver\Src\stm32l4xx_ll_utils.c - - system_stm32l4xx.c 1 Libraries\CMSIS\Device\ST\STM32L4xx\Source\Templates\system_stm32l4xx.c - - startup_stm32l476xx.s 2 @@ -1034,92 +875,66 @@ 1 ..\..\src\clock.c - - components.c 1 ..\..\src\components.c - - device.c 1 ..\..\src\device.c - - idle.c 1 ..\..\src\idle.c - - ipc.c 1 ..\..\src\ipc.c - - irq.c 1 ..\..\src\irq.c - - kservice.c 1 ..\..\src\kservice.c - - mem.c 1 ..\..\src\mem.c - - mempool.c 1 ..\..\src\mempool.c - - object.c 1 ..\..\src\object.c - - scheduler.c 1 ..\..\src\scheduler.c - - signal.c 1 ..\..\src\signal.c - - thread.c 1 ..\..\src\thread.c - - timer.c 1 @@ -1135,29 +950,21 @@ 1 ..\..\libcpu\arm\cortex-m4\cpuport.c - - context_rvds.S 2 ..\..\libcpu\arm\cortex-m4\context_rvds.S - - backtrace.c 1 ..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\libcpu\arm\common\div0.c - - showmem.c 1 @@ -1173,50 +980,36 @@ 1 ..\..\components\drivers\misc\pin.c - - serial.c 1 ..\..\components\drivers\serial\serial.c - - completion.c 1 ..\..\components\drivers\src\completion.c - - dataqueue.c 1 ..\..\components\drivers\src\dataqueue.c - - pipe.c 1 ..\..\components\drivers\src\pipe.c - - ringbuffer.c 1 ..\..\components\drivers\src\ringbuffer.c - - waitqueue.c 1 ..\..\components\drivers\src\waitqueue.c - - workqueue.c 1 @@ -1232,85 +1025,76 @@ 1 ..\..\components\finsh\shell.c - - symbol.c 1 ..\..\components\finsh\symbol.c - - cmd.c 1 ..\..\components\finsh\cmd.c - - + + msh.c + 1 + ..\..\components\finsh\msh.c + + + msh_cmd.c + 1 + ..\..\components\finsh\msh_cmd.c + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + finsh_compiler.c 1 ..\..\components\finsh\finsh_compiler.c - - finsh_error.c 1 ..\..\components\finsh\finsh_error.c - - finsh_heap.c 1 ..\..\components\finsh\finsh_heap.c - - finsh_init.c 1 ..\..\components\finsh\finsh_init.c - - finsh_node.c 1 ..\..\components\finsh\finsh_node.c - - finsh_ops.c 1 ..\..\components\finsh\finsh_ops.c - - finsh_parser.c 1 ..\..\components\finsh\finsh_parser.c - - finsh_var.c 1 ..\..\components\finsh\finsh_var.c - - finsh_vm.c 1 ..\..\components\finsh\finsh_vm.c - - finsh_token.c 1 @@ -1318,19 +1102,24 @@ + + ::CMSIS + + - + - + - + - + + diff --git a/bsp/stm32l476-nucleo/rtconfig.h b/bsp/stm32l476-nucleo/rtconfig.h index 89428e1cf4..6feeae870b 100644 --- a/bsp/stm32l476-nucleo/rtconfig.h +++ b/bsp/stm32l476-nucleo/rtconfig.h @@ -1,161 +1,162 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +/* RT-Thread Kernel */ -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +/* RT_THREAD_PRIORITY_8 is not set */ +#define RT_THREAD_PRIORITY_32 +/* RT_THREAD_PRIORITY_256 is not set */ +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_DEBUG #define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ +#define RT_DEBUG_INIT 0 +#define RT_DEBUG_THREAD 0 #define RT_USING_HOOK +#define IDLE_THREAD_STACK_SIZE 256 +/* RT_USING_TIMER_SOFT is not set */ -#define IDLE_THREAD_STACK_SIZE 1024 +/* Inter-Thread communication */ -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX - -/* Using Event */ #define RT_USING_EVENT - -/* Using MailBox */ #define RT_USING_MAILBOX - -/* Using Message Queue */ #define RT_USING_MESSAGEQUEUE +/* RT_USING_SIGNALS is not set */ + +/* Memory Management */ -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ #define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ +/* RT_USING_MEMHEAP is not set */ +/* RT_USING_NOHEAP is not set */ +#define RT_USING_SMALL_MEM +/* RT_USING_SLAB is not set */ #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM +/* Kernel Device Object */ -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE -#define RT_USING_DEVICE_IPC -/* Using serial framework */ -#define RT_USING_SERIAL - -#define RT_USING_UART1 -#define RT_USING_UART2 -#define RT_USING_UART3 - -/* Using GPIO pin framework */ -#define RT_USING_PIN - -/* Using Hardware Timer framework */ -//#define RT_USING_HWTIMER - -/* SECTION: Console options */ +/* RT_USING_INTERRUPT_INFO is not set */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +/* RT_USING_MODULE is not set */ -/* SECTION: finsh, a C-Express shell */ -#define RT_USING_FINSH -/* Using symbol table */ -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION +/* RT-Thread Components */ #define RT_USING_COMPONENTS_INIT +/* RT_USING_USER_MAIN is not set */ -/* SECTION: device filesystem */ -/* Using Device file system */ -/* #define RT_USING_DFS */ -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +/* C++ features */ -/* Using ELM FATFS */ -//#define RT_USING_DFS_ELMFAT -#define RT_DFS_ELM_WORD_ACCESS -/* Reentrancy (thread safe) of the FatFs module. */ -#define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +/* RT_USING_CPLUSPLUS is not set */ -/* Using ROM file system */ -// #define RT_USING_DFS_ROMFS +/* Command shell */ -/* SECTION: lwip, a lighwight TCP/IP protocol stack */ -/* #define RT_USING_LWIP */ -/* Enable ICMP protocol*/ -#define RT_LWIP_ICMP -/* Enable UDP protocol*/ -#define RT_LWIP_UDP -/* Enable TCP protocol*/ -#define RT_LWIP_TCP -/* Enable DNS */ -#define RT_LWIP_DNS +#define RT_USING_FINSH +#define FINSH_USING_HISTORY +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +/* FINSH_USING_AUTH is not set */ +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +/* FINSH_USING_MSH_ONLY is not set */ -/* the number of simulatenously active TCP connections*/ -#define RT_LWIP_TCP_PCB_NUM 5 +/* Device virtual file system */ -/* ip address of target*/ -#define RT_LWIP_IPADDR0 192 -#define RT_LWIP_IPADDR1 168 -#define RT_LWIP_IPADDR2 1 -#define RT_LWIP_IPADDR3 201 +/* RT_USING_DFS is not set */ -/* gateway address of target*/ -#define RT_LWIP_GWADDR0 192 -#define RT_LWIP_GWADDR1 168 -#define RT_LWIP_GWADDR2 1 -#define RT_LWIP_GWADDR3 1 +/* Device Drivers */ -/* mask address of target*/ -#define RT_LWIP_MSKADDR0 255 -#define RT_LWIP_MSKADDR1 255 -#define RT_LWIP_MSKADDR2 255 -#define RT_LWIP_MSKADDR3 0 +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +/* RT_USING_CAN is not set */ +/* RT_USING_HWTIMER is not set */ +/* RT_USING_I2C is not set */ +#define RT_USING_PIN +/* RT_USING_MTD_NOR is not set */ +/* RT_USING_MTD_NAND is not set */ +/* RT_USING_RTC is not set */ +/* RT_USING_SDIO is not set */ +/* RT_USING_SPI is not set */ +/* RT_USING_WDT is not set */ +/* RT_USING_USB_HOST is not set */ +/* RT_USING_USB_DEVICE is not set */ -/* tcp thread options */ -#define RT_LWIP_TCPTHREAD_PRIORITY 12 -#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4 -#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +/* POSIX layer and C standard library */ -/* ethernet if thread options */ -#define RT_LWIP_ETHTHREAD_PRIORITY 15 -#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4 -#define RT_LWIP_ETHTHREAD_STACKSIZE 512 +/* RT_USING_LIBC is not set */ +/* RT_USING_PTHREADS is not set */ -/* TCP sender buffer space */ -#define RT_LWIP_TCP_SND_BUF 8192 -/* TCP receive window. */ -#define RT_LWIP_TCP_WND 8192 +/* Network stack */ + +/* light weight TCP/IP stack */ + +/* RT_USING_LWIP is not set */ + +/* Modbus master and slave stack */ + +/* RT_USING_MODBUS is not set */ + +/* RT-Thread UI Engine */ + +/* RT_USING_GUIENGINE is not set */ + +/* VBUS(Virtual Software BUS) */ + +/* RT_USING_VBUS is not set */ + +/* RT-Thread online packages */ + +/* system packages */ + +/* PKG_USING_PARTITION is not set */ +/* PKG_USING_SQLITE is not set */ + +/* IoT - internet of things */ + +/* PKG_USING_PAHOMQTT is not set */ +/* PKG_USING_WEBCLIENT is not set */ +/* PKG_USING_MONGOOSE is not set */ +/* PKG_USING_WEBTERMINAL is not set */ +/* PKG_USING_CJSON is not set */ +/* PKG_USING_EZXML is not set */ + +/* Marvell WiFi */ + +/* PKG_USING_MARVELLWIFI is not set */ + +/* security packages */ + +/* PKG_USING_MBEDTLS is not set */ + +/* language packages */ + +/* PKG_USING_JERRYSCRIPT is not set */ + +/* multimedia packages */ + +/* PKG_USING_FASTLZ is not set */ + +/* tools packages */ + +/* PKG_USING_CMBACKTRACE is not set */ +/* PKG_USING_EASYLOGGER is not set */ +/* PKG_USING_SYSTEMVIEW is not set */ + +/* miscellaneous packages */ + +/* PKG_USING_HELLO is not set */ +#define RT_USING_UART2 -/* RT_GDB_STUB */ -//#define RT_USING_GDB #endif diff --git a/bsp/stm32l476-nucleo/rtconfig.py b/bsp/stm32l476-nucleo/rtconfig.py index 50b58434d9..3b863008b2 100644 --- a/bsp/stm32l476-nucleo/rtconfig.py +++ b/bsp/stm32l476-nucleo/rtconfig.py @@ -28,7 +28,7 @@ if os.getenv('RTT_EXEC_PATH'): EXEC_PATH = os.getenv('RTT_EXEC_PATH') BUILD = 'debug' -STM32_TYPE = 'STM32F429xx' +STM32_TYPE = 'STM32L4x6' if PLATFORM == 'gcc': # toolchains