- SPI is now supported on ls2k1000 platform.
- Multi-Port & Adjustable Buadrate of UART controller feature added.
This commit is contained in:
0xcccccccccccc
parent
11132bcb64
commit
0fc2b13b45
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@ -90,7 +90,7 @@ void rt_hw_board_init(void)
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/* init hardware UART device */
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rt_hw_uart_init();
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/* set console device */
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rt_console_set_device("uart");
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rt_console_set_device("uart0");
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#endif
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#ifdef RT_USING_HEAP
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@ -0,0 +1,269 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <rtthread.h>
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#include <drivers/spi.h>
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#include "drv_spi.h"
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#ifdef RT_USING_SPI
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static void spi_init(uint8_t spre_spr,uint8_t copl,uint8_t cpha)
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{
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//rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha);
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int d;
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SET_SPI(SPSR, 0xc0|(spre_spr&0b00000011));
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SET_SPI(PARAM, 0x40);
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SET_SPI(PARAM2,0x01);
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SET_SPI(SPER, (spre_spr&0b00001100)>>2);
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SET_SPI(SPCR, 0x50|copl<<3|cpha<<2);
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SET_SPI(SOFTCS,0xff);
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}
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static void spi_set_csn(uint8_t val) //old method
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{
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SET_SPI(SOFTCS,val);
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}
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// #define RT_USING_SPI_GPIOCS
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#ifdef RT_USING_SPI_GPIOCS
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#include <drivers/pin.h>
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#endif
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static void spi_set_cs(unsigned char cs, int new_status)
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{
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if(cs<4){
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unsigned char val = 0;
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val = GET_SPI(SOFTCS);
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val |= 0x01 << cs ; // csen=1
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if (new_status) // cs = 1
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{
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val |= (0x10 << cs); // csn=1
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}
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else // cs = 0
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{
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val &= ~(0x10 << cs); // csn=0
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}
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SET_SPI(SOFTCS,val);
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return ;
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}
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#ifdef RT_USING_SPI_GPIOCS
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else{
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//rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n ");
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//rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status);
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rt_pin_mode(cs,PIN_MODE_OUTPUT);
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rt_pin_write(cs,new_status);
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}
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#endif
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}
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static uint8_t spi_write_for_response(uint8_t data)
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{
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uint8_t val;
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SET_SPI(TXFIFO,data);
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while((GET_SPI(SPSR))&RFEMPTY);//wait for echo
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val = GET_SPI(RXFIFO);
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return val;
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}
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static int cmd_spi_init(int argc,char* argv[])
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{
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uint8_t spre_spr,cpol,cpha;
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switch (argc)
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{
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case 2:
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spre_spr=strtoul(argv[1], NULL, 0);
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spi_init(spre_spr,0,0);
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break;
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case 4:
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spre_spr=strtoul(argv[1], NULL, 0);
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cpol=strtoul(argv[2], NULL, 0);
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cpha=strtoul(argv[3], NULL, 0);
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spi_init(spre_spr,0,0);
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break;
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default:
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printf("\nusage : cmd_spi_init spre_spr <cpol> <cpha>\n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n");
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break;
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}
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}
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MSH_CMD_EXPORT(cmd_spi_init,cmd_spi_init);
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static int cmd_spi_set_csn(int argc,char* argv[])
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{
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uint8_t val,csn;
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switch (argc)
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{
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case 3:
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csn=strtoul(argv[1], NULL, 0);
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val=strtoul(argv[2], NULL, 0);
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spi_set_cs(csn,val);
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break;
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default:
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printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n");
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break;
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}
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}
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MSH_CMD_EXPORT(cmd_spi_set_csn,cmd_spi_set_csn);
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static int cmd_spi_write(int argc,char* argv[])
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{
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uint8_t data,resp;
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switch (argc)
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{
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case 2:
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data=strtoul(argv[1], NULL, 0);
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resp=spi_write_for_response(data);
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printf("resp:%2X\n",resp);
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break;
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default:
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printf("usage:cmd_spi_write data\n");
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break;
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}
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}
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MSH_CMD_EXPORT(cmd_spi_write,cmd_spi_write);
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static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
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static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message);
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const static unsigned char SPI_DIV_TABLE[]={0b0000,0b0001,0b0100,0b0010,0b0011,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011};
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// 2 4 8 16 32 64 128 256 512 1024 2048 4096
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static rt_err_t configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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unsigned char cpol = 0;
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unsigned char cpha = 0;
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RT_ASSERT(NULL != device);
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RT_ASSERT(NULL != configuration);
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// baudrate
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if (configuration->mode & RT_SPI_CPOL) // cpol
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{
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cpol = 1;
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}
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else
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{
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cpol = 0;
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}
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if (configuration->mode & RT_SPI_CPHA) // cpha
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{
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cpha = 1;
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}
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else
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{
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cpha = 0;
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}
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//rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha);
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float spi_max_speed=((float)APB_MAX_SPEED)/(8.0/(float)APB_FREQSCALE);
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//rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed);
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uint64_t div=(uint64_t)(spi_max_speed/(float)configuration->max_hz);
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//rt_kprintf("require speed: %ld\n",configuration->max_hz);
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int ctr=0;
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while(div!=1 && ctr<12){
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ctr++;
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div=div>>1;
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}
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//rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<<ctr)));
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spi_init(SPI_DIV_TABLE[ctr],cpol,cpha);
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return RT_EOK;
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}
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static rt_uint32_t xfer(struct rt_spi_device *device,
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struct rt_spi_message *message)
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{
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//rt_kprintf("xfer:\n");
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unsigned char cs = 0;
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rt_uint32_t size = 0;
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const rt_uint8_t *send_ptr = NULL;
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rt_uint8_t *recv_ptr = NULL;
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rt_uint8_t data = 0;
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RT_ASSERT(NULL != device);
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RT_ASSERT(NULL != message);
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cs =(unsigned char )(device->parent.user_data);
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size = message->length;
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//rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs);
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// take cs
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if (message->cs_take)
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{
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spi_set_cs(cs, 0);
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}
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// send data
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send_ptr = message->send_buf;
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recv_ptr = message->recv_buf;
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while (size--)
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{
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data = 0xFF;
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if (NULL != send_ptr)
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{
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data = *send_ptr++;
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}
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if (NULL != recv_ptr)
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{
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*recv_ptr++ = spi_write_for_response(data);
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}
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else
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{
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spi_write_for_response(data);
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}
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}
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// release cs
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if (message->cs_release)
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{
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spi_set_cs(cs, 1);
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}
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return message->length;
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}
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static struct rt_spi_ops loongson_spi_ops =
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{
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.configure = configure,
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.xfer = xfer
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};
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static struct rt_spi_bus loongson_spi;
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static int loongson_spi_init()
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{
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//rt_kprintf("spi_init\n");
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return rt_spi_bus_register(&loongson_spi,"spi",&loongson_spi_ops);
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}
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INIT_BOARD_EXPORT(loongson_spi_init);
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#endif
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@ -0,0 +1,43 @@
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#ifndef DRV_SPI_H
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#define DRV_SPI_H
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#include <rtthread.h>
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#include <rthw.h>
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#define RFEMPTY 1
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#define KSEG1_STORE8(addr,val) *(volatile char *)(0xffffffffa0000000 | addr) = val
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#define KSEG1_LOAD8(addr) *(volatile char *)(0xffffffffa0000000 | addr)
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#define APB_MAX_SPEED 125000000U
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#define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1)
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#define SPI_BASE 0x1fff0220
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#define PMON_ADDR 0xa1000000
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#define FLASH_ADDR 0x000000
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#define SPCR 0x0
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#define SPSR 0x1
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#define FIFO 0x2
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#define TXFIFO 0x2
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#define RXFIFO 0x2
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#define SPER 0x3
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#define PARAM 0x4
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#define SOFTCS 0x5
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#define PARAM2 0x6
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#define SET_SPI(addr,val) KSEG1_STORE8(SPI_BASE+addr,val)
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#define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr)
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//void spi_init(uint8_t ,uint8_t,uint8_t);
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//void spi_set_csn(uint8_t);
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//uint8_t spi_write_for_response(uint8_t);
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#endif
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@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2020-04-05 bigmagic Initial version
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* 2020-10-28 ma Buadrate & Multi-Port support
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*/
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/**
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@ -21,22 +22,51 @@
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#define TRUE 1
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#define FALSE 0
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const struct serial_configure config_uart0 = {
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BAUD_RATE_115200, /* 921600 bits/s */
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DATA_BITS_8, /* 8 databits */
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STOP_BITS_1, /* 1 stopbit */
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PARITY_NONE, /* No parity */
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BIT_ORDER_LSB, /* LSB first sent */
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NRZ_NORMAL, /* Normal mode */
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RT_SERIAL_RB_BUFSZ, /* Buffer size */
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0
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};
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struct rt_uart_ls2k
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{
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void *base;
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rt_uint32_t IRQ;
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};
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static rt_err_t ls2k_uart_set_buad(struct rt_serial_device *serial,struct serial_configure *cfg)
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{
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struct rt_uart_ls2k *uart_dev = RT_NULL;
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rt_err_t ret=RT_EOK;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
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uint64_t brtc = (125000000U) / (16*(cfg->baud_rate));
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UART_LCR(uart_dev->base)=0x80; // Activate buadcfg
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UART_LSB(uart_dev->base)= brtc & 0xff;
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UART_MSB(uart_dev->base)= brtc >> 8;
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if(((((short)UART_MSB(uart_dev->base))<<8) | UART_LSB(uart_dev->base)) != brtc) ret=RT_ERROR;
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UART_LCR(uart_dev->base)= CFCR_8BITS;// Back to normal
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UART_MCR(uart_dev->base)= MCR_IENABLE/* | MCR_DTR | MCR_RTS*/;
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UART_IER(uart_dev->base) = 0;
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}
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static rt_err_t ls2k_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct rt_uart_ls2k *uart_dev = RT_NULL;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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ls2k_uart_set_buad(serial,cfg);
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uart_dev = (struct rt_uart_ls2k *)serial->parent.user_data;
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HWREG8(0xffffffffbfe10428)=0x1f;// Enable Multi-Port Support, by default it's 0x11 ,which means UART0 & UART4 Controller is in single port mode.
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UART_IER(uart_dev->base) = 0; /* clear interrupt */
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UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
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/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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@ -154,25 +184,47 @@ struct rt_uart_ls2k uart_dev0 =
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(void *)UARTx_BASE(0),
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LS2K_UART_0_1_2_3_IRQ,
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};
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struct rt_serial_device serial;
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struct rt_uart_ls2k uart_dev4 =
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{
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(void *)UARTx_BASE(4),
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LS2K_UART_4_5_6_7_IRQ ,
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};
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struct rt_serial_device serial,serial4;
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void rt_hw_uart_init(void)
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{
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struct rt_uart_ls2k *uart;
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//UART0_1_ENABLE=0xff;
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struct rt_uart_ls2k *uart,*uart4;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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uart = &uart_dev0;
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uart4=&uart_dev4;
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serial.ops = &ls2k_uart_ops;
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serial.config = config;
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serial.config = config_uart0;
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rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
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serial4.ops= &ls2k_uart_ops;
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serial4.config=config;
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rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART0");
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rt_hw_interrupt_install(uart4->IRQ, uart_irq_handler, &serial4, "UART4");
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/* register UART device */
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rt_hw_serial_register(&serial,
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"uart",
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"uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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uart);
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rt_hw_serial_register(&serial4,
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"uart4",
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RT_DEVICE_FLAG_RDWR| RT_DEVICE_FLAG_INT_RX,
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&uart_dev4);
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}
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/*@}*/
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