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AT32UC3A: Implement initial BSP support for SimpleMachines' Mizar32-B (#8186)

This commit is contained in:
Raman 2023-11-16 11:34:21 +05:30 committed by GitHub
parent 4ac9754f5b
commit 0e82e13cc3
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GPG Key ID: 4AEE18F83AFDEB23
84 changed files with 9219 additions and 4101 deletions
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1016
bsp/avr32/at32uc3a0256/.config Normal file
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136
bsp/avr32/at32uc3a0256/Kconfig Normal file
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
menu "Hardware Drivers Config"
config SOC_AVR32
bool
default y
choice
prompt "Select BSP board"
default BSP_BOARD_MIZAR32B
config BSP_BOARD_MIZAR32B
bool "Mizar32-B"
endchoice
menu "On-chip Peripheral Drivers"
config BSP_USING_PIN
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
select RT_USING_SERIAL
default y
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default n
if BSP_USING_UART0
choice
prompt "uart0 tx pin number (GP)"
depends on BSP_USING_UART0
default BSP_UART0_TX_PIN_43
config BSP_UART0_TX_PIN_19
bool "19"
config BSP_UART0_TX_PIN_43
bool "43"
endchoice
config BSP_UART0_TX_PIN
int
default 19 if BSP_UART0_TX_PIN_19
default 43 if BSP_UART0_TX_PIN_43
config BSP_UART0_TX_PIN_FUNCTION
int
default 0 if BSP_UART0_TX_PIN_19
default 2 if BSP_UART0_TX_PIN_43
choice
prompt "uart0 rx pin number (GP)"
depends on BSP_USING_UART0
default BSP_UART0_RX_PIN_42
config BSP_UART0_RX_PIN_18
bool "18"
config BSP_UART0_RX_PIN_42
bool "42"
endchoice
config BSP_UART0_RX_PIN
int
default 18 if BSP_UART0_RX_PIN_18
default 42 if BSP_UART0_RX_PIN_42
config BSP_UART0_RX_PIN_FUNCTION
int
default 0 if BSP_UART0_RX_PIN_18
default 2 if BSP_UART0_RX_PIN_42
endif
config BSP_USING_UART1
bool "Enable UART1"
default y
if BSP_USING_UART1
choice
prompt "uart1 tx pin number (GP)"
depends on BSP_USING_UART1
default BSP_UART1_TX_PIN_6
config BSP_UART1_TX_PIN_6
bool "6"
config BSP_UART1_TX_PIN_95
bool "95"
endchoice
config BSP_UART1_TX_PIN
int
default 6 if BSP_UART1_TX_PIN_6
default 95 if BSP_UART1_TX_PIN_95
config BSP_UART1_TX_PIN_FUNCTION
int
default 0 if BSP_UART1_TX_PIN_6
default 1 if BSP_UART1_TX_PIN_95
choice
prompt "uart1 rx pin number (GP)"
depends on BSP_USING_UART1
default BSP_UART1_RX_PIN_5
config BSP_UART1_RX_PIN_5
bool "5"
config BSP_UART1_RX_PIN_96
bool "96"
endchoice
config BSP_UART1_RX_PIN
int
default 5 if BSP_UART1_RX_PIN_5
default 96 if BSP_UART1_RX_PIN_96
config BSP_UART1_RX_PIN_FUNCTION
int
default 0 if BSP_UART1_RX_PIN_5
default 1 if BSP_UART1_RX_PIN_96
endif
endif
endmenu
endmenu

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bsp/avr32/at32uc3a0256/README.md Normal file
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# SimpleMachines' Mizar32 Development Board
## Introduction
The Mizar32 is a 32-bit computer based on the AVR32 processor. It is
clocked at 66MHz and has 32MB of main memory. It supports mass storage
on SD card, a USB connector, an on-board LED, two buttons, a JTAG port
and six bus connectors.
![board-snap](figures/board-snap.png)
The bus connectors let you add other stackable hardware modules such
as serial ports, ethernet, a 16x2 character LCD display and a
VGA/keyboard/mouse/audio board based on the 8-core Parallax Propeller
processor.
The Mizar32 is designed by SimpleMachines, Italy.
This board support package aims at adding RT-Thread support for the
following Mizar32 development boards.
| Model | Flash | SRAM | SDRAM |
| --------- | ----- | ---- | ---- |
| Mizar32-A | 512KB | 64KB | 32MB |
| Mizar32-B | 256KB | 64KB | 32MB |
| Mizar32-C | 128KB | 64KB | 32MB |
## Specification
- Main processor: AVR32 UC3A0 @ 66 MHz
- Internal fast SRAM: 32KB or 64KB with single-cycle access time
- On-board SDRAM: 32MB with 2-cycle access time
- Internal Flash memory: 128/256/512KB with single-cycle access time
- External Flash memory: up to 4GB on micro SD card.
- Internal operating Voltage: 3.3V with 5V input tolerant I/O
- Digital I/O Pins: 66
- Timer/Counter: 3 channel, 16-bit.
- Analog-to-Digital input pins: 8 with 10-bit resolution measuring 0-3.3v at up to 384,000 samples per second
- Stereo audio bitstream Digital-to-Analog Converter with 16 bit resolution at up to 48kHz
- Pulse Width Modulation channels (PWM): 7
- Universal Sync/Async RX/TX (USART): 2
- Serial Periperal Interface (SPI): 2
- Two-Wire Interface (TWI): 1, I2C-compatible at up to 400kbit/s
- Universal Serial Bus (USB): 1 OTG host with dedicated cable.
- Debug Port: JTAG connector
- Ethernet MAC 10/100: 1 (requires add-on hardware module)
- Oscillators: 2 (12MHz and 32768Hz)
- Buttons: Reset button, user button
- LEDs: Power LED, User LED
- Power supply: 5V USB or 7.5V-35V DC, 80mA (base board) to 222mA (with all add-on modules)
- Dimensions: 96,5mm x 63,5mm
- Weight: 42.5 grams
- Temperature range: -45 to +85°C
## Embedded Hardware Interfaces
- MicroSD
- USB
- JTAG
- Add-on bus connectors 1-6 interfaces on the Add-on Bus
- 12 General Purpose I/O pins
- 2 UARTs: one basic, one with modem control signals
- 2 SPI
- I2C interface with 2-way splitter
- 8 ADC inputs
- 3 high-resolution timers
- Ethernet
## Optional Stacked Modules
![Ethernet and Real Time Clock](figures/Mizar32_Ethernet_RTC_Module.jpg)
![16x2 I2C LCD Module](figures/Mizar32_I2C_LCD_Module.jpg)
![RS-232/RS-485 Module](figures/Mizar32_RS_232_485_Module.jpg)
![VGA Output, PS/2 Input, Audio Output](figures/Mizar32_VGA_Propeller_Module.jpg)
![PHT Prototype Board](figures/Mizar32_Protoboard_PHT.jpg)
![SMD Prototype Board](figures/Mizar32_Protoboard_SMD.jpg)
This README is essentially a work-in-progress. I will try to further
and documentation as and when I further the device driver base for the
Mizar32 target.
If you feel like reaching out to me for questions pertaining to the
target development board, you can write to me: ramangopalan AT gmail
dot com.
## Supported compiler
This BSP is built with the AVR32 GCC that comes with the Microchip
Studio. I am using the Microchip Studio version 7.0.2594. Make sure
that avr32-gcc.exe is visible on your command line. Add the binary
directory to you PATH.
![env-windows-avr32-gcc](figures/env-windows-avr32-gcc.png)
I use Git Bash (Windows) for compiling the RT-Thread system. Once you
set your path correctly, invoke Git Bash to query avr32-gcc.exe's
version. The output should look similar to this:
```bash
$ avr32-gcc.exe --version
avr32-gcc.exe (AVR_32_bit_GNU_Toolchain_3.4.2_435) 4.4.7
Copyright (C) 2010 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
```
If you see this, you're all set to compile RT-Thread for Mizar32.
## Program firmware
### Step 1: download the RT-Thread codebase and navigate to bsp/avr32uc3a0.
```bash
$ cd bsp/avr32uc3a0/
```
### Step 2: build
```bash
scons -c
scons
```
### Step 3: flash
If everything went well, scons should have generated an elf file:
rtthread-uc3a0256.elf. Let us program the file. The program 'atprogram'
comes with Microchip Studio. I didn't have to do much here. Just make sure
`atprogram.exe' is in your PATH.
```bash
atprogram -t atmelice -i jtag -d at32uc3a0256 program -f rtthread-uc3a0256.elf
```
Note that you should already see the on-board LED (PB29) blink if your
programming was successful. I use the Atmel ICE programmer. To access
msh with the default menuconfig's configuration, you'll need the VGA
shield. Connect the target board to a 12 VDC wall adapter. Also
connect the shield to a VGA monitor and a PS/2 keyboard.
## Running Result
The output information on serial port for `ps' the command should look like this:
```bash
0x000003c0 tidle0 31 ready 0x00000054 0x00000100 67% 0x00000009 OK
0x00001650 tshell 20 running 0x000000b4 0x00001000 13% 0x0000000a OK
0x00001350 led1 5 suspend 0x0000007c 0x00000400 12% 0x00000005 EINTRPT
```
Here is a picture of the RT-Thread session on the VGA monitor:
![RT-Thread VGA Session on Mizar32](figures/mizar32-vga-out.jpg)
## Peripheral Support
| Drive | Support | Remark |
| ----- | ------- | ------- |
| UART | Support | UART0/1 |
| GPIO | Support | - |
| I2C | - | - |
| RTC | - | - |
| SPI | - | - |
| TIMER | - | - |
| WDT | - | - |

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bsp/avr32/at32uc3a0256/SConscript Normal file
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import rtconfig
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
src = File(src_bsp)
CPPPATH = [RTT_ROOT + '/bsp/avr32']
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

7
bsp/avr32uc3b0/SConstruct → bsp/avr32/at32uc3a0256/SConstruct
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@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
@ -27,7 +27,10 @@ Export('rtconfig')
objs = PrepareBuilding(env, RTT_ROOT)
# AVR32 software framework building script
objs = objs + SConscript(RTT_ROOT + '/bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/SConscript', variant_dir='bsp/SOFTWARE_FRAMEWORK', duplicate=0)
objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/software_framework/SConscript', variant_dir='build/software_framework', duplicate=0)
# Driver abstractions
objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/drivers/SConscript', variant_dir='build/drivers/', duplicate=0)
# make a building
DoBuilding(TARGET, objs)

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bsp/avr32/at32uc3a0256/application.c Normal file
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
* 2023-10-25 Raman Gopalan AT32UC3A: Access GPIO using RT's pin abstractions
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "compiler.h"
#include "gpio.h"
/* Mizar32's built-in LED */
#define USER_LED_1 AVR32_PIN_PB29
char thread_led1_stack[1024];
struct rt_thread thread_led1;
static void rt_thread_entry_led1(void* parameter)
{
rt_pin_mode(USER_LED_1, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(USER_LED_1, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */
rt_pin_write(USER_LED_1, 0);
rt_thread_delay(RT_TICK_PER_SECOND / 2);
}
}
int rt_application_init()
{
/* create led1 thread */
rt_thread_init(&thread_led1,
"led1",
rt_thread_entry_led1,
RT_NULL,
&thread_led1_stack[0],
sizeof(thread_led1_stack), 5, 5);
rt_thread_startup(&thread_led1);
return 0;
}

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bsp/avr32/at32uc3a0256/avr32elf_uc3a0256.lds Normal file
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/* Default linker script, for normal executables */
OUTPUT_FORMAT("elf32-avr32", "elf32-avr32",
"elf32-avr32")
OUTPUT_ARCH(avr32:uc)
ENTRY(_start)
SEARCH_DIR("/home/mingwbuild/mingwavr32/avr32/lib");
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
FLASH (rxai!w) : ORIGIN = 0x80002000, LENGTH = 256K
CPUSRAM (wxa!ri) : ORIGIN = 0x00000004, LENGTH = 0xFFFC
USERPAGE : ORIGIN = 0x80800000, LENGTH = 512
FACTORYPAGE : ORIGIN = 0x80800200, LENGTH = 512
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0x80000000); . = 0x80000000;
.interp : { *(.interp) } >FLASH AT>FLASH
.reset : { *(.reset) } >FLASH AT>FLASH
.hash : { *(.hash) } >FLASH AT>FLASH
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.dynstr : { *(.dynstr) } >FLASH AT>FLASH
.gnu.version : { *(.gnu.version) } >FLASH AT>FLASH
.gnu.version_d : { *(.gnu.version_d) } >FLASH AT>FLASH
.gnu.version_r : { *(.gnu.version_r) } >FLASH AT>FLASH
.rel.init : { *(.rel.init) } >FLASH AT>FLASH
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.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) } >FLASH AT>FLASH
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.rel.dtors : { *(.rel.dtors) } >FLASH AT>FLASH
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.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) } >FLASH AT>FLASH
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.rel.plt : { *(.rel.plt) } >FLASH AT>FLASH
.rela.plt : { *(.rela.plt) } >FLASH AT>FLASH
.init :
{
KEEP (*(.init))
} >FLASH AT>FLASH =0xd703d703
.plt : { *(.plt) } >FLASH AT>FLASH
.text :
{
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
} >FLASH AT>FLASH =0xd703d703
.fini :
{
KEEP (*(.fini))
} >FLASH AT>FLASH =0xd703d703
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >FLASH AT>FLASH
.rodata1 : { *(.rodata1) } >FLASH AT>FLASH
.eh_frame_hdr : { *(.eh_frame_hdr) } >FLASH AT>FLASH
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >FLASH AT>FLASH
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >FLASH AT>FLASH
.dalign : { . = ALIGN(8); PROVIDE(_data_lma = .); } >FLASH AT>FLASH
PROVIDE (_data = ORIGIN(CPUSRAM));
. = ORIGIN(CPUSRAM);
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >CPUSRAM AT>FLASH
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >CPUSRAM AT>FLASH
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >CPUSRAM AT>FLASH
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >CPUSRAM
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
PROVIDE (__preinit_array_start = ALIGN(32 / 8));
.preinit_array : { KEEP (*(.preinit_array)) } >CPUSRAM AT>FLASH
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { KEEP (*(.init_array)) } >CPUSRAM AT>FLASH
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { KEEP (*(.fini_array)) } >CPUSRAM AT>FLASH
PROVIDE (__fini_array_end = .);
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >CPUSRAM AT>FLASH
.dtors :
{
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >CPUSRAM AT>FLASH
.jcr : { KEEP (*(.jcr)) } >CPUSRAM AT>FLASH
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >CPUSRAM AT>FLASH
.dynamic : { *(.dynamic) } >CPUSRAM AT>FLASH
.got : { *(.got.plt) *(.got) } >CPUSRAM AT>FLASH
.data :
{
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
} >CPUSRAM AT>FLASH
.data1 : { *(.data1) } >CPUSRAM AT>FLASH
.balign : { . = ALIGN(8); _edata = .; } >CPUSRAM AT>FLASH
_edata = .;
PROVIDE (edata = .);
__bss_start = .;
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(8);
} >CPUSRAM
. = ALIGN(8);
_end = .;
PROVIDE (end = .);
__heap_start__ = ALIGN(8);
. = ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size;
__heap_end__ = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
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/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.stack ORIGIN(CPUSRAM) + LENGTH(CPUSRAM) - _stack_size :
{
_stack = .;
*(.stack)
. = _stack_size;
_estack = .;
} >CPUSRAM
.userpage : { *(.userpage .userpage.*) } >USERPAGE AT>USERPAGE
.factorypage : { *(.factorypage .factorypage.*) } >FACTORYPAGE AT>FACTORYPAGE
/DISCARD/ : { *(.note.GNU-stack) }
}

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248
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@ -0,0 +1,248 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_CPUS_NR 1
#define RT_ALIGN_SIZE 8
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 512
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* kservice optimization */
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_HEAP
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50100
#define RT_BACKTRACE_LEVEL_MAX_NR 32
/* RT-Thread Components */
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* C/C++ and POSIX layer */
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
/* POSIX (Portable Operating System Interface) layer */
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
/* Utilities */
/* Memory management */
/* Memory protection */
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Arduino libraries */
/* Projects and Demos */
/* Sensors */
/* Display */
/* Timing */
/* Data Processing */
/* Data Storage */
/* Communication */
/* Device Control */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Hardware Drivers Config */
#define SOC_AVR32
#define BSP_BOARD_MIZAR32B
/* On-chip Peripheral Drivers */
#define BSP_USING_PIN
#define BSP_USING_UART
#define BSP_USING_UART1
#define BSP_UART1_TX_PIN_6
#define BSP_UART1_TX_PIN 6
#define BSP_UART1_TX_PIN_FUNCTION 0
#define BSP_UART1_RX_PIN_5
#define BSP_UART1_RX_PIN 5
#define BSP_UART1_RX_PIN_FUNCTION 0
#endif

61
bsp/avr32/at32uc3a0256/rtconfig.py Normal file
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@ -0,0 +1,61 @@
import os
# toolchains options
ARCH = 'avr32'
CPU = 'uc3'
PART = 'uc3a0256'
BOARD = 'USERBOARD'
ATOMICS = ' -D__STDC_NO_ATOMICS__'
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = 'C:/Program Files (x86)/Atmel/AVR Tools/AVR Toolchain/bin'
elif CROSS_TOOL == 'keil':
print('================ERROR============================')
print('Not support keil yet!')
print('=================================================')
exit(0)
elif CROSS_TOOL == 'iar':
print('================ERROR============================')
print('Not support iar yet!')
print('=================================================')
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
#BUILD = 'debug'
BUILD = 'release'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'avr32-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mpart=' + PART
CFLAGS = DEVICE + ' -DBOARD=' + BOARD + ATOMICS + ' -fmessage-length=0 -ffunction-sections -masm-addr-pseudos'
AFLAGS = ' -c -x assembler-with-cpp' + DEVICE
LFLAGS = DEVICE + ' -Wl,--gc-sections --rodata-writable -Wl,--direct-data -Lsoftware_framework/utils/libs/newlib_addons -T avr32elf_uc3a0256.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -g3 -Wall'
AFLAGS += ' -g3'
else:
CFLAGS += ' -O2 -Wall'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

0
bsp/avr32uc3b0/startup.c → bsp/avr32/at32uc3a0256/startup.c
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16
bsp/avr32uc3b0/.config → bsp/avr32/at32uc3b0256/.config
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@ -22,7 +22,7 @@ CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_IDLE_THREAD_STACK_SIZE=512
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
@ -36,7 +36,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
CONFIG_RT_USING_DEBUG=y
CONFIG_RT_DEBUGING_COLOR=y
CONFIG_RT_DEBUGING_CONTEXT=y
# CONFIG_RT_DEBUGING_CONTEXT is not set
# CONFIG_RT_DEBUGING_INIT is not set
#
@ -223,6 +223,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
#
# CONFIG_RT_USING_MEMBLOCK is not set
#
# Memory protection
#
# CONFIG_RT_USING_MEM_PROTECTION is not set
# CONFIG_RT_USING_HW_STACK_GUARD is not set
#
# RT-Thread Utestcases
#
@ -987,6 +993,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
# Uncategorized
#
#
# Hardware Drivers Config
#
CONFIG_SOC_AVR32=y
CONFIG_BSP_BOARD_MCUZONE_AVR32DEV1=y
#
# On-chip Peripheral Drivers
#

17
bsp/avr32uc3b0/Kconfig → bsp/avr32/at32uc3b0256/Kconfig
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@ -8,7 +8,7 @@ config BSP_DIR
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
@ -26,6 +26,20 @@ config ENV_DIR
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
menu "Hardware Drivers Config"
config SOC_AVR32
bool
default y
choice
prompt "Select BSP board"
default BSP_BOARD_MCUZONE_AVR32DEV1
config BSP_BOARD_MCUZONE_AVR32DEV1
bool "MCUZone AVR32DEV1 Kit"
endchoice
menu "On-chip Peripheral Drivers"
config BSP_USING_PIN
@ -119,3 +133,4 @@ menu "On-chip Peripheral Drivers"
endif
endif
endmenu
endmenu

0
bsp/avr32uc3b0/README.md → bsp/avr32/at32uc3b0256/README.md
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11
bsp/avr32/at32uc3b0256/SConscript Normal file
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@ -0,0 +1,11 @@
import rtconfig
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
src = File(src_bsp)
CPPPATH = [RTT_ROOT + '/bsp/avr32']
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

36
bsp/avr32/at32uc3b0256/SConstruct Normal file
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@ -0,0 +1,36 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-' + rtconfig.PART + '.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# AVR32 software framework building script
objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/software_framework/SConscript', variant_dir='build/software_framework', duplicate=0)
# Driver abstractions
objs = objs + SConscript(RTT_ROOT + '/bsp/avr32/drivers/SConscript', variant_dir='build/drivers/', duplicate=0)
# make a building
DoBuilding(TARGET, objs)

0
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0
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84
bsp/avr32/at32uc3b0256/board.c Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
* 2023-10-13 Raman Gopalan Move UART specific code sections into the drv_uart files
* 2023-10-20 Raman Gopalan Initialize GPIO sub-system
*/
#include <rtthread.h>
#include "compiler.h"
#include "pm.h"
#include "gpio.h"
#include "usart.h"
#include "intc.h"
#include "drv_uart.h"
#include "drv_gpio.h"
/**
* System tick interrupt handler.
*/
static void rt_hw_timer_handler(void)
{
// Clears the interrupt request.
Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
rt_tick_increase();
}
/**
* Initialize system clock and all peripherals.
*/
static void peripherals_init(void)
{
/*
* PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
*/
pm_freq_param_t pm_freq_param =
{
.cpu_f = FCPU,
.pba_f = FPBA,
.osc0_f = FOSC0,
.osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
};
pm_configure_clocks(&pm_freq_param);
INTC_init_interrupts();
}
/**
* Initialize CPU cycle counter for system tick.
*/
static void cpu_counter_init(void)
{
INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
Set_system_register(AVR32_COUNT, 0);
}
void rt_hw_board_init(void)
{
Disable_global_interrupt();
peripherals_init();
cpu_counter_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_SERIAL
rt_hw_uart_init();
#endif
#ifdef RT_USING_PIN
rt_hw_gpio_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}

0
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11
bsp/avr32uc3b0/rtconfig.h → bsp/avr32/at32uc3b0256/rtconfig.h
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@ -17,7 +17,7 @@
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define IDLE_THREAD_STACK_SIZE 512
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
@ -26,7 +26,6 @@
#define RT_USING_DEBUG
#define RT_DEBUGING_COLOR
#define RT_DEBUGING_CONTEXT
/* Inter-Thread communication */
@ -110,6 +109,9 @@
/* Memory management */
/* Memory protection */
/* RT-Thread Utestcases */
@ -226,6 +228,11 @@
/* Uncategorized */
/* Hardware Drivers Config */
#define SOC_AVR32
#define BSP_BOARD_MCUZONE_AVR32DEV1
/* On-chip Peripheral Drivers */
#define BSP_USING_PIN

0
bsp/avr32uc3b0/rtconfig.py → bsp/avr32/at32uc3b0256/rtconfig.py
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50
bsp/avr32/at32uc3b0256/startup.c Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-30 Kyle First version
*/
#include <rtthread.h>
extern void rt_hw_board_init(void);
extern void rt_application_init(void);
#ifdef RT_USING_FINSH
extern int finsh_system_init(void);
extern void finsh_set_device(const char* device);
#endif
int main(void)
{
#ifdef RT_USING_HEAP
extern void __heap_start__;
extern void __heap_end__;
#endif
rt_hw_board_init();
rt_system_timer_init();
#ifdef RT_USING_HEAP
rt_system_heap_init(&__heap_start__, &__heap_end__);
#endif
rt_system_scheduler_init();
rt_application_init();
#ifdef RT_USING_FINSH
/* init finsh */
finsh_system_init();
#if !defined(RT_USING_POSIX_STDIO) && defined(RT_USING_DEVICE)
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#endif
rt_thread_idle_init();
rt_system_scheduler_start();
return 0;
}

23
bsp/avr32/drivers/SConscript Normal file
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@ -0,0 +1,23 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = []
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_uart_v2.c']
else:
src += ['drv_uart.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')

24
bsp/avr32uc3b0/drv_gpio.c → bsp/avr32/drivers/drv_gpio.c
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@ -5,19 +5,21 @@
*
* Change Logs:
* Date Author Notes
* 2023-10-18 Raman Gopalan Initial version
* 2023-10-25 Raman Gopalan Initial version
* 2023-11-06 Raman Gopalan Abstraction for GPIO driver boilerplate
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "gpio.h"
#include <rtdbg.h>
#include "drv_gpio.h"
#ifdef RT_USING_PIN
static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
static void at32uc3_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t mode)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
/* Pointer to the register set for this GPIO port */
volatile avr32_gpio_port_t *gpio_regs = &AVR32_GPIO.port[pin >> 5];
@ -36,7 +38,7 @@ static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t
gpio_regs->puers = 1 << (pin & 0x1F);
break;
case PIN_MODE_INPUT_PULLDOWN:
LOG_W("Pull-down enable register not defined for AT32UC3B.");
LOG_W("Pull-down enable register not defined for this SOC.");
break;
case PIN_MODE_OUTPUT_OD:
LOG_W("The open-drain mode is not synthesized on the current AVR32 products.");
@ -44,9 +46,9 @@ static void at32uc3b0_pin_mode(struct rt_device *dev, rt_base_t pin, rt_uint8_t
}
}
static void at32uc3b0_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
static void at32uc3_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t value)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
if (value == PIN_HIGH)
{
gpio_set_gpio_pin(pin);
@ -57,17 +59,17 @@ static void at32uc3b0_pin_write(struct rt_device *dev, rt_base_t pin, rt_uint8_t
}
}
static rt_int8_t at32uc3b0_pin_read(struct rt_device *device, rt_base_t pin)
static rt_int8_t at32uc3_pin_read(struct rt_device *device, rt_base_t pin)
{
RT_ASSERT((AVR32_PIN_PA03 <= pin) && (pin <= AVR32_PIN_PB11));
RT_ASSERT((AVR32_BSP_GPIO_PMIN <= pin) && (pin <= AVR32_BSP_GPIO_PMAX));
return (gpio_get_pin_value(pin) ? PIN_HIGH : PIN_LOW);
}
static const struct rt_pin_ops ops =
{
at32uc3b0_pin_mode,
at32uc3b0_pin_write,
at32uc3b0_pin_read,
at32uc3_pin_mode,
at32uc3_pin_write,
at32uc3_pin_read,
RT_NULL,
RT_NULL,
RT_NULL,

31
bsp/avr32/drivers/drv_gpio.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-25 Raman Gopalan Initial version
* 2023-11-06 Raman Gopalan Abstraction for GPIO driver boilerplate
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtconfig.h>
#ifdef RT_USING_PIN
#ifndef BSP_BOARD_MIZAR32B
#define AVR32_BSP_GPIO_PMIN AVR32_PIN_PA03
#define AVR32_BSP_GPIO_PMAX AVR32_PIN_PB11
#else
#define AVR32_BSP_GPIO_PMIN AVR32_PIN_PA00
#define AVR32_BSP_GPIO_PMAX AVR32_PIN_PX11
#endif
int rt_hw_gpio_init(void);
#endif /* #ifdef RT_USING_PIN */
#endif /* __DRV_GPIO_H__ */

59
bsp/avr32uc3b0/drv_uart.c → bsp/avr32/drivers/drv_uart.c
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@ -10,7 +10,8 @@
* in the buffer.
* 2010-03-29 Bernard cleanup code.
* 2010-03-30 Kyle Ported from STM32 to AVR32.
* 2023-10-13 Raman Gopalan UART driver for at32uc3b: Initial version
* 2023-10-25 Raman Gopalan UART driver for at32uc3a: Initial version
* 2023-11-06 Raman Gopalan Driver abstractions for uc3a and uc3b devices
*/
#include <rthw.h>
@ -31,19 +32,19 @@
#endif
#ifdef BSP_USING_UART0
void avr32uc3b_uart0_isr(void);
void avr32uc3_uart0_isr(void);
#endif
#ifdef BSP_USING_UART1
void avr32uc3b_uart1_isr(void);
void avr32uc3_uart1_isr(void);
#endif
#ifdef BSP_USING_UART2
void avr32uc3b_uart2_isr(void);
void avr32uc3_uart2_isr(void);
#endif
/* AVR32UC3B uart driver */
struct avr32uc3b_uart_dev
struct avr32uc3_uart_dev
{
rt_serial_t parent;
avr32_usart_t *instance;
@ -56,7 +57,7 @@ struct avr32uc3b_uart_dev
void (*uart_isr)(void);
};
static struct avr32uc3b_uart_dev uart_dev[] =
static struct avr32uc3_uart_dev uart_dev[] =
{
#ifdef BSP_USING_UART0
{
@ -67,7 +68,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
.tx_pin_function = BSP_UART0_TX_PIN_FUNCTION,
.rx_pin = BSP_UART0_RX_PIN,
.rx_pin_function = BSP_UART0_RX_PIN_FUNCTION,
.uart_isr = avr32uc3b_uart0_isr,
.uart_isr = avr32uc3_uart0_isr,
},
#endif
@ -80,7 +81,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
.tx_pin_function = BSP_UART1_TX_PIN_FUNCTION,
.rx_pin = BSP_UART1_RX_PIN,
.rx_pin_function = BSP_UART1_RX_PIN_FUNCTION,
.uart_isr = avr32uc3b_uart1_isr,
.uart_isr = avr32uc3_uart1_isr,
},
#endif
@ -93,7 +94,7 @@ static struct avr32uc3b_uart_dev uart_dev[] =
.tx_pin_function = BSP_UART2_TX_PIN_FUNCTION,
.rx_pin = BSP_UART2_RX_PIN,
.rx_pin_function = BSP_UART2_RX_PIN_FUNCTION,
.uart_isr = avr32uc3b_uart2_isr,
.uart_isr = avr32uc3_uart2_isr,
},
#endif
};
@ -114,7 +115,7 @@ enum
};
#ifdef BSP_USING_UART0
void avr32uc3b_uart0_isr(void)
void avr32uc3_uart0_isr(void)
{
rt_interrupt_enter();
/* read interrupt status and clear it */
@ -128,7 +129,7 @@ void avr32uc3b_uart0_isr(void)
#endif
#ifdef BSP_USING_UART1
void avr32uc3b_uart1_isr(void)
void avr32uc3_uart1_isr(void)
{
rt_interrupt_enter();
/* read interrupt status and clear it */
@ -142,7 +143,7 @@ void avr32uc3b_uart1_isr(void)
#endif
#ifdef BSP_USING_UART2
void avr32uc3b_uart2_isr(void)
void avr32uc3_uart2_isr(void)
{
rt_interrupt_enter();
/* read interrupt status and clear it */
@ -160,9 +161,9 @@ void avr32uc3b_uart2_isr(void)
*/
/*@{*/
static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
static rt_err_t avr32uc3_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct avr32uc3b_uart_dev *uart = RT_NULL;
struct avr32uc3_uart_dev *uart = RT_NULL;
unsigned char l_parity;
unsigned short l_stop;
unsigned long l_baud;
@ -171,7 +172,7 @@ static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
// Set the TX and RX pins by using the function select on the GPIO
// Set datasheet for more information on function select
gpio_enable_module_pin(uart->tx_pin, uart->tx_pin_function);
@ -203,16 +204,16 @@ static rt_err_t avr32uc3b_uart_configure(struct rt_serial_device *serial, struct
.channelmode = USART_NORMAL_CHMODE
};
usart_init_rs232(uart->instance, &usart_options, FCPU);
usart_init_rs232(uart->instance, &usart_options, FPBA);
return RT_EOK;
}
static rt_err_t avr32uc3b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
static rt_err_t avr32uc3_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct avr32uc3b_uart_dev *uart = RT_NULL;
struct avr32uc3_uart_dev *uart = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
switch (cmd)
{
@ -229,21 +230,21 @@ static rt_err_t avr32uc3b_uart_control(struct rt_serial_device *serial, int cmd,
return RT_EOK;
}
static int avr32uc3b_uart_putc(struct rt_serial_device *serial, char c)
static int avr32uc3_uart_putc(struct rt_serial_device *serial, char c)
{
struct avr32uc3b_uart_dev *uart = RT_NULL;
struct avr32uc3_uart_dev *uart = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
usart_putchar(uart->instance, c);
return 1;
}
static int avr32uc3b_uart_getc(struct rt_serial_device *serial)
static int avr32uc3_uart_getc(struct rt_serial_device *serial)
{
struct avr32uc3b_uart_dev *uart = RT_NULL;
struct avr32uc3_uart_dev *uart = RT_NULL;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct avr32uc3b_uart_dev, parent);
uart = rt_container_of(serial, struct avr32uc3_uart_dev, parent);
int ch;
if (usart_read_char(uart->instance, &ch) == USART_SUCCESS)
@ -254,10 +255,10 @@ static int avr32uc3b_uart_getc(struct rt_serial_device *serial)
const static struct rt_uart_ops _uart_ops =
{
avr32uc3b_uart_configure,
avr32uc3b_uart_control,
avr32uc3b_uart_putc,
avr32uc3b_uart_getc,
avr32uc3_uart_configure,
avr32uc3_uart_control,
avr32uc3_uart_putc,
avr32uc3_uart_getc,
RT_NULL,
};

11
bsp/avr32uc3b0/drv_uart.h → bsp/avr32/drivers/drv_uart.h
View File

@ -8,7 +8,8 @@
* 2009-01-05 Bernard first version
* 2010-03-29 Bernard remove interrupt tx and DMA rx mode.
* 2010-03-30 Kyle Ported from STM32 to AVR32.
* 2023-10-13 Raman Gopalan UART driver for at32uc3b: Initial version
* 2023-10-25 Raman Gopalan UART driver for at32uc3a: Initial version
* 2023-11-06 Raman Gopalan Driver abstractions for uc3a and uc3b devices
*/
#ifndef __RT_HW_SERIAL_H__
@ -20,10 +21,18 @@
#include "usart.h"
#define FOSC0 12000000
#ifndef BSP_BOARD_MIZAR32B
#define FCPU 60000000
#define FHSB FCPU
#define FPBA FCPU
#define FPBB FCPU
#else
#define FCPU 66000000
#define FHSB FCPU
#define FPBA 16500000
#define FPBB FCPU
#endif
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_DMA_NODE_SIZE 4

32
bsp/avr32/software_framework/SConscript Normal file
View File

@ -0,0 +1,32 @@
import rtconfig
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Split("""
drivers/flashc/flashc.c
drivers/gpio/gpio.c
drivers/intc/intc.c
drivers/pm/pm.c
drivers/pm/pm_conf_clocks.c
drivers/pm/power_clocks_lib.c
drivers/usart/usart.c
drivers/adc/adc.c
""")
CPPPATH = [
cwd + '/boards',
cwd + '/utils',
cwd + '/utils/preprocessor',
cwd + '/drivers/flashc',
cwd + '/drivers/gpio',
cwd + '/drivers/intc',
cwd + '/drivers/pm',
cwd + '/drivers/usart',
cwd + '/drivers/adc',
]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

0
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/BOARDS/board.h → bsp/avr32/software_framework/boards/board.h
View File

191
bsp/avr32/software_framework/drivers/adc/adc.c Normal file
View File

@ -0,0 +1,191 @@
/*****************************************************************************
*
* \file
*
* \brief ADC driver for AVR UC3.
*
* This file defines a useful set of functions for ADC on AVR UC3 devices.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <avr32/io.h>
#include "compiler.h"
#include "adc.h"
/** \brief Configure ADC. Mandatory to call.
* If not called, ADC channels will have side effects
*
* \param *adc Base address of the ADC
*/
void adc_configure(volatile avr32_adc_t *adc)
{
Assert( adc != NULL );
#ifdef USE_ADC_8_BITS
adc->mr |= 1 << AVR32_ADC_LOWRES_OFFSET;
#endif
/* Set Sample/Hold time to max so that the ADC capacitor should be
* loaded entirely */
adc->mr |= 0xF << AVR32_ADC_SHTIM_OFFSET;
/* Set Startup to max so that the ADC capacitor should be loaded
* entirely */
adc->mr |= 0x1F << AVR32_ADC_STARTUP_OFFSET;
}
/** \brief Start analog to digital conversion
* \param *adc Base address of the ADC
*/
void adc_start(volatile avr32_adc_t *adc)
{
Assert( adc != NULL );
/* start conversion */
adc->cr = AVR32_ADC_START_MASK;
}
/** \brief Enable channel
*
* \param *adc Base address of the ADC
* \param channel channel to enable (0 to 7)
*/
void adc_enable(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
**/
/* enable channel */
adc->cher = (1 << channel);
}
/** \brief Disable channel
*
* \param *adc Base address of the ADC
* \param channel channel to disable (0 to 7)
*/
void adc_disable(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
**/
if (adc_get_status(adc, channel) == true) {
/* disable channel */
adc->chdr |= (1 << channel);
}
}
/** \brief Get channel 0 to 7 status
*
* \param *adc Base address of the ADC
* \param channel channel to handle (0 to 7)
* \return bool true if channel is enabled
* false if channel is disabled
*/
bool adc_get_status(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
**/
return ((adc->chsr & (1 << channel)) ? true : false);
}
/** \brief Check channel conversion status
*
* \param *adc Base address of the ADC
* \param channel channel to check (0 to 7)
* \return bool true if conversion not running
* false if conversion running
*/
bool adc_check_eoc(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
**/
/* get SR register : EOC bit for channel */
return ((adc->sr & (1 << channel)) ? true : false);
}
/** \brief Check channel conversion overrun error
*
* \param *adc Base address of the ADC
* \param channel channel to check (0 to 7)
* \return bool FAIL if an error occurred
* PASS if no error occurred
*/
bool adc_check_ovr(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB ); /* check if channel exist
**/
/* get SR register : OVR bit for channel */
return ((adc->sr & (1 << (channel + 8))) ? FAIL : PASS);
}
/** \brief Get channel value
*
* \param *adc Base address of the ADC
* \param channel channel to handle (0 to 7)
* \return The value acquired (unsigned long)
*/
uint32_t adc_get_value(volatile avr32_adc_t *adc, uint16_t channel)
{
Assert( adc != NULL );
Assert( channel <= AVR32_ADC_CHANNELS_MSB );
/* wait for end of conversion */
while (adc_check_eoc(adc, channel) != true) {
}
return *((uint32_t *)((&(adc->cdr0)) + channel));
}
/** \brief Wait for the next converted data and return its value
*
* \param *adc Base address of the ADC
* \return The latest converted value (unsigned long)
*/
uint32_t adc_get_latest_value(volatile avr32_adc_t *adc)
{
Assert( adc != NULL );
/* Wait for the data ready flag */
while ((adc->sr & AVR32_ADC_DRDY_MASK) != AVR32_ADC_DRDY_MASK) {
}
return adc->lcdr;
}

87
bsp/avr32/software_framework/drivers/adc/adc.h Normal file
View File

@ -0,0 +1,87 @@
/*****************************************************************************
*
* \file
*
* \brief ADC header for AVR UC3 UC3.
*
* This file defines a useful set of functions for ADC on AVR UC3 devices.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _ADC_H_
#define _ADC_H_
/**
* \defgroup group_avr32_drivers_adc ADC - Analog to Digital Converter
*
* Analog to Digital Converter is able to capture analog signals and transform
* them
* into digital format with 10-bit resolution.
*
* \{
*/
#include <avr32/io.h>
#include "compiler.h"
/* if using 8 bits for ADC, define this flag in your compiler options */
/** Max value for ADC resolution */
#ifdef USE_ADC_8_BITS
# define ADC_MAX_VALUE 0xFF
#else
# define ADC_MAX_VALUE 0x3FF
#endif
void adc_configure(volatile avr32_adc_t *adc);
void adc_start(volatile avr32_adc_t *adc);
void adc_enable(volatile avr32_adc_t *adc, uint16_t channel);
void adc_disable(volatile avr32_adc_t *adc, uint16_t channel);
bool adc_get_status(volatile avr32_adc_t *adc, uint16_t channel);
bool adc_check_eoc(volatile avr32_adc_t *adc, uint16_t channel);
bool adc_check_ovr(volatile avr32_adc_t *adc, uint16_t channel);
uint32_t adc_get_value(volatile avr32_adc_t *adc,
uint16_t channel);
uint32_t adc_get_latest_value(volatile avr32_adc_t *adc);
/**
* \}
*/
#endif /* _ADC_H_ */

973
bsp/avr32/software_framework/drivers/flashc/flashc.c Normal file
View File

@ -0,0 +1,973 @@
/**
* \file
*
* \brief FLASHC driver for AVR32 UC3.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <avr32/io.h>
#include <stddef.h>
#include "compiler.h"
#include "flashc.h"
/*! \name FLASHC Writable Bit-Field Registers
*/
//! @{
typedef union {
unsigned long fcr;
avr32_flashc_fcr_t FCR;
} u_avr32_flashc_fcr_t;
typedef union {
unsigned long fcmd;
avr32_flashc_fcmd_t FCMD;
} u_avr32_flashc_fcmd_t;
//! @}
/*! \name Flash Properties
*/
//! @{
unsigned int flashc_get_flash_size(void)
{
#if (AVR32_FLASHC_H_VERSION >= 300)
const uint16_t FLASH_SIZE[] = {
4,
8,
16,
32,
48,
64,
96,
128,
192,
256,
384,
512,
768,
1024,
2048,
};
return ((unsigned int)FLASH_SIZE[(AVR32_FLASHC.pr & AVR32_FLASHC_PR_FSZ_MASK)
>> AVR32_FLASHC_PR_FSZ_OFFSET])<<10;
#else // in older flashc version, FSZ is located in FSR register
const uint16_t FLASH_SIZE[] = {
32,
64,
128,
256,
384,
512,
768,
1024,
};
return ((unsigned int)FLASH_SIZE[(AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FSZ_MASK)
>> AVR32_FLASHC_FSR_FSZ_OFFSET]) << 10;
#endif
}
unsigned int flashc_get_page_count(void)
{
return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE;
}
unsigned int flashc_get_page_count_per_region(void)
{
return flashc_get_page_count() / AVR32_FLASHC_REGIONS;
}
unsigned int flashc_get_page_region(int page_number)
{
return ((page_number >= 0) ? page_number
: flashc_get_page_number()) / flashc_get_page_count_per_region();
}
unsigned int flashc_get_region_first_page_number(unsigned int region)
{
return region * flashc_get_page_count_per_region();
}
//! @}
/*! \name FLASHC Control
*/
//! @{
unsigned int flashc_get_wait_state(void)
{
return (AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FWS_MASK) >> AVR32_FLASHC_FCR_FWS_OFFSET;
}
void flashc_set_wait_state(unsigned int wait_state)
{
u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
u_avr32_flashc_fcr.FCR.fws = wait_state;
AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
}
void flashc_set_bus_freq(unsigned int cpu_f_hz)
{
if (cpu_f_hz >= AVR32_FLASHC_FWS_0_MAX_FREQ) {
// Set 1 WS.
flashc_set_wait_state(1);
} else {
// Set 0 WS.
flashc_set_wait_state(0);
}
}
bool flashc_is_ready_int_enabled(void)
{
return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_FRDY_MASK) != 0);
}
void flashc_enable_ready_int(bool enable)
{
u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
u_avr32_flashc_fcr.FCR.frdy = (enable != false);
AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
}
bool flashc_is_lock_error_int_enabled(void)
{
return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_LOCKE_MASK) != 0);
}
void flashc_enable_lock_error_int(bool enable)
{
u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
u_avr32_flashc_fcr.FCR.locke = (enable != false);
AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
}
bool flashc_is_prog_error_int_enabled(void)
{
return ((AVR32_FLASHC.fcr & AVR32_FLASHC_FCR_PROGE_MASK) != 0);
}
void flashc_enable_prog_error_int(bool enable)
{
u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
u_avr32_flashc_fcr.FCR.proge = (enable != false);
AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
}
//! @}
/*! \name FLASHC Status
*/
//! @{
bool flashc_is_ready(void)
{
return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_FRDY_MASK) != 0);
}
void flashc_default_wait_until_ready(void)
{
while (!flashc_is_ready());
}
void (*volatile flashc_wait_until_ready)(void) = flashc_default_wait_until_ready;
/*! \brief Gets the error status of the FLASHC.
*
* \return The error status of the FLASHC built up from
* \c AVR32_FLASHC_FSR_LOCKE_MASK and \c AVR32_FLASHC_FSR_PROGE_MASK.
*
* \warning This hardware error status is cleared by all functions reading the
* Flash Status Register (FSR). This function is therefore not part of
* the driver's API which instead presents \ref flashc_is_lock_error
* and \ref flashc_is_programming_error.
*/
static unsigned int flashc_get_error_status(void)
{
return AVR32_FLASHC.fsr & (AVR32_FLASHC_FSR_LOCKE_MASK |
AVR32_FLASHC_FSR_PROGE_MASK);
}
//! Sticky error status of the FLASHC.
//! This variable is updated by functions that issue FLASHC commands. It
//! contains the cumulated FLASHC error status of all the FLASHC commands issued
//! by a function.
static unsigned int flashc_error_status = 0;
bool flashc_is_lock_error(void)
{
return ((flashc_error_status & AVR32_FLASHC_FSR_LOCKE_MASK) != 0);
}
bool flashc_is_programming_error(void)
{
return ((flashc_error_status & AVR32_FLASHC_FSR_PROGE_MASK) != 0);
}
//! @}
/*! \name FLASHC Command Control
*/
//! @{
unsigned int flashc_get_command(void)
{
return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_CMD_MASK) >> AVR32_FLASHC_FCMD_CMD_OFFSET;
}
unsigned int flashc_get_page_number(void)
{
return (AVR32_FLASHC.fcmd & AVR32_FLASHC_FCMD_PAGEN_MASK) >> AVR32_FLASHC_FCMD_PAGEN_OFFSET;
}
void flashc_issue_command(unsigned int command, int page_number)
{
u_avr32_flashc_fcmd_t u_avr32_flashc_fcmd;
flashc_wait_until_ready();
u_avr32_flashc_fcmd.fcmd = AVR32_FLASHC.fcmd;
u_avr32_flashc_fcmd.FCMD.cmd = command;
if (page_number >= 0) {
u_avr32_flashc_fcmd.FCMD.pagen = page_number;
}
u_avr32_flashc_fcmd.FCMD.key = AVR32_FLASHC_FCMD_KEY_KEY;
AVR32_FLASHC.fcmd = u_avr32_flashc_fcmd.fcmd;
flashc_error_status = flashc_get_error_status();
flashc_wait_until_ready();
}
//! @}
/*! \name FLASHC Global Commands
*/
//! @{
void flashc_no_operation(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_NOP, -1);
}
void flashc_erase_all(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EA, -1);
}
//! @}
/*! \name FLASHC Protection Mechanisms
*/
//! @{
bool flashc_is_security_bit_active(void)
{
return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_SECURITY_MASK) != 0);
}
void flashc_activate_security_bit(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_SSB, -1);
}
unsigned int flashc_get_bootloader_protected_size(void)
{
unsigned int bootprot = (1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 -
flashc_read_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET,
AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE);
return (bootprot) ? AVR32_FLASHC_PAGE_SIZE << bootprot : 0;
}
unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_size)
{
flashc_set_gp_fuse_bitfield(AVR32_FLASHC_FGPFRLO_BOOTPROT_OFFSET,
AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE,
(1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1 -
((bootprot_size) ?
32 - clz((((min(max(bootprot_size, AVR32_FLASHC_PAGE_SIZE << 1),
AVR32_FLASHC_PAGE_SIZE <<
((1 << AVR32_FLASHC_FGPFRLO_BOOTPROT_SIZE) - 1)) +
AVR32_FLASHC_PAGE_SIZE - 1) /
AVR32_FLASHC_PAGE_SIZE) << 1) - 1) - 1 :
0));
return flashc_get_bootloader_protected_size();
}
bool flashc_is_external_privileged_fetch_locked(void)
{
return (!flashc_read_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET));
}
void flashc_lock_external_privileged_fetch(bool lock)
{
flashc_set_gp_fuse_bit(AVR32_FLASHC_FGPFRLO_EPFL_OFFSET, !lock);
}
bool flashc_is_page_region_locked(int page_number)
{
return flashc_is_region_locked(flashc_get_page_region(page_number));
}
bool flashc_is_region_locked(unsigned int region)
{
return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCK0_MASK << (region & (AVR32_FLASHC_REGIONS - 1))) != 0);
}
void flashc_lock_page_region(int page_number, bool lock)
{
flashc_issue_command((lock) ? AVR32_FLASHC_FCMD_CMD_LP : AVR32_FLASHC_FCMD_CMD_UP, page_number);
}
void flashc_lock_region(unsigned int region, bool lock)
{
flashc_lock_page_region(flashc_get_region_first_page_number(region), lock);
}
void flashc_lock_all_regions(bool lock)
{
unsigned int error_status = 0;
unsigned int region = AVR32_FLASHC_REGIONS;
while (region) {
flashc_lock_region(--region, lock);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
}
//! @}
/*! \name Access to General-Purpose Fuses
*/
//! @{
bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit)
{
return ((flashc_read_all_gp_fuses() & 1ULL << (gp_fuse_bit & 0x3F)) != 0);
}
uint64_t flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width)
{
return flashc_read_all_gp_fuses() >> (pos & 0x3F) & ((1ULL << min(width, 64)) - 1);
}
uint8_t flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte)
{
return flashc_read_all_gp_fuses() >> ((gp_fuse_byte & 0x07) << 3);
}
uint64_t flashc_read_all_gp_fuses(void)
{
return AVR32_FLASHC.fgpfrlo | (uint64_t)AVR32_FLASHC.fgpfrhi << 32;
}
bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, bool check)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EGPB, gp_fuse_bit & 0x3F);
return (check) ? flashc_read_gp_fuse_bit(gp_fuse_bit) : true;
}
bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, bool check)
{
unsigned int error_status = 0;
unsigned int gp_fuse_bit;
pos &= 0x3F;
width = min(width, 64);
for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++) {
flashc_erase_gp_fuse_bit(gp_fuse_bit, false);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
return (check) ? (flashc_read_gp_fuse_bitfield(pos, width) == (1ULL << width) - 1) : true;
}
bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, bool check)
{
unsigned int error_status;
unsigned int current_gp_fuse_byte;
uint64_t value = flashc_read_all_gp_fuses();
flashc_erase_all_gp_fuses(false);
error_status = flashc_error_status;
for (current_gp_fuse_byte = 0; current_gp_fuse_byte < 8; current_gp_fuse_byte++, value >>= 8) {
if (current_gp_fuse_byte != gp_fuse_byte) {
flashc_write_gp_fuse_byte(current_gp_fuse_byte, value);
error_status |= flashc_error_status;
}
}
flashc_error_status = error_status;
return (check) ? (flashc_read_gp_fuse_byte(gp_fuse_byte) == 0xFF) : true;
}
bool flashc_erase_all_gp_fuses(bool check)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EAGPF, -1);
return (check) ? (flashc_read_all_gp_fuses() == 0xFFFFFFFFFFFFFFFFULL) : true;
}
void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, bool value)
{
if (!value) {
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WGPB, gp_fuse_bit & 0x3F);
}
}
void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, uint64_t value)
{
unsigned int error_status = 0;
unsigned int gp_fuse_bit;
pos &= 0x3F;
width = min(width, 64);
for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) {
flashc_write_gp_fuse_bit(gp_fuse_bit, value & 0x01);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
}
void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, uint8_t value)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_PGPFB, (gp_fuse_byte & 0x07) | value << 3);
}
void flashc_write_all_gp_fuses(uint64_t value)
{
unsigned int error_status = 0;
unsigned int gp_fuse_byte;
for (gp_fuse_byte = 0; gp_fuse_byte < 8; gp_fuse_byte++, value >>= 8) {
flashc_write_gp_fuse_byte(gp_fuse_byte, value);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
}
void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, bool value)
{
if (value) {
flashc_erase_gp_fuse_bit(gp_fuse_bit, false);
} else {
flashc_write_gp_fuse_bit(gp_fuse_bit, false);
}
}
void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, uint64_t value)
{
unsigned int error_status = 0;
unsigned int gp_fuse_bit;
pos &= 0x3F;
width = min(width, 64);
for (gp_fuse_bit = pos; gp_fuse_bit < pos + width; gp_fuse_bit++, value >>= 1) {
flashc_set_gp_fuse_bit(gp_fuse_bit, value & 0x01);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
}
void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, uint8_t value)
{
unsigned int error_status;
switch (value) {
case 0xFF:
flashc_erase_gp_fuse_byte(gp_fuse_byte, false);
break;
case 0x00:
flashc_write_gp_fuse_byte(gp_fuse_byte, 0x00);
break;
default:
flashc_erase_gp_fuse_byte(gp_fuse_byte, false);
error_status = flashc_error_status;
flashc_write_gp_fuse_byte(gp_fuse_byte, value);
flashc_error_status |= error_status;
break;
}
}
void flashc_set_all_gp_fuses(uint64_t value)
{
unsigned int error_status;
switch (value) {
case 0xFFFFFFFFFFFFFFFFULL:
flashc_erase_all_gp_fuses(false);
break;
case 0x0000000000000000ULL:
flashc_write_all_gp_fuses(0x0000000000000000ULL);
break;
default:
flashc_erase_all_gp_fuses(false);
error_status = flashc_error_status;
flashc_write_all_gp_fuses(value);
flashc_error_status |= error_status;
break;
}
}
//! @}
/*! \name Access to Flash Pages
*/
//! @{
void flashc_clear_page_buffer(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_CPB, -1);
}
bool flashc_is_page_erased(void)
{
return ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK) != 0);
}
bool flashc_quick_page_read(int page_number)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPR, page_number);
return flashc_is_page_erased();
}
bool flashc_erase_page(int page_number, bool check)
{
bool page_erased = true;
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EP, page_number);
if (check) {
unsigned int error_status = flashc_error_status;
page_erased = flashc_quick_page_read(-1);
flashc_error_status |= error_status;
}
return page_erased;
}
bool flashc_erase_all_pages(bool check)
{
bool all_pages_erased = true;
unsigned int error_status = 0;
unsigned int page_number = flashc_get_page_count();
while (page_number) {
all_pages_erased &= flashc_erase_page(--page_number, check);
error_status |= flashc_error_status;
}
flashc_error_status = error_status;
return all_pages_erased;
}
void flashc_write_page(int page_number)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WP, page_number);
}
bool flashc_quick_user_page_read(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_QPRUP, -1);
return flashc_is_page_erased();
}
bool flashc_erase_user_page(bool check)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_EUP, -1);
return (check) ? flashc_quick_user_page_read() : true;
}
void flashc_write_user_page(void)
{
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_WUP, -1);
}
volatile void *flashc_memset8(volatile void *dst, uint8_t src, size_t nbytes, bool erase)
{
return flashc_memset16(dst, src | (uint16_t)src << 8, nbytes, erase);
}
volatile void *flashc_memset16(volatile void *dst, uint16_t src, size_t nbytes, bool erase)
{
return flashc_memset32(dst, src | (uint32_t)src << 16, nbytes, erase);
}
volatile void *flashc_memset32(volatile void *dst, uint32_t src, size_t nbytes, bool erase)
{
return flashc_memset64(dst, src | (uint64_t)src << 32, nbytes, erase);
}
volatile void *flashc_memset64(volatile void *dst, uint64_t src, size_t nbytes, bool erase)
{
// Use aggregated pointers to have several alignments available for a same address.
UnionCVPtr flash_array_end;
UnionVPtr dest;
Union64 source = {0};
StructCVPtr dest_end;
UnionCVPtr flash_page_source_end;
bool incomplete_flash_page_end;
Union64 flash_dword;
UnionVPtr tmp;
unsigned int error_status = 0;
unsigned int i;
// Reformat arguments.
flash_array_end.u8ptr = AVR32_FLASH + flashc_get_flash_size();
dest.u8ptr = dst;
for (i = (Get_align((uint32_t)dest.u8ptr, sizeof(uint64_t)) - 1) & (sizeof(uint64_t) - 1);
src; i = (i - 1) & (sizeof(uint64_t) - 1)) {
source.u8[i] = src;
src >>= 8;
}
dest_end.u8ptr = dest.u8ptr + nbytes;
// If destination is outside flash, go to next flash page if any.
if (dest.u8ptr < AVR32_FLASH) {
dest.u8ptr = AVR32_FLASH;
} else if (flash_array_end.u8ptr <= dest.u8ptr && dest.u8ptr < AVR32_FLASHC_USER_PAGE) {
dest.u8ptr = AVR32_FLASHC_USER_PAGE;
}
// If end of destination is outside flash, move it to the end of the previous flash page if any.
if (dest_end.u8ptr > AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE) {
dest_end.u8ptr = AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE;
} else if (AVR32_FLASHC_USER_PAGE >= dest_end.u8ptr && dest_end.u8ptr > flash_array_end.u8ptr) {
dest_end.u8ptr = flash_array_end.u8ptr;
}
// Align each end of destination pointer with its natural boundary.
dest_end.u16ptr = (uint16_t *)Align_down((uint32_t)dest_end.u8ptr, sizeof(uint16_t));
dest_end.u32ptr = (uint32_t *)Align_down((uint32_t)dest_end.u16ptr, sizeof(uint32_t));
dest_end.u64ptr = (uint64_t *)Align_down((uint32_t)dest_end.u32ptr, sizeof(uint64_t));
// While end of destination is not reached...
while (dest.u8ptr < dest_end.u8ptr) {
// Clear the page buffer in order to prepare data for a flash page write.
flashc_clear_page_buffer();
error_status |= flashc_error_status;
// Determine where the source data will end in the current flash page.
flash_page_source_end.u64ptr =
(uint64_t *)min((uint32_t)dest_end.u64ptr,
Align_down((uint32_t)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) + AVR32_FLASHC_PAGE_SIZE);
// Determine if the current destination page has an incomplete end.
incomplete_flash_page_end = (Align_down((uint32_t)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE) >=
Align_down((uint32_t)dest_end.u8ptr, AVR32_FLASHC_PAGE_SIZE));
// Use a flash double-word buffer to manage unaligned accesses.
flash_dword.u64 = source.u64;
// If destination does not point to the beginning of the current flash page...
if (!Test_align((uint32_t)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE)) {
// Fill the beginning of the page buffer with the current flash page data.
// This is required by the hardware, even if page erase is not requested,
// in order to be able to write successfully to erased parts of flash
// pages that have already been written to.
for (tmp.u8ptr = (uint8_t *)Align_down((uint32_t)dest.u8ptr, AVR32_FLASHC_PAGE_SIZE);
tmp.u64ptr < (uint64_t *)Align_down((uint32_t)dest.u8ptr, sizeof(uint64_t));
tmp.u64ptr++) {
*tmp.u64ptr = *tmp.u64ptr;
}
// If destination is not 64-bit aligned...
if (!Test_align((uint32_t)dest.u8ptr, sizeof(uint64_t))) {
// Fill the beginning of the flash double-word buffer with the current
// flash page data.
// This is required by the hardware, even if page erase is not
// requested, in order to be able to write successfully to erased parts
// of flash pages that have already been written to.
for (i = 0; i < Get_align((uint32_t)dest.u8ptr, sizeof(uint64_t)); i++) {
flash_dword.u8[i] = *tmp.u8ptr++;
}
// Align the destination pointer with its 64-bit boundary.
dest.u64ptr = (uint64_t *)Align_down((uint32_t)dest.u8ptr, sizeof(uint64_t));
// If the current destination double-word is not the last one...
if (dest.u64ptr < dest_end.u64ptr) {
// Write the flash double-word buffer to the page buffer and reinitialize it.
*dest.u64ptr++ = flash_dword.u64;
flash_dword.u64 = source.u64;
}
}
}
// Write the source data to the page buffer with 64-bit alignment.
for (i = flash_page_source_end.u64ptr - dest.u64ptr; i; i--) {
*dest.u64ptr++ = source.u64;
}
// If the current destination page has an incomplete end...
if (incomplete_flash_page_end) {
// This is required by the hardware, even if page erase is not requested,
// in order to be able to write successfully to erased parts of flash
// pages that have already been written to.
{
tmp.u8ptr = (volatile uint8_t *)dest_end.u8ptr;
// If end of destination is not 64-bit aligned...
if (!Test_align((uint32_t)dest_end.u8ptr, sizeof(uint64_t))) {
// Fill the end of the flash double-word buffer with the current flash page data.
for (i = Get_align((uint32_t)dest_end.u8ptr, sizeof(uint64_t)); i < sizeof(uint64_t); i++)
flash_dword.u8[i] = *tmp.u8ptr++;
// Write the flash double-word buffer to the page buffer.
*dest.u64ptr++ = flash_dword.u64;
}
// Fill the end of the page buffer with the current flash page data.
for (; !Test_align((uint32_t)tmp.u64ptr, AVR32_FLASHC_PAGE_SIZE); tmp.u64ptr++) {
*tmp.u64ptr = *tmp.u64ptr;
}
}
}
// If the current flash page is in the flash array...
if (dest.u8ptr <= AVR32_FLASHC_USER_PAGE) {
// Erase the current page if requested and write it from the page buffer.
if (erase) {
flashc_erase_page(-1, false);
error_status |= flashc_error_status;
}
flashc_write_page(-1);
error_status |= flashc_error_status;
// If the end of the flash array is reached, go to the User page.
if (dest.u8ptr >= flash_array_end.u8ptr) {
dest.u8ptr = AVR32_FLASHC_USER_PAGE;
}
} else {
// Erase the User page if requested and write it from the page buffer.
if (erase) {
flashc_erase_user_page(false);
error_status |= flashc_error_status;
}
flashc_write_user_page();
error_status |= flashc_error_status;
}
}
// Update the FLASHC error status.
flashc_error_status = error_status;
// Return the initial destination pointer as the standard memset function does.
return dst;
}
volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, bool erase)
{
uint16_t page_pos;
Union64 flash_dword;
uint8_t i;
bool b_user_page;
unsigned int error_status = 0;
uint8_t* flash_add;
uint8_t* dest_add=(uint8_t*)dst;
const uint8_t* src_buf=(const uint8_t*)src;
// Copy area must be in flash array or flash user page
Assert( (((uint8_t *)dst >= AVR32_FLASH)
&& (((uint8_t *)dst + nbytes) <= (AVR32_FLASH + flashc_get_flash_size())))
|| (((uint8_t *)dst >= AVR32_FLASHC_USER_PAGE)
&& (((uint8_t *)dst + nbytes) <= (AVR32_FLASHC_USER_PAGE + AVR32_FLASHC_USER_PAGE_SIZE))) );
b_user_page = (volatile uint8_t *)dst >= AVR32_FLASHC_USER_PAGE;
flash_add = (uint8_t*)((uint32_t)dest_add - ((uint32_t)dest_add % AVR32_FLASHC_PAGE_SIZE));
while (nbytes) {
// Clear the page buffer in order to prepare data for a flash page write.
flashc_clear_page_buffer();
error_status |= flashc_error_status;
// Loop in the page
for (page_pos=0; page_pos<AVR32_FLASHC_PAGE_SIZE; page_pos+=sizeof(uint64_t) ) {
// Read the flash double-word buffer
flash_dword.u64 = *(volatile uint64_t*)flash_add;
// Update double-word if necessary
for (i = 0; i < sizeof(uint64_t); i++) {
if (nbytes && (flash_add == dest_add)) {
// Update page with data source
flash_dword.u8[i] = *src_buf++;
dest_add++;
nbytes--;
}
flash_add++;
}
// Write the flash double-word buffer to the page buffer.
*(volatile uint64_t*)((uint32_t)flash_add - sizeof(uint64_t))= flash_dword.u64;
}
// Erase the current page if requested and write it from the page buffer.
if (erase) {
(b_user_page)? flashc_erase_user_page(false) : flashc_erase_page(-1, false);
error_status |= flashc_error_status;
}
// Write the page
(b_user_page)? flashc_write_user_page() : flashc_write_page(-1);
error_status |= flashc_error_status;
}
// Update the FLASHC error status.
flashc_error_status = error_status;
// Return the initial destination pointer as the standard memcpy function does.
return dst;
}
#if UC3C
void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz)
{
//! Device-specific data
#undef AVR32_FLASHC_FWS_0_MAX_FREQ
#undef AVR32_FLASHC_FWS_1_MAX_FREQ
#undef AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ
#undef AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ
#define AVR32_FLASHC_FWS_0_MAX_FREQ 33000000
#define AVR32_FLASHC_FWS_1_MAX_FREQ 66000000
#define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ 33000000
#define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ 72000000
// These defines are missing from or wrong in the toolchain header files uc3cxxx.h
// Put a Bugzilla
if (cpu_f_hz > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) { // > 33MHz
// Set a wait-state
flashc_set_wait_state(1);
if (cpu_f_hz <= AVR32_FLASHC_FWS_1_MAX_FREQ) { // <= 66MHz and >33Mhz
// Disable the high-speed read mode.
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
} else { // > 66Mhz
// Enable the high-speed read mode.
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
}
} else { // <= 33 MHz
// Disable wait-state
flashc_set_wait_state(0);
// Disable the high-speed read mode.
flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
}
}
#endif // UC3C device-specific implementation
//! @}

293
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.h → bsp/avr32/software_framework/drivers/flashc/flashc.h
View File

@ -1,62 +1,58 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/**
* \file
*
* \brief FLASHC driver for AVR32 UC3.
*
* AVR32 Flash Controller driver module.
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a FLASHC module can be used.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
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*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* \asf_license_stop
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/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _FLASHC_H_
#define _FLASHC_H_
/**
* \defgroup group_avr32_drivers_flashc MEMORY - FLASHC - Flash Controller
*
* FLASHC interfaces a flash block with the 32-bit internal HSB bus.
*
* \{
*/
#include <avr32/io.h>
#include <stddef.h>
#include "compiler.h"
//! Number of flash regions defined by the FLASHC.
#define AVR32_FLASHC_REGIONS (AVR32_FLASHC_FLASH_SIZE /\
(AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE))
(AVR32_FLASHC_PAGES_PR_REGION * AVR32_FLASHC_PAGE_SIZE))
/*! \name Flash Properties
@ -120,44 +116,56 @@ extern unsigned int flashc_get_wait_state(void);
*/
extern void flashc_set_wait_state(unsigned int wait_state);
/*! \brief Depending on the CPU frequency, set the wait states of flash read
* accesses.
*
* \param cpu_f_hz The CPU frequency
*/
extern void flashc_set_bus_freq(unsigned int cpu_f_hz);
/*! \brief Alias on the flashc_set_bus_freq() function.
*
* \param cpu_f_hz The CPU frequency
*/
#define flash_set_bus_freq(cpu_f_hz) flashc_set_bus_freq(cpu_f_hz)
/*! \brief Tells whether the Flash Ready interrupt is enabled.
*
* \return Whether the Flash Ready interrupt is enabled.
*/
extern Bool flashc_is_ready_int_enabled(void);
extern bool flashc_is_ready_int_enabled(void);
/*! \brief Enables or disables the Flash Ready interrupt.
*
* \param enable Whether to enable the Flash Ready interrupt: \c TRUE or
* \c FALSE.
* \param enable Whether to enable the Flash Ready interrupt: \c true or
* \c false.
*/
extern void flashc_enable_ready_int(Bool enable);
extern void flashc_enable_ready_int(bool enable);
/*! \brief Tells whether the Lock Error interrupt is enabled.
*
* \return Whether the Lock Error interrupt is enabled.
*/
extern Bool flashc_is_lock_error_int_enabled(void);
extern bool flashc_is_lock_error_int_enabled(void);
/*! \brief Enables or disables the Lock Error interrupt.
*
* \param enable Whether to enable the Lock Error interrupt: \c TRUE or
* \c FALSE.
* \param enable Whether to enable the Lock Error interrupt: \c true or
* \c false.
*/
extern void flashc_enable_lock_error_int(Bool enable);
extern void flashc_enable_lock_error_int(bool enable);
/*! \brief Tells whether the Programming Error interrupt is enabled.
*
* \return Whether the Programming Error interrupt is enabled.
*/
extern Bool flashc_is_prog_error_int_enabled(void);
extern bool flashc_is_prog_error_int_enabled(void);
/*! \brief Enables or disables the Programming Error interrupt.
*
* \param enable Whether to enable the Programming Error interrupt: \c TRUE or
* \c FALSE.
* \param enable Whether to enable the Programming Error interrupt: \c true or
* \c false.
*/
extern void flashc_enable_prog_error_int(Bool enable);
extern void flashc_enable_prog_error_int(bool enable);
//! @}
@ -170,7 +178,7 @@ extern void flashc_enable_prog_error_int(Bool enable);
*
* \return Whether the FLASHC is ready to run a new command.
*/
extern Bool flashc_is_ready(void);
extern bool flashc_is_ready(void);
/*! \brief Waits actively until the FLASHC is ready to run a new command.
*
@ -190,7 +198,7 @@ extern void (*volatile flashc_wait_until_ready)(void);
* \return Whether a Lock Error has occurred during the last function called
* that issued one or more FLASHC commands.
*/
extern Bool flashc_is_lock_error(void);
extern bool flashc_is_lock_error(void);
/*! \brief Tells whether a Programming Error has occurred during the last
* function called that issued one or more FLASHC commands.
@ -198,7 +206,7 @@ extern Bool flashc_is_lock_error(void);
* \return Whether a Programming Error has occurred during the last function
* called that issued one or more FLASHC commands.
*/
extern Bool flashc_is_programming_error(void);
extern bool flashc_is_programming_error(void);
//! @}
@ -283,7 +291,7 @@ extern void flashc_erase_all(void);
*
* \return Whether the Security bit is active.
*/
extern Bool flashc_is_security_bit_active(void);
extern bool flashc_is_security_bit_active(void);
/*! \brief Activates the Security bit.
*
@ -318,18 +326,18 @@ extern unsigned int flashc_set_bootloader_protected_size(unsigned int bootprot_s
*
* \return Whether external privileged fetch is locked.
*/
extern Bool flashc_is_external_privileged_fetch_locked(void);
extern bool flashc_is_external_privileged_fetch_locked(void);
/*! \brief Locks or unlocks external privileged fetch.
*
* \param lock Whether to lock external privileged fetch: \c TRUE or \c FALSE.
* \param lock Whether to lock external privileged fetch: \c true or \c false.
*
* \warning A Lock Error is issued if the Security bit is active.
*
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern void flashc_lock_external_privileged_fetch(Bool lock);
extern void flashc_lock_external_privileged_fetch(bool lock);
/*! \brief Tells whether the region of a page is locked.
*
@ -340,7 +348,7 @@ extern void flashc_lock_external_privileged_fetch(Bool lock);
*
* \return Whether the region of the specified page is locked.
*/
extern Bool flashc_is_page_region_locked(int page_number);
extern bool flashc_is_page_region_locked(int page_number);
/*! \brief Tells whether a region is locked.
*
@ -348,7 +356,7 @@ extern Bool flashc_is_page_region_locked(int page_number);
*
* \return Whether the specified region is locked.
*/
extern Bool flashc_is_region_locked(unsigned int region);
extern bool flashc_is_region_locked(unsigned int region);
/*! \brief Locks or unlocks the region of a page.
*
@ -356,32 +364,32 @@ extern Bool flashc_is_region_locked(unsigned int region);
* \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within
* the flash array;
* \arg <tt>< 0</tt>: the current page number.
* \param lock Whether to lock the region of the specified page: \c TRUE or
* \c FALSE.
* \param lock Whether to lock the region of the specified page: \c true or
* \c false.
*
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern void flashc_lock_page_region(int page_number, Bool lock);
extern void flashc_lock_page_region(int page_number, bool lock);
/*! \brief Locks or unlocks a region.
*
* \param region The region number: \c 0 to <tt>(AVR32_FLASHC_REGIONS - 1)</tt>.
* \param lock Whether to lock the specified region: \c TRUE or \c FALSE.
* \param lock Whether to lock the specified region: \c true or \c false.
*
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern void flashc_lock_region(unsigned int region, Bool lock);
extern void flashc_lock_region(unsigned int region, bool lock);
/*! \brief Locks or unlocks all regions.
*
* \param lock Whether to lock the regions: \c TRUE or \c FALSE.
* \param lock Whether to lock the regions: \c true or \c false.
*
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern void flashc_lock_all_regions(Bool lock);
extern void flashc_lock_all_regions(bool lock);
//! @}
@ -400,7 +408,7 @@ extern void flashc_lock_all_regions(Bool lock);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit);
extern bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit);
/*! \brief Reads a general-purpose fuse bit-field.
*
@ -415,7 +423,7 @@ extern Bool flashc_read_gp_fuse_bit(unsigned int gp_fuse_bit);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width);
extern uint64_t flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width);
/*! \brief Reads a general-purpose fuse byte.
*
@ -427,7 +435,7 @@ extern U64 flashc_read_gp_fuse_bitfield(unsigned int pos, unsigned int width);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte);
extern uint8_t flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte);
/*! \brief Reads all general-purpose fuses.
*
@ -437,14 +445,14 @@ extern U8 flashc_read_gp_fuse_byte(unsigned int gp_fuse_byte);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern U64 flashc_read_all_gp_fuses(void);
extern uint64_t flashc_read_all_gp_fuses(void);
/*! \brief Erases a general-purpose fuse bit.
*
* \param gp_fuse_bit The general-purpose fuse bit: \c 0 to \c 63.
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if the Security bit is active and the command
@ -459,7 +467,7 @@ extern U64 flashc_read_all_gp_fuses(void);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check);
extern bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, bool check);
/*! \brief Erases a general-purpose fuse bit-field.
*
@ -467,9 +475,9 @@ extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check);
* \c 63.
* \param width The bit-width of the general-purpose fuse bit-field: \c 0 to
* \c 64.
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if the Security bit is active and the command
@ -484,14 +492,14 @@ extern Bool flashc_erase_gp_fuse_bit(unsigned int gp_fuse_bit, Bool check);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, Bool check);
extern bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width, bool check);
/*! \brief Erases a general-purpose fuse byte.
*
* \param gp_fuse_byte The general-purpose fuse byte: \c 0 to \c 7.
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if the Security bit is active.
@ -505,13 +513,13 @@ extern Bool flashc_erase_gp_fuse_bitfield(unsigned int pos, unsigned int width,
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check);
extern bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, bool check);
/*! \brief Erases all general-purpose fuses.
*
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if the Security bit is active.
@ -525,7 +533,7 @@ extern Bool flashc_erase_gp_fuse_byte(unsigned int gp_fuse_byte, Bool check);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern Bool flashc_erase_all_gp_fuses(Bool check);
extern bool flashc_erase_all_gp_fuses(bool check);
/*! \brief Writes a general-purpose fuse bit.
*
@ -538,13 +546,14 @@ extern Bool flashc_erase_all_gp_fuses(Bool check);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*
* \note The actual number of general-purpose fuse bits implemented by hardware
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);
extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, bool value);
/*! \brief Writes a general-purpose fuse bit-field.
*
@ -560,13 +569,14 @@ extern void flashc_write_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*
* \note The actual number of general-purpose fuse bits implemented by hardware
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value);
extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width, uint64_t value);
/*! \brief Writes a general-purpose fuse byte.
*
@ -578,13 +588,14 @@ extern void flashc_write_gp_fuse_bitfield(unsigned int pos, unsigned int width,
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*
* \note The actual number of general-purpose fuse bits implemented by hardware
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);
extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, uint8_t value);
/*! \brief Writes all general-purpose fuses.
*
@ -595,13 +606,14 @@ extern void flashc_write_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*
* \note The actual number of general-purpose fuse bits implemented by hardware
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_write_all_gp_fuses(U64 value);
extern void flashc_write_all_gp_fuses(uint64_t value);
/*! \brief Sets a general-purpose fuse bit with the appropriate erase and write
* operations.
@ -619,7 +631,7 @@ extern void flashc_write_all_gp_fuses(U64 value);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);
extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, bool value);
/*! \brief Sets a general-purpose fuse bit-field with the appropriate erase and
* write operations.
@ -640,7 +652,7 @@ extern void flashc_set_gp_fuse_bit(unsigned int gp_fuse_bit, Bool value);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U64 value);
extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, uint64_t value);
/*! \brief Sets a general-purpose fuse byte with the appropriate erase and write
* operations.
@ -657,7 +669,7 @@ extern void flashc_set_gp_fuse_bitfield(unsigned int pos, unsigned int width, U6
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);
extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, uint8_t value);
/*! \brief Sets all general-purpose fuses with the appropriate erase and write
* operations.
@ -673,7 +685,7 @@ extern void flashc_set_gp_fuse_byte(unsigned int gp_fuse_byte, U8 value);
* is given by \c AVR32_FLASHC_GPF_NUM. The other bits among the 64 are
* fixed at 1 by hardware.
*/
extern void flashc_set_all_gp_fuses(U64 value);
extern void flashc_set_all_gp_fuses(uint64_t value);
//! @}
@ -700,7 +712,7 @@ extern void flashc_clear_page_buffer(void);
* \return Whether the page to which the last Quick Page Read or Quick Page Read
* User Page command was applied was erased.
*/
extern Bool flashc_is_page_erased(void);
extern bool flashc_is_page_erased(void);
/*! \brief Applies the Quick Page Read command to a page.
*
@ -714,7 +726,7 @@ extern Bool flashc_is_page_erased(void);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern Bool flashc_quick_page_read(int page_number);
extern bool flashc_quick_page_read(int page_number);
/*! \brief Erases a page.
*
@ -722,9 +734,9 @@ extern Bool flashc_quick_page_read(int page_number);
* \arg \c 0 to <tt>(flashc_get_page_count() - 1)</tt>: a page number within
* the flash array;
* \arg <tt>< 0</tt>: the current page number.
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if the command is applied to a page belonging
@ -735,13 +747,13 @@ extern Bool flashc_quick_page_read(int page_number);
*
* \note An erase operation can only set bits.
*/
extern Bool flashc_erase_page(int page_number, Bool check);
extern bool flashc_erase_page(int page_number, bool check);
/*! \brief Erases all pages within the flash array.
*
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \warning A Lock Error is issued if at least one region is locked or the
@ -752,7 +764,7 @@ extern Bool flashc_erase_page(int page_number, Bool check);
*
* \note An erase operation can only set bits.
*/
extern Bool flashc_erase_all_pages(Bool check);
extern bool flashc_erase_all_pages(bool check);
/*! \brief Writes a page from the page buffer.
*
@ -769,7 +781,8 @@ extern Bool flashc_erase_all_pages(Bool check);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*/
extern void flashc_write_page(int page_number);
@ -780,13 +793,13 @@ extern void flashc_write_page(int page_number);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern Bool flashc_quick_user_page_read(void);
extern bool flashc_quick_user_page_read(void);
/*! \brief Erases the User page.
*
* \param check Whether to check erase: \c TRUE or \c FALSE.
* \param check Whether to check erase: \c true or \c false.
*
* \return Whether the erase succeeded or always \c TRUE if erase check was not
* \return Whether the erase succeeded or always \c true if erase check was not
* requested.
*
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
@ -794,7 +807,7 @@ extern Bool flashc_quick_user_page_read(void);
*
* \note An erase operation can only set bits.
*/
extern Bool flashc_erase_user_page(Bool check);
extern bool flashc_erase_user_page(bool check);
/*! \brief Writes the User page from the page buffer.
*
@ -803,26 +816,25 @@ extern Bool flashc_erase_user_page(Bool check);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*
* \note A write operation can only clear bits.
* \note A write operation can only clear bits; in other words, an erase operation
* must first be done if some bits need to be set to 1.
*/
extern void flashc_write_user_page(void);
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the repeated \a src source byte.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Source byte.
* \param nbytes Number of bytes to set.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -834,24 +846,21 @@ extern void flashc_write_user_page(void);
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes, Bool erase);
extern volatile void *flashc_memset8(volatile void *dst, uint8_t src, size_t nbytes, bool erase);
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the repeated \a src big-endian source half-word.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Source half-word.
* \param nbytes Number of bytes to set.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -863,24 +872,21 @@ extern volatile void *flashc_memset8(volatile void *dst, U8 src, size_t nbytes,
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes, Bool erase);
extern volatile void *flashc_memset16(volatile void *dst, uint16_t src, size_t nbytes, bool erase);
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the repeated \a src big-endian source word.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Source word.
* \param nbytes Number of bytes to set.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -892,24 +898,21 @@ extern volatile void *flashc_memset16(volatile void *dst, U16 src, size_t nbytes
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes, Bool erase);
extern volatile void *flashc_memset32(volatile void *dst, uint32_t src, size_t nbytes, bool erase);
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the repeated \a src big-endian source double-word.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Source double-word.
* \param nbytes Number of bytes to set.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -921,25 +924,22 @@ extern volatile void *flashc_memset32(volatile void *dst, U32 src, size_t nbytes
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes, Bool erase);
extern volatile void *flashc_memset64(volatile void *dst, uint64_t src, size_t nbytes, bool erase);
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the repeated \a src big-endian source pattern.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Source double-word.
* \param src_width \a src width in bits: 8, 16, 32 or 64.
* \param nbytes Number of bytes to set.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -952,27 +952,27 @@ extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes
* \ref flashc_is_programming_error is updated.
*/
#define flashc_memset(dst, src, src_width, nbytes, erase) \
TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase))
TPASTE2(flashc_memset, src_width)((dst), (src), (nbytes), (erase))
/*! \brief Copies \a nbytes bytes to the flash destination pointed to by \a dst
* from the source pointed to by \a src.
*
* The destination areas that are not within the flash array or the User page
* are ignored.
* The destination areas that are not within the flash
* array or the User page are caught by an Assert() operation.
*
* All pointer and size alignments are supported.
*
* \param dst Pointer to flash destination.
* \param src Pointer to source data.
* \param nbytes Number of bytes to copy.
* \param erase Whether to erase before writing: \c TRUE or \c FALSE.
* \param erase Whether to erase before writing: \c true or \c false.
*
* \return The value of \a dst.
*
* \warning If copying takes place between areas that overlap, the behavior is
* undefined.
*
* \warning This function may be called with \a erase set to \c FALSE only if
* \warning This function may be called with \a erase set to \c false only if
* the destination consists only of erased words, i.e. this function
* can not be used to write only one bit of a previously written word.
* E.g., if \c 0x00000001 then \c 0xFFFFFFFE are written to a word, the
@ -984,11 +984,11 @@ extern volatile void *flashc_memset64(volatile void *dst, U64 src, size_t nbytes
* \note The FLASHC error status returned by \ref flashc_is_lock_error and
* \ref flashc_is_programming_error is updated.
*/
extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, Bool erase);
extern volatile void *flashc_memcpy(volatile void *dst, const void *src, size_t nbytes, bool erase);
#if UC3C
/*! \brief Depednding to the CPU frequency, set the wait states of flash read
/*! \brief Depending to the CPU frequency, set the wait states of flash read
* accesses and enable or disable the High speed read mode.
*
* \param cpu_f_hz The CPU frequency
@ -998,5 +998,8 @@ void flashc_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz);
//! @}
/**
* \}
*/
#endif // _FLASHC_H_

842
bsp/avr32/software_framework/drivers/gpio/gpio.c Normal file
View File

@ -0,0 +1,842 @@
/*****************************************************************************
*
* \file
*
* \brief GPIO software driver interface for AVR UC3.
*
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "gpio.h"
/** \name Peripheral Bus Interface
*
* @{
*/
/** \brief Enables specific module modes for a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
uint32_t gpio_enable_module(const gpio_map_t gpiomap, uint32_t size)
{
uint32_t status = GPIO_SUCCESS;
uint32_t i;
for (i = 0; i < size; i++) {
status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
gpiomap++;
}
return status;
}
/** \brief Enables a specific module mode for a pin.
*
* \note A pin and pin function index can be found in the device part header
* file. The \c AVR32_*_PIN constants map a GPIO number from the device
* datasheet to the appropriate pin function, while the corresponding
* \c AVR32_*_FUNCTION macro contains the appropriate function index.
* \n\n
* For example, the constants \c AVR32_PWM_3_PIN and
* \c AVR32_PWM_3_FUNCTION contain the pin and function index of the PWM
* module, channel 3, for the current device (if available).
*
* \param pin The pin number.
* \param function The pin function.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
uint32_t gpio_enable_module_pin(uint32_t pin, uint32_t function)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Enable the correct function. */
switch (function) {
case 0: /* A function. */
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if (AVR32_GPIO_H_VERSION >= 210)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 1: /* B function. */
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if (AVR32_GPIO_H_VERSION >= 210)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 2: /* C function. */
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if (AVR32_GPIO_H_VERSION >= 210)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 3: /* D function. */
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if (AVR32_GPIO_H_VERSION >= 210)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
#if (AVR32_GPIO_H_VERSION >= 210)
case 4: /* E function. */
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 5: /* F function. */
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 6: /* G function. */
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 7: /* H function. */
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
#endif
default:
return GPIO_INVALID_ARGUMENT;
}
/* Disable GPIO control. */
gpio_port->gperc = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
/** \brief Enables the GPIO mode of a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*/
void gpio_enable_gpio(const gpio_map_t gpiomap, uint32_t size)
{
uint32_t i;
for (i = 0; i < size; i++) {
gpio_enable_gpio_pin(gpiomap->pin);
gpiomap++;
}
}
/** \brief Enables the GPIO mode of a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for pin definitions. E.g., to enable the
* GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
* AVR32_PWM_3_PIN for PWM channel 3 can also be used to release
* module pins for GPIO.
*/
void gpio_enable_gpio_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F);
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Enables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_pull_up(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
gpio_port->pderc = 1 << (pin & 0x1F);
#endif
}
/** \brief Disables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_pull_up(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
}
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
/* Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control. */
/** \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_pull_down(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/** \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_pull_down(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->pderc = 1 << (pin & 0x1F);
}
/** \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_buskeeper(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/** \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_buskeeper(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pderc = 1 << (pin & 0x1F);
}
#endif
/** \brief Configuration functionality on a pin.
*
* \param pin The pin number.
* \param flags The configuration.
*/
void gpio_configure_pin(uint32_t pin, uint32_t flags)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Both pull-up and pull-down set means buskeeper */
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
if (flags & GPIO_PULL_DOWN) {
gpio_port->pders = 1 << (pin & 0x1F);
} else {
gpio_port->pderc = 1 << (pin & 0x1F);
}
#endif
if (flags & GPIO_PULL_UP) {
gpio_port->puers = 1 << (pin & 0x1F);
} else {
gpio_port->puerc = 1 << (pin & 0x1F);
}
/* Enable open-drain mode if requested */
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
if (flags & GPIO_OPEN_DRAIN) {
gpio_port->odmers = 1 << (pin & 0x1F);
} else {
gpio_port->odmerc = 1 << (pin & 0x1F);
}
#endif
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
/* Select drive strength */
if (flags & GPIO_DRIVE_LOW) {
gpio_port->odcr0s = 1 << (pin & 0x1F);
} else {
gpio_port->odcr0c = 1 << (pin & 0x1F);
}
if (flags & GPIO_DRIVE_HIGH) {
gpio_port->odcr1s = 1 << (pin & 0x1F);
} else {
gpio_port->odcr1c = 1 << (pin & 0x1F);
}
#endif
/* Select interrupt level for group */
if (flags & GPIO_INTERRUPT) {
if (flags & GPIO_BOTHEDGES) {
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
} else if (flags & GPIO_RISING) {
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
} else if (flags & GPIO_FALLING) {
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
}
}
/* Select direction and initial pin state */
if (flags & GPIO_DIR_OUTPUT) {
if (flags & GPIO_INIT_HIGH) {
gpio_port->ovrs = 1 << (pin & 0x1F);
} else {
gpio_port->ovrc = 1 << (pin & 0x1F);
}
gpio_port->oders = 1 << (pin & 0x1F);
} else {
gpio_port->oderc = 1 << (pin & 0x1F);
}
/* Enable GPIO */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Configuration functionality on a port.
*
* \param port The port number.
* \param mask The mask.
* \param flags The configuration.
*/
void gpio_configure_group(uint32_t port, uint32_t mask, uint32_t flags)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[port];
/* Both pull-up and pull-down set means buskeeper */
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
if (flags & GPIO_PULL_DOWN) {
gpio_port->pders = mask;
} else {
gpio_port->pderc = mask;
}
#endif
if (flags & GPIO_PULL_UP) {
gpio_port->puers = mask;
} else {
gpio_port->puerc = mask;
}
/* Enable open-drain mode if requested */
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
if (flags & GPIO_OPEN_DRAIN) {
gpio_port->odmers = mask;
} else {
gpio_port->odmerc = mask;
}
if (flags & GPIO_OPEN_DRAIN) {
gpio_port->pders = mask;
} else {
gpio_port->pderc = mask;
}
#endif
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
/* Select drive strength */
if (flags & GPIO_DRIVE_LOW) {
gpio_port->odcr0s = mask;
} else {
gpio_port->odcr0c = mask;
}
if (flags & GPIO_DRIVE_HIGH) {
gpio_port->odcr1s = mask;
} else {
gpio_port->odcr1c = mask;
}
#endif
/* Select interrupt level for group */
if (flags & GPIO_INTERRUPT) {
if (flags & GPIO_BOTHEDGES) {
gpio_port->imr0c = mask;
gpio_port->imr1c = mask;
} else if (flags & GPIO_RISING) {
gpio_port->imr0s = mask;
gpio_port->imr1c = mask;
} else if (flags & GPIO_FALLING) {
gpio_port->imr0c = mask;
gpio_port->imr1s = mask;
}
}
/* Select direction and initial pin state */
if (flags & GPIO_DIR_OUTPUT) {
if (flags & GPIO_INIT_HIGH) {
gpio_port->ovrs = mask;
} else {
gpio_port->ovrc = mask;
}
gpio_port->oders = mask;
} else {
gpio_port->oderc = mask;
}
/* Enable GPIO */
gpio_port->gpers = mask;
}
/** \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*/
bool gpio_get_pin_value(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
return (gpio_port->pvr >> (pin & 0x1F)) & 1;
}
/** \brief Returns the output value set for a GPIO pin.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with \ref gpio_set_gpio_pin,
* \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin.
*/
bool gpio_get_gpio_pin_output_value(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
return (gpio_port->ovr >> (pin & 0x1F)) & 1;
}
/** \brief Returns the output value set for a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with
* \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin
* and \ref gpio_tgl_gpio_open_drain_pin.
*/
bool gpio_get_gpio_open_drain_pin_output_value(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;
}
/** \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*/
void gpio_set_gpio_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line: 1. */
gpio_port->ovrs = 1 << (pin & 0x1F);
/* The GPIO output driver is enabled for that pin. */
gpio_port->oders = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*
* \note The function \ref gpio_configure_pin must be called before.
*/
void gpio_set_pin_high(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line: 1. */
gpio_port->ovrs = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO port to 1.
*
* \param port The port number.
* \param mask The mask.
*/
void gpio_set_group_high(uint32_t port, uint32_t mask)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[port];
/* Value to be driven on the I/O group: 1. */
gpio_port->ovrs = mask;
}
/** \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*
* \note The function \ref gpio_configure_pin must be called before.
*/
void gpio_set_pin_low(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line: 0. */
gpio_port->ovrc = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*/
void gpio_clr_gpio_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line: 0. */
gpio_port->ovrc = 1 << (pin & 0x1F);
/* The GPIO output driver is enabled for that pin. */
gpio_port->oders = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO port to 0.
*
* \param port The port number.
* \param mask The mask.
*/
void gpio_set_group_low(uint32_t port, uint32_t mask)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[port];
/* Value to be driven on the I/O group: 0. */
gpio_port->ovrc = mask;
}
/** \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*/
void gpio_tgl_gpio_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Toggle the I/O line. */
gpio_port->ovrt = 1 << (pin & 0x1F);
/* The GPIO output driver is enabled for that pin. */
gpio_port->oders = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*
* \note The function \ref gpio_configure_pin must be called before.
*/
void gpio_toggle_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Toggle the I/O line. */
gpio_port->ovrt = 1 << (pin & 0x1F);
}
/** \brief Toggles a GPIO group.
*
* \param port The port number.
* \param mask The mask.
*/
void gpio_toggle_group(uint32_t port, uint32_t mask)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[port];
/* Toggle the I/O port. */
gpio_port->ovrt = mask;
}
/** \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*/
void gpio_set_gpio_open_drain_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* The GPIO output driver is disabled for that pin. */
gpio_port->oderc = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*/
void gpio_clr_gpio_open_drain_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line: 0. */
gpio_port->ovrc = 1 << (pin & 0x1F);
/* The GPIO output driver is enabled for that pin. */
gpio_port->oders = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*/
void gpio_tgl_gpio_open_drain_pin(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Value to be driven on the I/O line if the GPIO output driver is
* enabled: 0. */
gpio_port->ovrc = 1 << (pin & 0x1F);
/* The GPIO output driver is toggled for that pin. */
gpio_port->odert = 1 << (pin & 0x1F);
/* The GPIO module controls that pin. */
gpio_port->gpers = 1 << (pin & 0x1F);
}
/** \brief Enables the glitch filter of a pin.
*
* When the glitch filter is enabled, a glitch with duration of less than 1
* clock cycle is automatically rejected, while a pulse with duration of 2 clock
* cycles or more is accepted. For pulse durations between 1 clock cycle and 2
* clock cycles, the pulse may or may not be taken into account, depending on
* the precise timing of its occurrence. Thus for a pulse to be guaranteed
* visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
* filtered out, its duration must not exceed 1 clock cycle. The filter
* introduces 2 clock cycles latency.
*
* \param pin The pin number.
*/
void gpio_enable_pin_glitch_filter(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->gfers = 1 << (pin & 0x1F);
}
/** \brief Disables the glitch filter of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_glitch_filter(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->gferc = 1 << (pin & 0x1F);
}
/** \brief Configure the edge detector of an input pin
*
* \param pin The pin number.
* \param mode The edge detection mode (\ref GPIO_PIN_CHANGE,
* \ref GPIO_RISING_EDGE or \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
static uint32_t gpio_configure_edge_detector(uint32_t pin, uint32_t mode)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Configure the edge detector. */
switch (mode) {
case GPIO_PIN_CHANGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_RISING_EDGE:
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_FALLING_EDGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
return GPIO_SUCCESS;
}
/** \brief Enables the interrupt of a pin with the specified settings.
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
uint32_t gpio_enable_pin_interrupt(uint32_t pin, uint32_t mode)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
/* Enable the glitch filter. */
gpio_port->gfers = 1 << (pin & 0x1F);
/* Configure the edge detector. */
if (GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode)) {
return(GPIO_INVALID_ARGUMENT);
}
/* Enable interrupt. */
gpio_port->iers = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
/** \brief Disables the interrupt of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_interrupt(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
gpio_port->ierc = 1 << (pin & 0x1F);
}
/** \brief Gets the interrupt flag of a pin.
*
* \param pin The pin number.
*
* \return The pin interrupt flag.
*/
bool gpio_get_pin_interrupt_flag(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
return (gpio_port->ifr >> (pin & 0x1F)) & 1;
}
/** \brief Clears the interrupt flag of a pin.
*
* \param pin The pin number.
*/
void gpio_clear_pin_interrupt_flag(uint32_t pin)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
#if (AVR32_GPIO_H_VERSION == 211)
/* GPIO erratum - Writing a one to the GPIO.IFRC register */
/* to clear an interrupt will be ignored if interrupt is enabled for the */
/* corresponding port. */
/* Work around for the erratum - Disable the interrupt, clear it by
* writing */
/* a one to GPIO.IFRC, then enable the interrupt. */
/* Save interrupt enable register. */
uint32_t const gpio_ier = gpio_port->ier;
/* Disable interrupt. */
gpio_port->ierc = gpio_ier;
/* Clear pin interrupt. */
gpio_port->ifrc = 1 << (pin & 0x1F);
/* Restore interrupt enable register. */
gpio_port->ier = gpio_ier;
#else
gpio_port->ifrc = 1 << (pin & 0x1F);
#endif
}
#if UC3L
/** \brief Configure the peripheral event trigger mode of a pin
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
* \param use_igf use the Input Glitch Filter (true) or not (false).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
uint32_t gpio_configure_pin_periph_event_mode(uint32_t pin, uint32_t mode,
uint32_t use_igf)
{
volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[pin >> 5];
if (true == use_igf) {
/* Enable the glitch filter. */
gpio_port->gfers = 1 << (pin & 0x1F);
} else {
/* Disable the glitch filter. */
gpio_port->gferc = 1 << (pin & 0x1F);
}
/* Configure the edge detector. */
return gpio_configure_edge_detector(pin, mode);
}
#endif
/** @} */

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/*****************************************************************************
*
* \file
*
* \brief GPIO software driver interface for AVR UC3.
*
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _GPIO_H_
#define _GPIO_H_
/**
* \defgroup group_avr32_drivers_gpio GPIO - General-Purpose Input/Output
*
* GPIO gives access to the MCU pins.
*
* @{
*/
#include <avr32/io.h>
#include "compiler.h"
/** \name Return Values of the GPIO API
* @{ */
#define GPIO_SUCCESS 0 /**< Function successfully completed. */
#define GPIO_INVALID_ARGUMENT 1 /**< Input parameters are out of range. */
/** @} */
/** \name Interrupt Trigger Modes
* @{ */
#define GPIO_PIN_CHANGE 0 /**< Interrupt triggered upon pin change. */
#define GPIO_RISING_EDGE 1 /**< Interrupt triggered upon rising edge. */
#define GPIO_FALLING_EDGE 2 /**< Interrupt triggered upon falling edge. */
/** @} */
/** \name Common defines for GPIO_FLAGS parameter
* @{ */
#define GPIO_DIR_INPUT (0 << 0) /**< Pin is Input */
#define GPIO_DIR_OUTPUT (1 << 0) /**< Pin is Output */
#define GPIO_INIT_LOW (0 << 1) /**< Initial Output State is Low */
#define GPIO_INIT_HIGH (1 << 1) /**< Initial Output State is High */
#define GPIO_PULL_UP (1 << 2) /**< Pull-Up (when input) */
#define GPIO_PULL_DOWN (2 << 2) /**< Pull-Down (when input) */
#define GPIO_BUSKEEPER (3 << 2) /**< Bus Keeper */
#define GPIO_DRIVE_MIN (0 << 4) /**< Drive Min Configuration */
#define GPIO_DRIVE_LOW (1 << 4) /**< Drive Low Configuration */
#define GPIO_DRIVE_HIGH (2 << 4) /**< Drive High Configuration */
#define GPIO_DRIVE_MAX (3 << 4) /**< Drive Max Configuration */
#define GPIO_OPEN_DRAIN (1 << 6) /**< Open-Drain (when output) */
#define GPIO_INTERRUPT (1 << 7) /**< Enable Pin/Group Interrupt */
#define GPIO_BOTHEDGES (3 << 7) /**< Sense Both Edges */
#define GPIO_RISING (5 << 7) /**< Sense Rising Edge */
#define GPIO_FALLING (7 << 7) /**< Sense Falling Edge */
/** @} */
/** A type definition of pins and modules connectivity. */
typedef struct {
uint32_t pin; /**< Module pin. */
uint32_t function; /**< Module function. */
} gpio_map_t[];
/** \name Peripheral Bus Interface
*
* Low-speed interface with a non-deterministic number of clock cycles per
* access.
*
* This interface operates with lower clock frequencies (fPB <= fCPU), and its
* timing is not deterministic since it needs to access a shared bus which may
* be heavily loaded.
*
* \note This interface is immediately available without initialization.
*
* @{
*/
uint32_t gpio_enable_module(const gpio_map_t gpiomap, uint32_t size);
uint32_t gpio_enable_module_pin(uint32_t pin, uint32_t function);
void gpio_enable_gpio(const gpio_map_t gpiomap, uint32_t size);
void gpio_enable_gpio_pin(uint32_t pin);
void gpio_enable_pin_pull_up(uint32_t pin);
void gpio_disable_pin_pull_up(uint32_t pin);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || \
defined(AVR32_GPIO_212_H_INCLUDED)
void gpio_enable_pin_pull_down(uint32_t pin);
void gpio_disable_pin_pull_down(uint32_t pin);
void gpio_enable_pin_buskeeper(uint32_t pin);
void gpio_disable_pin_buskeeper(uint32_t pin);
#endif
void gpio_configure_pin(uint32_t pin, uint32_t flags);
void gpio_configure_group(uint32_t port, uint32_t mask, uint32_t flags);
bool gpio_get_pin_value(uint32_t pin);
/**
* \brief Check if the pin is in low logical level.
*
* \param pin The pin number.
* \return bool \c true if the pin is in low logical level
* \c false if the pin is not in low logical level
*/
__always_inline static bool gpio_pin_is_low(uint32_t pin)
{
return (gpio_get_pin_value(pin) == 0);
}
/**
* \brief Check if the pin is in high logical level.
*
* \param pin The pin number.
* \return bool \c true if the pin is in high logical level
* \c false if the pin is not in high logical level
*/
__always_inline static bool gpio_pin_is_high(uint32_t pin)
{
return (gpio_get_pin_value(pin) != 0);
}
bool gpio_get_gpio_pin_output_value(uint32_t pin);
bool gpio_get_gpio_open_drain_pin_output_value(uint32_t pin);
void gpio_set_gpio_pin(uint32_t pin);
void gpio_set_pin_high(uint32_t pin);
void gpio_set_group_high(uint32_t port, uint32_t mask);
void gpio_clr_gpio_pin(uint32_t pin);
void gpio_set_pin_low(uint32_t pin);
void gpio_set_group_low(uint32_t port, uint32_t mask);
void gpio_tgl_gpio_pin(uint32_t pin);
void gpio_toggle_pin(uint32_t pin);
void gpio_toggle_group(uint32_t port, uint32_t mask);
void gpio_set_gpio_open_drain_pin(uint32_t pin);
void gpio_clr_gpio_open_drain_pin(uint32_t pin);
void gpio_tgl_gpio_open_drain_pin(uint32_t pin);
void gpio_enable_pin_glitch_filter(uint32_t pin);
void gpio_disable_pin_glitch_filter(uint32_t pin);
uint32_t gpio_enable_pin_interrupt(uint32_t pin, uint32_t mode);
void gpio_disable_pin_interrupt(uint32_t pin);
bool gpio_get_pin_interrupt_flag(uint32_t pin);
void gpio_clear_pin_interrupt_flag(uint32_t pin);
/** @} */
#if (defined AVR32_GPIO_LOCAL_ADDRESS) || defined(__DOXYGEN__)
/** \name Local Bus Interface
*
* High-speed interface with only one clock cycle per access.
*
* This interface operates with high clock frequency (fCPU), and its timing is
* deterministic since it does not need to access a shared bus which may be
* heavily loaded.
*
* \warning To use this interface, the clock frequency of the peripheral bus on
* which the GPIO peripheral is connected must be set to the CPU clock
* frequency (fPB = fCPU).
*
* \note This interface has to be initialized in order to be available.
*
* @{
*/
/** \brief Enables the local bus interface for GPIO.
*
* \note This function must have been called at least once before using other
* functions in this interface.
*/
__always_inline static void gpio_local_init(void)
{
Set_system_register(AVR32_CPUCR,
Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
}
/** \brief Enables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
__always_inline static void gpio_local_enable_pin_output_driver(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/** \brief Disables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
__always_inline static void gpio_local_disable_pin_output_driver(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/** \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
__always_inline static bool gpio_local_get_pin_value(uint32_t pin)
{
return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
}
/** \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
__always_inline static void gpio_local_set_gpio_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
__always_inline static void gpio_local_clr_gpio_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/** \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
__always_inline static void gpio_local_tgl_gpio_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
}
/** \brief Initializes the configuration of a GPIO pin so that it can be used
* with GPIO open-drain functions.
*
* \note This function must have been called at least once before using
* \ref gpio_local_set_gpio_open_drain_pin,
* \ref gpio_local_clr_gpio_open_drain_pin or
* \ref gpio_local_tgl_gpio_open_drain_pin.
*/
__always_inline static void gpio_local_init_gpio_open_drain_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
__always_inline static void gpio_local_set_gpio_open_drain_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/** \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
__always_inline static void gpio_local_clr_gpio_open_drain_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/** \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
__always_inline static void gpio_local_tgl_gpio_open_drain_pin(uint32_t pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);
}
/** @} */
#endif /* AVR32_GPIO_LOCAL_ADDRESS */
#if UC3L
/** \name Peripheral Event System support
*
* The GPIO can be programmed to output peripheral events whenever an interrupt
* condition is detected, such as pin value change, or only when a rising or
* falling edge is detected.
*
* @{
*/
/** \brief Enables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
__always_inline static void gpio_enable_pin_periph_event(uint32_t pin)
{
AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); /* The GPIO output
* driver is
* disabled for
* that pin. */
AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);
}
/** \brief Disables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
__always_inline static void gpio_disable_pin_periph_event(uint32_t pin)
{
AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);
}
uint32_t gpio_configure_pin_periph_event_mode(uint32_t pin, uint32_t mode,
uint32_t use_igf);
/** @} */
#endif
/** @} */
#endif /* _GPIO_H_ */

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/**
* \file
*
* \brief INTC software driver for AVR UC3 devices.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
/**
* \internal
* \brief Import the _evba symbol from exception.S
*/
extern void _evba;
/**
* \internal
* \brief Import the symbols _int0, _int1, _int2, _int3 defined in exception.S
*/
extern void _int0, _int1, _int2, _int3;
/**
* \internal
* \brief Values to store in the interrupt priority registers for the various
* interrupt priority levels.
*/
#define IPR_INT0 ((AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
| ((int)&_int0 - (int)&_evba))
#define IPR_INT1 ((AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
| ((int)&_int1 - (int)&_evba))
#define IPR_INT2 ((AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
| ((int)&_int2 - (int)&_evba))
#define IPR_INT3 ((AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) \
| ((int)&_int3 - (int)&_evba))
/**
* \internal
* \brief Table of interrupt line handlers per interrupt group in order to
* optimize RAM space. Each line handler table contains a set of pointers to
* interrupt handlers.
*/
#if (defined __GNUC__)
# define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler \
_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#elif (defined __ICCAVR32__)
# define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __no_init __int_handler \
_int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#endif
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
/**
* \internal
* \brief Table containing for each interrupt group the number of interrupt
* request lines and a pointer to the table of interrupt line handlers.
*/
static const struct
{
unsigned int num_irqs;
volatile __int_handler *_int_line_handler_table;
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
{
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
#undef INSERT_INT_LINE_HANDLER_TABLE
};
/**
* \internal
* \brief Default interrupt handler.
*/
#if (defined __GNUC__)
__attribute__((__interrupt__))
#elif (defined __ICCAVR32__)
__interrupt
#endif
static void _unhandled_interrupt(void)
{
// Catch unregistered interrupts.
while (true);
}
/**
* \brief Gets the interrupt handler of the current event at the \a int_level
* interrupt priority level (called from exception.S).
*
* \param int_level Interrupt priority level to handle.
*
* \return Interrupt handler to execute.
*/
__int_handler _get_interrupt_handler(uint32_t int_level);
__int_handler _get_interrupt_handler(uint32_t int_level)
{
/* ICR3 is mapped first, ICR0 last.
Code in exception.S puts int_level in R12 which is used by the compiler
to pass a single argument to a function. */
uint32_t int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
uint32_t int_req = AVR32_INTC.irr[int_grp];
/* As an interrupt may disappear while it is being fetched by the CPU
(spurious interrupt caused by a delayed response from an MCU peripheral
to an interrupt flag clear or interrupt disable instruction), check if
there are remaining interrupt lines to process.
If a spurious interrupt occurs, the status register (SR) contains an
execution mode and interrupt level masks corresponding to a level 0
interrupt, whatever the interrupt priority level causing the spurious
event. This behavior has been chosen because a spurious interrupt has
not to be a priority one and because it may not cause any trouble to
other interrupts.
However, these spurious interrupts place the hardware in an unstable
state and could give problems in other/future versions of the CPU, so
the software has to be written so that they never occur. The only safe
way of achieving this is to always clear or disable peripheral
interrupts with the following sequence:
1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
2: Perform the bus access to the peripheral register that clears or
disables the interrupt.
3: Wait until the interrupt has actually been cleared or disabled by the
peripheral. This is usually performed by reading from a register in the
same peripheral (it DOES NOT have to be the same register that was
accessed in step 2, but it MUST be in the same peripheral), what takes
bus system latencies into account, but peripheral internal latencies
(generally 0 cycle) also have to be considered.
4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
Note that steps 1 and 4 are useless inside interrupt handlers as the
corresponding interrupt level is automatically masked by IxM (unless IxM
is explicitly cleared by the software).*/
/* Get the right IRQ handler.
If several interrupt lines are active in the group, the interrupt line
with the highest number is selected. This is to be coherent with the
prioritization of interrupt groups performed by the hardware interrupt
controller.
If no handler has been registered for the pending interrupt,
_unhandled_interrupt will be selected thanks to the initialization of
_int_line_handler_table_x by INTC_init_interrupts.
exception.S will provide the interrupt handler with a clean interrupt
stack frame, with nothing more pushed onto the stack. The interrupt
handler must manage the `rete' instruction, which can be done using
pure assembly, inline assembly or the `__attribute__((__interrupt__))'
C function attribute.*/
return (int_req)
? _int_handler_table[int_grp]._int_line_handler_table[32
- clz(int_req) - 1]
: NULL;
}
/**
* \internal
* \brief Init EVBA address. This operation may or may not have been done by the
* C startup process.
*/
static __inline__ void INTC_init_evba(void)
{
Set_system_register(AVR32_EVBA, (int32_t)&_evba );
}
/**
* \brief Initializes the hardware interrupt controller driver.
*
*/
void INTC_init_interrupts(void)
{
uint32_t int_grp, int_req;
INTC_init_evba();
// For all interrupt groups,
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
{
// For all interrupt request lines of each group,
for (int_req = 0;
int_req < _int_handler_table[int_grp].num_irqs;
int_req++)
{
/* Assign _unhandled_interrupt as the default interrupt
handler. */
_int_handler_table[int_grp]
._int_line_handler_table[int_req]
= &_unhandled_interrupt;
}
/* Set the interrupt group priority register to its default
value.
By default, all interrupt groups are linked to the interrupt
priority level 0 and to the interrupt vector _int0. */
AVR32_INTC.ipr[int_grp] = IPR_INT0;
}
}
/**
* \brief Registers an interrupt handler.
*
* \param handler Interrupt handler to register.
* \param irq IRQ of the interrupt handler to register.
* \param int_level Interrupt priority level to assign to the group of this IRQ.
*
* \warning The interrupt handler must manage the `rete' instruction, which can
* be done using pure assembly, inline assembly or the
* `__attribute__((__interrupt__))' C function attribute.
*
* \warning If several interrupt handlers of a same group are registered with
* different priority levels, only the latest priority level set will
* be effective.
*
*/
void INTC_register_interrupt(__int_handler handler, uint32_t irq,
uint32_t int_level)
{
// Determine the group of the IRQ.
uint32_t int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
/* Store in _int_line_handler_table_x the pointer to the interrupt
handler, so that _get_interrupt_handler can retrieve it when the
interrupt is vectored. */
_int_handler_table[int_grp]
._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP]
= handler;
/* Program the corresponding IPRX register to set the interrupt priority
level and the interrupt vector offset that will be fetched by the core
interrupt system.
NOTE: The _intx functions are intermediate assembly functions between
the core interrupt system and the user interrupt handler. */
if (int_level == AVR32_INTC_INT0) {
AVR32_INTC.ipr[int_grp] = IPR_INT0;
} else if (int_level == AVR32_INTC_INT1) {
AVR32_INTC.ipr[int_grp] = IPR_INT1;
} else if (int_level == AVR32_INTC_INT2) {
AVR32_INTC.ipr[int_grp] = IPR_INT2;
} else {
AVR32_INTC.ipr[int_grp] = IPR_INT3;
}
}

77
bsp/avr32/software_framework/drivers/intc/intc.h Normal file
View File

@ -0,0 +1,77 @@
/**
* \file
*
* \brief INTC software driver API for AVR UC3 devices.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _INTC_H_
#define _INTC_H_
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup intc_group INTC Software Driver API for AVR UC3
*
* This is a software module to register interrupt handlers at any specified
* interrupt level to any interrupt line managed by the INTC module in AVR UC3
* devices.
* @{
*/
//! Maximal number of interrupt request lines per group.
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
//! Number of interrupt priority levels.
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
#ifdef __AVR32_ABI_COMPILER__
// (Automatically defined when compiling for AVR UC3, not when assembling).
extern void INTC_init_interrupts(void);
extern void INTC_register_interrupt(__int_handler handler, uint32_t irq,
uint32_t int_level);
#endif // __AVR32_ABI_COMPILER__
//! @}
#ifdef __cplusplus
}
#endif
#endif // _INTC_H_

96
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c → bsp/avr32/software_framework/drivers/pm/pm.c
View File

@ -1,51 +1,41 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief Power Manager driver.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "compiler.h"
#include "pm.h"
@ -326,6 +316,21 @@ void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
}
void pm_cksel_get(volatile avr32_pm_t *pm, unsigned long *p_cksel)
{
*p_cksel = pm->cksel;
}
void pm_cksel_set(volatile avr32_pm_t *pm, unsigned long cksel)
{
pm->cksel = cksel;
// Wait for ckrdy bit and then clear it
while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
}
void pm_cksel(volatile avr32_pm_t *pm,
unsigned int pbadiv,
unsigned int pbasel,
@ -447,6 +452,13 @@ void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
}
unsigned long pm_get_clock(volatile avr32_pm_t *pm)
{
u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
return u_avr32_pm_mcctrl.MCCTRL.mcsel;
}
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
{
// Read
@ -474,12 +486,12 @@ void pm_bod_enable_irq(volatile avr32_pm_t *pm)
void pm_bod_disable_irq(volatile avr32_pm_t *pm)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
bool global_interrupt_enabled = cpu_irq_is_enabled();
if (global_interrupt_enabled) Disable_global_interrupt();
if (global_interrupt_enabled) cpu_irq_disable();
pm->idr = AVR32_PM_IDR_BODDET_MASK;
pm->isr;
if (global_interrupt_enabled) Enable_global_interrupt();
if (global_interrupt_enabled) cpu_irq_enable();
}

142
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h → bsp/avr32/software_framework/drivers/pm/pm.h
View File

@ -1,59 +1,61 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief Power Manager driver.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _PM_H_
#define _PM_H_
/**
* \defgroup group_avr32_drivers_pm CPU - PM - Power Manager
*
* The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device.
*
* \{
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
/*! \name Sleep Functions
*/
//! @{
/*! \brief Sets the MCU in the specified sleep mode.
*
* \param mode Sleep mode:
@ -66,6 +68,30 @@
*/
#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
/*! \brief Enable one or several asynchronous wake-up source.
*
* \param awen_mask Mask of asynchronous wake-up sources (use one of the defines
* AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under
* "toolchain folder"/avr32/inc(lude)/avr32/)
*/
__always_inline static void pm_asyn_wake_up_enable(unsigned long awen_mask)
{
AVR32_PM.awen |= awen_mask;
}
/*! \brief Disable one or several asynchronous wake-up sources
*
* \param awen_mask Mask of asynchronous wake-up sources (use one of the defines
* AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under
* "toolchain folder"/avr32/inc(lude)/avr32/)
*/
__always_inline static void pm_asyn_wake_up_disable(unsigned long awen_mask)
{
AVR32_PM.awen &= ~awen_mask;
}
//! @}
//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
typedef struct
@ -94,10 +120,7 @@ typedef struct
* \return The MCU reset cause which can be masked with the
* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
__always_inline static unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
{
return pm->rcause;
}
@ -285,7 +308,7 @@ extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
* \param mul PLL MUL in the PLL formula
* \param div PLL DIV in the PLL formula
* \param osc OSC number (0 for osc0, 1 for osc1)
* \param lockcount PLL lockount
* \param lockcount PLL lock count
*/
extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
@ -340,6 +363,30 @@ extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
/*!
* \brief This function returns the cksel (Clock Select).
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param p_cksel output cksel value
*/
extern void pm_cksel_get(volatile avr32_pm_t *pm, unsigned long* p_cksel);
/*!
* \brief This function set the cksel (Clock Select).
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \param cksel The cksel value.
*/
extern void pm_cksel_set(volatile avr32_pm_t *pm, unsigned long cksel);
/*!
* \brief This function returns the power manager main clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
* \retval The main clock value.
*/
extern unsigned long pm_get_clock(volatile avr32_pm_t *pm);
/*!
* \brief This function will switch the power manager main clock.
* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
@ -436,7 +483,7 @@ extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
@ -449,7 +496,7 @@ extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
@ -489,5 +536,8 @@ extern int pm_configure_clocks(pm_freq_param_t *param);
*/
extern void pm_configure_usb_clock(void);
/**
* \}
*/
#endif // _PM_H_

78
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c → bsp/avr32/software_framework/drivers/pm/pm_conf_clocks.c
View File

@ -1,51 +1,41 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief Power Manager clocks configuration helper.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include <string.h>
#include "compiler.h"
#include "pm.h"
@ -79,7 +69,7 @@ int pm_configure_clocks(pm_freq_param_t *param)
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
Bool b_div2_pba, b_div2_cpu;
bool b_div2_pba, b_div2_cpu;
// Switch to external Oscillator 0
pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
@ -179,19 +169,19 @@ int pm_configure_clocks(pm_freq_param_t *param)
if (div2_cpu)
{
b_div2_cpu = TRUE;
b_div2_cpu = true;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
b_div2_cpu = false;
if (div2_pba)
{
b_div2_pba = TRUE;
b_div2_pba = true;
div2_pba--;
}
else
b_div2_pba = FALSE;
b_div2_pba = false;
pm_cksel(&AVR32_PM
, b_div2_pba, div2_pba // PBA

294
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c → bsp/avr32/software_framework/drivers/pm/power_clocks_lib.c
View File

@ -1,52 +1,42 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief High-level library abstracting features such as oscillators/pll/dfll
* configuration, clock configuration, System-sensible parameters
* configuration, buses clocks configuration, sleep mode, reset.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "power_clocks_lib.h"
@ -59,15 +49,24 @@ static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD d
static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration
#endif
#if UC3D
static long int pcl_configure_clocks_uc3d(pcl_freq_param_t *param); // FORWARD declaration
#endif
long int pcl_configure_clocks(pcl_freq_param_t *param)
{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
return(pm_configure_clocks(param));
#else
#ifdef AVR32_PM_410_H_INCLUDED
// Implementation for UC3C parts.
return(pcl_configure_clocks_uc3c(param));
#if (defined AVR32_PM_410_H_INCLUDED ) || (defined AVR32_PM_412_H_INCLUDED )
#if UC3D
// Implementation for UC3D parts.
return(pcl_configure_clocks_uc3d(param));
#else
// Implementation for UC3C parts.
return(pcl_configure_clocks_uc3c(param));
#endif
#else
// Implementation for UC3L parts.
return(pcl_configure_clocks_uc3l(param));
@ -211,7 +210,7 @@ long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
// Implementation note: this implementation configures the DFLL in closed-loop
// mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
// as a reference (RCSYS being used as the generic clock source, undivided).
scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, true);
return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
}
@ -297,6 +296,170 @@ static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
#define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
#define AVR32_PM_PBA_MAX_FREQ 66000000
#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
// Implementation for UC3C parts.
// Supported frequencies:
// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
// 12 15 1 192 1 12 12
// 12 9 3 40 1 20 20 PLL out of spec
// 12 15 1 192 1 24 12
// 12 9 1 120 1 30 15
// 12 9 3 40 0 40 20 PLL out of spec
// 12 15 1 192 1 48 12
// 12 15 1 192 1 48 24
// 12 8 1 108 1 54 27
// 12 9 1 120 1 60 15
// 12 9 1 120 1 60 30
// 12 10 1 132 1 66 16.5
//
unsigned long in_cpu_f = param->cpu_f;
unsigned long in_osc0_f = param->osc0_f;
unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
unsigned long pll_freq, rest;
bool b_div2_pba, b_div2_cpu;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Start with CPU freq config
if (in_cpu_f == in_osc0_f)
{
param->cpu_f = in_osc0_f;
param->pba_f = in_osc0_f;
return PASS;
}
else if (in_cpu_f < in_osc0_f)
{
// TBD
}
rest = in_cpu_f % in_osc0_f;
for (div = 1; div < 32; div++)
{
if ((div * rest) % in_osc0_f == 0)
break;
}
if (div == 32)
return FAIL;
mul = (in_cpu_f * div) / in_osc0_f;
if (mul > PM_MAX_MUL)
return FAIL;
// export 2power from PLL div to div2_cpu
while (!(div % 2))
{
div /= 2;
div2_cpu++;
}
// Here we know the mul and div parameter of the PLL config.
// . Check out if the PLL has a valid in_cpu_f.
// . Try to have for the PLL frequency (VCO output) the highest possible value
// to reduce jitter.
while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
{
if (2 * mul > PM_MAX_MUL)
break;
mul *= 2;
div2_cpu++;
}
if (div2_cpu != 0)
{
div2_cpu--;
div2_en = 1;
}
pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
// Update real CPU Frequency
param->cpu_f = pll_freq / (1 << div2_cpu);
mul--;
scif_pll_opt_t opt;
opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1
opt.lockcount = 16, // lockcount in main clock for the PLL wait lock
opt.div = div, // DIV=1 in the formula
opt.mul = mul, // MUL=7 in the formula
opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
rest = pll_freq;
while (rest > AVR32_PM_PBA_MAX_FREQ ||
rest != param->pba_f)
{
div2_pba++;
rest = pll_freq / (1 << div2_pba);
if (rest < param->pba_f)
break;
}
// Update real PBA Frequency
param->pba_f = pll_freq / (1 << div2_pba);
if (div2_cpu)
{
b_div2_cpu = true;
div2_cpu--;
}
else
b_div2_cpu = false;
if (div2_pba)
{
b_div2_pba = true;
div2_pba--;
}
else
b_div2_pba = false;
if (b_div2_cpu == true )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
}
if (b_div2_pba == true )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
}
// Set Flashc Wait State
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
return PASS;
}
#endif // UC3C device-specific implementation
#if UC3D
static long int pcl_configure_clocks_uc3d(pcl_freq_param_t *param)
{
#define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
#define AVR32_PM_PBA_MAX_FREQ 48000000
#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
// Implementation for UC3C parts.
@ -396,7 +559,7 @@ static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
@ -420,41 +583,41 @@ static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
if (div2_cpu)
{
b_div2_cpu = TRUE;
b_div2_cpu = true;
div2_cpu--;
}
else
b_div2_cpu = FALSE;
b_div2_cpu = false;
if (div2_pba)
{
b_div2_pba = TRUE;
b_div2_pba = true;
div2_pba--;
}
else
b_div2_pba = FALSE;
b_div2_pba = false;
if (b_div2_cpu == TRUE )
if (b_div2_cpu == true )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
}
if (b_div2_pba == TRUE )
if (b_div2_pba == true )
{
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
}
// Set Flashc Wait State
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
return PASS;
}
#endif // UC3C device-specific implementation
#endif // UC3D device-specific implementation
long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
{
@ -482,7 +645,7 @@ long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int st
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, startup, true);
// Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
#if UC3L
#if UC3L || UC3D
flashcdw_set_flash_waitstate_and_readmode(fcrystal);
#elif UC3C
flashc_set_flash_waitstate_and_readmode(fcrystal);
@ -506,7 +669,7 @@ long int pcl_configure_usb_clock(void)
pm_configure_usb_clock();
return PASS;
#else
#ifdef AVR32_PM_410_H_INCLUDED
#if UC3C
const scif_pll_opt_t opt = {
.osc = SCIF_OSC0, // Sel Osc0 or Osc1
.lockcount = 16, // lockcount in main clock for the PLL wait lock
@ -518,7 +681,7 @@ long int pcl_configure_usb_clock(void)
};
/* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL1, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL1 */
scif_pll_enable(SCIF_PLL1);
@ -528,16 +691,27 @@ long int pcl_configure_usb_clock(void)
// Implementation for UC3C parts.
// Setup the generic clock for USB
scif_gc_setup(AVR32_SCIF_GCLK_USB,
scif_gc_setup(
#if (defined AVR32_USBB)
AVR32_SCIF_GCLK_USB,
#else
AVR32_SCIF_GCLK_USBC,
#endif
SCIF_GCCTRL_PLL1,
AVR32_SCIF_GC_NO_DIV_CLOCK,
0);
// Now enable the generic clock
scif_gc_enable(AVR32_SCIF_GCLK_USB);
scif_gc_enable(
#if (defined AVR32_USBB)
AVR32_SCIF_GCLK_USB
#else
AVR32_SCIF_GCLK_USBC
#endif
);
return PASS;
#else
#else
return PCL_NOT_SUPPORTED;
#endif
#endif
#endif
}

98
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h → bsp/avr32/software_framework/drivers/pm/power_clocks_lib.h
View File

@ -1,56 +1,53 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief High-level library abstracting features such as oscillators/pll/dfll
* configuration, clock configuration, System-sensible parameters
* configuration, buses clocks configuration, sleep mode, reset.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _POWER_CLOCKS_LIB_H_
#define _POWER_CLOCKS_LIB_H_
/**
* \defgroup group_avr32_drivers_pm_power_clocks_lib Power Clocks Library
* \ingroup group_avr32_drivers_pm
*
* \{
*/
#ifdef __cplusplus
extern "C" {
#endif
@ -63,7 +60,7 @@ extern "C" {
#include "pm.h"
#else
//! Device-specific data
#if UC3L
#if UC3L
#include "pm_uc3l.h"
#include "scif_uc3l.h"
#include "flashcdw.h"
@ -71,8 +68,12 @@ extern "C" {
#include "pm_uc3c.h"
#include "scif_uc3c.h"
#include "flashc.h"
#elif UC3D
#include "pm_uc3d.h"
#include "scif_uc3d.h"
#include "flashcdw.h"
#endif
#endif
#endif
/*! \name Clocks Management
*/
@ -141,7 +142,7 @@ typedef struct
//! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency)
unsigned long dfll_f;
//! Other parameters that might be necessary depending on the device (implementation-dependent).
// For the UC3L DFLL setup, this parameter should be pointing to a structure of
// type (scif_gclk_opt_t *).
@ -298,7 +299,7 @@ extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param);
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup);
@ -311,7 +312,7 @@ extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
@ -330,7 +331,7 @@ extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
@ -341,11 +342,10 @@ extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned
#endif
/*! \brief Configure the USB Clock
*
*
* \return Status.
* \retval 0 Success.
* \retval <0 An error occured.
* \retval <0 An error occurred.
*/
extern long int pcl_configure_usb_clock(void);
@ -376,4 +376,8 @@ extern void pcl_write_gplp(unsigned long gplp, unsigned long value);
}
#endif
/**
* \}
*/
#endif // _POWER_CLOCKS_LIB_H_

96
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.c → bsp/avr32/software_framework/drivers/usart/usart.c
View File

@ -1,53 +1,44 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief USART driver for AVR32 UC3.
*
* This file contains basic functions for the AVR32 USART, with support for all
* modes, settings and clock speeds.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a USART module can be used.
* - AppNote:
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#include "compiler.h"
#include "usart.h"
@ -64,10 +55,7 @@
*
* \return \c 1 if the USART is in multidrop mode, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
__always_inline static int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
{
return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;
}
@ -257,14 +245,14 @@ static int usart_set_spi_slave_baudrate(volatile avr32_usart_t *usart)
void usart_reset(volatile avr32_usart_t *usart)
{
Bool global_interrupt_enabled = Is_global_interrupt_enabled();
bool global_interrupt_enabled = cpu_irq_is_enabled();
// Disable all USART interrupts.
// Interrupts needed should be set explicitly on every reset.
if (global_interrupt_enabled) Disable_global_interrupt();
if (global_interrupt_enabled) cpu_irq_disable();
usart->idr = 0xFFFFFFFF;
usart->csr;
if (global_interrupt_enabled) Enable_global_interrupt();
if (global_interrupt_enabled) cpu_irq_enable();
// Reset mode and other registers that could cause unpredictable behavior after reset.
usart->mr = 0;
@ -596,7 +584,7 @@ int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_option
// Set FIDI register: bit rate = selected clock/FI_DI_ratio/16.
usart->fidi = opt->fidi_ratio;
// Set ISO7816 spesific options in the MODE register.
// Set ISO7816 specific options in the MODE register.
usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
AVR32_USART_MR_CLKO_MASK | // Enable clock output.
opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET |
@ -821,16 +809,6 @@ int usart_putchar(volatile avr32_usart_t *usart, int c)
{
int timeout = USART_DEFAULT_TIMEOUT;
if (c == '\n')
{
do
{
if (!timeout--) return USART_FAILURE;
} while (usart_write_char(usart, '\r') != USART_SUCCESS);
timeout = USART_DEFAULT_TIMEOUT;
}
do
{
if (!timeout--) return USART_FAILURE;
@ -890,7 +868,7 @@ int usart_get_echo_line(volatile avr32_usart_t *usart)
rx_char = usart_getchar(usart);
if (rx_char == USART_FAILURE)
{
usart_write_line(usart, "Error!!!\n");
usart_write_line(usart, "Error!!!\r\n");
retval = USART_FAILURE;
break;
}
@ -901,7 +879,7 @@ int usart_get_echo_line(volatile avr32_usart_t *usart)
}
usart_putchar(usart, rx_char);
if (rx_char == '\r')
{
{ // Add a LF and consider this as the end of the line.
usart_putchar(usart, '\n');
break;
}

212
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/USART/usart.h → bsp/avr32/software_framework/drivers/usart/usart.h
View File

@ -1,56 +1,56 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief USART driver for AVR32 UC3.
*
* This file contains basic functions for the AVR32 USART, with support for all
* modes, settings and clock speeds.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a USART module can be used.
* - AppNote:
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _USART_H_
#define _USART_H_
/**
* \defgroup group_avr32_drivers_usart USART - Univ. Sync/Async Serial Rec/Trans
*
* Driver for the USART (Universal Synchronous Asynchronous Receiver Transmitter).
* The driver supports the following modes: RS232, RS485, SPI, LIN and ISO7816.
*
* \{
*/
#include <avr32/io.h>
#include "compiler.h"
@ -110,7 +110,7 @@
//! @{
#define USART_LIN_PUBLISH_ACTION AVR32_USART_LINMR_NACT_PUBLISH //!< The USART transmits the response.
#define USART_LIN_SUBSCRIBE_ACTION AVR32_USART_LINMR_NACT_SUBSCRIBE //!< The USART receives the response.
#define USART_LIN_IGNORE_ACTION AVR32_USART_LINMR_NACT_IGNORE //!< The USART does not transmit and does not receive the reponse.
#define USART_LIN_IGNORE_ACTION AVR32_USART_LINMR_NACT_IGNORE //!< The USART does not transmit and does not receive the response.
//! @}
/*! \name LIN Checksum Types
@ -172,7 +172,7 @@ typedef struct
//! Disable successive NACKs.
//! Successive parity errors are counted up to the value in the \ref max_iterations field.
//! These parity errors generate a NACK on the ISO line. As soon as this value is reached,
//! no addititional NACK is sent on the ISO line. The ITERATION flag is asserted.
//! no additional NACK is sent on the ISO line. The ITERATION flag is asserted.
int dis_suc_nack;
//! Max number of repetitions (0 to 7).
@ -401,10 +401,7 @@ extern int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_o
*
* \param usart Base address of the USART instance.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart)
__always_inline static void usart_reset_status(volatile avr32_usart_t *usart)
{
usart->cr = AVR32_USART_CR_RSTSTA_MASK;
}
@ -415,10 +412,7 @@ extern __inline__ void usart_reset_status(volatile avr32_usart_t *usart)
*
* \return \c 1 if a parity error has been detected, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart)
__always_inline static int usart_parity_error(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_PARE_MASK) != 0;
}
@ -429,10 +423,7 @@ extern __inline__ int usart_parity_error(volatile avr32_usart_t *usart)
*
* \return \c 1 if a framing error has been detected, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart)
__always_inline static int usart_framing_error(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_FRAME_MASK) != 0;
}
@ -443,10 +434,7 @@ extern __inline__ int usart_framing_error(volatile avr32_usart_t *usart)
*
* \return \c 1 if a overrun error has been detected, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart)
__always_inline static int usart_overrun_error(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_OVRE_MASK) != 0;
}
@ -463,10 +451,7 @@ extern __inline__ int usart_overrun_error(volatile avr32_usart_t *usart)
*
* \retval The binary value of the error field.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_lin_get_error(volatile avr32_usart_t *usart)
__always_inline static int usart_lin_get_error(volatile avr32_usart_t *usart)
{
return (usart->csr & (AVR32_USART_CSR_LINSNRE_MASK |
AVR32_USART_CSR_LINCE_MASK |
@ -491,10 +476,7 @@ extern __inline__ int usart_lin_get_error(volatile avr32_usart_t *usart)
*
* \param usart Base address of the USART instance.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_iso7816_enable_receiver(volatile avr32_usart_t *usart)
__always_inline static void usart_iso7816_enable_receiver(volatile avr32_usart_t *usart)
{
usart->cr = AVR32_USART_CR_TXDIS_MASK | AVR32_USART_CR_RXEN_MASK;
}
@ -505,10 +487,7 @@ extern __inline__ void usart_iso7816_enable_receiver(volatile avr32_usart_t *usa
*
* \param usart Base address of the USART instance.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_iso7816_enable_transmitter(volatile avr32_usart_t *usart)
__always_inline static void usart_iso7816_enable_transmitter(volatile avr32_usart_t *usart)
{
usart->cr = AVR32_USART_CR_RXDIS_MASK | AVR32_USART_CR_TXEN_MASK;
}
@ -534,10 +513,7 @@ extern __inline__ void usart_iso7816_enable_transmitter(volatile avr32_usart_t *
* \ref USART_LIN_SUBSCRIBE_ACTION or
* \ref USART_LIN_IGNORE_ACTION.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_set_node_action(volatile avr32_usart_t *usart, unsigned char action)
__always_inline static void usart_lin_set_node_action(volatile avr32_usart_t *usart, unsigned char action)
{
usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_NACT_MASK) |
action << AVR32_USART_LINMR_NACT_OFFSET;
@ -546,12 +522,9 @@ extern __inline__ void usart_lin_set_node_action(volatile avr32_usart_t *usart,
/*! \brief Enables or disables the Identifier parity.
*
* \param usart Base address of the USART instance.
* \param parity Whether to enable the Identifier parity: \c TRUE or \c FALSE.
* \param parity Whether to enable the Identifier parity: \c true or \c false.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_enable_parity(volatile avr32_usart_t *usart, unsigned char parity)
__always_inline static void usart_lin_enable_parity(volatile avr32_usart_t *usart, unsigned char parity)
{
usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_PARDIS_MASK) |
!parity << AVR32_USART_LINMR_PARDIS_OFFSET;
@ -560,12 +533,9 @@ extern __inline__ void usart_lin_enable_parity(volatile avr32_usart_t *usart, un
/*! \brief Enables or disables the checksum.
*
* \param usart Base address of the USART instance.
* \param parity Whether to enable the checksum: \c TRUE or \c FALSE.
* \param parity Whether to enable the checksum: \c true or \c false.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_enable_checksum(volatile avr32_usart_t *usart, unsigned char checksum)
__always_inline static void usart_lin_enable_checksum(volatile avr32_usart_t *usart, unsigned char checksum)
{
usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKDIS_MASK) |
!checksum << AVR32_USART_LINMR_CHKDIS_OFFSET;
@ -577,10 +547,7 @@ extern __inline__ void usart_lin_enable_checksum(volatile avr32_usart_t *usart,
* \param chktyp The checksum type: \ref USART_LIN_ENHANCED_CHEKSUM or
* \ref USART_LIN_CLASSIC_CHECKSUM.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_set_checksum(volatile avr32_usart_t *usart, unsigned char chktyp)
__always_inline static void usart_lin_set_checksum(volatile avr32_usart_t *usart, unsigned char chktyp)
{
usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_CHKTYP_MASK) |
chktyp << AVR32_USART_LINMR_CHKTYP_OFFSET;
@ -592,10 +559,7 @@ extern __inline__ void usart_lin_set_checksum(volatile avr32_usart_t *usart, uns
*
* \return The response data length.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned char usart_lin_get_data_length(volatile avr32_usart_t *usart)
__always_inline static unsigned char usart_lin_get_data_length(volatile avr32_usart_t *usart)
{
if (usart->linmr & AVR32_USART_LINMR_DLM_MASK)
{
@ -612,10 +576,7 @@ extern __inline__ unsigned char usart_lin_get_data_length(volatile avr32_usart_t
*
* \param usart Base address of the USART instance.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_set_data_length_lin1x(volatile avr32_usart_t *usart)
__always_inline static void usart_lin_set_data_length_lin1x(volatile avr32_usart_t *usart)
{
usart->linmr |= AVR32_USART_LINMR_DLM_MASK;
}
@ -625,10 +586,7 @@ extern __inline__ void usart_lin_set_data_length_lin1x(volatile avr32_usart_t *u
* \param usart Base address of the USART instance.
* \param data_length The response data length.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_set_data_length_lin2x(volatile avr32_usart_t *usart, unsigned char data_length)
__always_inline static void usart_lin_set_data_length_lin2x(volatile avr32_usart_t *usart, unsigned char data_length)
{
usart->linmr = (usart->linmr & ~(AVR32_USART_LINMR_DLC_MASK |
AVR32_USART_LINMR_DLM_MASK)) |
@ -638,13 +596,10 @@ extern __inline__ void usart_lin_set_data_length_lin2x(volatile avr32_usart_t *u
/*! \brief Enables or disables the frame slot mode.
*
* \param usart Base address of the USART instance.
* \param frameslot Whether to enable the frame slot mode: \c TRUE or
* \c FALSE.
* \param frameslot Whether to enable the frame slot mode: \c true or
* \c false.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_enable_frameslot(volatile avr32_usart_t *usart, unsigned char frameslot)
__always_inline static void usart_lin_enable_frameslot(volatile avr32_usart_t *usart, unsigned char frameslot)
{
usart->linmr = (usart->linmr & ~AVR32_USART_LINMR_FSDIS_MASK) |
!frameslot << AVR32_USART_LINMR_FSDIS_OFFSET;
@ -656,10 +611,7 @@ extern __inline__ void usart_lin_enable_frameslot(volatile avr32_usart_t *usart,
*
* \return The Identifier character.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned char usart_lin_get_id_char(volatile avr32_usart_t *usart)
__always_inline static unsigned char usart_lin_get_id_char(volatile avr32_usart_t *usart)
{
return (usart->linir & AVR32_USART_LINIR_IDCHR_MASK) >> AVR32_USART_LINIR_IDCHR_OFFSET;
}
@ -669,10 +621,7 @@ extern __inline__ unsigned char usart_lin_get_id_char(volatile avr32_usart_t *us
* \param usart Base address of the USART instance.
* \param id_char The Identifier character.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_set_id_char(volatile avr32_usart_t *usart, unsigned char id_char)
__always_inline static void usart_lin_set_id_char(volatile avr32_usart_t *usart, unsigned char id_char)
{
usart->linir = (usart->linir & ~AVR32_USART_LINIR_IDCHR_MASK) |
id_char << AVR32_USART_LINIR_IDCHR_OFFSET;
@ -742,10 +691,7 @@ extern int usart_send_address(volatile avr32_usart_t *usart, int address);
*
* \return \c 1 if the USART Transmit Holding Register is free, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_tx_ready(volatile avr32_usart_t *usart)
__always_inline static int usart_tx_ready(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_TXRDY_MASK) != 0;
}
@ -765,10 +711,7 @@ extern int usart_write_char(volatile avr32_usart_t *usart, int c);
* \param usart Base address of the USART instance.
* \param c The character (up to 9 bits) to transmit.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_bw_write_char(volatile avr32_usart_t *usart, int c)
__always_inline static void usart_bw_write_char(volatile avr32_usart_t *usart, int c)
{
while (usart_write_char(usart, c) != USART_SUCCESS);
}
@ -790,10 +733,7 @@ extern int usart_putchar(volatile avr32_usart_t *usart, int c);
* \return \c 1 if the USART Transmit Shift Register and the USART Transmit
* Holding Register are free, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_tx_empty(volatile avr32_usart_t *usart)
__always_inline static int usart_tx_empty(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_TXEMPTY_MASK) != 0;
}
@ -804,10 +744,7 @@ extern __inline__ int usart_tx_empty(volatile avr32_usart_t *usart)
*
* \return \c 1 if the USART Receive Holding Register is full, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_test_hit(volatile avr32_usart_t *usart)
__always_inline static int usart_test_hit(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_RXRDY_MASK) != 0;
}
@ -821,7 +758,7 @@ extern __inline__ int usart_test_hit(volatile avr32_usart_t *usart)
*
* \retval USART_SUCCESS The character was read successfully.
* \retval USART_RX_EMPTY The RX buffer was empty.
* \retval USART_RX_ERROR An error was deteceted.
* \retval USART_RX_ERROR An error was detected.
*/
extern int usart_read_char(volatile avr32_usart_t *usart, int *c);
@ -840,7 +777,7 @@ extern int usart_getchar(volatile avr32_usart_t *usart);
*/
extern void usart_write_line(volatile avr32_usart_t *usart, const char *string);
/*! \brief Gets and echoes characters until end of line.
/*! \brief Gets and echoes characters until end of line (detected by a CR character).
*
* \param usart Base address of the USART instance.
*
@ -859,10 +796,7 @@ extern int usart_get_echo_line(volatile avr32_usart_t *usart);
*
* \param usart Base address of the USART instance.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void usart_lin_abort(volatile avr32_usart_t *usart)
__always_inline static void usart_lin_abort(volatile avr32_usart_t *usart)
{
usart->cr = AVR32_USART_LINABT_MASK;
}
@ -873,10 +807,7 @@ extern __inline__ void usart_lin_abort(volatile avr32_usart_t *usart)
*
* \return \c 1 if a LIN transfer has been completed, otherwise \c 0.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int usart_lin_transfer_completed(volatile avr32_usart_t *usart)
__always_inline static int usart_lin_transfer_completed(volatile avr32_usart_t *usart)
{
return (usart->csr & AVR32_USART_CSR_LINTC_MASK) != 0;
}
@ -885,5 +816,8 @@ extern __inline__ int usart_lin_transfer_completed(volatile avr32_usart_t *usart
//! @}
/**
* \}
*/
#endif // _USART_H_

861
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/compiler.h → bsp/avr32/software_framework/utils/compiler.h
View File

@ -1,65 +1,60 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/**
* \file
*
* \brief Compiler file for AVR32.
* \brief Commonly used includes, types and macros.
*
* This file defines commonly used types and macros.
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
* \asf_license_start
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \page License
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _COMPILER_H_
#define _COMPILER_H_
#ifndef _COMPILER_AVR32_H_
#define _COMPILER_AVR32_H_
/**
* \defgroup group_avr32_utils Compiler abstraction layer and code utilities
*
* Compiler abstraction layer and code utilities for 32-bit AVR.
* This module provides various abstraction layers and utilities to make code compatible between different compilers.
*
* \{
*/
#if ((defined __GNUC__) && (defined __AVR32__)) || (defined __ICCAVR32__ || defined __AAVR32__)
# include <avr32/io.h>
#endif
#if (defined __ICCAVR32__)
# include <intrinsics.h>
#endif
#include "preprocessor.h"
#include "parts.h"
#include <parts.h>
#include <avr32/io.h>
#include "header_files/uc3d_defines_fix.h"
#include "header_files/uc3l3_l4_defines_fix.h"
//_____ D E C L A R A T I O N S ____________________________________________
@ -67,6 +62,8 @@
#include <stddef.h>
#include <stdlib.h>
#include <stdbool.h>
#include <stdint.h>
#if (defined __ICCAVR32__)
@ -80,9 +77,127 @@
#define __inline__ inline
#define __volatile__
//! @}
#endif
/**
* \def UNUSED
* \brief Marking \a v as a unused parameter or value.
*/
#define UNUSED(v) (void)(v)
/**
* \def unused
* \brief Marking \a v as a unused parameter or value.
*/
#define unused(v) do { (void)(v); } while(0)
/**
* \def barrier
* \brief Memory barrier
*/
#if defined(__GNUC__)
# define barrier() asm volatile("" ::: "memory")
#elif defined(__ICCAVR32__)
# define barrier() __asm__ __volatile__ ("")
#endif
/**
* \brief Emit the compiler pragma \a arg.
*
* \param arg The pragma directive as it would appear after \e \#pragma
* (i.e. not stringified).
*/
#define COMPILER_PRAGMA(arg) _Pragma(#arg)
/**
* \def COMPILER_PACK_SET(alignment)
* \brief Set maximum alignment for subsequent struct and union
* definitions to \a alignment.
*/
#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment))
/**
* \def COMPILER_PACK_RESET()
* \brief Set default alignment for subsequent struct and union
* definitions.
*/
#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack())
/**
* \brief Set aligned boundary.
*/
#if (defined __GNUC__)
#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a)))
#elif (defined __ICCAVR32__)
#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a)
#endif
/**
* \brief Set word-aligned boundary.
*/
#if (defined __GNUC__)
#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4)))
#elif (defined __ICCAVR32__)
#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4)
#endif
/**
* \name System Register Access
* @{
*/
#if defined(__GNUC__) || defined(__DOXYGEN__)
/**
* \brief Get value of system register
*
* \param reg Address of the system register of which to get the value.
*
* \return Value of system register \a reg.
*/
# define sysreg_read(reg) __builtin_mfsr(reg)
/**
* \name Tag functions as deprecated
*
* Tagging a function as deprecated will produce a warning when and only
* when the function is called.
*
* Usage is to add the __DEPRECATED__ symbol before the function definition.
* E.g.:
* __DEPRECATED__ uint8_t some_deprecated_function (void)
* {
* ...
* }
*
* \note Only supported by GCC 3.1 and above, no IAR support
* @{
*/
#if ((defined __GNUC__) && (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >=1)))
#define __DEPRECATED__ __attribute__((__deprecated__))
#else
#define __DEPRECATED__
#endif
//! @}
/**
* \brief Set value of system register
*
* \param reg Address of the system register of which to set the value.
* \param val Value to set the system register \a reg to.
*/
# define sysreg_write(reg, val) __builtin_mtsr(reg, val)
#elif defined(__ICCAVR32__)
# define sysreg_read(reg) __get_system_register(reg)
# define sysreg_write(reg, val) __set_system_register(reg, val)
#endif
// Deprecated definitions
#define Get_system_register(reg) sysreg_read(reg)
#define Set_system_register(reg, val) sysreg_write(reg, val)
//! @}
#include "interrupt.h"
/*! \name Usual Types
*/
@ -93,23 +208,28 @@ typedef unsigned char Bool; //!< Boolean.
typedef unsigned char bool; //!< Boolean.
#endif
#endif
typedef signed char S8 ; //!< 8-bit signed integer.
typedef unsigned char U8 ; //!< 8-bit unsigned integer.
typedef signed short int S16; //!< 16-bit signed integer.
typedef unsigned short int U16; //!< 16-bit unsigned integer.
typedef signed long int S32; //!< 32-bit signed integer.
typedef unsigned long int U32; //!< 32-bit unsigned integer.
typedef int8_t S8 ; //!< 8-bit signed integer.
typedef uint8_t U8 ; //!< 8-bit unsigned integer.
typedef int16_t S16; //!< 16-bit signed integer.
typedef uint16_t U16; //!< 16-bit unsigned integer.
typedef uint16_t le16_t;
typedef uint16_t be16_t;
typedef int32_t S32; //!< 32-bit signed integer.
typedef uint32_t U32; //!< 32-bit unsigned integer.
typedef uint32_t le32_t;
typedef uint32_t be32_t;
typedef signed long long int S64; //!< 64-bit signed integer.
typedef unsigned long long int U64; //!< 64-bit unsigned integer.
typedef float F32; //!< 32-bit floating-point number.
typedef double F64; //!< 64-bit floating-point number.
typedef uint32_t iram_size_t;
//! @}
/*! \name Status Types
*/
//! @{
typedef Bool Status_bool_t; //!< Boolean status.
typedef bool Status_bool_t; //!< Boolean status.
typedef U8 Status_t; //!< 8-bit-coded status.
//! @}
@ -267,31 +387,56 @@ typedef struct
//! @{
#define DISABLE 0
#define ENABLE 1
#define DISABLED 0
#define ENABLED 1
#define OFF 0
#define ON 1
#define FALSE 0
#define TRUE 1
#ifndef __cplusplus
#if !defined(__bool_true_false_are_defined)
#define false FALSE
#define true TRUE
#define false 0
#define true 1
#endif
#endif
#define KO 0
#define OK 1
#define PASS 0
#define FAIL 1
#define LOW 0
#define HIGH 1
#define CLR 0
#define SET 1
//! @}
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//! \name Optimization Control
//@{
/**
* \def likely(exp)
* \brief The expression \a exp is likely to be true
*/
#ifndef likely
# define likely(exp) (exp)
#endif
/**
* \def unlikely(exp)
* \brief The expression \a exp is unlikely to be true
*/
#ifndef unlikely
# define unlikely(exp) (exp)
#endif
/**
* \def is_constant(exp)
* \brief Determine if an expression evaluates to a constant value.
*
* \param exp Any expression
*
* \return true if \a exp is constant, false otherwise.
*/
#ifdef __GNUC__
# define is_constant(exp) __builtin_constant_p(exp)
#else
# define is_constant(exp) (0)
#endif
//! @}
/*! \name Bit-Field Handling
*/
//! @{
@ -374,20 +519,43 @@ typedef struct
//! @}
/*! \brief This macro makes the CPU take a small break for a few cycles. This should
* be used when waiting for an event. It will reduce the internal bus load.
*
* "sub pc, pc, -4" (or "sub pc, -2") forces the IF stage to wait until the result
* of the calculation before it can fetch the next instruction. This makes sure
* there are nothing stuck in the LS pipe when you start a new iteration and guarantee
* to flush the pipeline without having any other effect.
* (A nop doesn't have any effect on the IF stage.)
*/
#if (defined __GNUC__)
# define cpu_relax() __asm__ __volatile__("sub pc, pc, -4" ::: "memory", "cc")
#elif (defined __ICCAVR32__)
# define cpu_relax() __asm__ __volatile__("sub pc, pc, -4")
#endif
/*! \brief This macro is used to test fatal errors.
*
* The macro tests if the expression is FALSE. If it is, a fatal error is
* detected and the application hangs up.
* The macro tests if the expression is false. If it is, a fatal error is
* detected and the application hangs up. If TEST_SUITE_DEFINE_ASSERT_MACRO
* is defined, a unit test version of the macro is used, to allow execution
* of further tests after a false expression.
*
* \param expr Expression to evaluate and supposed to be nonzero.
*/
#ifdef _ASSERT_ENABLE_
#define Assert(expr) \
{\
if (!(expr)) while (TRUE);\
}
#if defined(_ASSERT_ENABLE_)
# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO)
// Assert() is defined in unit_test/suite.h
# include "unit_test/suite.h"
# else
# define Assert(expr) \
{\
if (!(expr)) while (true);\
}
# endif
#else
#define Assert(expr)
# define Assert(expr) ((void) 0)
#endif
@ -412,9 +580,15 @@ typedef struct
* \return The count of leading zero bits in \a u.
*/
#if (defined __GNUC__)
#define clz(u) __builtin_clz(u)
#define clz(u) ((u) ? __builtin_clz(u) : 32)
#elif (defined __ICCAVR32__)
#define clz(u) __count_leading_zeros(u)
#if (__VER__ == 330) && (__SUBVERSION__ <= 1)
// __count_leading_zeros is broken and returns a value which is offset by
// -32 when called with a constant parameter.
#define clz(v) (0 == v ? 32 : (31 & __count_leading_zeros(v)))
#else
#define clz(v) __count_leading_zeros(v)
#endif
#endif
/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
@ -424,13 +598,71 @@ typedef struct
* \return The count of trailing zero bits in \a u.
*/
#if (defined __GNUC__)
#define ctz(u) __builtin_ctz(u)
#define ctz(u) ((u) ? __builtin_ctz(u) : 32)
#elif (defined __ICCAVR32__)
#define ctz(u) __count_trailing_zeros(u)
#endif
//! @}
//! \name Logarithmic functions
//! @{
/**
* \internal
* Undefined function. Will cause a link failure if ilog2() is called
* with an invalid constant value.
*/
int_fast8_t ilog2_undefined(void);
/**
* \brief Calculate the base-2 logarithm of a number rounded down to
* the nearest integer.
*
* \param x A 32-bit value
* \return The base-2 logarithm of \a x, or -1 if \a x is 0.
*/
static inline int_fast8_t ilog2(uint32_t x)
{
if (is_constant(x))
return ((x) & (1ULL << 31) ? 31 :
(x) & (1ULL << 30) ? 30 :
(x) & (1ULL << 29) ? 29 :
(x) & (1ULL << 28) ? 28 :
(x) & (1ULL << 27) ? 27 :
(x) & (1ULL << 26) ? 26 :
(x) & (1ULL << 25) ? 25 :
(x) & (1ULL << 24) ? 24 :
(x) & (1ULL << 23) ? 23 :
(x) & (1ULL << 22) ? 22 :
(x) & (1ULL << 21) ? 21 :
(x) & (1ULL << 20) ? 20 :
(x) & (1ULL << 19) ? 19 :
(x) & (1ULL << 18) ? 18 :
(x) & (1ULL << 17) ? 17 :
(x) & (1ULL << 16) ? 16 :
(x) & (1ULL << 15) ? 15 :
(x) & (1ULL << 14) ? 14 :
(x) & (1ULL << 13) ? 13 :
(x) & (1ULL << 12) ? 12 :
(x) & (1ULL << 11) ? 11 :
(x) & (1ULL << 10) ? 10 :
(x) & (1ULL << 9) ? 9 :
(x) & (1ULL << 8) ? 8 :
(x) & (1ULL << 7) ? 7 :
(x) & (1ULL << 6) ? 6 :
(x) & (1ULL << 5) ? 5 :
(x) & (1ULL << 4) ? 4 :
(x) & (1ULL << 3) ? 3 :
(x) & (1ULL << 2) ? 2 :
(x) & (1ULL << 1) ? 1 :
(x) & (1ULL << 0) ? 0 :
ilog2_undefined());
return 31 - clz(x);
}
//! @}
/*! \name Bit Reversing
*/
@ -755,35 +987,6 @@ typedef struct
#endif
/*! \name System Register Access
*/
//! @{
/*! \brief Gets the value of the \a sysreg system register.
*
* \param sysreg Address of the system register of which to get the value.
*
* \return Value of the \a sysreg system register.
*/
#if (defined __GNUC__)
#define Get_system_register(sysreg) __builtin_mfsr(sysreg)
#elif (defined __ICCAVR32__)
#define Get_system_register(sysreg) __get_system_register(sysreg)
#endif
/*! \brief Sets the value of the \a sysreg system register to \a value.
*
* \param sysreg Address of the system register of which to set the value.
* \param value Value to set the \a sysreg system register to.
*/
#if (defined __GNUC__)
#define Set_system_register(sysreg, value) __builtin_mtsr(sysreg, value)
#elif (defined __ICCAVR32__)
#define Set_system_register(sysreg, value) __set_system_register(sysreg, value)
#endif
//! @}
/*! \name CPU Status Register Access
*/
@ -811,70 +1014,6 @@ typedef struct
#define Enable_global_exception() (__clear_status_flag(AVR32_SR_EM_OFFSET))
#endif
/*! \brief Tells whether interrupts are globally enabled.
*
* \return \c 1 if interrupts are globally enabled, else \c 0.
*/
#define Is_global_interrupt_enabled() (!Tst_bits(Get_system_register(AVR32_SR), AVR32_SR_GM_MASK))
/*! \brief Disables interrupts globally.
*/
#if (defined __GNUC__)
#define Disable_global_interrupt() ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
#elif (defined __ICCAVR32__)
#define Disable_global_interrupt() (__disable_interrupt())
#endif
/*! \brief Enables interrupts globally.
*/
#if (defined __GNUC__)
#define Enable_global_interrupt() ({__asm__ __volatile__ ("csrf\t%0" : : "i" (AVR32_SR_GM_OFFSET));})
#elif (defined __ICCAVR32__)
#define Enable_global_interrupt() (__enable_interrupt())
#endif
/*! \brief Tells whether interrupt level \a int_level is enabled.
*
* \param int_level Interrupt level (0 to 3).
*
* \return \c 1 if interrupt level \a int_level is enabled, else \c 0.
*/
#define Is_interrupt_level_enabled(int_level) (!Tst_bits(Get_system_register(AVR32_SR), TPASTE3(AVR32_SR_I, int_level, M_MASK)))
/*! \brief Disables interrupt level \a int_level.
*
* \param int_level Interrupt level to disable (0 to 3).
*/
#if (defined __GNUC__)
#define Disable_interrupt_level(int_level) ({__asm__ __volatile__ ("ssrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
#elif (defined __ICCAVR32__)
#define Disable_interrupt_level(int_level) (__set_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
#endif
/*! \brief Enables interrupt level \a int_level.
*
* \param int_level Interrupt level to enable (0 to 3).
*/
#if (defined __GNUC__)
#define Enable_interrupt_level(int_level) ({__asm__ __volatile__ ("csrf\t%0" : : "i" (TPASTE3(AVR32_SR_I, int_level, M_OFFSET)));})
#elif (defined __ICCAVR32__)
#define Enable_interrupt_level(int_level) (__clear_status_flag(TPASTE3(AVR32_SR_I, int_level, M_OFFSET)))
#endif
/*! \brief Protects subsequent code from interrupts.
*/
#define AVR32_ENTER_CRITICAL_REGION( ) \
{ \
Bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
Disable_global_interrupt(); // Disable the appropriate interrupts.
/*! \brief This macro must always be used in conjunction with AVR32_ENTER_CRITICAL_REGION
* so that interrupts are enabled again.
*/
#define AVR32_LEAVE_CRITICAL_REGION( ) \
if (global_interrupt_enabled) Enable_global_interrupt(); \
}
//! @}
@ -907,120 +1046,82 @@ typedef struct
//! @}
#endif // __AVR32_ABI_COMPILER__
//! Boolean evaluating MCU little endianism.
#if ((defined __GNUC__) && (defined __AVR32__)) || ((defined __ICCAVR32__) || (defined __AAVR32__))
#define LITTLE_ENDIAN_MCU FALSE
#else
#error If you are here, you should check what is exactly the processor you are using...
#define LITTLE_ENDIAN_MCU FALSE
#endif
// Check that MCU endianism is correctly defined.
#ifndef LITTLE_ENDIAN_MCU
#error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE
#endif
//! Boolean evaluating MCU big endianism.
#define BIG_ENDIAN_MCU (!LITTLE_ENDIAN_MCU)
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
/*! \name MCU Endianism Handling
/*! \name Force Assembly Inline Code Section
*/
//! @{
#if (LITTLE_ENDIAN_MCU==TRUE)
#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16.
#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16.
#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
#define LSB0W(u32) (((U8 *)&(u32))[0]) //!< Least significant byte of 1st rank of \a u32.
#define LSB1W(u32) (((U8 *)&(u32))[1]) //!< Least significant byte of 2nd rank of \a u32.
#define LSB2W(u32) (((U8 *)&(u32))[2]) //!< Least significant byte of 3rd rank of \a u32.
#define LSB3W(u32) (((U8 *)&(u32))[3]) //!< Least significant byte of 4th rank of \a u32.
#define MSB3W(u32) LSB0W(u32) //!< Most significant byte of 4th rank of \a u32.
#define MSB2W(u32) LSB1W(u32) //!< Most significant byte of 3rd rank of \a u32.
#define MSB1W(u32) LSB2W(u32) //!< Most significant byte of 2nd rank of \a u32.
#define MSB0W(u32) LSB3W(u32) //!< Most significant byte of 1st rank of \a u32.
#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
#define LSH0(u64) (((U16 *)&(u64))[0]) //!< Least significant half-word of 1st rank of \a u64.
#define LSH1(u64) (((U16 *)&(u64))[1]) //!< Least significant half-word of 2nd rank of \a u64.
#define LSH2(u64) (((U16 *)&(u64))[2]) //!< Least significant half-word of 3rd rank of \a u64.
#define LSH3(u64) (((U16 *)&(u64))[3]) //!< Least significant half-word of 4th rank of \a u64.
#define MSH3(u64) LSH0(u64) //!< Most significant half-word of 4th rank of \a u64.
#define MSH2(u64) LSH1(u64) //!< Most significant half-word of 3rd rank of \a u64.
#define MSH1(u64) LSH2(u64) //!< Most significant half-word of 2nd rank of \a u64.
#define MSH0(u64) LSH3(u64) //!< Most significant half-word of 1st rank of \a u64.
#define LSB0D(u64) (((U8 *)&(u64))[0]) //!< Least significant byte of 1st rank of \a u64.
#define LSB1D(u64) (((U8 *)&(u64))[1]) //!< Least significant byte of 2nd rank of \a u64.
#define LSB2D(u64) (((U8 *)&(u64))[2]) //!< Least significant byte of 3rd rank of \a u64.
#define LSB3D(u64) (((U8 *)&(u64))[3]) //!< Least significant byte of 4th rank of \a u64.
#define LSB4D(u64) (((U8 *)&(u64))[4]) //!< Least significant byte of 5th rank of \a u64.
#define LSB5D(u64) (((U8 *)&(u64))[5]) //!< Least significant byte of 6th rank of \a u64.
#define LSB6D(u64) (((U8 *)&(u64))[6]) //!< Least significant byte of 7th rank of \a u64.
#define LSB7D(u64) (((U8 *)&(u64))[7]) //!< Least significant byte of 8th rank of \a u64.
#define MSB7D(u64) LSB0D(u64) //!< Most significant byte of 8th rank of \a u64.
#define MSB6D(u64) LSB1D(u64) //!< Most significant byte of 7th rank of \a u64.
#define MSB5D(u64) LSB2D(u64) //!< Most significant byte of 6th rank of \a u64.
#define MSB4D(u64) LSB3D(u64) //!< Most significant byte of 5th rank of \a u64.
#define MSB3D(u64) LSB4D(u64) //!< Most significant byte of 4th rank of \a u64.
#define MSB2D(u64) LSB5D(u64) //!< Most significant byte of 3rd rank of \a u64.
#define MSB1D(u64) LSB6D(u64) //!< Most significant byte of 2nd rank of \a u64.
#define MSB0D(u64) LSB7D(u64) //!< Most significant byte of 1st rank of \a u64.
#elif (BIG_ENDIAN_MCU==TRUE)
#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.
#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.
#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.
#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.
#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.
#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.
#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.
#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.
#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.
#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.
#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.
#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.
#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.
#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.
#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.
#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.
#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.
#define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64.
#define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64.
#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.
#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.
#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.
#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
#else
#error Unknown endianism.
#if (defined __GNUC__)
#define __always_inline inline __attribute__((__always_inline__))
#elif (defined __ICCAVR32__)
#define __always_inline _Pragma("inline=forced")
#endif
//! @}
/*! \name MCU Endianism Handling
* AVR32 is MCU big endianism.
*/
//! @{
#define MSB(u16) (((U8 *)&(u16))[0]) //!< Most significant byte of \a u16.
#define LSB(u16) (((U8 *)&(u16))[1]) //!< Least significant byte of \a u16.
#define MSH(u32) (((U16 *)&(u32))[0]) //!< Most significant half-word of \a u32.
#define LSH(u32) (((U16 *)&(u32))[1]) //!< Least significant half-word of \a u32.
#define MSB0W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 1st rank of \a u32.
#define MSB1W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 2nd rank of \a u32.
#define MSB2W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 3rd rank of \a u32.
#define MSB3W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 4th rank of \a u32.
#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32.
#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32.
#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32.
#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32.
#define MSW(u64) (((U32 *)&(u64))[0]) //!< Most significant word of \a u64.
#define LSW(u64) (((U32 *)&(u64))[1]) //!< Least significant word of \a u64.
#define MSH0(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 1st rank of \a u64.
#define MSH1(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 2nd rank of \a u64.
#define MSH2(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 3rd rank of \a u64.
#define MSH3(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 4th rank of \a u64.
#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64.
#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64.
#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64.
#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64.
#define MSB0D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 1st rank of \a u64.
#define MSB1D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 2nd rank of \a u64.
#define MSB2D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 3rd rank of \a u64.
#define MSB3D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 4th rank of \a u64.
#define MSB4D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 5th rank of \a u64.
#define MSB5D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 6th rank of \a u64.
#define MSB6D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 7th rank of \a u64.
#define MSB7D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 8th rank of \a u64.
#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64.
#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64.
#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64.
#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64.
#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64.
#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64.
#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64.
#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64.
#define LE16(x) Swap16(x)
#define le16_to_cpu(x) swap16(x)
#define cpu_to_le16(x) swap16(x)
#define LE16_TO_CPU(x) Swap16(x)
#define CPU_TO_LE16(x) Swap16(x)
#define be16_to_cpu(x) (x)
#define cpu_to_be16(x) (x)
#define BE16_TO_CPU(x) (x)
#define CPU_TO_BE16(x) (x)
#define le32_to_cpu(x) swap32(x)
#define cpu_to_le32(x) swap32(x)
#define LE32_TO_CPU(x) Swap32(x)
#define CPU_TO_LE32(x) Swap32(x)
#define be32_to_cpu(x) (x)
#define cpu_to_be32(x) (x)
#define BE32_TO_CPU(x) (x)
#define CPU_TO_BE32(x) (x)
//! @}
@ -1078,7 +1179,12 @@ typedef struct
* \note More optimized if only used with values unknown at compile time.
*/
#if (defined __GNUC__)
# if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__
#define swap16(u16) ((U16)__builtin_bswap_16((U16)(u16)))
# else
// swap_16 must be not used when GCC's -Os command option is used
#define swap16(u16) Swap16(u16)
# endif
#elif (defined __ICCAVR32__)
#define swap16(u16) ((U16)__swap_bytes_in_halfwords((U16)(u16)))
#endif
@ -1139,7 +1245,200 @@ typedef U8 Byte; //!< 8-bit unsigned integer.
//! @}
/**
* \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using
* integer arithmetic.
*
* \param a An integer
* \param b Another integer
*
* \return (\a a / \a b) rounded up to the nearest integer.
*/
#define div_ceil(a, b) (((a) + (b) - 1) / (b))
#if (defined __GNUC__)
#define SHORTENUM __attribute__ ((packed))
#elif (defined __ICCAVR32__)
#define SHORTENUM /**/
#endif
#define FUNC_PTR void *
#if (defined __GNUC__)
#define FLASH_DECLARE(x) const x
#elif (defined __ICCAVR32__)
#define FLASH_DECLARE(x) x
#endif
#if (defined __GNUC__)
#define FLASH_EXTERN(x) extern const x
#elif (defined __ICCAVR32__)
#define FLASH_EXTERN(x) extern x
#endif
/*Program Memory Space Storage abstraction definition*/
#if (defined __GNUC__)
#define CMD_ID_OCTET (0)
#elif (defined __ICCAVR32__)
#define CMD_ID_OCTET (3)
#endif
/* Converting of values from CPU endian to little endian. */
#define CPU_ENDIAN_TO_LE16(x) swap16(x)
#define CPU_ENDIAN_TO_LE32(x) swap32(x)
#define CPU_ENDIAN_TO_LE64(x) swap64(x)
/* Converting of values from little endian to CPU endian. */
#define LE16_TO_CPU_ENDIAN(x) swap16(x)
#define LE32_TO_CPU_ENDIAN(x) swap32(x)
#define LE64_TO_CPU_ENDIAN(x) swap64(x)
/* Converting of constants from CPU endian to little endian. */
#define CCPU_ENDIAN_TO_LE16(x) ((uint16_t)(\
(((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \
(((uint16_t)(x) & (uint16_t)0xff00U) >> 8)))
#define CCPU_ENDIAN_TO_LE32(x) ((uint32_t)(\
(((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
(((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
(((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
(((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
#define CCPU_ENDIAN_TO_LE64(x) ((uint64_t)(\
(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \
(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \
(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56)))
/* Converting of constants from little endian to CPU endian. */
#define CLE16_TO_CPU_ENDIAN(x) CCPU_ENDIAN_TO_LE16(x)
#define CLE32_TO_CPU_ENDIAN(x) CCPU_ENDIAN_TO_LE32(x)
#define CLE64_TO_CPU_ENDIAN(x) CCPU_ENDIAN_TO_LE64(x)
/**
* Address copy from the source to the Destination Memory
*/
#define ADDR_COPY_DST_SRC_16(dst, src) memcpy((&(dst)), (&(src)), sizeof(uint16_t))
#define ADDR_COPY_DST_SRC_64(dst, src) do {dst=src;}while(0)
#define MEMCPY_ENDIAN memcpy_be
#ifndef FREERTOS_USED
#if (EXT_BOARD != SPB104)
#ifndef BIG_ENDIAN
#define BIG_ENDIAN
#endif
#endif
#endif
/* Converts a 8 Byte array into a 64-Bit value */
static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data)
{
union
{
uint64_t u64;
uint8_t u8[8];
}long_addr;
uint8_t index;
for (index = 0; index <= 7; index++)
{
long_addr.u8[index] = *data++;
}
return long_addr.u64;
}
/* Converts a 64-Bit value into a 2 Byte array */
#define convert_64_bit_to_byte_array(value, data) \
memcpy((data), (&(value)), sizeof(uint64_t))
/* Converts a 2 Byte array into a 16-Bit value */
static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
{
return (data[1] | ((uint16_t)data[0] << 8));
}
/* Converts a 16-Bit value into a 2 Byte array */
static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data)
{
data[1] = value & 0xFF;
data[0] = (value >> 8) & 0xFF;
}
/* Converts a 8 Byte array into a 32-Bit value */
static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
{
union
{
uint32_t u32;
uint8_t u8[8];
}long_addr;
uint8_t index;
for (index = 0; index < 4; index++)
{
long_addr.u8[index] = *data++;
}
return long_addr.u32;
}
/* Converts a 32-Bit value into a 2 Byte array */
#define convert_32_bit_to_byte_array(value, data) \
memcpy((data), (&(value)), sizeof(uint32_t))
/* Converts a 16-Bit value into a 2 Byte array */
static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data)
{
data[0] = value & 0xFF;
data[1] = (value >> 8) & 0xFF;
}
/* Converts a 16-Bit value into a 2 Byte array */
static inline void convert_16_bit_to_byte_address(uint64_t value, uint8_t *data)
{
data[1] = (value >> 48) & 0xFF;
data[0] = (value >> 56) & 0xFF;
}
#define PGM_READ_BYTE(x) *(x)
#define PGM_READ_WORD(x) *(x)
#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len))
#if (defined __GNUC__)
#define nop() do { __asm__ __volatile__ ("nop"); } while (0)
#elif (defined __ICCAVR32__)
#define nop() __no_operation()
#endif
/* Copy char s2[n] to s1[n] in any order */
static inline void *memcpy_be(void *s1, const void *s2, char n)
{
char *su1 = (char *)s1;
const char *su2 = (const char *)s2;
signed char count = 0x00, count1 = 0x00;
if ((n - 1) == 0)
{
*(su1 + count1) = *(su2 + count);
}
for (count = (n - 1), count1 = 0; count >= 0;)
{
*(su1 + count1++) = *(su2 + count--);
}
return (s1);
}
/**
* \}
*/
#endif // __AVR32_ABI_COMPILER__
#endif // _COMPILER_H_
#endif // _COMPILER_AVR32_H_

113
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@ -0,0 +1,113 @@
/**
* \file
*
* \brief Missing Toolchain Definition for UC3 D header files
*
* Copyright (c) 2011-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _UC3D_DEFINES_FIX_
#define _UC3D_DEFINES_FIX_
#include <parts.h>
#if (UC3D)
// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h
#ifndef AVR32_SCIF_GC_NO_DIV_CLOCK
#define AVR32_SCIF_GC_NO_DIV_CLOCK 0
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GC_NO_DIV_CLOCK
#ifndef AVR32_SCIF_GCLK_ADCIFD
#define AVR32_SCIF_GCLK_ADCIFD 8
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_ADCIFD
#ifndef AVR32_SCIF_GCLK_AST
#define AVR32_SCIF_GCLK_AST 6
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_AST
#ifndef AVR32_SCIF_GCLK_GLOC
#define AVR32_SCIF_GCLK_GLOC 0
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_GLOC
#ifndef AVR32_SCIF_GCLK_IISC
#define AVR32_SCIF_GCLK_IISC 5
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_IISC
#ifndef AVR32_SCIF_GCLK_PWMA
#define AVR32_SCIF_GCLK_PWMA 4
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_PWMA
#ifndef AVR32_SCIF_GCLK_USBC
#define AVR32_SCIF_GCLK_USBC 3
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // end AVR32_SCIF_GCLK_USBC
#ifndef AVR32_PM_CPU_MAX_FREQ
#define AVR32_PM_CPU_MAX_FREQ 48000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_CPU_MAX_FREQ
#ifndef AVR32_PM_HSB_MAX_FREQ
#define AVR32_PM_HSB_MAX_FREQ 48000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_HSB_MAX_FREQ
#ifndef AVR32_PM_PBA_MAX_FREQ
#define AVR32_PM_PBA_MAX_FREQ 48000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_PBA_MAX_FREQ
#ifndef AVR32_PM_PBB_MAX_FREQ
#define AVR32_PM_PBB_MAX_FREQ 48000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_PBB_MAX_FREQ
#endif // end UC3D
#endif // _UC3D_DEFINES_FIX

107
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@ -0,0 +1,107 @@
/**
* \file
*
* \brief Missing Toolchain Definition for UC3 L3 and UC3 L4 header files
*
* Copyright (c) 2012-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _UCL3_L4_DEFINES_FIX_
#define _UCL3_L4_DEFINES_FIX_
#include <parts.h>
#if (UC3L3_L4)
// These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h
#ifndef AVR32_PM_CPU_MAX_FREQ
#define AVR32_PM_CPU_MAX_FREQ 50000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_CPU_MAX_FREQ
#ifndef AVR32_PM_HSB_MAX_FREQ
#define AVR32_PM_HSB_MAX_FREQ 50000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_HSB_MAX_FREQ
#ifndef AVR32_PM_PBA_MAX_FREQ
#define AVR32_PM_PBA_MAX_FREQ 50000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_PBA_MAX_FREQ
#ifndef AVR32_PM_PBB_MAX_FREQ
#define AVR32_PM_PBB_MAX_FREQ 50000000
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_PBB_MAX_FREQ
#ifndef AVR32_PM_MCSEL_SLOW
#define AVR32_PM_MCSEL_SLOW 0
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_MCSEL_SLOW
#ifndef AVR32_PM_MCSEL_OSC0
#define AVR32_PM_MCSEL_OSC0 1
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_MCSEL_OSC0
#ifndef AVR32_PM_MCSEL_DFLL0
#define AVR32_PM_MCSEL_DFLL0 2
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_MCSEL_DFLL0
#ifndef AVR32_PM_MCSEL_RC120M
#define AVR32_PM_MCSEL_RC120M 3
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_MCSEL_RC120M
#ifndef AVR32_PM_MCSEL_PLL0
#define AVR32_PM_MCSEL_PLL0 5
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_PM_MCSEL_PLL0
#ifndef AVR32_CORE_COMPARE_IRQ
#define AVR32_CORE_COMPARE_IRQ 0
#else
#warning "Duplicate define(s) to remove from the ASF"
#endif // AVR32_CORE_COMPARE_IRQ
#endif // end UC3L3_L4
#endif // _UCL3_L4_DEFINES_FIX

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/**
* \file
*
* \brief Global interrupt management for 8- and 32-bit AVR
*
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef UTILS_INTERRUPT_H
#define UTILS_INTERRUPT_H
#include <parts.h>
#if XMEGA || MEGA
# include "interrupt/interrupt_avr8.h"
#elif UC3
# include "interrupt/interrupt_avr32.h"
#elif SAM || SAMB
# include "interrupt/interrupt_sam_nvic.h"
#else
# error Unsupported device.
#endif
/**
* \defgroup interrupt_group Global interrupt management
*
* This is a driver for global enabling and disabling of interrupts.
*
* @{
*/
#if defined(__DOXYGEN__)
/**
* \def CONFIG_INTERRUPT_FORCE_INTC
* \brief Force usage of the ASF INTC driver
*
* Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
* This is useful to ensure compatibility across compilers and shall be used only when required
* by the application needs.
*/
# define CONFIG_INTERRUPT_FORCE_INTC
#endif
//! \name Global interrupt flags
//@{
/**
* \typedef irqflags_t
* \brief Type used for holding state of interrupt flag
*/
/**
* \def cpu_irq_enable
* \brief Enable interrupts globally
*/
/**
* \def cpu_irq_disable
* \brief Disable interrupts globally
*/
/**
* \fn irqflags_t cpu_irq_save(void)
* \brief Get and clear the global interrupt flags
*
* Use in conjunction with \ref cpu_irq_restore.
*
* \return Current state of interrupt flags.
*
* \note This function leaves interrupts disabled.
*/
/**
* \fn void cpu_irq_restore(irqflags_t flags)
* \brief Restore global interrupt flags
*
* Use in conjunction with \ref cpu_irq_save.
*
* \param flags State to set interrupt flag to.
*/
/**
* \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
* \brief Check if interrupts are globally enabled in supplied flags
*
* \param flags Currents state of interrupt flags.
*
* \return True if interrupts are enabled.
*/
/**
* \def cpu_irq_is_enabled
* \brief Check if interrupts are globally enabled
*
* \return True if interrupts are enabled.
*/
//@}
//! @}
/**
* \ingroup interrupt_group
* \defgroup interrupt_deprecated_group Deprecated interrupt definitions
*/
#endif /* UTILS_INTERRUPT_H */

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@ -0,0 +1,341 @@
/**
* \file
*
* \brief Global interrupt management for 32-bit AVR
*
* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef UTILS_INTERRUPT_INTERRUPT_H
#define UTILS_INTERRUPT_INTERRUPT_H
#include <compiler.h>
#include <preprocessor/tpaste.h>
/**
* \weakgroup interrupt_group
*
* @{
*/
//! Pointer to interrupt handler.
#if (defined __GNUC__)
typedef void (*__int_handler)(void);
#elif (defined __ICCAVR32__)
typedef void (__interrupt *__int_handler)(void);
#endif
/**
* \name Interrupt Service Routine definition and registration
*
* @{
*/
#if defined(__GNUC__) || defined(__DOXYGEN__)
/**
* \brief Macro to declare an interrupt service routine
*
* With GCC, this macro only causes the function to be defined as an interrupt
* service routine, i.e., it does not add any initialization code. A valid
* function name is required for use with \ref irq_register_handler.
*
* With IAR, this macro defines the function as an interrupt service routine and
* causes the compiler to add initialization code for the interrupt controller
* (INTC). The interrupt group and level, as well as a valid function name are
* therefore required.\n
* \note If \ref CONFIG_INTERRUPT_FORCE_INTC is defined, only a valid function
* name is required for use with \ref irq_register_handler. The initialization
* code will be handled by the interrupt controller itself.
*
* Usage:
* \code
ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n)
{
// Function definition
...
}
\endcode
*
* \param func Name for the function, needed by \ref irq_register_handler.
* \param int_grp Interrupt group to define service routine for.
* \param int_lvl Priority level to set for the interrupt group, in the range
* \c 0 to \c 3.
*
* \note The interrupt groups can be found in the device header files for the
* IAR toolchain (avr32/io\<part\>.h).
*
* \todo Update to use IRQ numbers when these are made available in the
* device header files of both IAR and GCC.
*/
# define ISR(func, int_grp, int_lvl) \
__attribute__((__interrupt__)) static void func (void)
#elif defined(__ICCAVR32__) && defined(CONFIG_INTERRUPT_FORCE_INTC)
# define ISR(func, int_grp, int_lvl) \
__interrupt static void func (void)
#elif defined(__ICCAVR32__)
# define ISR0(...) _Pragma(#__VA_ARGS__)
# define ISR(func, int_grp, int_lvl) \
ISR0(handler=int_grp, int_lvl) \
__interrupt static void func (void)
#endif
#if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC)
# include <intc.h>
/**
* \brief Initialize interrupt vectors
*
* With GCC, this macro adds code for initialization of the interrupt vectors
* with the driver for the interrupt controller (INTC).
*
* With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
* adds no code, since initialization of the INTC is handled by the compiler.
* \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
* INTC driver, replacing the compiler built-in interrupt handler.
*
* This must be called prior to \ref irq_register_handler.
*/
# define irq_initialize_vectors() INTC_init_interrupts()
/**
* \brief Register handler for interrupt
*
* With GCC, this macro adds code for registering an interrupt handler with the
* driver for the interrupt controller (INTC).
*
* With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
* adds no code, since initialization of the INTC is handled by the compiler.
* \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
* INTC driver, replacing the compiler built-in interrupt handler.
*
* \param func Name of handler function to register for interrupt.
* \param int_num Number of the interrupt line to register function for.
* \param int_lvl Priority level to set for the interrupt's group, in the range
* \c 0 to \c 3.
*
* Usage:
* \code
irq_initialize_vectors();
irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n);
\endcode
*
* \note The function \a func must be defined with the \ref ISR macro.
* \note The interrupt line number can be found in the device header files for
* the GCC toolchain (avr32/\<part\>.h).
*/
# define irq_register_handler(func, int_num, int_lvl) \
INTC_register_interrupt(func, int_num, \
TPASTE2(AVR32_INTC_INT, int_lvl))
#elif defined(__ICCAVR32__)
# define irq_initialize_vectors() do{ } while(0)
# define irq_register_handler(func, int_num, int_lvl) do{ } while(0)
#endif
//@}
#if (defined __GNUC__)
# define cpu_irq_enable() \
do { \
barrier(); \
__builtin_csrf(AVR32_SR_GM_OFFSET); \
} while (0)
# define cpu_irq_disable() \
do { \
__builtin_ssrf(AVR32_SR_GM_OFFSET); \
barrier(); \
} while (0)
#elif (defined __ICCAVR32__)
# if (defined CONFIG_INTERRUPT_FORCE_INTC)
# define cpu_irq_enable() \
do { \
barrier(); \
__clear_status_flag(AVR32_SR_GM_OFFSET); \
} while(0)
# define cpu_irq_disable() \
do { \
__set_status_flag(AVR32_SR_GM_OFFSET); \
barrier(); \
} while (0)
# else
# define cpu_irq_enable() __enable_interrupt()
# define cpu_irq_disable() __disable_interrupt()
# endif
#endif
typedef uint32_t irqflags_t;
static inline irqflags_t cpu_irq_save(void)
{
volatile irqflags_t flags;
flags = sysreg_read(AVR32_SR);
cpu_irq_disable();
return flags;
}
static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
{
return !(flags & AVR32_SR_GM_MASK);
}
static inline void cpu_irq_restore(irqflags_t flags)
{
barrier();
/* Restore the global IRQ mask status flag if it was previously set */
if ( cpu_irq_is_enabled_flags(flags) ) {
cpu_irq_enable();
}
barrier();
}
#define cpu_irq_is_enabled() cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR))
//! \name Global interrupt levels
//@{
/**
* \brief Check if interrupt level is enabled in supplied flags
*
* \param flags State of interrupt flags.
* \param level Bit position for interrupt level.
*
* \return True if interrupt level is enabled.
*/
static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
uint32_t level)
{
return !(flags & (1 << level));
}
/**
* \brief Check if interrupt level is enabled
*
* \param level Interrupt level (0 to 3).
*
* \return True if interrupt level \a level is enabled.
*
* \note The interrupt level must be known at compile time.
*/
#define cpu_irq_level_is_enabled(level) \
cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR), \
TPASTE3(AVR32_SR_I, level, M_OFFSET))
#if defined(__GNUC__) || defined(__DOXYGEN__)
/**
* \brief Enable interrupt level
*
* \param level Interrupt level to enable (0 to 3).
*
* \note The interrupt level must be known at compile time.
*/
# define cpu_irq_enable_level(level) \
do { \
barrier(); \
__builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
} while (0)
/**
* \brief Disable interrupt level
*
* \param level Interrupt level to disable (0 to 3).
*
* \note The interrupt level must be known at compile time.
*/
# define cpu_irq_disable_level(level) \
do { \
__builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
barrier(); \
} while (0)
#elif (defined __ICCAVR32__)
# define cpu_irq_enable_level(level) \
do { \
barrier(); \
__clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
} while(0)
# define cpu_irq_disable_level(level) \
do { \
__set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
barrier(); \
} while (0)
#endif
//@}
//@}
/**
* \weakgroup interrupt_deprecated_group
* @{
*/
#define Enable_global_interrupt() cpu_irq_enable()
#define Disable_global_interrupt() cpu_irq_disable()
#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
#define Enable_interrupt_level(level) cpu_irq_enable_level(level)
#define Disable_interrupt_level(level) cpu_irq_disable_level(level)
#define Is_interrupt_level_enabled(level) cpu_irq_level_is_enabled(level)
/**
* \name Interrupt protection of code sections
* \note Use \ref cpu_irq_save and \ref cpu_irq_restore instead of these macros.
* @{
*/
/**
* \brief Start section with code protected against interrupts
*/
#define AVR32_ENTER_CRITICAL_REGION() \
{ \
bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
Disable_global_interrupt();
/**
* \brief End section with code protected against interrupts
*
* \note This macro must always be used in conjunction with
* \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again.
*/
#define AVR32_LEAVE_CRITICAL_REGION() \
if (global_interrupt_enabled) Enable_global_interrupt(); \
}
//@}
//@}
#endif /* UTILS_INTERRUPT_INTERRUPT_H */

0
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_cpu.h → bsp/avr32/software_framework/utils/libs/newlib_addons/include/nlao_cpu.h
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bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_exceptions.h → bsp/avr32/software_framework/utils/libs/newlib_addons/include/nlao_exceptions.h
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0
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_interrupts.h → bsp/avr32/software_framework/utils/libs/newlib_addons/include/nlao_interrupts.h
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0
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_io.h → bsp/avr32/software_framework/utils/libs/newlib_addons/include/nlao_io.h
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0
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/LIBS/NEWLIB_ADDONS/INCLUDE/nlao_usart.h → bsp/avr32/software_framework/utils/libs/newlib_addons/include/nlao_usart.h
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79
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@ -1,52 +1,52 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief Preprocessor macro repeating utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _MREPEAT_H_
#define _MREPEAT_H_
/**
* \defgroup group_avr32_utils_mrepeat Preprocessor - Macro Repeat
*
* \ingroup group_avr32_utils
*
* \{
*/
#include "preprocessor.h"
@ -324,5 +324,8 @@
#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data)
#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data)
/**
* \}
*/
#endif // _MREPEAT_H_

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/*****************************************************************************
*
* \file
*
* \brief Preprocessor utils.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_
#include "tpaste.h"
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_

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/*****************************************************************************
*
* \file
*
* \brief Preprocessor stringizing utils.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_
/**
* \defgroup group_avr32_utils_stringz Preprocessor - Stringize
*
* \ingroup group_avr32_utils
*
* \{
*/
/*! \brief Stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* May be used only within macros with the token passed as an argument if the token is \#defined.
*
* For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
* and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
* writing "A0".
*/
#define STRINGZ(x) #x
/*! \brief Absolute stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* No restriction of use if the token is \#defined.
*
* For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
* equivalent to writing "A0".
*/
#define ASTRINGZ(x) STRINGZ(x)
/**
* \}
*/
#endif // _STRINGZ_H_

78
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/UTILS/PREPROCESSOR/tpaste.h → bsp/avr32/software_framework/utils/preprocessor/tpaste.h
View File

@ -1,52 +1,51 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
/*****************************************************************************
*
* \file
*
* \brief Preprocessor token pasting utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef _TPASTE_H_
#define _TPASTE_H_
/**
* \defgroup group_avr32_utils_tpaste Preprocessor - Token Paste
*
* \ingroup group_avr32_utils
*
* \{
*/
/*! \name Token Paste
*
@ -91,5 +90,8 @@
#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j)
//! @}
/**
* \}
*/
#endif // _TPASTE_H_

111
bsp/avr32/software_framework/utils/status_codes.h Normal file
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@ -0,0 +1,111 @@
/**
* \file
*
* \brief Status code definitions.
*
* This file defines various status codes returned by functions,
* indicating success or failure as well as what kind of failure.
*
* Copyright (c) 2009-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
*/
#ifndef STATUS_CODES_H_INCLUDED
#define STATUS_CODES_H_INCLUDED
/**
* \defgroup group_avr32_utils_status_codes Status Codes
*
* \ingroup group_avr32_utils
*
* \{
*/
/* Note: this is a local workaround to avoid a pre-processor clash due to the
* lwIP macro ERR_TIMEOUT. */
#if defined(__LWIP_ERR_H__) && defined(ERR_TIMEOUT)
#if (ERR_TIMEOUT != -3)
/* Internal check to make sure that the later restore of lwIP's ERR_TIMEOUT
* macro is set to the correct value. Note that it is highly improbable that
* this value ever changes in lwIP. */
#error ASF developers: check lwip err.h new value for ERR_TIMEOUT
#endif
#undef ERR_TIMEOUT
#endif
/**
* Status code that may be returned by shell commands and protocol
* implementations.
*
* \note Any change to these status codes and the corresponding
* message strings is strictly forbidden. New codes can be added,
* however, but make sure that any message string tables are updated
* at the same time.
*/
enum status_code {
STATUS_OK = 0, //!< Success
ERR_IO_ERROR = -1, //!< I/O error
ERR_FLUSHED = -2, //!< Request flushed from queue
ERR_TIMEOUT = -3, //!< Operation timed out
ERR_BAD_DATA = -4, //!< Data integrity check failed
ERR_PROTOCOL = -5, //!< Protocol error
ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device
ERR_NO_MEMORY = -7, //!< Insufficient memory
ERR_INVALID_ARG = -8, //!< Invalid argument
ERR_BAD_ADDRESS = -9, //!< Bad address
ERR_BUSY = -10, //!< Resource is busy
ERR_BAD_FORMAT = -11, //!< Data format not recognized
ERR_NO_TIMER = -12, //!< No timer available
ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running
ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running
/**
* \brief Operation in progress
*
* This status code is for driver-internal use when an operation
* is currently being performed.
*
* \note Drivers should never return this status code to any
* callers. It is strictly for internal use.
*/
OPERATION_IN_PROGRESS = -128,
};
typedef enum status_code status_code_t;
#if defined(__LWIP_ERR_H__)
#define ERR_TIMEOUT -3
#endif
/**
* \}
*/
#endif /* STATUS_CODES_H_INCLUDED */

20
bsp/avr32uc3b0/SConscript
View File

@ -1,20 +0,0 @@
import rtconfig
Import('RTT_ROOT')
from building import *
src_bsp = ['application.c', 'startup.c', 'board.c']
if GetDepend(['RT_USING_PIN']):
src_bsp += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
if GetDepend(['RT_USING_SERIAL_V2']):
src_bsp += ['drv_uart_v2.c']
else:
src_bsp += ['drv_uart.c']
src = File(src_bsp)
CPPPATH = [RTT_ROOT + '/bsp/avr32uc3b0']
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

1117
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/FLASHC/flashc.c
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File diff suppressed because it is too large Load Diff

458
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c
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@ -1,458 +0,0 @@
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO driver for AVR32 UC3.
*
* This file defines a useful set of functions for the GPIO.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include "gpio.h"
//! GPIO module instance.
#define GPIO AVR32_GPIO
/*! \name Peripheral Bus Interface
*/
//! @{
int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
{
int status = GPIO_SUCCESS;
unsigned int i;
for (i = 0; i < size; i++)
{
status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
gpiomap++;
}
return status;
}
int gpio_enable_module_pin(unsigned int pin, unsigned int function)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the correct function.
switch (function)
{
case 0: // A function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 1: // B function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 2: // C function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
case 3: // D function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pmr2c = 1 << (pin & 0x1F);
#endif
break;
#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
case 4: // E function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 5: // F function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1c = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 6: // G function.
gpio_port->pmr0c = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
case 7: // H function.
gpio_port->pmr0s = 1 << (pin & 0x1F);
gpio_port->pmr1s = 1 << (pin & 0x1F);
gpio_port->pmr2s = 1 << (pin & 0x1F);
break;
#endif
default:
return GPIO_INVALID_ARGUMENT;
}
// Disable GPIO control.
gpio_port->gperc = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
{
unsigned int i;
for (i = 0; i < size; i++)
{
gpio_enable_gpio_pin(gpiomap->pin);
gpiomap++;
}
}
void gpio_enable_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F);
gpio_port->gpers = 1 << (pin & 0x1F);
}
// The open-drain mode is not synthesized on the current AVR32 products.
// If one day some AVR32 products have this feature, the corresponding part
// numbers should be listed in the #if below.
// Note that other functions are available in this driver to use pins with open
// drain in GPIO mode. The advantage of the open-drain mode functions over these
// other functions is that they can be used not only in GPIO mode but also in
// module mode.
#if 0
void gpio_enable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_open_drain(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->odmerc = 1 << (pin & 0x1F);
}
#endif
void gpio_enable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
gpio_port->pderc = 1 << (pin & 0x1F);
#endif
}
void gpio_disable_pin_pull_up(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
}
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
/*! \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_pull_down(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->pderc = 1 << (pin & 0x1F);
}
/*! \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_enable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puers = 1 << (pin & 0x1F);
gpio_port->pders = 1 << (pin & 0x1F);
}
/*! \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
void gpio_disable_pin_buskeeper(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->puerc = 1 << (pin & 0x1F);
gpio_port->pderc = 1 << (pin & 0x1F);
}
#endif
int gpio_get_pin_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->pvr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ovr >> (pin & 0x1F)) & 1;
}
int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;
}
void gpio_set_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrs = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrt = 1 << (pin & 0x1F); // Toggle the I/O line.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_set_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_clr_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_tgl_gpio_open_drain_pin(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ovrc = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0.
gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin.
gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
}
void gpio_enable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gfers = 1 << (pin & 0x1F);
}
void gpio_disable_pin_glitch_filter(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->gferc = 1 << (pin & 0x1F);
}
/*! \brief Configure the edge detector of an input pin
*
* \param pin The pin number.
* \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE
* or \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Configure the edge detector.
switch (mode)
{
case GPIO_PIN_CHANGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_RISING_EDGE:
gpio_port->imr0s = 1 << (pin & 0x1F);
gpio_port->imr1c = 1 << (pin & 0x1F);
break;
case GPIO_FALLING_EDGE:
gpio_port->imr0c = 1 << (pin & 0x1F);
gpio_port->imr1s = 1 << (pin & 0x1F);
break;
default:
return GPIO_INVALID_ARGUMENT;
}
return GPIO_SUCCESS;
}
int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
// Configure the edge detector.
if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode))
return(GPIO_INVALID_ARGUMENT);
// Enable interrupt.
gpio_port->iers = 1 << (pin & 0x1F);
return GPIO_SUCCESS;
}
void gpio_disable_pin_interrupt(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ierc = 1 << (pin & 0x1F);
}
int gpio_get_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
return (gpio_port->ifr >> (pin & 0x1F)) & 1;
}
void gpio_clear_pin_interrupt_flag(unsigned int pin)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
gpio_port->ifrc = 1 << (pin & 0x1F);
}
//#
//# Peripheral Event System Support.
//#
#if UC3L
int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf)
{
volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
if(TRUE == use_igf)
{
// Enable the glitch filter.
gpio_port->gfers = 1 << (pin & 0x1F);
}
else
{
// Disable the glitch filter.
gpio_port->gferc = 1 << (pin & 0x1F);
}
// Configure the edge detector.
return(gpio_configure_edge_detector(pin, mode));
}
#endif
//! @}

583
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h
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@ -1,583 +0,0 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief GPIO header for AVR32 UC3.
*
* This file contains basic GPIO driver functions.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with a GPIO module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
*****************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <avr32/io.h>
#include "compiler.h"
/*! \name Return Values of the GPIO API
*/
//! @{
#define GPIO_SUCCESS 0 //!< Function successfully completed.
#define GPIO_INVALID_ARGUMENT 1 //!< Input parameters are out of range.
//! @}
/*! \name Interrupt Trigger Modes
*/
//! @{
#define GPIO_PIN_CHANGE 0 //!< Interrupt triggered upon pin change.
#define GPIO_RISING_EDGE 1 //!< Interrupt triggered upon rising edge.
#define GPIO_FALLING_EDGE 2 //!< Interrupt triggered upon falling edge.
//! @}
//! A type definition of pins and modules connectivity.
typedef struct
{
unsigned char pin; //!< Module pin.
unsigned char function; //!< Module function.
} gpio_map_t[];
/*! \name Peripheral Bus Interface
*
* Low-speed interface with a non-deterministic number of clock cycles per
* access.
*
* This interface operates with lower clock frequencies (fPB <= fCPU), and its
* timing is not deterministic since it needs to access a shared bus which may
* be heavily loaded.
*
* \note This interface is immediately available without initialization.
*/
//! @{
/*! \brief Enables specific module modes for a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables a specific module mode for a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for module pins. E.g., to enable a PWM
* channel output, the pin number can be AVR32_PWM_3_PIN for PWM
* channel 3.
* \param function The pin function.\n
* Refer to the product header file `uc3x.h' (where x is the
* part number; e.g. x = a0512) for module pin functions. E.g.,
* to enable a PWM channel output, the pin function can be
* AVR32_PWM_3_FUNCTION for PWM channel 3.
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);
/*! \brief Enables the GPIO mode of a set of pins.
*
* \param gpiomap The pin map.
* \param size The number of pins in \a gpiomap.
*/
extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
/*! \brief Enables the GPIO mode of a pin.
*
* \param pin The pin number.\n
* Refer to the product header file `uc3x.h' (where x is the part
* number; e.g. x = a0512) for pin definitions. E.g., to enable the
* GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
* AVR32_PWM_3_PIN for PWM channel 3 can also be used to release
* module pins for GPIO.
*/
extern void gpio_enable_gpio_pin(unsigned int pin);
// The open-drain mode is not synthesized on the current AVR32 products.
// If one day some AVR32 products have this feature, the corresponding part
// numbers should be listed in the #if below.
// Note that other functions are available in this driver to use pins with open
// drain in GPIO mode. The advantage of the open-drain mode functions over these
// other functions is that they can be used not only in GPIO mode but also in
// module mode.
#if 0
/*! \brief Enables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_open_drain(unsigned int pin);
/*! \brief Disables the open-drain mode of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_open_drain(unsigned int pin);
#endif
/*! \brief Enables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_pull_up(unsigned int pin);
/*! \brief Disables the pull-up resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_pull_up(unsigned int pin);
#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
/*! \brief Enables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_pull_down(unsigned int pin);
/*! \brief Disables the pull-down resistor of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_pull_down(unsigned int pin);
/*! \brief Enables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_buskeeper(unsigned int pin);
/*! \brief Disables the buskeeper functionality on a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_buskeeper(unsigned int pin);
#endif
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*/
extern int gpio_get_pin_value(unsigned int pin);
/*! \brief Returns the output value set for a GPIO pin.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with \ref gpio_set_gpio_pin,
* \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin.
*/
extern int gpio_get_gpio_pin_output_value(unsigned int pin);
/*! \brief Returns the output value set for a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \return The pin output value.
*
* \note This function must be used in conjunction with
* \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin
* and \ref gpio_tgl_gpio_open_drain_pin.
*/
extern int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin);
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*/
extern void gpio_set_gpio_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*/
extern void gpio_clr_gpio_pin(unsigned int pin);
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*/
extern void gpio_tgl_gpio_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*/
extern void gpio_set_gpio_open_drain_pin(unsigned int pin);
/*! \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*/
extern void gpio_clr_gpio_open_drain_pin(unsigned int pin);
/*! \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*/
extern void gpio_tgl_gpio_open_drain_pin(unsigned int pin);
/*! \brief Enables the glitch filter of a pin.
*
* When the glitch filter is enabled, a glitch with duration of less than 1
* clock cycle is automatically rejected, while a pulse with duration of 2 clock
* cycles or more is accepted. For pulse durations between 1 clock cycle and 2
* clock cycles, the pulse may or may not be taken into account, depending on
* the precise timing of its occurrence. Thus for a pulse to be guaranteed
* visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
* filtered out, its duration must not exceed 1 clock cycle. The filter
* introduces 2 clock cycles latency.
*
* \param pin The pin number.
*/
extern void gpio_enable_pin_glitch_filter(unsigned int pin);
/*! \brief Disables the glitch filter of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_glitch_filter(unsigned int pin);
/*! \brief Enables the interrupt of a pin with the specified settings.
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);
/*! \brief Disables the interrupt of a pin.
*
* \param pin The pin number.
*/
extern void gpio_disable_pin_interrupt(unsigned int pin);
/*! \brief Gets the interrupt flag of a pin.
*
* \param pin The pin number.
*
* \return The pin interrupt flag.
*/
extern int gpio_get_pin_interrupt_flag(unsigned int pin);
/*! \brief Clears the interrupt flag of a pin.
*
* \param pin The pin number.
*/
extern void gpio_clear_pin_interrupt_flag(unsigned int pin);
//! @}
#if (defined AVR32_GPIO_LOCAL_ADDRESS)
/*! \name Local Bus Interface
*
* High-speed interface with only one clock cycle per access.
*
* This interface operates with high clock frequency (fCPU), and its timing is
* deterministic since it does not need to access a shared bus which may be
* heavily loaded.
*
* \warning To use this interface, the clock frequency of the peripheral bus on
* which the GPIO peripheral is connected must be set to the CPU clock
* frequency (fPB = fCPU).
*
* \note This interface has to be initialized in order to be available.
*/
//! @{
/*! \brief Enables the local bus interface for GPIO.
*
* \note This function must have been called at least once before using other
* functions in this interface.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_init(void)
{
Set_system_register(AVR32_CPUCR,
Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
}
/*! \brief Enables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/*! \brief Disables the output driver of a pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/*! \brief Returns the value of a pin.
*
* \param pin The pin number.
*
* \return The pin value.
*
* \note \ref gpio_local_init must have been called beforehand.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ int gpio_local_get_pin_value(unsigned int pin)
{
return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
}
/*! \brief Drives a GPIO pin to 1.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 0.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/*! \brief Toggles a GPIO pin.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init must have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin nor its output
* driver. \ref gpio_enable_gpio_pin and
* \ref gpio_local_enable_pin_output_driver can be called for this
* purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
}
/*! \brief Initializes the configuration of a GPIO pin so that it can be used
* with GPIO open-drain functions.
*
* \note This function must have been called at least once before using
* \ref gpio_local_set_gpio_open_drain_pin,
* \ref gpio_local_clr_gpio_open_drain_pin or
* \ref gpio_local_tgl_gpio_open_drain_pin.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_init_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 1 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_set_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
}
/*! \brief Drives a GPIO pin to 0 using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_clr_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
}
/*! \brief Toggles a GPIO pin using open drain.
*
* \param pin The pin number.
*
* \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
* have been called beforehand.
*
* \note This function does not enable the GPIO mode of the pin.
* \ref gpio_enable_gpio_pin can be called for this purpose.
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_local_tgl_gpio_open_drain_pin(unsigned int pin)
{
AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);
}
//! @}
#endif // AVR32_GPIO_LOCAL_ADDRESS
#if UC3L
//! @{
/*! \name Peripheral Event System support
*
* The GPIO can be programmed to output peripheral events whenever an interrupt
* condition is detected, such as pin value change, or only when a rising or
* falling edge is detected.
*
*/
/*! \brief Enables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_enable_pin_periph_event(unsigned int pin)
{
AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);
}
/*! \brief Disables the peripheral event generation of a pin.
*
* \param pin The pin number.
*
*/
#if (defined __GNUC__)
__attribute__((__always_inline__))
#endif
extern __inline__ void gpio_disable_pin_periph_event(unsigned int pin)
{
AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);
}
/*! \brief Configure the peripheral event trigger mode of a pin
*
* \param pin The pin number.
* \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
* \ref GPIO_FALLING_EDGE).
* \param use_igf use the Input Glitch Filter (TRUE) or not (FALSE).
*
* \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
*/
extern int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf);
//! @}
#endif
#endif // _GPIO_H_

239
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x
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@ -1,239 +0,0 @@
/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supported by an AVR32.
*
* - Compiler: GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#if !__AVR32_UC__ && !__AVR32_AP__
#error Implementation of the AVR32 architecture not supported by the INTC driver.
#endif
#include <avr32/io.h>
//! @{
//! \verbatim
.section .exception, "ax", @progbits
// Start of Exception Vector Table.
// EVBA must be aligned with a power of two strictly greater than the EVBA-
// relative offset of the last vector.
.balign 0x200
// Export symbol.
.global _evba
.type _evba, @function
_evba:
.org 0x000
// Unrecoverable Exception.
_handle_Unrecoverable_Exception:
rjmp $
.org 0x004
// TLB Multiple Hit.
_handle_TLB_Multiple_Hit:
rjmp $
.org 0x008
// Bus Error Data Fetch.
_handle_Bus_Error_Data_Fetch:
rjmp $
.org 0x00C
// Bus Error Instruction Fetch.
_handle_Bus_Error_Instruction_Fetch:
rjmp $
.org 0x010
// NMI.
_handle_NMI:
rjmp $
.org 0x014
// Instruction Address.
_handle_Instruction_Address:
rjmp $
.org 0x018
// ITLB Protection.
_handle_ITLB_Protection:
rjmp $
.org 0x01C
// Breakpoint.
_handle_Breakpoint:
rjmp $
.org 0x020
// Illegal Opcode.
_handle_Illegal_Opcode:
rjmp $
.org 0x024
// Unimplemented Instruction.
_handle_Unimplemented_Instruction:
rjmp $
.org 0x028
// Privilege Violation.
_handle_Privilege_Violation:
rjmp $
.org 0x02C
// Floating-Point: UNUSED IN AVR32UC and AVR32AP.
_handle_Floating_Point:
rjmp $
.org 0x030
// Coprocessor Absent: UNUSED IN AVR32UC.
_handle_Coprocessor_Absent:
rjmp $
.org 0x034
// Data Address (Read).
_handle_Data_Address_Read:
rjmp $
.org 0x038
// Data Address (Write).
_handle_Data_Address_Write:
rjmp $
.org 0x03C
// DTLB Protection (Read).
_handle_DTLB_Protection_Read:
rjmp $
.org 0x040
// DTLB Protection (Write).
_handle_DTLB_Protection_Write:
rjmp $
.org 0x044
// DTLB Modified: UNUSED IN AVR32UC.
_handle_DTLB_Modified:
rjmp $
.org 0x050
// ITLB Miss.
_handle_ITLB_Miss:
rjmp $
.org 0x060
// DTLB Miss (Read).
_handle_DTLB_Miss_Read:
rjmp $
.org 0x070
// DTLB Miss (Write).
_handle_DTLB_Miss_Write:
rjmp $
.org 0x100
// Supervisor Call.
_handle_Supervisor_Call:
rjmp $
// Interrupt support.
// The interrupt controller must provide the offset address relative to EVBA.
// Important note:
// All interrupts call a C function named _get_interrupt_handler.
// This function will read group and interrupt line number to then return in
// R12 a pointer to a user-provided interrupt handler.
.balign 4
.irp priority, 0, 1, 2, 3
_int\priority:
#if __AVR32_UC__
// R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
// CPU upon interrupt entry. No other register is saved by hardware.
#elif __AVR32_AP__
// PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
// the CPU upon interrupt entry. No other register is saved by hardware.
pushm r8-r12, lr
#endif
mov r12, \priority // Pass the int_level parameter to the _get_interrupt_handler function.
call _get_interrupt_handler
cp.w r12, 0 // Get the pointer to the interrupt handler returned by the function.
#if __AVR32_UC__
movne pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
#elif __AVR32_AP__
breq spint\priority // If this was a spurious interrupt (R12 == NULL), branch.
st.w --sp, r12 // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
popm r8-r12, lr, pc // Restore registers and jump to the handler.
spint\priority:
popm r8-r12, lr
#endif
rete // If this was a spurious interrupt (R12 == NULL), return from event handler.
.endr
// Constant data area.
.balign 4
// Values to store in the interrupt priority registers for the various interrupt priority levels.
// The interrupt priority registers contain the interrupt priority level and
// the EVBA-relative interrupt vector offset.
.global ipr_val
.type ipr_val, @object
ipr_val:
.word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
(AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
(AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
(AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
//! \endverbatim
//! @}

214
bsp/avr32uc3b0/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c
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/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
#include "intc.h"
// define _evba from exception.S
extern void _evba;
//! Values to store in the interrupt priority registers for the various interrupt priority levels.
extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
//! Each line handler table contains a set of pointers to interrupt handlers.
#if (defined __GNUC__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#elif (defined __ICCAVR32__)
#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
#endif
MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
#undef DECL_INT_LINE_HANDLER_TABLE
//! Table containing for each interrupt group the number of interrupt request
//! lines and a pointer to the table of interrupt line handlers.
static const struct
{
unsigned int num_irqs;
volatile __int_handler *_int_line_handler_table;
} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
{
#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
{AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
#undef INSERT_INT_LINE_HANDLER_TABLE
};
/*! \brief Default interrupt handler.
*
* \note Taken and adapted from Newlib.
*/
#if (defined __GNUC__)
__attribute__((__interrupt__))
#elif (defined __ICCAVR32__)
__interrupt
#endif
static void _unhandled_interrupt(void)
{
// Catch unregistered interrupts.
while (TRUE);
}
/*! \brief Gets the interrupt handler of the current event at the \a int_level
* interrupt priority level (called from exception.S).
*
* \param int_level Interrupt priority level to handle.
*
* \return Interrupt handler to execute.
*
* \note Taken and adapted from Newlib.
*/
__int_handler _get_interrupt_handler(unsigned int int_level)
{
// ICR3 is mapped first, ICR0 last.
// Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
// pass a single argument to a function.
unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
unsigned int int_req = AVR32_INTC.irr[int_grp];
// As an interrupt may disappear while it is being fetched by the CPU
// (spurious interrupt caused by a delayed response from an MCU peripheral to
// an interrupt flag clear or interrupt disable instruction), check if there
// are remaining interrupt lines to process.
// If a spurious interrupt occurs, the status register (SR) contains an
// execution mode and interrupt level masks corresponding to a level 0
// interrupt, whatever the interrupt priority level causing the spurious
// event. This behavior has been chosen because a spurious interrupt has not
// to be a priority one and because it may not cause any trouble to other
// interrupts.
// However, these spurious interrupts place the hardware in an unstable state
// and could give problems in other/future versions of the CPU, so the
// software has to be written so that they never occur. The only safe way of
// achieving this is to always clear or disable peripheral interrupts with the
// following sequence:
// 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
// 2: Perform the bus access to the peripheral register that clears or
// disables the interrupt.
// 3: Wait until the interrupt has actually been cleared or disabled by the
// peripheral. This is usually performed by reading from a register in the
// same peripheral (it DOES NOT have to be the same register that was
// accessed in step 2, but it MUST be in the same peripheral), what takes
// bus system latencies into account, but peripheral internal latencies
// (generally 0 cycle) also have to be considered.
// 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
// Note that steps 1 and 4 are useless inside interrupt handlers as the
// corresponding interrupt level is automatically masked by IxM (unless IxM is
// explicitly cleared by the software).
//
// Get the right IRQ handler.
//
// If several interrupt lines are active in the group, the interrupt line with
// the highest number is selected. This is to be coherent with the
// prioritization of interrupt groups performed by the hardware interrupt
// controller.
//
// If no handler has been registered for the pending interrupt,
// _unhandled_interrupt will be selected thanks to the initialization of
// _int_line_handler_table_x by INTC_init_interrupts.
//
// exception.S will provide the interrupt handler with a clean interrupt stack
// frame, with nothing more pushed onto the stack. The interrupt handler must
// manage the `rete' instruction, what can be done thanks to pure assembly,
// inline assembly or the `__attribute__((__interrupt__))' C function
// attribute.
return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
}
//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
static __inline__ void INTC_init_evba(void)
{
Set_system_register(AVR32_EVBA, (int)&_evba );
}
void INTC_init_interrupts(void)
{
unsigned int int_grp, int_req;
INTC_init_evba();
// For all interrupt groups,
for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
{
// For all interrupt request lines of each group,
for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
{
// Assign _unhandled_interrupt as default interrupt handler.
_int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
}
// Set the interrupt group priority register to its default value.
// By default, all interrupt groups are linked to the interrupt priority
// level 0 and to the interrupt vector _int0.
AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
}
}
void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
{
// Determine the group of the IRQ.
unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
// Store in _int_line_handler_table_x the pointer to the interrupt handler, so
// that _get_interrupt_handler can retrieve it when the interrupt is vectored.
_int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
// Program the corresponding IPRX register to set the interrupt priority level
// and the interrupt vector offset that will be fetched by the core interrupt
// system.
// NOTE: The _intx functions are intermediate assembly functions between the
// core interrupt system and the user interrupt handler.
AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
}

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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief INTC driver for AVR32 UC3.
*
* AVR32 Interrupt Controller driver module.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices with an INTC module can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _INTC_H_
#define _INTC_H_
#include "compiler.h"
//! Maximal number of interrupt request lines per group.
#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32
//! Number of interrupt priority levels.
#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
//! Pointer to interrupt handler.
#if (defined __GNUC__)
typedef void (*__int_handler)(void);
#elif (defined __ICCAVR32__)
typedef void (__interrupt *__int_handler)(void);
#endif
/*! \brief Initializes the hardware interrupt controller driver.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_init_interrupts(void);
/*! \brief Registers an interrupt handler.
*
* \param handler Interrupt handler to register.
* \param irq IRQ of the interrupt handler to register.
* \param int_level Interrupt priority level to assign to the group of this IRQ.
*
* \warning The interrupt handler must manage the `rete' instruction, what can
* be done thanks to pure assembly, inline assembly or the
* `__attribute__((__interrupt__))' C function attribute.
*
* \warning If several interrupt handlers of a same group are registered with
* different priority levels, only the latest priority level set will
* be effective.
*
* \note Taken and adapted from Newlib.
*/
extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level);
#endif // __AVR32_ABI_COMPILER__
#endif // _INTC_H_

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@ -1,30 +0,0 @@
import rtconfig
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Split("""
DRIVERS/FLASHC/flashc.c
DRIVERS/GPIO/gpio.c
DRIVERS/INTC/intc.c
DRIVERS/PM/pm.c
DRIVERS/PM/pm_conf_clocks.c
DRIVERS/PM/power_clocks_lib.c
DRIVERS/USART/usart.c
""")
CPPPATH = [
cwd + '/BOARDS',
cwd + '/UTILS',
cwd + '/UTILS/PREPROCESSOR',
cwd + '/DRIVERS/FLASHC',
cwd + '/DRIVERS/GPIO',
cwd + '/DRIVERS/INTC',
cwd + '/DRIVERS/PM',
cwd + '/DRIVERS/USART',
]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

55
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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _PREPROCESSOR_H_
#define _PREPROCESSOR_H_
#include "tpaste.h"
#include "stringz.h"
#include "mrepeat.h"
#endif // _PREPROCESSOR_H_

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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Preprocessor stringizing utils.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _STRINGZ_H_
#define _STRINGZ_H_
/*! \brief Stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* May be used only within macros with the token passed as an argument if the token is \#defined.
*
* For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN)
* and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to
* writing "A0".
*/
#define STRINGZ(x) #x
/*! \brief Absolute stringize.
*
* Stringize a preprocessing token, this token being allowed to be \#defined.
*
* No restriction of use if the token is \#defined.
*
* For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is
* equivalent to writing "A0".
*/
#define ASTRINGZ(x) STRINGZ(x)
#endif // _STRINGZ_H_

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@ -1,203 +0,0 @@
/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Arch file for AVR32.
*
* This file defines common AVR32 UC3 series.
*
* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
* - Supported devices: All AVR32 devices can be used.
* - AppNote:
*
* \author Atmel Corporation: http://www.atmel.com \n
* Support and FAQ: http://support.atmel.no/
*
******************************************************************************/
/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an Atmel
* AVR product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
*
*/
#ifndef _ARCH_H_
#define _ARCH_H_
// UC3 A Series
#define UC3A0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A0128__) || \
defined (__AVR32_UC3A0256__) || \
defined (__AVR32_UC3A0512__) || \
defined (__AVR32_UC3A0512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A0128__) || \
defined (__AT32UC3A0256__) || \
defined (__AT32UC3A0512__) || \
defined (__AT32UC3A0512ES__)))
#define UC3A1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A1128__) || \
defined (__AVR32_UC3A1256__) || \
defined (__AVR32_UC3A1512__) || \
defined (__AVR32_UC3A1512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A1128__) || \
defined (__AT32UC3A1256__) || \
defined (__AT32UC3A1512__) || \
defined (__AT32UC3A1512ES__)))
#define UC3A3 ( defined (__GNUC__) && \
( defined (__AVR32_UC3A364__) || \
defined (__AVR32_UC3A364S__) || \
defined (__AVR32_UC3A3128__) || \
defined (__AVR32_UC3A3128S__) || \
defined (__AVR32_UC3A3256__) || \
defined (__AVR32_UC3A3256S__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3A364__) || \
defined (__AT32UC3A364S__) || \
defined (__AT32UC3A3128__) || \
defined (__AT32UC3A3128S__) || \
defined (__AT32UC3A3256__) || \
defined (__AT32UC3A3256S__)))
#define UC3A (UC3A0 || UC3A1 || UC3A3)
// UC3 B Series
#define UC3B0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3B064__) || \
defined (__AVR32_UC3B0128__) || \
defined (__AVR32_UC3B0256__) || \
defined (__AVR32_UC3B0256ES__) || \
defined (__AVR32_UC3B0512__) || \
defined (__AVR32_UC3B0512REVC_))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3B064__) || \
defined (__AT32UC3B0128__) || \
defined (__AT32UC3B0256__) || \
defined (__AT32UC3B0256ES__) || \
defined (__AT32UC3B0512__) || \
defined (__AT32UC3B0512REVC__)))
#define UC3B1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3B164__) || \
defined (__AVR32_UC3B1128__) || \
defined (__AVR32_UC3B1256__) || \
defined (__AVR32_UC3B1256ES__) || \
defined (__AVR32_UC3B1512__) || \
defined (__AVR32_UC3B1512ES__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3B164__) || \
defined (__AT32UC3B1128__) || \
defined (__AT32UC3B1256__) || \
defined (__AT32UC3B1256ES__) || \
defined (__AT32UC3B1512__) || \
defined (__AT32UC3B1512REVC__)))
#define UC3B (UC3B0 || UC3B1 )
// UC3 C Series
#define UC3C0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C064C__) || \
defined (__AVR32_UC3C0128C__) || \
defined (__AVR32_UC3C0256C__) || \
defined (__AVR32_UC3C0512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C064C__) || \
defined (__AT32UC3C0128C__) || \
defined (__AT32UC3C0256C__) || \
defined (__AT32UC3C0512C__)))
#define UC3C1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C164C__) || \
defined (__AVR32_UC3C1128C__) || \
defined (__AVR32_UC3C1256C__) || \
defined (__AVR32_UC3C1512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C164C__) || \
defined (__AT32UC3C1128C__) || \
defined (__AT32UC3C1256C__) || \
defined (__AT32UC3C1512C__)))
#define UC3C2 ( defined (__GNUC__) && \
( defined (__AVR32_UC3C264C__) || \
defined (__AVR32_UC3C2128C__) || \
defined (__AVR32_UC3C2256C__) || \
defined (__AVR32_UC3C2512CREVC__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3C264C__) || \
defined (__AT32UC3C2128C__) || \
defined (__AT32UC3C2256C__) || \
defined (__AT32UC3C2512C__)))
#define UC3C (UC3C0 || UC3C1 || UC3C2)
// UC3 L Device series
#define UC3L0 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L016__) || \
defined (__AVR32_UC3L032__) || \
defined (__AVR32_UC3L064__) || \
defined (__AVR32_UC3L064REVB__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L016__) || \
defined (__AT32UC3L032__) || \
defined (__AT32UC3L064__) || \
defined (__AT32UC3L064REVB__)))
#define UC3L1 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L116__) || \
defined (__AVR32_UC3L132__) || \
defined (__AVR32_UC3L164__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L116__) || \
defined (__AT32UC3L132__) || \
defined (__AT32UC3L164__)))
#define UC3L2 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L216__) || \
defined (__AVR32_UC3L232__) || \
defined (__AVR32_UC3L264__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L216__) || \
defined (__AT32UC3L232__) || \
defined (__AT32UC3L264__)))
#define UC3L3 ( defined (__GNUC__) && \
( defined (__AVR32_UC3L316__) || \
defined (__AVR32_UC3L332__) || \
defined (__AVR32_UC3L364__))) \
||((defined(__ICCAVR32__) || defined(__AAVR32__)) && \
( defined (__AT32UC3L316__) || \
defined (__AT32UC3L332__) || \
defined (__AT32UC3L364__)))
#define UC3L (UC3L0 || UC3L1 || UC3L2 || UC3L3)
#endif // _ARCH_H_

20
bsp/avr32uc3b0/drv_gpio.h
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@ -1,20 +0,0 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-10-18 Raman Gopalan Initial version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtconfig.h>
#ifdef RT_USING_PIN
int rt_hw_gpio_init(void);
#endif
#endif /* __DRV_GPIO_H__ */